OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Blame information for rev 205

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3
// Filename:    cpuops.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7 69 dgisselq
// Purpose:     This supports the instruction set reordering of operations
8
//              created by the second generation instruction set, as well as
9
//      the new operations of POPC (population count) and BREV (bit reversal).
10 2 dgisselq
//
11 69 dgisselq
//
12 2 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
13 69 dgisselq
//              Gisselquist Technology, LLC
14 2 dgisselq
//
15 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
16 2 dgisselq
//
17 201 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
18 2 dgisselq
//
19
// This program is free software (firmware): you can redistribute it and/or
20
// modify it under the terms of  the GNU General Public License as published
21
// by the Free Software Foundation, either version 3 of the License, or (at
22
// your option) any later version.
23
//
24
// This program is distributed in the hope that it will be useful, but WITHOUT
25
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
26
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
27
// for more details.
28
//
29 201 dgisselq
// You should have received a copy of the GNU General Public License along
30
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
31
// target there if the PDF file isn't present.)  If not, see
32
// <http://www.gnu.org/licenses/> for a copy.
33
//
34 2 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
35
//              http://www.gnu.org/licenses/gpl.html
36
//
37
//
38 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
39 2 dgisselq
//
40 193 dgisselq
`include "cpudefs.v"
41
//
42
module  cpuops(i_clk,i_rst, i_ce, i_op, i_a, i_b, o_c, o_f, o_valid,
43
                        o_busy);
44
        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;
45 2 dgisselq
        input           i_clk, i_rst, i_ce;
46
        input           [3:0]    i_op;
47
        input           [31:0]   i_a, i_b;
48
        output  reg     [31:0]   o_c;
49
        output  wire    [3:0]    o_f;
50
        output  reg             o_valid;
51 71 dgisselq
        output  wire            o_busy;
52 2 dgisselq
 
53 62 dgisselq
        // Shift register pre-logic
54 175 dgisselq
        wire    [32:0]           w_lsr_result, w_asr_result, w_lsl_result;
55
        wire    signed  [32:0]   w_pre_asr_input, w_pre_asr_shifted;
56
        assign  w_pre_asr_input = { i_a, 1'b0 };
57
        assign  w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0];
58 56 dgisselq
        assign  w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
59 175 dgisselq
                                : w_pre_asr_shifted;// ASR
60
        assign  w_lsr_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
61
                                :((i_b[5])?{32'h0,i_a[31]}
62
 
63
                                : ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR
64
        assign  w_lsl_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00
65
                                :((i_b[5])?{i_a[0], 32'h0}
66
                                : ({1'b0, i_a } << i_b[4:0]));   // LSL
67 2 dgisselq
 
68 69 dgisselq
        // Bit reversal pre-logic
69
        wire    [31:0]   w_brev_result;
70
        genvar  k;
71
        generate
72
        for(k=0; k<32; k=k+1)
73 80 dgisselq
        begin : bit_reversal_cpuop
74 69 dgisselq
                assign w_brev_result[k] = i_b[31-k];
75 80 dgisselq
        end endgenerate
76 25 dgisselq
 
77 69 dgisselq
        // Prelogic for our flags registers
78 2 dgisselq
        wire    z, n, v;
79 201 dgisselq
        reg     c, pre_sign, set_ovfl, keep_sgn_on_ovfl;
80 2 dgisselq
        always @(posedge i_clk)
81 69 dgisselq
                if (i_ce) // 1 LUT
82 201 dgisselq
                        set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
83 69 dgisselq
                                ||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD
84
                                ||(i_op == 4'h6) // LSL
85
                                ||(i_op == 4'h5)); // LSR
86 201 dgisselq
        always @(posedge i_clk)
87
                if (i_ce) // 1 LUT
88
                        keep_sgn_on_ovfl<=
89
                                (((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP
90
                                ||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD
91 56 dgisselq
 
92 193 dgisselq
        wire    [63:0]   mpy_result; // Where we dump the multiply result
93
        reg     mpyhi;          // Return the high half of the multiply
94
        wire    mpybusy;        // The multiply is busy if true
95
        wire    mpydone;        // True if we'll be valid on the next clock;
96 62 dgisselq
 
97
        // A 4-way multiplexer can be done in one 6-LUT.
98
        // A 16-way multiplexer can therefore be done in 4x 6-LUT's with
99
        //      the Xilinx multiplexer fabric that follows. 
100
        // Given that we wish to apply this multiplexer approach to 33-bits,
101
        // this will cost a minimum of 132 6-LUTs.
102 193 dgisselq
 
103
        wire    this_is_a_multiply_op;
104 201 dgisselq
        assign  this_is_a_multiply_op = (i_ce)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc));
105 193 dgisselq
 
106 56 dgisselq
        generate
107
        if (IMPLEMENT_MPY == 0)
108 193 dgisselq
        begin // No multiply support.
109
                assign  mpy_result = 63'h00;
110
        end else if (IMPLEMENT_MPY == 1)
111
        begin // Our single clock option (no extra clocks)
112
                wire    signed  [63:0]   w_mpy_a_input, w_mpy_b_input;
113
                assign  w_mpy_a_input = {{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
114
                assign  w_mpy_b_input = {{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
115
                assign  mpy_result = w_mpy_a_input * w_mpy_b_input;
116
                assign  mpybusy = 1'b0;
117
                assign  mpydone = 1'b0;
118
                always @(*) mpyhi = 1'b0; // Not needed
119
        end else if (IMPLEMENT_MPY == 2)
120
        begin // Our two clock option (ALU must pause for 1 clock)
121
                reg     signed  [63:0]   r_mpy_a_input, r_mpy_b_input;
122 56 dgisselq
                always @(posedge i_clk)
123 2 dgisselq
                begin
124 193 dgisselq
                        r_mpy_a_input <={{(32){(i_a[31])&(i_op[0])}},i_a[31:0]};
125
                        r_mpy_b_input <={{(32){(i_b[31])&(i_op[0])}},i_b[31:0]};
126 56 dgisselq
                end
127 71 dgisselq
 
128 193 dgisselq
                assign  mpy_result = r_mpy_a_input * r_mpy_b_input;
129
                assign  mpybusy = 1'b0;
130 71 dgisselq
 
131 205 dgisselq
                reg     mpypipe;
132 193 dgisselq
                initial mpypipe = 1'b0;
133 71 dgisselq
                always @(posedge i_clk)
134 193 dgisselq
                        if (i_rst)
135
                                mpypipe <= 1'b0;
136
                        else
137
                                mpypipe <= (this_is_a_multiply_op);
138
 
139
                assign  mpydone = mpypipe; // this_is_a_multiply_op;
140
                always @(posedge i_clk)
141
                        if (this_is_a_multiply_op)
142
                                mpyhi  = i_op[1];
143
        end else if (IMPLEMENT_MPY == 3)
144
        begin // Our three clock option (ALU pauses for 2 clocks)
145
                reg     signed  [63:0]   r_smpy_result;
146
                reg             [63:0]   r_umpy_result;
147
                reg     signed  [31:0]   r_mpy_a_input, r_mpy_b_input;
148
                reg             [1:0]    mpypipe;
149
                reg             [1:0]    r_sgn;
150
 
151
                initial mpypipe = 2'b0;
152
                always @(posedge i_clk)
153
                        if (i_rst)
154
                                mpypipe <= 2'b0;
155
                        else
156
                        mpypipe <= { mpypipe[0], this_is_a_multiply_op };
157
 
158
                // First clock
159
                always @(posedge i_clk)
160
                begin
161
                        r_mpy_a_input <= i_a[31:0];
162
                        r_mpy_b_input <= i_b[31:0];
163
                        r_sgn <= { r_sgn[0], i_op[0] };
164
                end
165
 
166
                // Second clock
167
`ifdef  VERILATOR
168
                wire    signed  [63:0]   s_mpy_a_input, s_mpy_b_input;
169
                wire            [63:0]   u_mpy_a_input, u_mpy_b_input;
170
 
171
                assign  s_mpy_a_input = {{(32){r_mpy_a_input[31]}},r_mpy_a_input};
172
                assign  s_mpy_b_input = {{(32){r_mpy_b_input[31]}},r_mpy_b_input};
173
                assign  u_mpy_a_input = {32'h00,r_mpy_a_input};
174
                assign  u_mpy_b_input = {32'h00,r_mpy_b_input};
175
                always @(posedge i_clk)
176
                        r_smpy_result = s_mpy_a_input * s_mpy_b_input;
177
                always @(posedge i_clk)
178
                        r_umpy_result = u_mpy_a_input * u_mpy_b_input;
179
`else
180
 
181
                wire            [31:0]   u_mpy_a_input, u_mpy_b_input;
182
 
183
                assign  u_mpy_a_input = r_mpy_a_input;
184
                assign  u_mpy_b_input = r_mpy_b_input;
185
 
186
                always @(posedge i_clk)
187
                        r_smpy_result = r_mpy_a_input * r_mpy_b_input;
188
                always @(posedge i_clk)
189
                        r_umpy_result = u_mpy_a_input * u_mpy_b_input;
190 133 dgisselq
`endif
191 193 dgisselq
 
192
                always @(posedge i_clk)
193
                        if (this_is_a_multiply_op)
194
                                mpyhi  = i_op[1];
195
                assign  mpybusy = mpypipe[0];
196
                assign  mpy_result = (r_sgn[1])?r_smpy_result:r_umpy_result;
197
                assign  mpydone = mpypipe[1];
198
 
199
                // Results are then set on the third clock
200
        end else // if (IMPLEMENT_MPY <= 4)
201
        begin // The three clock option
202 133 dgisselq
                reg     [63:0]   r_mpy_result;
203 193 dgisselq
                reg     [31:0]   r_mpy_a_input, r_mpy_b_input;
204
                reg             r_mpy_signed;
205
                reg     [2:0]    mpypipe;
206 133 dgisselq
 
207 193 dgisselq
                // First clock, latch in the inputs
208 205 dgisselq
                initial mpypipe = 3'b0;
209 193 dgisselq
                always @(posedge i_clk)
210
                begin
211
                        // mpypipe indicates we have a multiply in the
212
                        // pipeline.  In this case, the multiply
213
                        // pipeline is a two stage pipeline, so we need 
214
                        // two bits in the pipe.
215
                        if (i_rst)
216
                                mpypipe <= 3'h0;
217
                        else begin
218
                                mpypipe[0] <= this_is_a_multiply_op;
219 133 dgisselq
                                mpypipe[1] <= mpypipe[0];
220 193 dgisselq
                                mpypipe[2] <= mpypipe[1];
221 133 dgisselq
                        end
222
 
223 193 dgisselq
                        if (i_op[0]) // i.e. if signed multiply
224 133 dgisselq
                        begin
225 193 dgisselq
                                r_mpy_a_input <= {(~i_a[31]),i_a[30:0]};
226
                                r_mpy_b_input <= {(~i_b[31]),i_b[30:0]};
227
                        end else begin
228
                                r_mpy_a_input <= i_a[31:0];
229
                                r_mpy_b_input <= i_b[31:0];
230 133 dgisselq
                        end
231 193 dgisselq
                        // The signed bit really only matters in the
232
                        // case of 64 bit multiply.  We'll keep track
233
                        // of it, though, and pretend in all other
234
                        // cases.
235
                        r_mpy_signed  <= i_op[0];
236 133 dgisselq
 
237 193 dgisselq
                        if (this_is_a_multiply_op)
238
                                mpyhi  = i_op[1];
239
                end
240 56 dgisselq
 
241 193 dgisselq
                assign  mpybusy = |mpypipe[1:0];
242
                assign  mpydone = mpypipe[2];
243
 
244
                // Second clock, do the multiplies, get the "partial
245
                // products".  Here, we break our input up into two
246
                // halves, 
247 62 dgisselq
                //
248 193 dgisselq
                //   A  = (2^16 ah + al)
249
                //   B  = (2^16 bh + bl)
250 62 dgisselq
                //
251 193 dgisselq
                // and use these to compute partial products.
252
                //
253
                //   AB = (2^32 ah*bh + 2^16 (ah*bl + al*bh) + (al*bl)
254
                //
255
                // Since we're following the FOIL algorithm to get here,
256
                // we'll name these partial products according to FOIL.
257
                //
258
                // The trick is what happens if A or B is signed.  In
259
                // those cases, the real value of A will not be given by
260
                //      A = (2^16 ah + al)
261
                // but rather
262
                //      A = (2^16 ah[31^] + al) - 2^31
263
                //  (where we have flipped the sign bit of A)
264
                // and so ...
265
                //
266
                // AB= (2^16 ah + al - 2^31) * (2^16 bh + bl - 2^31)
267
                //      = 2^32(ah*bh)
268
                //              +2^16 (ah*bl+al*bh)
269
                //              +(al*bl)
270
                //              - 2^31 (2^16 bh+bl + 2^16 ah+al)
271
                //              - 2^62
272
                //      = 2^32(ah*bh)
273
                //              +2^16 (ah*bl+al*bh)
274
                //              +(al*bl)
275
                //              - 2^31 (2^16 bh+bl + 2^16 ah+al + 2^31)
276
                //
277
                reg     [31:0]   pp_f, pp_l; // F and L from FOIL
278
                reg     [32:0]   pp_oi; // The O and I from FOIL
279
                reg     [32:0]   pp_s;
280 56 dgisselq
                always @(posedge i_clk)
281
                begin
282 193 dgisselq
                        pp_f<=r_mpy_a_input[31:16]*r_mpy_b_input[31:16];
283
                        pp_oi<=r_mpy_a_input[31:16]*r_mpy_b_input[15: 0]
284
                                + r_mpy_a_input[15: 0]*r_mpy_b_input[31:16];
285
                        pp_l<=r_mpy_a_input[15: 0]*r_mpy_b_input[15: 0];
286
                        // And a special one for the sign
287
                        if (r_mpy_signed)
288
                                pp_s <= 32'h8000_0000-(
289
                                        r_mpy_a_input[31:0]
290
                                        + r_mpy_b_input[31:0]);
291
                        else
292
                                pp_s <= 33'h0;
293
                end
294 2 dgisselq
 
295 193 dgisselq
                // Third clock, add the results and produce a product
296 56 dgisselq
                always @(posedge i_clk)
297 193 dgisselq
                begin
298
                        r_mpy_result[15:0] <= pp_l[15:0];
299
                        r_mpy_result[63:16] <=
300
                                { 32'h00, pp_l[31:16] }
301
                                + { 15'h00, pp_oi }
302
                                + { pp_s, 15'h00 }
303
                                + { pp_f, 16'h00 };
304
                end
305 71 dgisselq
 
306 193 dgisselq
                assign  mpy_result = r_mpy_result;
307
                // Fourth clock -- results are clocked into writeback
308
        end
309
        endgenerate // All possible multiply results have been determined
310 71 dgisselq
 
311 193 dgisselq
        //
312
        // The master ALU case statement
313
        //
314
        always @(posedge i_clk)
315
        if (i_ce)
316
        begin
317
                pre_sign <= (i_a[31]);
318
                c <= 1'b0;
319
                casez(i_op)
320
                4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB
321
                4'b0001:   o_c   <= i_a & i_b;          // BTST/And
322
                4'b0010:{c,o_c } <= i_a + i_b;          // Add
323
                4'b0011:   o_c   <= i_a | i_b;          // Or
324
                4'b0100:   o_c   <= i_a ^ i_b;          // Xor
325
                4'b0101:{o_c,c } <= w_lsr_result[32:0];  // LSR
326
                4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL
327
                4'b0111:{o_c,c } <= w_asr_result[32:0];  // ASR
328 201 dgisselq
                4'b1000:   o_c   <= w_brev_result;      // BREV
329 193 dgisselq
                4'b1001:   o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
330 201 dgisselq
                4'b1010:   o_c   <= mpy_result[63:32];  // MPYHU
331
                4'b1011:   o_c   <= mpy_result[63:32];  // MPYHS
332
                4'b1100:   o_c   <= mpy_result[31:0];    // MPY
333 193 dgisselq
                default:   o_c   <= i_b;                // MOV, LDI
334
                endcase
335
        end else // if (mpydone)
336
                o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0];
337 56 dgisselq
 
338 193 dgisselq
        reg     r_busy;
339
        initial r_busy = 1'b0;
340
        always @(posedge i_clk)
341
                if (i_rst)
342
                        r_busy <= 1'b0;
343
                else
344
                        r_busy <= ((IMPLEMENT_MPY > 1)
345
                                        &&(this_is_a_multiply_op))||mpybusy;
346
        assign  o_busy = (r_busy); // ||((IMPLEMENT_MPY>1)&&(this_is_a_multiply_op));
347
 
348
 
349 2 dgisselq
        assign  z = (o_c == 32'h0000);
350
        assign  n = (o_c[31]);
351
        assign  v = (set_ovfl)&&(pre_sign != o_c[31]);
352 201 dgisselq
        wire    vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]);
353 2 dgisselq
 
354 201 dgisselq
        assign  o_f = { v, n^vx, c, z };
355 2 dgisselq
 
356
        initial o_valid = 1'b0;
357
        always @(posedge i_clk)
358
                if (i_rst)
359
                        o_valid <= 1'b0;
360 193 dgisselq
                else if (IMPLEMENT_MPY <= 1)
361
                        o_valid <= (i_ce);
362 56 dgisselq
                else
363 193 dgisselq
                        o_valid <=((i_ce)&&(!this_is_a_multiply_op))||(mpydone);
364
 
365 2 dgisselq
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.