OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [cpuops.v] - Blame information for rev 56

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    cpuops.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     
8
//
9
// Creator:     Dan Gisselquist, Ph.D.
10
//              Gisselquist Tecnology, LLC
11
//
12
///////////////////////////////////////////////////////////////////////////
13
//
14
// Copyright (C) 2015, Gisselquist Technology, LLC
15
//
16
// This program is free software (firmware): you can redistribute it and/or
17
// modify it under the terms of  the GNU General Public License as published
18
// by the Free Software Foundation, either version 3 of the License, or (at
19
// your option) any later version.
20
//
21
// This program is distributed in the hope that it will be useful, but WITHOUT
22
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
23
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
24
// for more details.
25
//
26
// License:     GPL, v3, as defined and found on www.gnu.org,
27
//              http://www.gnu.org/licenses/gpl.html
28
//
29
//
30
///////////////////////////////////////////////////////////////////////////
31
//
32 56 dgisselq
module  cpuops(i_clk, i_rst, i_ce, i_valid, i_op, i_a, i_b, o_c, o_f, o_valid,
33
                        o_illegal);
34
        parameter       IMPLEMENT_MPY = 1;
35 2 dgisselq
        input           i_clk, i_rst, i_ce;
36
        input           [3:0]    i_op;
37
        input           [31:0]   i_a, i_b;
38
        input                   i_valid;
39
        output  reg     [31:0]   o_c;
40
        output  wire    [3:0]    o_f;
41
        output  reg             o_valid;
42 56 dgisselq
        output  wire            o_illegal;
43 2 dgisselq
 
44
        wire    [63:0]   w_rol_tmp;
45
        assign  w_rol_tmp = { i_a, i_a } << i_b[4:0];
46
        wire    [31:0]   w_rol_result;
47
        assign  w_rol_result = w_rol_tmp[63:32]; // Won't set flags
48 56 dgisselq
`ifndef NEW_NOT_OLD_CODE
49 15 dgisselq
        wire    [33:0]           w_lsr_result, w_asr_result;
50
        wire    signed  [33:0]   w_ia_input;
51
        assign  w_ia_input = { i_a[31], i_a, 1'b0 };
52
        assign  w_asr_result = (|i_b[31:5])? {(34){i_a[31]}}
53
                                : ( w_ia_input >>> (i_b[4:0]) );// ASR
54
        assign  w_lsr_result = (|i_b[31:5])? 34'h00
55
                                : { 1'b0, i_a, 1'b0 } >> (i_b[4:0]);// LSR
56 56 dgisselq
`else
57
        wire    [32:0]           w_lsr_result, w_asr_result;
58
        assign  w_asr_result = (|i_b[31:5])? {(33){i_a[31]}}
59
                                : ( {i_a, 1'b0 } >>> (i_b[4:0]) );// ASR
60
        assign  w_lsr_result = (|i_b[31:5])? 33'h00
61
                                : ( { i_a, 1'b0 } >> (i_b[4:0]) );// LSR
62
`endif
63 2 dgisselq
 
64 25 dgisselq
 
65 2 dgisselq
        wire    z, n, v;
66
        reg     c, pre_sign, set_ovfl;
67
        always @(posedge i_clk)
68
                if (i_ce)
69
                        set_ovfl =((((i_op==4'h0)||(i_op==4'h8)) // SUB&CMP
70
                                                &&(i_a[31] != i_b[31]))
71
                                ||((i_op==4'ha)&&(i_a[31] == i_b[31])) // ADD
72
                                ||(i_op == 4'hd) // LSL
73
                                ||(i_op == 4'hf)); // LSR
74 56 dgisselq
 
75
        generate
76
        if (IMPLEMENT_MPY == 0)
77
        begin
78
                always @(posedge i_clk)
79 2 dgisselq
                if (i_ce)
80
                begin
81
                        pre_sign <= (i_a[31]);
82
                        c <= 1'b0;
83 3 dgisselq
                        casez(i_op)
84
                        4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
85
                        4'b?001:   o_c   <= i_a & i_b;          // BTST/And
86 56 dgisselq
                        4'h5:      o_c   <= w_rol_result;       // ROL
87
                        4'h6:      o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
88
                        4'h7:      o_c   <= { i_b[15:0], i_a[15:0] }; // LODIHI
89
                        4'ha: { c, o_c } <= i_a + i_b;          // Add
90
                        4'hb:      o_c   <= i_a | i_b;          // Or
91
                        4'hc:      o_c   <= i_a ^ i_b;          // Xor
92
                        4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];     // LSL
93
                        4'he: { o_c, c } <= w_asr_result[32:0];// ASR
94
                        4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR
95
                        default:   o_c   <=       i_b;          // MOV, LDI
96
                        endcase
97
                end
98
        end else begin
99
                wire    signed  [16:0]   w_mpy_a_input, w_mpy_b_input;
100
                wire    signed  [33:0]   w_mpy_result;
101
                assign  w_mpy_a_input = { ((i_a[15])&&(i_op[2])), i_a[15:0] };
102
                assign  w_mpy_b_input = { ((i_b[15])&&(i_op[2])), i_b[15:0] };
103
                assign  w_mpy_result  = w_mpy_a_input * w_mpy_b_input;
104
 
105
                always @(posedge i_clk)
106
                if (i_ce)
107
                begin
108
                        pre_sign <= (i_a[31]);
109
                        c <= 1'b0;
110
                        casez(i_op)
111
                        4'b?000:{c,o_c } <= {(i_b>i_a),i_a - i_b};// CMP/SUB
112
                        4'b?001:   o_c   <= i_a & i_b;          // BTST/And
113 25 dgisselq
                        4'h3: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S
114
                        4'h4: { c, o_c } <= {1'b0,w_mpy_result[31:0]}; // MPYU/S
115 2 dgisselq
                        4'h5:      o_c   <= w_rol_result;       // ROL
116
                        4'h6:      o_c   <= { i_a[31:16], i_b[15:0] }; // LODILO
117
                        4'h7:      o_c   <= { i_b[15:0], i_a[15:0] }; // LODIHI
118
                        4'ha: { c, o_c } <= i_a + i_b;          // Add
119
                        4'hb:      o_c   <= i_a | i_b;          // Or
120
                        4'hc:      o_c   <= i_a ^ i_b;          // Xor
121 12 dgisselq
                        4'hd: { c, o_c } <= (|i_b[31:5])? 33'h00 : {1'b0, i_a } << i_b[4:0];     // LSL
122 15 dgisselq
                        4'he: { o_c, c } <= w_asr_result[32:0];// ASR
123
                        4'hf: { o_c, c } <= w_lsr_result[32:0];// LSR
124 2 dgisselq
                        default:   o_c   <=       i_b;          // MOV, LDI
125
                        endcase
126
                end
127 56 dgisselq
        end endgenerate
128 2 dgisselq
 
129 56 dgisselq
        generate
130
        if (IMPLEMENT_MPY == 0)
131
        begin
132
                reg     r_illegal;
133
                always @(posedge i_clk)
134
                        r_illegal <= (i_op == 4'h3)||(i_op == 4'h4);
135
                assign o_illegal = r_illegal;
136
        end else
137
                assign o_illegal = 1'b0;
138
        endgenerate
139
 
140 2 dgisselq
        assign  z = (o_c == 32'h0000);
141
        assign  n = (o_c[31]);
142
        assign  v = (set_ovfl)&&(pre_sign != o_c[31]);
143
 
144
        assign  o_f = { v, n, c, z };
145
 
146
        initial o_valid = 1'b0;
147
        always @(posedge i_clk)
148
                if (i_rst)
149
                        o_valid <= 1'b0;
150 56 dgisselq
                else
151
                        o_valid <= (i_ce)&&(i_valid);
152 2 dgisselq
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.