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////////////////////////////////////////////////////////////////////////////////

//

// Filename:    dcache.v

//

// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core

//

// Purpose:     To provide a simple data cache for the ZipCPU.  The cache is

//              designed to be a drop in replacement for the pipememm memory

//      unit currently existing within the ZipCPU.  The goal of this unit is

//      to achieve single cycle read access to any memory in the last cache line

//      used, or two cycle access to any memory currently in the cache.

//

//      The cache separates between four types of accesses, one write and three

//      read access types.  The read accesses are split between those that are

//      not cacheable, those that are in the cache, and those that are not.

//

//      1. Write accesses always create writes to the bus.  For these reasons,

//              these may always be considered cache misses.

//

//              Writes to memory locations within the cache must also update

//              cache memory immediately, to keep the cache in synch.

//

//              It is our goal to be able to maintain single cycle write

//              accesses for memory bursts.

//

//      2. Read access to non-cacheable memory locations will also immediately

//              go to the bus, just as all write accesses go to the bus.

//

//      3. Read accesses to cacheable memory locations will immediately read

//              from the appropriate cache line.  However, since thee valid

//              line will take a second clock to read, it may take up to two

//              clocks to know if the memory was in cache.  For this reason,

//              we bypass the test for the last validly accessed cache line.

//

//              We shall design these read accesses so that reads to the cache

//              may take place concurrently with other writes to the bus.

//

//      Errors in cache reads will void the entire cache line.  For this reason,

//      cache lines must always be of a smaller in size than any associated

//      virtual page size--lest in the middle of reading a page a TLB miss

//      take place referencing only a part of the cacheable page.

//

//

//

//

// Creator:     Dan Gisselquist, Ph.D.

//              Gisselquist Technology, LLC

//

////////////////////////////////////////////////////////////////////////////////

//

// Copyright (C) 2016-2019, Gisselquist Technology, LLC

//

// This program is free software (firmware): you can redistribute it and/or

// modify it under the terms of  the GNU General Public License as published

// by the Free Software Foundation, either version 3 of the License, or (at

// your option) any later version.

//

// This program is distributed in the hope that it will be useful, but WITHOUT

// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// License:     GPL, v3, as defined and found on www.gnu.org,

//              http://www.gnu.org/licenses/gpl.html

//

//

////////////////////////////////////////////////////////////////////////////////

//

//

`default_nettype        none

//

//

`ifdef  FORMAL

`define ASSERT  assert

`ifdef DCACHE

`define ASSUME  assume

`else

`define ASSUME  assert

`endif

`endif

module  dcache(i_clk, i_reset, i_pipe_stb, i_lock,

                i_op, i_addr, i_data, i_oreg,

                        o_busy, o_pipe_stalled, o_valid, o_err, o_wreg,o_data,

                o_wb_cyc_gbl, o_wb_cyc_lcl, o_wb_stb_gbl, o_wb_stb_lcl,

                        o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,

                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data

`ifdef  FORMAL

                , f_nreqs, f_nacks, f_outstanding, f_pc

`endif

        );

        parameter       LGCACHELEN = 8,

                        ADDRESS_WIDTH=30,

                        LGNLINES=(LGCACHELEN-3), // Log of the number of separate cache lines

                        NAUX=5; // # of aux d-wires to keep aligned w/memops

        parameter [0:0]   OPT_LOCAL_BUS=1'b1;

        parameter [0:0]   OPT_PIPE=1'b1;

        parameter [0:0]   OPT_LOCK=1'b1;

        parameter [0:0]   OPT_DUAL_READ_PORT=1'b1;

        parameter       OPT_FIFO_DEPTH = 4;

        localparam      AW = ADDRESS_WIDTH; // Just for ease of notation below

        localparam      CS = LGCACHELEN; // Number of bits in a cache address

        localparam      LS = CS-LGNLINES; // Bits to spec position w/in cline

        parameter       F_LGDEPTH=1 + (((!OPT_PIPE)||(LS > OPT_FIFO_DEPTH))

                                        ? LS : OPT_FIFO_DEPTH);

        localparam      LGAUX = 3; // log_2 of the maximum number of piped data

        localparam      DW = 32; // Bus data width

        localparam      DP = OPT_FIFO_DEPTH;

        //

        localparam [1:0] DC_IDLE  = 2'b00; // Bus is idle

        localparam [1:0] DC_WRITE = 2'b01; // Write

        localparam [1:0] DC_READS = 2'b10; // Read a single value(!cachd)

        localparam [1:0] DC_READC = 2'b11; // Read a whole cache line

        //

        input   wire            i_clk, i_reset;

        // Interface from the CPU

        input   wire            i_pipe_stb, i_lock;

        input   wire [2:0]               i_op;

        input   wire [(DW-1):0]  i_addr;

        input   wire [(DW-1):0]  i_data;

        input   wire [(NAUX-1):0] i_oreg; // Aux data, such as reg to write to

        // Outputs, going back to the CPU

        output  reg             o_busy;

        output  reg             o_pipe_stalled;

        output  reg             o_valid, o_err;

        output reg [(NAUX-1):0]  o_wreg;

        output  reg [(DW-1):0]   o_data;

        // Wishbone bus master outputs

        output  wire            o_wb_cyc_gbl, o_wb_cyc_lcl;

        output  reg             o_wb_stb_gbl, o_wb_stb_lcl;

        output  reg             o_wb_we;

        output  reg [(AW-1):0]   o_wb_addr;

        output  reg [(DW-1):0]   o_wb_data;

        output  wire [(DW/8-1):0] o_wb_sel;

        // Wishbone bus slave response inputs

        input   wire                    i_wb_ack, i_wb_stall, i_wb_err;

        input   wire    [(DW-1):0]       i_wb_data;

`ifdef FORMAL

        output  wire [(F_LGDEPTH-1):0]   f_nreqs, f_nacks, f_outstanding;

        output  wire                    f_pc;

        reg     f_past_valid;

`endif

        //

        // output       reg     [31:0]          o_debug;

        reg     cyc, stb, last_ack, end_of_line, last_line_stb;

        reg     r_wb_cyc_gbl, r_wb_cyc_lcl;

        // npending is the number of pending non-cached operations, counted

        // from the i_pipe_stb to the o_wb_ack

        reg     [DP:0]   npending;

        reg     [((1<<LGNLINES)-1):0] c_v;       // One bit per cache line, is it valid?

        reg     [(AW-LS-1):0]    c_vtags [0:((1<<LGNLINES)-1)];

        reg     [(DW-1):0]       c_mem   [0:((1<<CS)-1)];

        reg                     set_vflag;

        reg     [1:0]            state;

        reg     [(CS-1):0]       wr_addr;

        reg     [(DW-1):0]       cached_idata, cached_rdata;

        reg     [DW-1:0] pre_data;

        reg                     lock_gbl, lock_lcl;

        // To simplify writing to the cache, and the job of the synthesizer to

        // recognize that a cache write needs to take place, we'll take an extra

        // clock to get there, and use these c_w... registers to capture the

        // data in the meantime.

        reg                     c_wr;

        reg     [(DW-1):0]       c_wdata;

        reg     [(DW/8-1):0]     c_wsel;

        reg     [(CS-1):0]       c_waddr;

        reg     [(AW-LS-1):0]    last_tag;

        reg                     last_tag_valid;

        wire    [(LGNLINES-1):0] i_cline;

        wire    [(CS-1):0]       i_caddr;

`ifdef  FORMAL

        reg     [F_LGDEPTH-1:0]  f_fill;

        reg     [AW:0]           f_return_address;

        reg     [AW:0]           f_pending_addr;

`endif

        assign  i_cline = i_addr[(CS+1):LS+2];

        assign  i_caddr = i_addr[(CS+1):2];

        wire    cache_miss_inow, w_cachable;

        assign  cache_miss_inow = (!last_tag_valid)

                                        ||(last_tag != i_addr[(AW+1):LS+2])

                                        ||(!c_v[i_cline]);

        wire    raw_cachable_address;

        iscachable chkaddress(i_addr[AW+1:2], raw_cachable_address);

        assign  w_cachable = ((!OPT_LOCAL_BUS)||(i_addr[(DW-1):(DW-8)]!=8'hff))

                &&((!i_lock)||(!OPT_LOCK))&&(raw_cachable_address);

        reg     r_cachable, r_svalid, r_dvalid, r_rd, r_cache_miss,

                r_rd_pending;

        reg     [(AW-1):0]               r_addr;

        wire    [(LGNLINES-1):0] r_cline;

        wire    [(CS-1):0]               r_caddr;

        wire    [(AW-LS-1):0]            r_ctag;

        assign  r_cline = r_addr[(CS-1):LS];

        assign  r_caddr = r_addr[(CS-1):0];

        assign  r_ctag  = r_addr[(AW-1):LS];

        reg     wr_cstb, r_iv, in_cache;

        reg     [(AW-LS-1):0]    r_itag;

        reg     [DW/8-1:0]       r_sel;

        reg     [(NAUX+4-1):0]   req_data;

        reg                     gie;

        //

        // The one-clock delayed read values from the cache.

        //

        initial r_rd = 1'b0;

        initial r_cachable = 1'b0;

        initial r_svalid = 1'b0;

        initial r_dvalid = 1'b0;

        initial r_cache_miss = 1'b0;

        initial r_addr = 0;

        initial last_tag_valid = 0;

        initial r_rd_pending = 0;

        always @(posedge i_clk)

        if (i_reset)

        begin

                r_rd <= 1'b0;

                r_cachable <= 1'b0;

                r_svalid <= 1'b0;

                r_dvalid <= 1'b0;

                r_cache_miss <= 1'b0;

                r_addr <= 0;

                r_rd_pending <= 0;

                last_tag_valid <= 0;

        end else begin

                // The single clock path

                // The valid for the single clock path

                //      Only ... we need to wait if we are currently writing

                //      to our cache.

                r_svalid<= (i_pipe_stb)&&(!i_op[0])&&(w_cachable)

                                &&(!cache_miss_inow)&&(!c_wr)&&(!wr_cstb);

                //

                // The two clock in-cache path

                //

                // Some preliminaries that needed to be calculated on the first

                // clock

                if ((!o_pipe_stalled)&&(!r_rd_pending))

                        r_addr <= i_addr[(AW+1):2];

                if ((!o_pipe_stalled)&&(!r_rd_pending))

                begin

                        r_iv   <= c_v[i_cline];

                        r_itag <= c_vtags[i_cline];

                        r_cachable <= (!i_op[0])&&(w_cachable)&&(i_pipe_stb);

                        r_rd_pending <= (i_pipe_stb)&&(!i_op[0])&&(w_cachable)

                                &&((cache_miss_inow)||(c_wr)||(wr_cstb));

                                // &&((!c_wr)||(!wr_cstb));

                end else begin

                        r_iv   <= c_v[r_cline];

                        r_itag <= c_vtags[r_cline];

                        r_rd_pending <= (r_rd_pending)

                                &&((!cyc)||(!i_wb_err))

                                &&((r_itag != r_ctag)||(!r_iv));

                end

                r_rd <= (i_pipe_stb)&&(!i_op[0]);

                // r_itag contains the tag we didn't have available to us on the

                // last clock, r_ctag is a bit select from r_addr containing a

                // one clock delayed address.

                r_dvalid <= (!r_svalid)&&(!r_dvalid)&&(r_itag == r_ctag)&&(r_iv)

                                                &&(r_cachable)&&(r_rd_pending);

                if ((r_itag == r_ctag)&&(r_iv)&&(r_cachable)&&(r_rd_pending))

                begin

                        last_tag_valid <= 1'b1;

                        last_tag <= r_ctag;

                end else if ((state == DC_READC)

                                &&(last_tag[CS-LS-1:0]==o_wb_addr[CS-1:LS])

                                &&((i_wb_ack)||(i_wb_err)))

                        last_tag_valid <= 1'b0;

                // r_cache miss takes a clock cycle.  It is only ever true for

                // something that should be cachable, but isn't in the cache.

                // A cache miss is only true _if_

                // 1. A read was requested

                // 2. It is for a cachable address, AND

                // 3. It isn't in the cache on the first read

                //      or the second read

                // 4. The read hasn't yet started to get this address

                r_cache_miss <= ((!cyc)||(o_wb_we))&&(r_cachable)

                                // One clock path -- miss

                                &&(!r_svalid)

                                // Two clock path -- misses as well

                                &&(r_rd)&&(!r_svalid)

                                &&((r_itag != r_ctag)||(!r_iv));

        end

        initial r_sel = 4'hf;

        always @(posedge i_clk)

        if (i_reset)

                r_sel <= 4'hf;

        else if (!o_pipe_stalled)

        begin

                casez({i_op[2:1], i_addr[1:0]})

                4'b0???: r_sel <= 4'b1111;

                4'b100?: r_sel <= 4'b1100;

                4'b101?: r_sel <= 4'b0011;

                4'b1100: r_sel <= 4'b1000;

                4'b1101: r_sel <= 4'b0100;

                4'b1110: r_sel <= 4'b0010;

                4'b1111: r_sel <= 4'b0001;

                endcase

        end

        assign  o_wb_sel = (state == DC_READC) ? 4'hf : r_sel;

        initial o_wb_data = 0;

        always @(posedge i_clk)

        if (i_reset)

                o_wb_data <= 0;

        else if ((!o_busy)||((stb)&&(!i_wb_stall)))

        begin

                casez(i_op[2:1])

                2'b0?: o_wb_data <= i_data;

                2'b10: o_wb_data <= { (2){i_data[15:0]} };

                2'b11: o_wb_data <= { (4){i_data[ 7:0]} };

                endcase

        end

        generate if (OPT_PIPE)

        begin : OPT_PIPE_FIFO

                reg     [NAUX+4-2:0]     fifo_data [0:((1<<OPT_FIFO_DEPTH)-1)];

                reg     [DP:0]           wraddr, rdaddr;

                always @(posedge i_clk)

                if (i_pipe_stb)

                        fifo_data[wraddr[DP-1:0]]

                                <= { i_oreg[NAUX-2:0], i_op[2:1], i_addr[1:0] };

                always @(posedge i_clk)

                if (i_pipe_stb)

                        gie <= i_oreg[NAUX-1];

`ifdef  NO_BKRAM

                reg     [NAUX+4-2:0]     r_req_data, r_last_data;

                reg                     single_write;

                always @(posedge i_clk)

                        r_req_data <= fifo_data[rdaddr[DP-1:0]];

                always @(posedge i_clk)

                        single_write <= (rdaddr == wraddr)&&(i_pipe_stb);

                always @(posedge i_clk)

                if (i_pipe_stb)

                        r_last_data <= { i_oreg[NAUX-2:0],

                                                i_op[2:1], i_addr[1:0] };

                always @(*)

                begin

                        req_data[NAUX+4-1] = gie;

                        // if ((r_svalid)||(state == DC_READ))

                        if (single_write)

                                req_data[NAUX+4-2:0] = r_last_data;

                        else

                                req_data[NAUX+4-2:0] = r_req_data;

                end

                always @(*)

                        `ASSERT(req_data == fifo_data[rdaddr[DP-1:0]]);

`else

                always @(*)

                        req_data[NAUX+4-2:0] = fifo_data[rdaddr[DP-1:0]];

                always @(*)

                        req_data[NAUX+4-1] = gie;

`endif

                initial wraddr = 0;

                always @(posedge i_clk)

                if ((i_reset)||((cyc)&&(i_wb_err)))

                        wraddr <= 0;

                else if (i_pipe_stb)

                        wraddr <= wraddr + 1'b1;

                initial rdaddr = 0;

                always @(posedge i_clk)

                if ((i_reset)||((cyc)&&(i_wb_err)))

                        rdaddr <= 0;

                else if ((r_dvalid)||(r_svalid))

                        rdaddr <= rdaddr + 1'b1;

                else if ((state == DC_WRITE)&&(i_wb_ack))

                        rdaddr <= rdaddr + 1'b1;

                else if ((state == DC_READS)&&(i_wb_ack))

                        rdaddr <= rdaddr + 1'b1;

`ifdef  FORMAL

                reg     [AW-1:0] f_fifo_addr [0:((1<<OPT_FIFO_DEPTH)-1)];

                reg     [F_LGDEPTH-1:0]  f_last_wraddr;

                reg     f_pc_pending;

                always @(*)

                begin

                        f_fill = 0;

                        f_fill[DP:0] = wraddr - rdaddr;

                end

                always @(*)

                        `ASSERT(f_fill <= { 1'b1, {(DP){1'b0}} });

                always @(*)

                if ((r_dvalid)||(r_svalid))

                begin

                        if (r_svalid)

                                `ASSERT(f_fill == 1);

                        else if (r_dvalid)

                                `ASSERT(f_fill == 1);

                        else

                                `ASSERT(f_fill == 0);

                end else if (r_rd_pending)

                        `ASSERT(f_fill == 1);

                else

                        `ASSERT(f_fill == npending);

                initial f_pc_pending = 0;

                always @(posedge i_clk)

                if (i_reset)

                        f_pc_pending <= 1'b0;

                else if (i_pipe_stb)

                        f_pc_pending <= (!i_op[0])&&(i_oreg[3:1] == 3'h7);

                else if (f_fill == 0)

                        f_pc_pending <= 1'b0;

                //else if ((o_valid)&&(o_wreg[3:1] == 3'h7)&&(f_fill == 0))

                //      f_pc_pending <= 1'b0;

                always @(posedge i_clk)

                if (f_pc_pending)

                        `ASSUME(!i_pipe_stb);

                always @(posedge i_clk)

                if (state == DC_WRITE)

                        `ASSERT(!f_pc_pending);

                always @(*)

                begin

                        f_last_wraddr = 0;

                        f_last_wraddr[DP:0] = wraddr - 1'b1;

                end

                always @(posedge i_clk)

                if (r_rd_pending)

                        `ASSERT(f_pc_pending == (fifo_data[f_last_wraddr][7:5] == 3'h7));

`define INSPECT_FIFO

                reg     [((1<<(DP+1))-1):0]      f_valid_fifo_entry;

                genvar  k;

                for(k=0; k<(1<<(DP+1)); k=k+1)

                begin

                        always @(*)

                        begin

                        f_valid_fifo_entry[k] = 1'b0;

                        /*

                        if ((rdaddr[DP] != wraddr[DP])

                                        &&(rdaddr[DP-1:0] == wraddr[DP-1:0]))

                                f_valid_fifo_entry[k] = 1'b1;

                        else */

                        if ((rdaddr < wraddr)&&(k < wraddr)

                                        &&(k >= rdaddr))

                                f_valid_fifo_entry[k] = 1'b1;

                        else if ((rdaddr > wraddr)&&(k >= rdaddr))

                                f_valid_fifo_entry[k] = 1'b1;

                        else if ((rdaddr > wraddr)&&(k <  wraddr))

                                f_valid_fifo_entry[k] = 1'b1;

                        end

`ifdef  INSPECT_FIFO

                        wire    [NAUX+4-2:0]     fifo_data_k;

                        assign  fifo_data_k = fifo_data[k[DP-1:0]];

                        always @(*)

                        if (f_valid_fifo_entry[k])

                        begin

                                if (!f_pc_pending)

                                        `ASSERT((o_wb_we)||(fifo_data_k[7:5] != 3'h7));

                                else if (k != f_last_wraddr)

                                        `ASSERT(fifo_data_k[7:5] != 3'h7);

                        end

`endif // INSPECT_FIFO

                end

`ifndef INSPECT_FIFO

                always @(posedge i_clk)

                if ((r_rd_pending)&&(rdaddr[DP:0] != f_last_wraddr[DP-1]))

                        assume(fifo_data[rdaddr][7:5] != 3'h7);

`endif // INSPECT_FIFO

                assign  f_pc = f_pc_pending;

                //

                //

                //

                always @(*)

                        f_pending_addr = f_fifo_addr[rdaddr];

                //

                //

                //

                always @(posedge i_clk)

                if (i_pipe_stb)

                        f_fifo_addr[wraddr[DP-1:0]] <= i_addr[AW+1:2];

                always @(*)

                begin

                        f_return_address[AW] = (o_wb_cyc_lcl);

                        f_return_address[AW-1:0] = f_fifo_addr[rdaddr];

                        if (state == DC_READC)

                                f_return_address[LS-1:0]

                                = (o_wb_addr[LS-1:0] - f_outstanding[LS-1:0]);

                end

`define TWIN_WRITE_TEST

`ifdef  TWIN_WRITE_TEST

                (* anyconst *)  reg     [DP:0]           f_twin_base;

                                reg     [DP:0]           f_twin_next;

                (* anyconst *)  reg     [AW+NAUX+4-2-1:0]        f_twin_first,

                                                        f_twin_second;

                // reg  [AW-1:0]        f_fifo_addr [0:((1<<OPT_FIFO_DEPTH)-1)];

                // reg  [NAUX+4-2:0]    fifo_data [0:((1<<OPT_FIFO_DEPTH)-1)];

                always @(*)     f_twin_next = f_twin_base+1;

                reg     f_twin_none, f_twin_single, f_twin_double, f_twin_last;

                reg     f_twin_valid_one, f_twin_valid_two;

                always @(*)

                begin

                        f_twin_valid_one = ((f_valid_fifo_entry[f_twin_base])

                                &&(f_twin_first == { f_fifo_addr[f_twin_base],

                                                fifo_data[f_twin_base] }));

                        f_twin_valid_two = ((f_valid_fifo_entry[f_twin_next])

                                &&(f_twin_second == { f_fifo_addr[f_twin_next],

                                                fifo_data[f_twin_next] }));

                end

                always @(*)

                begin

                        f_twin_none   =(!f_twin_valid_one)&&(!f_twin_valid_two);

                        f_twin_single =( f_twin_valid_one)&&(!f_twin_valid_two);

                        f_twin_double =( f_twin_valid_one)&&( f_twin_valid_two);

                        f_twin_last   =(!f_twin_valid_one)&&( f_twin_valid_two);

                end

                always @(posedge i_clk)

                if ((!f_past_valid)||($past(i_reset))||($past(cyc && i_wb_err)))

                        `ASSERT(f_twin_none);

                else if ($past(f_twin_none))

                        `ASSERT(f_twin_none || f_twin_single || f_twin_last);

                else if ($past(f_twin_single))

                        `ASSERT(f_twin_none || f_twin_single || f_twin_double || f_twin_last);