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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: dcache.v
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose: To provide a simple data cache for the ZipCPU. The cache is
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// designed to be a drop in replacement for the pipememm memory
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// unit currently existing within the ZipCPU. The goal of this unit is
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// to achieve single cycle read access to any memory in the last cache line
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// used, or two cycle access to any memory currently in the cache.
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//
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// The cache separates between four types of accesses, one write and three
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// read access types. The read accesses are split between those that are
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// not cacheable, those that are in the cache, and those that are not.
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//
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// 1. Write accesses always create writes to the bus. For these reasons,
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// these may always be considered cache misses.
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//
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// Writes to memory locations within the cache must also update
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// cache memory immediately, to keep the cache in synch.
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//
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// It is our goal to be able to maintain single cycle write
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// accesses for memory bursts.
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//
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// 2. Read access to non-cacheable memory locations will also immediately
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// go to the bus, just as all write accesses go to the bus.
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//
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// 3. Read accesses to cacheable memory locations will immediately read
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// from the appropriate cache line. However, since thee valid
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// line will take a second clock to read, it may take up to two
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// clocks to know if the memory was in cache. For this reason,
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// we bypass the test for the last validly accessed cache line.
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//
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// We shall design these read accesses so that reads to the cache
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// may take place concurrently with other writes to the bus.
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//
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// Errors in cache reads will void the entire cache line. For this reason,
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// cache lines must always be of a smaller in size than any associated
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// virtual page size--lest in the middle of reading a page a TLB miss
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// take place referencing only a part of the cacheable page.
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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module dcache(i_clk, i_rst, i_pipe_stb, i_lock,
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i_op, i_addr, i_data, i_oreg,
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o_busy, o_pipe_stalled, o_valid, o_err, o_wreg,o_data,
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o_wb_cyc_gbl, o_wb_cyc_lcl, o_wb_stb_gbl, o_wb_stb_lcl,
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o_wb_we, o_wb_addr, o_wb_data,
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i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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parameter LGCACHELEN = 8,
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ADDRESS_WIDTH=32,
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LGNLINES=5, // Log of the number of separate cache lines
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IMPLEMENT_LOCK=0,
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NAUX=5; // # of aux d-wires to keep aligned w/memops
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localparam SDRAM_BIT = 26;
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localparam FLASH_BIT = 22;
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localparam BLKRAM_BIT= 15;
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localparam AW = ADDRESS_WIDTH; // Just for ease of notation below
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localparam CS = LGCACHELEN; // Number of bits in a cache address
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localparam LS = CS-LGNLINES; // Bits to spec position w/in cline
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localparam LGAUX = 3; // log_2 of the maximum number of piped data
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input i_clk, i_rst;
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// Interface from the CPU
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input i_pipe_stb, i_lock;
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input i_op;
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input [31:0] i_addr;
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input [31:0] i_data;
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input [(NAUX-1):0] i_oreg; // Aux data, such as reg to write to
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// Outputs, going back to the CPU
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output wire o_busy, o_pipe_stalled, o_valid, o_err;
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output reg [(NAUX-1):0] o_wreg;
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output reg [31:0] o_data;
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// Wishbone bus master outputs
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output wire o_wb_cyc_gbl, o_wb_cyc_lcl;
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output reg o_wb_stb_gbl, o_wb_stb_lcl;
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output reg o_wb_we;
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output reg [(AW-1):0] o_wb_addr;
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output reg [31:0] o_wb_data;
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// Wishbone bus slave response inputs
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input i_wb_ack, i_wb_stall, i_wb_err;
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input [31:0] i_wb_data;
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reg cyc, stb, last_ack, end_of_line, last_line_stb;
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reg [((1<<LGNLINES)-1):0] c_v; // One bit per cache line, is it valid?
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reg [(AW-LS-1):0] c_vtags [0:((1<<LGNLINES)-1)];
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reg [31:0] c_mem [0:((1<<CS)-1)];
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// reg [((1<<LGNLINES)-1):0] c_wr; // Is the cache line writable?
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// reg c_wdata;
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// reg c_waddr;
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// To simplify writing to the cache, and the job of the synthesizer to
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// recognize that a cache write needs to take place, we'll take an extra
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// clock to get there, and use these c_w... registers to capture the
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// data in the meantime.
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reg c_wr;
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reg [31:0] c_wdata;
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reg [(CS-1):0] c_waddr;
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reg [(AW-LS-1):0] last_tag;
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wire [(LGNLINES-1):0] i_cline;
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wire [(CS-1):0] i_caddr;
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wire [(AW-LS-1):0] i_ctag;
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assign i_cline = i_addr[(CS-1):LS];
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assign i_caddr = i_addr[(CS-1):0];
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assign i_ctag = i_addr[(AW-1):LS];
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wire cache_miss_inow, w_cachable;
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assign cache_miss_inow = (last_tag != i_addr[31:LS])||(!c_v[i_cline]);
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assign w_cachable = (i_addr[31:30]!=2'b11)&&(!i_lock)&&(
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((SDRAM_BIT>0)&&(i_addr[SDRAM_BIT]))
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||((FLASH_BIT>0)&&(i_addr[FLASH_BIT]))
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||((BLKRAM_BIT>0)&&(i_addr[BLKRAM_BIT])));
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reg r_cachable, r_svalid, r_dvalid, r_rd, r_cache_miss, r_rvalid;
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reg [(AW-1):0] r_addr;
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reg [31:0] r_idata, r_ddata, r_rdata;
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wire [(LGNLINES-1):0] r_cline;
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wire [(CS-1):0] r_caddr;
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wire [(AW-LS-1):0] r_ctag;
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assign r_cline = r_addr[(CS-1):LS];
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assign r_caddr = r_addr[(CS-1):0];
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assign r_ctag = r_addr[(AW-1):LS];
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reg wr_cstb, r_iv, pipeable_op, non_pipeable_op, in_cache;
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reg [(AW-LS-1):0] r_itag;
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//
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// The one-clock delayed read values from the cache.
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//
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initial r_rd = 1'b0;
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initial r_cachable = 1'b0;
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initial r_svalid = 1'b0;
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initial r_dvalid = 1'b0;
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always @(posedge i_clk)
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begin
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// The single clock path
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r_idata <= c_mem[i_addr[(CS-1):0]];
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// The valid for the single clock path
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// Only ... we need to wait if we are currently writing
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// to our cache.
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r_svalid<= (!i_op)&&(!cache_miss_inow)&&(w_cachable)
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&&(i_pipe_stb)&&(!c_wr)&&(!wr_cstb);
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//
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// The two clock in-cache path
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//
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// Some preliminaries that needed to be calculated on the first
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// clock
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if (!o_busy)
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begin
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r_iv <= c_v[i_cline];
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r_itag <= c_vtags[i_cline];
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r_addr <= i_addr;
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r_cachable <= (!i_op)&&(w_cachable)&&(i_pipe_stb);
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end else begin
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r_iv <= c_v[r_cline];
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r_itag <= c_vtags[r_cline];
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end
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// r_idata still contains the right answer
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r_rd <= (i_pipe_stb)&&(!i_op);
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r_ddata <= r_idata;
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// r_itag contains the tag we didn't have available to us on the
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// last clock, r_ctag is a bit select from r_addr containing a
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// one clock delayed address.
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r_dvalid <= (r_itag == r_ctag)&&(r_iv)&&(r_cachable);
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if ((r_itag == r_ctag)&&(r_iv)&&(r_cachable))
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last_tag <= r_ctag;
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// r_cache miss takes a clock cycle. It is only ever true for
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// something that should be cachable, but isn't in the cache.
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// A cache miss is only true _if_
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// 1. A read was requested
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// 2. It is for a cachable address, AND
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// 3. It isn't in the cache on the first read
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// or the second read
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// 4. The read hasn't yet started to get this address
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r_cache_miss <= ((!cyc)||(o_wb_we))&&(r_cachable)
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// One clock path -- miss
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&&(!r_svalid)
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// Two clock path -- misses as well
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&&(r_rd)&&(!r_svalid)
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&&((r_itag != r_ctag)||(!r_iv));
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r_rdata <= c_mem[r_addr[(CS-1):0]];
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r_rvalid<= ((i_wb_ack)&&(last_ack));
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end
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`define DC_IDLE 2'b00
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`define DC_WRITE 2'b01
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`define DC_READS 2'b10
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`define DC_READC 2'b11
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reg [1:0] state;
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reg [(AW-LS-1):0] wr_wtag, wr_vtag;
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reg [31:0] wr_data;
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reg [(CS-1):0] wr_addr;
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always @(posedge i_clk)
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begin
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// By default, update the cache from the write 1-clock ago
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c_wr <= (wr_cstb)&&(wr_wtag == wr_vtag);
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c_wdata <= wr_data;
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c_waddr <= wr_addr[(CS-1):0];
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wr_cstb <= 1'b0;
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wr_vtag <= c_vtags[o_wb_addr[(CS-LS-1):0]];
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wr_wtag <= o_wb_addr[(AW-LS-1):0];
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wr_data <= o_wb_data;
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wr_addr <= o_wb_addr[(CS-1):0];
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if (LS <= 1)
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end_of_line <= 1'b1;
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else
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end_of_line<=(cyc)&&((c_waddr[(LS-1):1]=={(LS-1){1'b1}})
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||((i_wb_ack)
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&&(c_waddr[(LS-1):0]=={{(LS-2){1'b1}},2'b01})));
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if (LS <= 1)
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last_line_stb <= 1'b1;
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else
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last_line_stb <= (stb)&&
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((o_wb_addr[(LS-1):1]=={(LS-1){1'b1}})
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||((!i_wb_stall)
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&&(o_wb_addr[(LS-1):0]
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=={{(LS-2){1'b1}},2'b01})));
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//
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if (state == `DC_IDLE)
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pipeable_op <= 1'b0;
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if (state == `DC_IDLE)
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non_pipeable_op <= 1'b0;
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if (state == `DC_IDLE)
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begin
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o_wb_we <= 1'b0;
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o_wb_data <= i_data;
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pipeable_op <= 1'b0;
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non_pipeable_op <= 1'b1;
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cyc <= 1'b0;
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stb <= 1'b0;
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r_wb_cyc_gbl <= 1'b0;
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r_wb_cyc_lcl <= 1'b0;
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o_wb_stb_gbl <= 1'b0;
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o_wb_stb_lcl <= 1'b0;
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in_cache <= (i_op)&&(w_cachable);
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if ((i_pipe_stb)&&(i_op))
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begin // Write operation
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state <= `DC_WRITE;
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o_wb_addr <= i_addr;
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o_wb_we <= 1'b1;
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pipeable_op <= 1'b1;
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cyc <= 1'b1;
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stb <= 1'b1;
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r_wb_cyc_gbl <= (i_addr[31:30]!=2'b11);
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r_wb_cyc_lcl <= (i_addr[31:30]==2'b11);
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o_wb_stb_gbl <= (i_addr[31:30]!=2'b11);
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o_wb_stb_lcl <= (i_addr[31:30]==2'b11);
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end else if (r_cache_miss)
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begin
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state <= `DC_READC;
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o_wb_addr <= { i_ctag, {(LS){1'b0}} };
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non_pipeable_op <= 1'b1;
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cyc <= 1'b1;
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stb <= 1'b1;
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| 307 |
|
|
r_wb_cyc_gbl <= 1'b1;
|
| 308 |
|
|
o_wb_stb_gbl <= 1'b1;
|
| 309 |
|
|
end else if ((i_pipe_stb)&&(!w_cachable))
|
| 310 |
|
|
begin // Read non-cachable memory area
|
| 311 |
|
|
state <= `DC_READS;
|
| 312 |
|
|
o_wb_addr <= i_addr;
|
| 313 |
|
|
pipeable_op <= 1'b1;
|
| 314 |
|
|
|
| 315 |
|
|
cyc <= 1'b1;
|
| 316 |
|
|
stb <= 1'b1;
|
| 317 |
|
|
r_wb_cyc_gbl <= (i_addr[31:30]!=2'b11);
|
| 318 |
|
|
r_wb_cyc_lcl <= (i_addr[31:30]==2'b11);
|
| 319 |
|
|
o_wb_stb_gbl <= (i_addr[31:30]!=2'b11);
|
| 320 |
|
|
o_wb_stb_lcl <= (i_addr[31:30]==2'b11);
|
| 321 |
|
|
end // else we stay idle
|
| 322 |
|
|
|
| 323 |
|
|
end else if (state == `DC_READC)
|
| 324 |
|
|
begin
|
| 325 |
|
|
// We enter here once we have committed to reading
|
| 326 |
|
|
// data into a cache line.
|
| 327 |
|
|
if ((stb)&&(!i_wb_stall))
|
| 328 |
|
|
begin
|
| 329 |
|
|
stb <= (!last_line_stb);
|
| 330 |
|
|
o_wb_stb_gbl <= (!last_line_stb);
|
| 331 |
|
|
o_wb_addr[(LS-1):0] <= o_wb_addr[(LS-1):0]+1'b1;
|
| 332 |
|
|
end
|
| 333 |
|
|
|
| 334 |
|
|
if(stb)
|
| 335 |
|
|
c_v[o_wb_addr[(CS-LS-1):0]] <= 1'b0;
|
| 336 |
|
|
|
| 337 |
|
|
c_wr <= (i_wb_ack);
|
| 338 |
|
|
c_wdata <= o_wb_data;
|
| 339 |
|
|
c_waddr <= ((c_wr)?(c_waddr+1'b1):c_waddr);
|
| 340 |
|
|
|
| 341 |
|
|
c_vtags[o_wb_addr[(CS-LS-1):0]]<= o_wb_addr[(AW-LS-1):0];
|
| 342 |
|
|
|
| 343 |
|
|
if (((i_wb_ack)&&(end_of_line))||(i_wb_err))
|
| 344 |
|
|
begin
|
| 345 |
|
|
state <= `DC_IDLE;
|
| 346 |
|
|
non_pipeable_op <= 1'b0;
|
| 347 |
|
|
cyc <= 1'b0;
|
| 348 |
|
|
r_wb_cyc_gbl <= 1'b0;
|
| 349 |
|
|
r_wb_cyc_lcl <= 1'b0;
|
| 350 |
|
|
//
|
| 351 |
|
|
c_v[o_wb_addr[(CS-LS-1):0]] <= i_wb_ack;
|
| 352 |
|
|
end
|
| 353 |
|
|
end else if (state == `DC_READS)
|
| 354 |
|
|
begin
|
| 355 |
|
|
// We enter here once we have committed to reading
|
| 356 |
|
|
// data that cannot go into a cache line
|
| 357 |
|
|
if ((!i_wb_stall)&&(!i_pipe_stb))
|
| 358 |
|
|
begin
|
| 359 |
|
|
stb <= 1'b0;
|
| 360 |
|
|
o_wb_stb_gbl <= 1'b0;
|
| 361 |
|
|
o_wb_stb_lcl <= 1'b0;
|
| 362 |
|
|
pipeable_op <= 1'b0;
|
| 363 |
|
|
end
|
| 364 |
|
|
|
| 365 |
|
|
if ((!i_wb_stall)&&(i_pipe_stb))
|
| 366 |
|
|
o_wb_addr <= i_data;
|
| 367 |
|
|
|
| 368 |
|
|
c_wr <= 1'b0;
|
| 369 |
|
|
|
| 370 |
|
|
if (((i_wb_ack)&&(last_ack))||(i_wb_err))
|
| 371 |
|
|
begin
|
| 372 |
|
|
state <= `DC_IDLE;
|
| 373 |
|
|
cyc <= 1'b0;
|
| 374 |
|
|
r_wb_cyc_gbl <= 1'b0;
|
| 375 |
|
|
r_wb_cyc_lcl <= 1'b0;
|
| 376 |
|
|
end
|
| 377 |
|
|
end else if (state == `DC_WRITE)
|
| 378 |
|
|
begin
|
| 379 |
|
|
// c_wr <= (c_v[])&&(c_tag[])&&(in_cache)&&(stb);
|
| 380 |
|
|
c_wdata <= o_wb_data;
|
| 381 |
|
|
c_waddr <= (state == `DC_IDLE)?i_caddr
|
| 382 |
|
|
: ((c_wr)?(c_waddr+1'b1):c_waddr);
|
| 383 |
|
|
|
| 384 |
|
|
if ((!i_wb_stall)&&(!i_pipe_stb))
|
| 385 |
|
|
begin
|
| 386 |
|
|
stb <= 1'b0;
|
| 387 |
|
|
o_wb_stb_gbl <= 1'b0;
|
| 388 |
|
|
o_wb_stb_lcl <= 1'b0;
|
| 389 |
|
|
pipeable_op <= 1'b0;
|
| 390 |
|
|
end
|
| 391 |
|
|
|
| 392 |
|
|
wr_cstb <= (stb)&&(!i_wb_stall)&&(in_cache);
|
| 393 |
|
|
|
| 394 |
|
|
if ((stb)&&(!i_wb_stall)&&(i_pipe_stb))
|
| 395 |
|
|
o_wb_addr <= i_addr;
|
| 396 |
|
|
if ((stb)&&(!i_wb_stall)&&(i_pipe_stb))
|
| 397 |
|
|
o_wb_data <= i_data;
|
| 398 |
|
|
|
| 399 |
|
|
if (((i_wb_ack)&&(last_ack))||(i_wb_err))
|
| 400 |
|
|
begin
|
| 401 |
|
|
state <= `DC_IDLE;
|
| 402 |
|
|
cyc <= 1'b0;
|
| 403 |
|
|
r_wb_cyc_gbl <= 1'b0;
|
| 404 |
|
|
r_wb_cyc_lcl <= 1'b0;
|
| 405 |
|
|
end
|
| 406 |
|
|
end
|
| 407 |
|
|
end
|
| 408 |
|
|
|
| 409 |
|
|
//
|
| 410 |
|
|
// Writes to the cache
|
| 411 |
|
|
//
|
| 412 |
|
|
// These have been made as simple as possible. Note that the c_wr
|
| 413 |
|
|
// line has already been determined, as have the write value and address
|
| 414 |
|
|
// on the last clock. Further, this structure is defined to match the
|
| 415 |
|
|
// block RAM design of as many architectures as possible.
|
| 416 |
|
|
//
|
| 417 |
|
|
always @(posedge i_clk)
|
| 418 |
|
|
if (c_wr)
|
| 419 |
|
|
c_mem[c_waddr] <= c_wdata;
|
| 420 |
|
|
|
| 421 |
|
|
//
|
| 422 |
|
|
// Reads from the cache
|
| 423 |
|
|
//
|
| 424 |
|
|
// Some architectures require that all reads be registered. We
|
| 425 |
|
|
// accomplish that here. Whether or not the result of this read is
|
| 426 |
|
|
// going to be our output will need to be determined with combinatorial
|
| 427 |
|
|
// logic on the output.
|
| 428 |
|
|
//
|
| 429 |
|
|
reg [31:0] cached_idata, cached_rdata;
|
| 430 |
|
|
always @(posedge i_clk)
|
| 431 |
|
|
cached_idata <= c_mem[i_caddr];
|
| 432 |
|
|
|
| 433 |
|
|
always @(posedge i_clk)
|
| 434 |
|
|
cached_rdata <= c_mem[r_caddr];
|
| 435 |
|
|
|
| 436 |
|
|
// o_data can come from one of three places:
|
| 437 |
|
|
// 1. The cache, assuming the data was in the last cache line
|
| 438 |
|
|
// 2. The cache, second clock, assuming the data was in the cache at all
|
| 439 |
|
|
// 3. The cache, after filling the cache
|
| 440 |
|
|
// 4. The wishbone state machine, upon reading the value desired.
|
| 441 |
|
|
always @(posedge i_clk)
|
| 442 |
|
|
if (r_svalid)
|
| 443 |
|
|
o_data <= cached_idata;
|
| 444 |
|
|
else if ((i_wb_ack)&&(pipeable_op))
|
| 445 |
|
|
o_data <= i_wb_data;
|
| 446 |
|
|
else
|
| 447 |
|
|
o_data <= cached_rdata;
|
| 448 |
|
|
always @(posedge i_clk)
|
| 449 |
|
|
o_valid <= (r_svalid)||((i_wb_ack)&&(pipeable_op))
|
| 450 |
|
|
||(r_dvalid)||(r_rvalid);
|
| 451 |
|
|
always @(posedge i_clk)
|
| 452 |
|
|
o_err <= (cyc)&&(i_wb_err);
|
| 453 |
|
|
|
| 454 |
|
|
assign o_busy = (state != `DC_IDLE);
|
| 455 |
|
|
|
| 456 |
|
|
|
| 457 |
|
|
//
|
| 458 |
|
|
// Handle our auxilliary data lines.
|
| 459 |
|
|
//
|
| 460 |
|
|
// These just go into a FIFO upon request, and then get fed back out
|
| 461 |
|
|
// upon completion of an OP.
|
| 462 |
|
|
//
|
| 463 |
|
|
// These are currently designed for handling bursts of writes or
|
| 464 |
|
|
// non-cachable reads.
|
| 465 |
|
|
//
|
| 466 |
|
|
// A very similar structure will be used once we switch to using an
|
| 467 |
|
|
// MMU, in order to make certain memory operations are synchronous
|
| 468 |
|
|
// enough to deal with bus errors.
|
| 469 |
|
|
//
|
| 470 |
|
|
reg [(LGAUX-1):0] aux_head, aux_tail;
|
| 471 |
|
|
reg [(NAUX-1):0] aux_fifo [0:((1<<LGAUX)-1)];
|
| 472 |
|
|
initial aux_head = 0;
|
| 473 |
|
|
initial aux_tail = 0;
|
| 474 |
|
|
always @(posedge i_clk)
|
| 475 |
|
|
begin
|
| 476 |
|
|
if ((i_rst)||(i_wb_err))
|
| 477 |
|
|
aux_head <= 0;
|
| 478 |
|
|
else if ((i_pipe_stb)&&(!o_busy))
|
| 479 |
|
|
aux_head <= aux_head + 1'b1;
|
| 480 |
|
|
aux_fifo[aux_head] <= i_oreg;
|
| 481 |
|
|
end
|
| 482 |
|
|
always @(posedge i_clk)
|
| 483 |
|
|
begin
|
| 484 |
|
|
if ((i_rst)||(i_wb_err))
|
| 485 |
|
|
aux_tail <= 0;
|
| 486 |
|
|
else if (o_valid) // ||(aux_tail[WBIT])&&(no-mmu-error)
|
| 487 |
|
|
aux_tail <= aux_tail + 1'b1;
|
| 488 |
|
|
o_wreg <= aux_fifo[aux_tail];
|
| 489 |
|
|
end
|
| 490 |
|
|
|
| 491 |
|
|
//
|
| 492 |
|
|
// We can use our FIFO addresses to pre-calculate when an ACK is going
|
| 493 |
|
|
// to be the last_noncachable_ack.
|
| 494 |
|
|
|
| 495 |
|
|
|
| 496 |
|
|
assign o_pipe_stalled=((pipeable_op)&&(i_wb_stall))||(non_pipeable_op);
|
| 497 |
|
|
// pipeable_op must become zero when stb goes low
|
| 498 |
|
|
|
| 499 |
|
|
always @(posedge i_clk)
|
| 500 |
|
|
begin
|
| 501 |
|
|
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
|
| 502 |
|
|
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl));
|
| 503 |
|
|
end
|
| 504 |
|
|
|
| 505 |
|
|
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
|
| 506 |
|
|
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
|
| 507 |
|
|
endmodule
|
