URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [div.v] - Blame information for rev 196

Go to most recent revision | Details | Compare with Previous | View Log


///////////////////////////////////////////////////////////////////////////////
//
// Filename:    div.v
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:     Provide an Integer divide capability to the Zip CPU.
//
//
// Creator:     Dan Gisselquist, Ph.D.
//              Gisselquist Technology, LLC
//
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////////
//
// `include "cpudefs.v"
//
module  div(i_clk, i_rst, i_wr, i_signed, i_numerator, i_denominator,
                o_busy, o_valid, o_err, o_quotient, o_flags);
        parameter               BW=32, LGBW = 5;
        input                   i_clk, i_rst;
        // Input parameters
        input                   i_wr, i_signed;
        input   [(BW-1):0]       i_numerator, i_denominator;
        // Output parameters
        output  reg             o_busy, o_valid, o_err;
        output  reg [(BW-1):0]   o_quotient;
        output  wire    [3:0]    o_flags;
 
        // r_busy is an internal busy register.  It will clear one clock
        // before we are valid, so it can't be o_busy ...
        //
        reg                     r_busy;
        reg     [(2*BW-2):0]     r_divisor;
        reg     [(BW-1):0]       r_dividend;
        wire    [(BW):0] diff; // , xdiff[(BW-1):0];
        assign  diff = r_dividend - r_divisor[(BW-1):0];
        // assign       xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };
 
        reg             r_sign, pre_sign, r_z, r_c, last_bit;
        reg     [(LGBW-1):0]     r_bit;
 
        reg     zero_divisor;
        initial zero_divisor = 1'b0;
        always @(posedge i_clk)
                zero_divisor <= (r_divisor == 0)&&(r_busy);
 
        initial r_busy = 1'b0;
        always @(posedge i_clk)
                if (i_rst)
                        r_busy <= 1'b0;
                else if (i_wr)
                        r_busy <= 1'b1;
                else if ((last_bit)||(zero_divisor))
                        r_busy <= 1'b0;
 
        initial o_busy = 1'b0;
        always @(posedge i_clk)
                if (i_rst)
                        o_busy <= 1'b0;
                else if (i_wr)
                        o_busy <= 1'b1;
                else if (((last_bit)&&(~r_sign))||(zero_divisor))
                        o_busy <= 1'b0;
                else if (~r_busy)
                        o_busy <= 1'b0;
 
        always @(posedge i_clk)
                if ((i_rst)||(i_wr))
                        o_valid <= 1'b0;
                else if (r_busy)
                begin
                        if ((last_bit)||(zero_divisor))
                                o_valid <= (zero_divisor)||(~r_sign);
                end else if (r_sign)
                begin
                        o_valid <= (~zero_divisor); // 1'b1;
                end else
                        o_valid <= 1'b0;
 
        initial o_err = 1'b0;
        always @(posedge i_clk)
                if((i_rst)||(o_valid))
                        o_err <= 1'b0;
                else if (((r_busy)||(r_sign))&&(zero_divisor))
                        o_err <= 1'b1;
                else
                        o_err <= 1'b0;
 
        initial last_bit = 1'b0;
        always @(posedge i_clk)
                if ((i_wr)||(pre_sign)||(i_rst))
                        last_bit <= 1'b0;
                else if (r_busy)
                        last_bit <= (r_bit == {{(LGBW-1){1'b0}},1'b1});
 
        always @(posedge i_clk)
                // if (i_rst) r_busy <= 1'b0;
                // else
                if (i_wr)
                begin
                        //
                        // Set our values upon an initial command.  Here's
                        // where we come in and start.
                        //
                        // r_busy <= 1'b1;
                        //
                        o_quotient <= 0;
                        r_bit <= {(LGBW){1'b1}};
                        r_divisor <= {  i_denominator, {(BW-1){1'b0}} };
                        r_dividend <=  i_numerator;
                        r_sign <= 1'b0;
                        pre_sign <= i_signed;
                        r_z <= 1'b1;
                end else if (pre_sign)
                begin
                        //
                        // Note that we only come in here, for one clock, if
                        // our initial value may have been signed.  If we are
                        // doing an unsigned divide, we then skip this step.
                        //
                        r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));
                        // Negate our dividend if necessary so that it becomes
                        // a magnitude only value
                        if (r_dividend[BW-1])
                                r_dividend <= -r_dividend;
                        // Do the same with the divisor--rendering it into
                        // a magnitude only.
                        if (r_divisor[(2*BW-2)])
                                r_divisor[(2*BW-2):(BW-1)] <= -r_divisor[(2*BW-2):(BW-1)];
                        //
                        // We only do this stage for a single clock, so go on
                        // with the rest of the divide otherwise.
                        pre_sign <= 1'b0;
                end else if (r_busy)
                begin
                        // While the divide is taking place, we examine each bit
                        // in turn here.
                        //
                        r_bit <= r_bit + {(LGBW){1'b1}}; // r_bit = r_bit - 1;
                        r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };
                        if (|r_divisor[(2*BW-2):(BW)])
                        begin
                        end else if (diff[BW])
                        begin
                                // 
                                // diff = r_dividend - r_divisor[(BW-1):0];
                                //
                                // If this value was negative, there wasn't
                                // enough value in the dividend to support
                                // pulling off a bit.  We'll move down a bit
                                // therefore and try again.
                                //
                        end else begin
                                //
                                // Put a '1' into our output accumulator.
                                // Subtract the divisor from the dividend,
                                // and then move on to the next bit
                                //
                                r_dividend <= diff[(BW-1):0];
                                o_quotient[r_bit[(LGBW-1):0]] <= 1'b1;
                                r_z <= 1'b0;
                        end
                        r_sign <= (r_sign)&&(~zero_divisor);
                end else if (r_sign)
                begin
                        r_sign <= 1'b0;
                        o_quotient <= -o_quotient;
                end
 
        // Set Carry on an exact divide
        wire    w_n;
        always @(posedge i_clk)
                r_c <= (r_busy)&&((diff == 0)||(r_dividend == 0));
        assign w_n = o_quotient[(BW-1)];
 
        assign o_flags = { 1'b0, w_n, r_c, r_z };
endmodule

Line No.	Rev	Author	Line
1	69	dgisselq	`///////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`// Filename: div.v`
4			`//`
5			`// Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
6			`//`
7			`// Purpose: Provide an Integer divide capability to the Zip CPU.`
8			`//`
9			`//`
10			`// Creator: Dan Gisselquist, Ph.D.`
11			`// Gisselquist Technology, LLC`
12			`//`
13			`///////////////////////////////////////////////////////////////////////////////`
14			`//`
15	160	dgisselq	`// Copyright (C) 2015-2016, Gisselquist Technology, LLC`
16	69	dgisselq	`//`
17			`// This program is free software (firmware): you can redistribute it and/or`
18			`// modify it under the terms of the GNU General Public License as published`
19			`// by the Free Software Foundation, either version 3 of the License, or (at`
20			`// your option) any later version.`
21			`//`
22			`// This program is distributed in the hope that it will be useful, but WITHOUT`
23			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
24			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
25			`// for more details.`
26			`//`
27			`// License: GPL, v3, as defined and found on www.gnu.org,`
28			`// http://www.gnu.org/licenses/gpl.html`
29			`//`
30			`//`
31			`///////////////////////////////////////////////////////////////////////////////`
32			`//`
33			// `include "cpudefs.v"
34			`//`
35			`module div(i_clk, i_rst, i_wr, i_signed, i_numerator, i_denominator,`
36			`o_busy, o_valid, o_err, o_quotient, o_flags);`
37	196	dgisselq	`parameter BW=32, LGBW = 5;`
38			`input i_clk, i_rst;`
39	69	dgisselq	`// Input parameters`
40			`input i_wr, i_signed;`
41			`input [(BW-1):0] i_numerator, i_denominator;`
42			`// Output parameters`
43			`output reg o_busy, o_valid, o_err;`
44			`output reg [(BW-1):0] o_quotient;`
45			`output wire [3:0] o_flags;`
46
47	160	dgisselq	`// r_busy is an internal busy register. It will clear one clock`
48			`// before we are valid, so it can't be o_busy ...`
49			`//`
50			`reg r_busy;`
51	69	dgisselq	`reg [(2*BW-2):0] r_divisor;`
52			`reg [(BW-1):0] r_dividend;`
53			`wire [(BW):0] diff; // , xdiff[(BW-1):0];`
54			`assign diff = r_dividend - r_divisor[(BW-1):0];`
55			`// assign xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };`
56
57	160	dgisselq	`reg r_sign, pre_sign, r_z, r_c, last_bit;`
58			`reg [(LGBW-1):0] r_bit;`
59	69	dgisselq
60	174	dgisselq	`reg zero_divisor;`
61			`initial zero_divisor = 1'b0;`
62			`always @(posedge i_clk)`
63			`zero_divisor <= (r_divisor == 0)&&(r_busy);`
64
65	160	dgisselq	`initial r_busy = 1'b0;`
66	69	dgisselq	`always @(posedge i_clk)`
67			`if (i_rst)`
68	160	dgisselq	`r_busy <= 1'b0;`
69			`else if (i_wr)`
70			`r_busy <= 1'b1;`
71	174	dgisselq	`else if ((last_bit)\|\|(zero_divisor))`
72	160	dgisselq	`r_busy <= 1'b0;`
73
74			`initial o_busy = 1'b0;`
75			`always @(posedge i_clk)`
76			`if (i_rst)`
77	69	dgisselq	`o_busy <= 1'b0;`
78	160	dgisselq	`else if (i_wr)`
79	69	dgisselq	`o_busy <= 1'b1;`
80	174	dgisselq	`else if (((last_bit)&&(~r_sign))\|\|(zero_divisor))`
81	88	dgisselq	`o_busy <= 1'b0;`
82	160	dgisselq	`else if (~r_busy)`
83			`o_busy <= 1'b0;`
84	88	dgisselq
85			`always @(posedge i_clk)`
86			`if ((i_rst)\|\|(i_wr))`
87	69	dgisselq	`o_valid <= 1'b0;`
88	160	dgisselq	`else if (r_busy)`
89	69	dgisselq	`begin`
90	174	dgisselq	`if ((last_bit)\|\|(zero_divisor))`
91			`o_valid <= (zero_divisor)\|\|(~r_sign);`
92	69	dgisselq	`end else if (r_sign)`
93			`begin`
94	174	dgisselq	`o_valid <= (~zero_divisor); // 1'b1;`
95	88	dgisselq	`end else`
96	69	dgisselq	`o_valid <= 1'b0;`
97
98	174	dgisselq	`initial o_err = 1'b0;`
99	69	dgisselq	`always @(posedge i_clk)`
100			`if((i_rst)\|\|(o_valid))`
101			`o_err <= 1'b0;`
102	174	dgisselq	`else if (((r_busy)\|\|(r_sign))&&(zero_divisor))`
103			`o_err <= 1'b1;`
104			`else`
105			`o_err <= 1'b0;`
106	69	dgisselq
107	160	dgisselq	`initial last_bit = 1'b0;`
108	69	dgisselq	`always @(posedge i_clk)`
109	160	dgisselq	`if ((i_wr)\|\|(pre_sign)\|\|(i_rst))`
110			`last_bit <= 1'b0;`
111			`else if (r_busy)`
112			`last_bit <= (r_bit == {{(LGBW-1){1'b0}},1'b1});`
113
114			`always @(posedge i_clk)`
115			`// if (i_rst) r_busy <= 1'b0;`
116			`// else`
117	69	dgisselq	`if (i_wr)`
118			`begin`
119	160	dgisselq	`//`
120			`// Set our values upon an initial command. Here's`
121			`// where we come in and start.`
122			`//`
123			`// r_busy <= 1'b1;`
124			`//`
125	69	dgisselq	`o_quotient <= 0;`
126	160	dgisselq	`r_bit <= {(LGBW){1'b1}};`
127	69	dgisselq	`r_divisor <= { i_denominator, {(BW-1){1'b0}} };`
128			`r_dividend <= i_numerator;`
129			`r_sign <= 1'b0;`
130			`pre_sign <= i_signed;`
131			`r_z <= 1'b1;`
132			`end else if (pre_sign)`
133			`begin`
134	160	dgisselq	`//`
135			`// Note that we only come in here, for one clock, if`
136			`// our initial value may have been signed. If we are`
137			`// doing an unsigned divide, we then skip this step.`
138			`//`
139			`r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));`
140			`// Negate our dividend if necessary so that it becomes`
141			`// a magnitude only value`
142	69	dgisselq	`if (r_dividend[BW-1])`
143			`r_dividend <= -r_dividend;`
144	160	dgisselq	`// Do the same with the divisor--rendering it into`
145			`// a magnitude only.`
146	69	dgisselq	`if (r_divisor[(2*BW-2)])`
147			`r_divisor[(2BW-2):(BW-1)] <= -r_divisor[(2BW-2):(BW-1)];`
148	160	dgisselq	`//`
149			`// We only do this stage for a single clock, so go on`
150			`// with the rest of the divide otherwise.`
151	69	dgisselq	`pre_sign <= 1'b0;`
152	160	dgisselq	`end else if (r_busy)`
153	69	dgisselq	`begin`
154	160	dgisselq	`// While the divide is taking place, we examine each bit`
155			`// in turn here.`
156			`//`
157			`r_bit <= r_bit + {(LGBW){1'b1}}; // r_bit = r_bit - 1;`
158	69	dgisselq	`r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };`
159			`if (\|r_divisor[(2*BW-2):(BW)])`
160			`begin`
161			`end else if (diff[BW])`
162			`begin`
163	160	dgisselq	`//`
164			`// diff = r_dividend - r_divisor[(BW-1):0];`
165			`//`
166			`// If this value was negative, there wasn't`
167			`// enough value in the dividend to support`
168			`// pulling off a bit. We'll move down a bit`
169			`// therefore and try again.`
170			`//`
171	69	dgisselq	`end else begin`
172	160	dgisselq	`//`
173			`// Put a '1' into our output accumulator.`
174			`// Subtract the divisor from the dividend,`
175			`// and then move on to the next bit`
176			`//`
177	69	dgisselq	`r_dividend <= diff[(BW-1):0];`
178			`o_quotient[r_bit[(LGBW-1):0]] <= 1'b1;`
179			`r_z <= 1'b0;`
180			`end`
181	174	dgisselq	`r_sign <= (r_sign)&&(~zero_divisor);`
182	69	dgisselq	`end else if (r_sign)`
183			`begin`
184			`r_sign <= 1'b0;`
185			`o_quotient <= -o_quotient;`
186			`end`
187
188			`// Set Carry on an exact divide`
189			`wire w_n;`
190			`always @(posedge i_clk)`
191	160	dgisselq	`r_c <= (r_busy)&&((diff == 0)\|\|(r_dividend == 0));`
192	69	dgisselq	`assign w_n = o_quotient[(BW-1)];`
193
194			`assign o_flags = { 1'b0, w_n, r_c, r_z };`
195			`endmodule`

Browse

Tools

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [div.v] - Blame information for rev 196