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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    div.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     Provide an Integer divide capability to the Zip CPU.  Provides
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//              for both signed and unsigned divide.
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//
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// Steps:
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//      i_rst   The DIVide unit starts in idle.  It can also be placed into an
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//      idle by asserting the reset input.
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//
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//      i_wr    When i_rst is asserted, a divide begins.  On the next clock:
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//
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//        o_busy is set high so everyone else knows we are at work and they can
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//              wait for us to complete.
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//
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//        pre_sign is set to true if we need to do a signed divide.  In this
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//              case, we take a clock cycle to turn the divide into an unsigned
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//              divide.
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//
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//        o_quotient, a place to store our result, is initialized to all zeros.
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//
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//        r_dividend is set to the numerator
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//
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//        r_divisor is set to 2^31 * the denominator (shift left by 31, or add
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//              31 zeros to the right of the number.
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//
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//      pre_sign When true (clock cycle after i_wr), a clock cycle is used
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//              to take the absolute value of the various arguments (r_dividend
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//              and r_divisor), and to calculate what sign the output result
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//              should be.
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//
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//
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//      At this point, the divide is has started.  The divide works by walking
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//      through every shift of the
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//
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//                  DIVIDEND    over the
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//              DIVISOR
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//
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//      If the DIVISOR is bigger than the dividend, the divisor is shifted
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//      right, and nothing is done to the output quotient.
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//
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//                  DIVIDEND
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//               DIVISOR
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//
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//      This repeats, until DIVISOR is less than or equal to the divident, as in
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//
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//              DIVIDEND
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//              DIVISOR
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//
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//      At this point, if the DIVISOR is less than the dividend, the
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//      divisor is subtracted from the dividend, and the DIVISOR is again
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//      shifted to the right.  Further, a '1' bit gets set in the output
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//      quotient.
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//
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//      Once we've done this for 32 clocks, we've accumulated our answer into
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//      the output quotient, and we can proceed to the next step.  If the
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//      result will be signed, the next step negates the quotient, otherwise
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//      it returns the result.
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//
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//      On the clock when we are done, o_busy is set to false, and o_valid set
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//      to true.  (It is a violation of the ZipCPU internal protocol for both
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//      busy and valid to ever be true on the same clock.  It is also a
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//      violation for busy to be false with valid true thereafter.)
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// `include "cpudefs.v"
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//
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module  div(i_clk, i_rst, i_wr, i_signed, i_numerator, i_denominator,
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                o_busy, o_valid, o_err, o_quotient, o_flags);
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        parameter               BW=32, LGBW = 5;
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        input                   i_clk, i_rst;
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        // Input parameters
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        input                   i_wr, i_signed;
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        input   [(BW-1):0]       i_numerator, i_denominator;
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        // Output parameters
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        output  reg             o_busy, o_valid, o_err;
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        output  reg [(BW-1):0]   o_quotient;
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        output  wire    [3:0]    o_flags;
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        // r_busy is an internal busy register.  It will clear one clock
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        // before we are valid, so it can't be o_busy ...
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        //
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        reg                     r_busy;
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        reg     [(2*BW-2):0]     r_divisor;
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        reg     [(BW-1):0]       r_dividend;
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        wire    [(BW):0] diff; // , xdiff[(BW-1):0];
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        assign  diff = r_dividend - r_divisor[(BW-1):0];
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        // assign       xdiff= r_dividend - { 1'b0, r_divisor[(BW-1):1] };
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        reg             r_sign, pre_sign, r_z, r_c, last_bit;
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        reg     [(LGBW-1):0]     r_bit;
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        reg     zero_divisor;
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        // The Divide logic begins with r_busy.  We use r_busy to determine
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        // whether or not the divide is in progress, vs being complete.
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        // Here, we clear r_busy on any reset and set it on i_wr (the request
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        // do to a divide).  The divide ends when we are on the last bit,
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        // or equivalently when we discover we are dividing by zero.
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        initial r_busy = 1'b0;
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        always @(posedge i_clk)
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                if (i_rst)
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                        r_busy <= 1'b0;
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                else if (i_wr)
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                        r_busy <= 1'b1;
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                else if ((last_bit)||(zero_divisor))
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                        r_busy <= 1'b0;
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        // o_busy is very similar to r_busy, save for some key differences.
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        // Primary among them is that o_busy needs to (possibly) be true
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        // for an extra clock after r_busy clears.  This would be that extra
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        // clock where we negate the result (assuming a signed divide, and that
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        // the result is supposed to be negative.)  Otherwise, the two are
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        // identical.
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        initial o_busy = 1'b0;
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        always @(posedge i_clk)
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                if (i_rst)
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                        o_busy <= 1'b0;
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                else if (i_wr)
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                        o_busy <= 1'b1;
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                else if (((last_bit)&&(~r_sign))||(zero_divisor))
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                        o_busy <= 1'b0;
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                else if (~r_busy)
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                        o_busy <= 1'b0;
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        // If we are asked to divide by zero, we need to halt.  The sooner
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        // we halt and report the error, the better.  Hence, here we look
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        // for a zero divisor while being busy.  The always above us will then
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        // look at this and halt a divide in the middle if we are trying to
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        // divide by zero.
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        //
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        // Note that this works off of the 2BW-1 length vector.  If we can
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        // simplify that, it should simplify our logic as well.
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        initial zero_divisor = 1'b0;
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        always @(posedge i_clk)
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                // zero_divisor <= (r_divisor == 0)&&(r_busy);
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                if (i_rst)
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                        zero_divisor <= 1'b0;
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                else if (i_wr)
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                        zero_divisor <= (i_denominator == 0);
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                else if (!r_busy)
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                        zero_divisor <= 1'b0;
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        // o_valid is part of the ZipCPU protocol.  It will be set to true
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        // anytime our answer is valid and may be used by the calling module.
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        // Indeed, the ZipCPU will halt (and ignore us) once the i_wr has been
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        // set until o_valid gets set.
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        //
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        // Here, we clear o_valid on a reset, and any time we are on the last
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        // bit while busy (provided the sign is zero, or we are dividing by
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        // zero).  Since o_valid is self-clearing, we don't need to clear
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        // it on an i_wr signal.
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        initial o_valid = 1'b0;
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        always @(posedge i_clk)
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                if (i_rst)
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                        o_valid <= 1'b0;
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                else if (r_busy)
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                begin
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                        if ((last_bit)||(zero_divisor))
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                                o_valid <= (zero_divisor)||(!r_sign);
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                end else if (r_sign)
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                begin
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                        o_valid <= (!zero_divisor); // 1'b1;
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                end else
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                        o_valid <= 1'b0;
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        // Division by zero error reporting.  Anytime we detect a zero divisor,
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        // we set our output error, and then hold it until we are valid and
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        // everything clears.
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        initial o_err = 1'b0;
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        always @(posedge i_clk)
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                if((i_rst)||(o_valid))
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                        o_err <= 1'b0;
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                else if (((r_busy)||(r_sign))&&(zero_divisor))
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                        o_err <= 1'b1;
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                else
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                        o_err <= 1'b0;
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        // r_bit
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        //
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        // Keep track of which "bit" of our divide we are on.  This number
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        // ranges from 31 down to zero.  On any write, we set ourselves to
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        // 5'h1f.  Otherwise, while we are busy (but not within the pre-sign
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        // adjustment stage), we subtract one from our value on every clock.
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        always @(posedge i_clk)
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                if ((r_busy)&&(!pre_sign))
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                        r_bit <= r_bit + {(LGBW){1'b1}};
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                else
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                        r_bit <= {(LGBW){1'b1}};
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        // last_bit
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        //
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        // This logic replaces a lot of logic that was inside our giant state
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        // machine with ... something simpler.  In particular, we'll use this
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        // logic to determine we are processing our last bit.  The only trick
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        // is, this bit needs to be set whenever (r_busy) and (r_bit == 0),
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        // hence we need to set on (r_busy) and (r_bit == 1) so as to be set
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        // when (r_bit == 0).
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        initial last_bit = 1'b0;
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        always @(posedge i_clk)
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                if (r_busy)
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                        last_bit <= (r_bit == {{(LGBW-1){1'b0}},1'b1});
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                else
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                        last_bit <= 1'b0;
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        // pre_sign
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        //
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        // This is part of the state machine.  pre_sign indicates that we need
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        // a extra clock to take the absolute value of our inputs.  It need only
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        // be true for the one clock, and then it must clear itself.
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        initial pre_sign = 1'b0;
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        always @(posedge i_clk)
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                if (i_wr)
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                        pre_sign <= i_signed;
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                else
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                        pre_sign <= 1'b0;
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        // As a result of our operation, we need to set the flags.  The most
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        // difficult of these is the "Z" flag indicating that the result is
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        // zero.  Here, we'll use the same logic that sets the low-order
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        // bit to clear our zero flag, and leave the zero flag set in all
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        // other cases.  Well ... not quite.  If we need to flip the sign of
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        // our value, then we can't quite clear the zero flag ... yet.
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        always @(posedge i_clk)
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                if((r_busy)&&(r_divisor[(2*BW-2):(BW)] == 0)&&(!diff[BW]))
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                        // If we are busy, the upper bits of our divisor are
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                        // zero (i.e., we got the shift right), and the top
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                        // (carry) bit of the difference is zero (no overflow),
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                        // then we could subtract our divisor from our dividend
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                        // and hence we add a '1' to the quotient, while setting
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                        // the zero flag to false.
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                        r_z <= 1'b0;
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                else if ((!r_busy)&&(!r_sign))
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                        r_z <= 1'b1;
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        // r_dividend
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        // This is initially the numerator.  On a signed divide, it then becomes
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        // the absolute value of the numerator.  We'll subtract from this value
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        // the divisor shifted as appropriate for every output bit we are
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        // looking for--just as with traditional long division.
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        always @(posedge i_clk)
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                if (pre_sign)
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                begin
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                        // If we are doing a signed divide, then take the
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                        // absolute value of the dividend
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                        if (r_dividend[BW-1])
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                                r_dividend <= -r_dividend;
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                        // The begin/end block is important so we don't lose
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                        // the fact that on an else we don't do anything.
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                end else if((r_busy)&&(r_divisor[(2*BW-2):(BW)]==0)&&(!diff[BW]))
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                        // This is the condition whereby we set a '1' in our
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                        // output quotient, and we subtract the (current)
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                        // divisor from our dividend.  (The difference is
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                        // already kept in the diff vector above.)
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                        r_dividend <= diff[(BW-1):0];
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                else if (!r_busy)
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                        // Once we are done, and r_busy is no longer high, we'll
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                        // always accept new values into our dividend.  This
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                        // guarantees that, when i_wr is set, the new value
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                        // is already set as desired.
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                        r_dividend <=  i_numerator;
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        initial r_divisor = 0;
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        always @(posedge i_clk)
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                if (pre_sign)
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                begin
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                        if (r_divisor[(2*BW-2)])
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                                r_divisor[(2*BW-2):(BW-1)]
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                                        <= -r_divisor[(2*BW-2):(BW-1)];
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                end else if (r_busy)
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                        r_divisor <= { 1'b0, r_divisor[(2*BW-2):1] };
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                else
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                        r_divisor <= {  i_denominator, {(BW-1){1'b0}} };
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        // r_sign
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        // is a flag for our state machine control(s).  r_sign will be set to
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        // true any time we are doing a signed divide and the result must be
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        // negative.  In that case, we take a final logic stage at the end of
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        // the divide to negate the output.  This flag is what tells us we need
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        // to do that.  r_busy will be true during the divide, then when r_busy
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        // goes low, r_sign will be checked, then the idle/reset stage will have
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        // been reached.  For this reason, we cannot set r_sign unless we are
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        // up to something.
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        initial r_sign = 1'b0;
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        always @(posedge i_clk)
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                if (pre_sign)
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                        r_sign <= ((r_divisor[(2*BW-2)])^(r_dividend[(BW-1)]));
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                else if (r_busy)
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                        r_sign <= (r_sign)&&(!zero_divisor);
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                else
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                        r_sign <= 1'b0;
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        always @(posedge i_clk)
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                if (r_busy)
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                begin
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                        o_quotient <= { o_quotient[(BW-2):0], 1'b0 };
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                        if ((r_divisor[(2*BW-2):(BW)] == 0)&&(!diff[BW]))
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                        begin
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                                o_quotient[0] <= 1'b1;
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                        end
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                end else if (r_sign)
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                        o_quotient <= -o_quotient;
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                else
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                        o_quotient <= 0;
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        // Set Carry on an exact divide
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        // Perhaps nothing uses this, but ... well, I suppose we could remove
339
        // this logic eventually, just ... not yet.
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        always @(posedge i_clk)
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                r_c <= (r_busy)&&((diff == 0)||(r_dividend == 0));
342 205 dgisselq
 
343
        // The last flag: Negative.  This flag is set assuming that the result
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        // of the divide was negative (i.e., the high order bit is set).  This
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        // will also be true of an unsigned divide--if the high order bit is
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        // ever set upon completion.  Indeed, you might argue that there's no
347
        // logic involved.
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        wire    w_n;
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        assign w_n = o_quotient[(BW-1)];
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        assign o_flags = { 1'b0, w_n, r_c, r_z };
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endmodule

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