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[/] [zipcpu/] [trunk/] [rtl/] [core/] [idecode.v] - Blame information for rev 130

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1 69 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    idecode.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This RTL file specifies how instructions are to be decoded
8
//              into their underlying meanings.  This is specifically a version
9
//      designed to support a "Next Generation", or "Version 2" instruction
10
//      set as (currently) activated by the OPT_NEW_INSTRUCTION_SET option
11
//      in cpudefs.v.
12
//
13
//      I expect to (eventually) retire the old instruction set, at which point
14
//      this will become the default instruction set decoder.
15
//
16
//
17
// Creator:     Dan Gisselquist, Ph.D.
18
//              Gisselquist Technology, LLC
19
//
20
///////////////////////////////////////////////////////////////////////////////
21
//
22
// Copyright (C) 2015, Gisselquist Technology, LLC
23
//
24
// This program is free software (firmware): you can redistribute it and/or
25
// modify it under the terms of  the GNU General Public License as published
26
// by the Free Software Foundation, either version 3 of the License, or (at
27
// your option) any later version.
28
//
29
// This program is distributed in the hope that it will be useful, but WITHOUT
30
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
31
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
32
// for more details.
33
//
34
// License:     GPL, v3, as defined and found on www.gnu.org,
35
//              http://www.gnu.org/licenses/gpl.html
36
//
37
//
38
///////////////////////////////////////////////////////////////////////////////
39
//
40
//
41
//
42
`define CPU_CC_REG      4'he
43
`define CPU_PC_REG      4'hf
44
//
45
`include "cpudefs.v"
46
//
47
//
48
//
49
module  idecode(i_clk, i_rst, i_ce, i_stalled,
50
                i_instruction, i_gie, i_pc, i_pf_valid,
51
                        i_illegal,
52
                o_phase, o_illegal,
53
                o_pc, o_gie,
54
                o_dcdR, o_dcdA, o_dcdB, o_I, o_zI,
55
                o_cond, o_wF,
56
                o_op, o_ALU, o_M, o_DV, o_FP, o_break, o_lock,
57
                o_wR, o_rA, o_rB,
58 105 dgisselq
                o_early_branch, o_branch_pc, o_ljmp,
59 71 dgisselq
                o_pipe
60 69 dgisselq
                );
61
        parameter       ADDRESS_WIDTH=24, IMPLEMENT_MPY=1, EARLY_BRANCHING=1,
62
                        IMPLEMENT_DIVIDE=1, IMPLEMENT_FPU=0, AW = ADDRESS_WIDTH;
63
        input                   i_clk, i_rst, i_ce, i_stalled;
64
        input   [31:0]           i_instruction;
65
        input                   i_gie;
66
        input   [(AW-1):0]       i_pc;
67
        input                   i_pf_valid, i_illegal;
68
        output  wire            o_phase;
69
        output  reg             o_illegal;
70
        output  reg     [(AW-1):0]       o_pc;
71
        output  reg             o_gie;
72
        output  reg     [6:0]    o_dcdR, o_dcdA, o_dcdB;
73
        output  wire    [31:0]   o_I;
74
        output  reg             o_zI;
75
        output  reg     [3:0]    o_cond;
76
        output  reg             o_wF;
77
        output  reg     [3:0]    o_op;
78 130 dgisselq
        output  reg             o_ALU, o_M, o_DV, o_FP, o_break;
79
        output  wire            o_lock;
80 69 dgisselq
        output  reg             o_wR, o_rA, o_rB;
81
        output  wire            o_early_branch;
82
        output  wire    [(AW-1):0]       o_branch_pc;
83 105 dgisselq
        output  wire            o_ljmp;
84 71 dgisselq
        output  reg             o_pipe;
85 69 dgisselq
 
86
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
87
        wire                    o_dcd_early_branch;
88
        wire    [(AW-1):0]       o_dcd_branch_pc;
89
        reg     o_dcdI, o_dcdIz;
90 130 dgisselq
`ifdef  OPT_PIPELINED
91
        reg     r_lock;
92
`endif
93 69 dgisselq
 
94
 
95
        wire    [4:0]    w_op;
96 130 dgisselq
        wire            w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev;
97 69 dgisselq
        wire    [4:0]    w_dcdR, w_dcdB, w_dcdA;
98
        wire            w_dcdR_pc, w_dcdR_cc;
99
        wire            w_dcdA_pc, w_dcdA_cc;
100
        wire            w_dcdB_pc, w_dcdB_cc;
101
        wire    [3:0]    w_cond;
102
        wire            w_wF, w_dcdM, w_dcdDV, w_dcdFP;
103
        wire            w_wR, w_rA, w_rB, w_wR_n;
104 105 dgisselq
        wire            w_ljmp;
105 118 dgisselq
        wire    [31:0]   iword;
106 69 dgisselq
 
107
 
108
`ifdef  OPT_VLIW
109
        reg     [16:0]   r_nxt_half;
110
        assign  iword = (o_phase)
111
                                // set second half as a NOOP ... but really 
112
                                // shouldn't matter
113
                        ? { r_nxt_half[16:7], 1'b0, r_nxt_half[6:0], 5'b11000, 3'h7, 6'h00 }
114
                        : i_instruction;
115
`else
116
        assign  iword = { 1'b0, i_instruction[30:0] };
117
`endif
118
 
119 118 dgisselq
        generate
120
        if (EARLY_BRANCHING != 0)
121
                assign  w_ljmp = (iword == 32'h7c87c000);
122
        else
123
                assign  w_ljmp = 1'b0;
124
        endgenerate
125
 
126
 
127 69 dgisselq
        assign  w_op= iword[26:22];
128
        assign  w_mov    = (w_op      == 5'h0f);
129
        assign  w_ldi    = (w_op[4:1] == 4'hb);
130 130 dgisselq
        assign  w_brev   = (w_op      == 5'hc);
131 69 dgisselq
        assign  w_cmptst = (w_op[4:1] == 4'h8);
132 130 dgisselq
        assign  w_ldilo  = (w_op[4:0] == 5'h9);
133 69 dgisselq
        assign  w_ALU    = (~w_op[4]);
134
 
135
        // 4 LUTs
136
        assign  w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
137
                                iword[30:27] };
138
        // 4 LUTs
139
        assign  w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
140
                                iword[17:14] };
141
 
142
        // 0 LUTs
143
        assign  w_dcdA = w_dcdR;
144
        // 2 LUTs, 1 delay each
145 105 dgisselq
        assign  w_dcdR_pc = (w_dcdR == {i_gie, `CPU_PC_REG});
146 69 dgisselq
        assign  w_dcdR_cc = (w_dcdR == {i_gie, `CPU_CC_REG});
147
        // 0 LUTs
148
        assign  w_dcdA_pc = w_dcdR_pc;
149
        assign  w_dcdA_cc = w_dcdR_cc;
150
        // 2 LUTs, 1 delays each
151
        assign  w_dcdB_pc = (w_dcdB[3:0] == `CPU_PC_REG);
152
        assign  w_dcdB_cc = (w_dcdB[3:0] == `CPU_CC_REG);
153
 
154
        // Under what condition will we execute this
155
        // instruction?  Only the load immediate instruction
156
        // is completely unconditional.
157
        //
158
        // 3+4 LUTs
159
        assign  w_cond = (w_ldi) ? 4'h8 :
160
                        (iword[31])?{(iword[20:19]==2'b00),
161
                                        1'b0,iword[20:19]}
162
                        : { (iword[21:19]==3'h0), iword[21:19] };
163
 
164
        // 1 LUT
165
        assign  w_dcdM    = (w_op[4:1] == 4'h9);
166
        // 1 LUT
167
        assign  w_dcdDV   = (w_op[4:1] == 4'ha);
168
        // 1 LUT
169
        assign  w_dcdFP   = (w_op[4:3] == 2'b11)&&(w_dcdR[3:1] != 3'h7);
170
        // 4 LUT's--since it depends upon FP/NOOP condition (vs 1 before)
171
        //      Everything reads A but ... NOOP/BREAK/LOCK, LDI, LOD, MOV
172
        assign  w_rA     = (w_dcdFP)
173
                                // Divide's read A
174
                                ||(w_dcdDV)
175
                                // ALU read's A, unless it's a MOV to A
176
                                // This includes LDIHI/LDILO
177
                                ||((~w_op[4])&&(w_op[3:0]!=4'hf))
178
                                // STO's read A
179
                                ||((w_dcdM)&&(w_op[0]))
180
                                // Test/compares
181
                                ||(w_op[4:1]== 4'h8);
182
        // 1 LUTs -- do we read a register for operand B?  Specifically, do
183
        // we need to stall if the register is not (yet) ready?
184 130 dgisselq
        assign  w_rB     = (w_mov)||((iword[18])&&(~w_ldi));
185 69 dgisselq
        // 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
186
        assign  w_wR_n   = ((w_dcdM)&&(w_op[0]))
187
                                ||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
188
                                ||(w_cmptst);
189
        assign  w_wR     = ~w_wR_n;
190 90 dgisselq
        //
191
        // 1-output bit (5 Opcode bits, 4 out-reg bits, 3 condition bits)
192 69 dgisselq
        //      
193
        //      This'd be 4 LUTs, save that we have the carve out for NOOPs
194 90 dgisselq
        //      and writes to the PC/CC register(s).
195 69 dgisselq
        assign  w_wF     = (w_cmptst)
196
                        ||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
197 130 dgisselq
                                ||((w_ALU)&&(~w_mov)&&(~w_ldilo)&&(~w_brev)
198 90 dgisselq
                                        &&(iword[30:28] != 3'h7))));
199 69 dgisselq
 
200
        // Bottom 13 bits: no LUT's
201
        // w_dcd[12: 0] -- no LUTs
202
        // w_dcd[   13] -- 2 LUTs
203
        // w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay
204
        // w_dcd[22:18] : 5 LUTs, 1 delay (assuming high bit is o/w determined)
205
        reg     [22:0]   r_I;
206
        wire    [22:0]   w_I, w_fullI;
207
        wire            w_Iz;
208
 
209
        assign  w_fullI = (w_ldi) ? { iword[22:0] } // LDI
210
                        :((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } // Move
211
                        :((~iword[18]) ? { {(23-18){iword[17]}}, iword[17:0] }
212
                        : { {(23-14){iword[13]}}, iword[13:0] }
213
                        ));
214
 
215
`ifdef  OPT_VLIW
216
        wire    [5:0]    w_halfI;
217
        assign  w_halfI = (w_ldi) ? iword[5:0]
218
                                :((iword[5]) ? 6'h00 : {iword[4],iword[4:0]});
219
        assign  w_I  = (iword[31])? {{(23-6){w_halfI[5]}}, w_halfI }:w_fullI;
220
`else
221
        assign  w_I  = w_fullI;
222
`endif
223
        assign  w_Iz = (w_I == 0);
224
 
225
 
226
`ifdef  OPT_VLIW
227
        //
228
        // The o_phase parameter is special.  It needs to let the software
229
        // following know that it cannot break/interrupt on an o_phase asserted
230
        // instruction, lest the break take place between the first and second
231
        // half of a VLIW instruction.  To do this, o_phase must be asserted
232
        // when the first instruction half is valid, but not asserted on either
233
        // a 32-bit instruction or the second half of a 2x16-bit instruction.
234
        reg     r_phase;
235
        initial r_phase = 1'b0;
236
        always @(posedge i_clk)
237
                if (i_rst) // When no instruction is in the pipe, phase is zero
238
                        r_phase <= 1'b0;
239
                else if (i_ce)
240
                        r_phase <= (o_phase)? 1'b0:(i_instruction[31]);
241
        // Phase is '1' on the first instruction of a two-part set
242
        // But, due to the delay in processing, it's '1' when our output is
243
        // valid for that first part, but that'll be the same time we
244
        // are processing the second part ... so it may look to us like a '1'
245
        // on the second half of processing.
246
 
247
        assign  o_phase = r_phase;
248
`else
249
        assign  o_phase = 1'b0;
250
`endif
251
 
252
 
253 71 dgisselq
        initial o_illegal = 1'b0;
254 69 dgisselq
        always @(posedge i_clk)
255 71 dgisselq
                if (i_rst)
256
                        o_illegal <= 1'b0;
257
                else if (i_ce)
258 69 dgisselq
                begin
259
`ifdef  OPT_VLIW
260 71 dgisselq
                        o_illegal <= (i_illegal);
261 69 dgisselq
`else
262
                        o_illegal <= ((i_illegal) || (i_instruction[31]));
263
`endif
264
                        if ((IMPLEMENT_MPY!=1)&&(w_op[4:1]==4'h5))
265
                                o_illegal <= 1'b1;
266
 
267
                        if ((IMPLEMENT_DIVIDE==0)&&(w_dcdDV))
268
                                o_illegal <= 1'b1;
269
                        else if ((IMPLEMENT_DIVIDE!=0)&&(w_dcdDV)&&(w_dcdR[3:1]==3'h7))
270
                                o_illegal <= 1'b1;
271
 
272
 
273
                        if ((IMPLEMENT_FPU!=0)&&(w_dcdFP)&&(w_dcdR[3:1]==3'h7))
274
                                o_illegal <= 1'b1;
275
                        else if ((IMPLEMENT_FPU==0)&&(w_dcdFP))
276
                                o_illegal <= 1'b1;
277
 
278 71 dgisselq
                        if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)
279
                                &&(
280 130 dgisselq
                                        (w_op[2:0] != 3'h1)      // BREAK
281
`ifdef  OPT_PIPELINED
282
                                        &&(w_op[2:0] != 3'h2)    // LOCK
283
`endif
284 71 dgisselq
                                        &&(w_op[2:0] != 3'h0)))  // NOOP
285
                                o_illegal <= 1'b1;
286
                end
287
 
288
 
289
        always @(posedge i_clk)
290
                if (i_ce)
291
                begin
292
`ifdef  OPT_VLIW
293
                        if (~o_phase)
294
                        begin
295
                                o_gie<= i_gie;
296
                                // i.e. dcd_pc+1
297
                                o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
298
                        end
299
`else
300
                        o_gie<= i_gie;
301
                        o_pc <= i_pc+{{(AW-1){1'b0}},1'b1};
302
`endif
303
 
304 69 dgisselq
                        // Under what condition will we execute this
305
                        // instruction?  Only the load immediate instruction
306
                        // is completely unconditional.
307
                        o_cond <= w_cond;
308
                        // Don't change the flags on conditional instructions,
309
                        // UNLESS: the conditional instruction was a CMP
310
                        // or TST instruction.
311
                        o_wF <= w_wF;
312
 
313
                        // Record what operation/op-code (4-bits) we are doing
314
                        //      Note that LDI magically becomes a MOV
315
                        //      instruction here.  That way it's a pass through
316
                        //      the ALU.  Likewise, the two compare instructions
317
                        //      CMP and TST becomes SUB and AND here as well.
318
                        // We keep only the bottom four bits, since we've
319
                        // already done the rest of the decode necessary to 
320
                        // settle between the other instructions.  For example,
321
                        // o_FP plus these four bits uniquely defines the FP
322
                        // instruction, o_DV plus the bottom of these defines
323
                        // the divide, etc.
324
                        o_op <= (w_ldi)? 4'hf:w_op[3:0];
325
 
326
                        // Default values
327
                        o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
328
                        o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA};
329
                        o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB};
330
                        o_wR  <= w_wR;
331
                        o_rA  <= w_rA;
332
                        o_rB  <= w_rB;
333
                        r_I    <= w_I;
334
                        o_zI   <= w_Iz;
335
 
336
                        o_ALU  <=  (w_ALU)||(w_ldi)||(w_cmptst); // 1 LUT
337
                        o_M    <=  w_dcdM;
338
                        o_DV   <=  w_dcdDV;
339
                        o_FP   <=  w_dcdFP;
340
 
341
                        o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
342 130 dgisselq
`ifdef  OPT_PIPELINED
343
                        r_lock  <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
344
`endif
345 69 dgisselq
`ifdef  OPT_VLIW
346
                        r_nxt_half <= { iword[31], iword[13:5],
347
                                ((iword[21])? iword[20:19] : 2'h0),
348
                                iword[4:0] };
349
`endif
350
                end
351
 
352 130 dgisselq
`ifdef  OPT_PIPELINED
353
        assign  o_lock = r_lock;
354
`else
355
        assign  o_lock = 1'b0;
356
`endif
357
 
358 69 dgisselq
        generate
359
        if (EARLY_BRANCHING!=0)
360
        begin
361 105 dgisselq
                reg                     r_early_branch, r_ljmp;
362 69 dgisselq
                reg     [(AW-1):0]       r_branch_pc;
363 105 dgisselq
 
364
                initial r_ljmp = 1'b0;
365 69 dgisselq
                always @(posedge i_clk)
366 105 dgisselq
                        if (i_rst)
367
                                r_ljmp <= 1'b0;
368
                        else if ((i_ce)&&(i_pf_valid))
369
                                r_ljmp <= (w_ljmp);
370
                assign  o_ljmp = r_ljmp;
371
 
372
                always @(posedge i_clk)
373
                if (i_rst)
374
                        r_early_branch <= 1'b0;
375
                else if ((i_ce)&&(i_pf_valid))
376 90 dgisselq
                begin
377 105 dgisselq
                        if (r_ljmp)
378
                                // LOD (PC),PC
379
                                r_early_branch <= 1'b1;
380
                        else if ((~iword[31])&&(iword[30:27]==`CPU_PC_REG)&&(w_cond[3]))
381 69 dgisselq
                        begin
382 90 dgisselq
                                if (w_op[4:1] == 4'hb) // LDI to PC
383 105 dgisselq
                                        // LDI x,PC
384 69 dgisselq
                                        r_early_branch     <= 1'b1;
385 105 dgisselq
                                else if ((w_op[4:0]==5'h02)&&(~iword[18]))
386
                                        // Add x,PC
387 69 dgisselq
                                        r_early_branch     <= 1'b1;
388 105 dgisselq
                                else begin
389 69 dgisselq
                                        r_early_branch     <= 1'b0;
390
                                end
391 90 dgisselq
                        end else
392
                                r_early_branch <= 1'b0;
393 105 dgisselq
                end else if (i_ce)
394
                        r_early_branch <= 1'b0;
395
 
396 69 dgisselq
                always @(posedge i_clk)
397
                        if (i_ce)
398
                        begin
399 105 dgisselq
                                if (r_ljmp)
400
                                        r_branch_pc <= iword[(AW-1):0];
401
                                else if (w_op[4:1] == 4'hb) // LDI
402 90 dgisselq
                                        r_branch_pc <= {{(AW-23){iword[22]}},iword[22:0]};
403
                                else // Add x,PC
404
                                r_branch_pc <= i_pc
405 105 dgisselq
                                        + {{(AW-17){iword[17]}},iword[16:0]}
406 90 dgisselq
                                        + {{(AW-1){1'b0}},1'b1};
407 69 dgisselq
                        end
408
 
409
                assign  o_early_branch     = r_early_branch;
410
                assign  o_branch_pc        = r_branch_pc;
411
        end else begin
412
                assign  o_early_branch = 1'b0;
413
                assign  o_branch_pc = {(AW){1'b0}};
414 105 dgisselq
                assign  o_ljmp = 1'b0;
415 69 dgisselq
        end endgenerate
416
 
417 71 dgisselq
 
418
        // To be a pipeable operation there must be ...
419
        //      1. Two valid adjacent instructions
420
        //      2. Both must be memory operations, of the same time (both lods
421
        //              or both stos)
422
        //      3. Both must use the same register base address
423
        //      4. Both must be to the same address, or the address incremented
424
        //              by one
425
        // Note that we're not using iword here ... there's a lot of logic
426
        // taking place, and it's only valid if the new word is not compressed.
427
        //
428
        reg     r_valid;
429
        always @(posedge i_clk)
430
                if (i_ce)
431
                        o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
432
                                &&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
433
                                &&(i_instruction[17:14] == o_dcdB[3:0])
434 130 dgisselq
                                &&(i_instruction[17:14] != o_dcdA[3:0])
435 71 dgisselq
                                &&(i_gie == o_gie)
436
                                &&((i_instruction[21:19]==o_cond[2:0])
437
                                        ||(o_cond[2:0] == 3'h0))
438
                                &&((i_instruction[13:0]==r_I[13:0])
439
                                        ||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
440
        always @(posedge i_clk)
441
                if (i_rst)
442
                        r_valid <= 1'b0;
443 105 dgisselq
                else if ((i_ce)&&(o_ljmp))
444
                        r_valid <= 1'b0;
445 71 dgisselq
                else if ((i_ce)&&(i_pf_valid))
446
                        r_valid <= 1'b1;
447
                else if (~i_stalled)
448
                        r_valid <= 1'b0;
449
 
450
 
451 69 dgisselq
        assign  o_I = { {(32-22){r_I[22]}}, r_I[21:0] };
452
 
453
endmodule

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