OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Blame information for rev 130

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    memops.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A memory unit to support a CPU.
8
//
9
//      In the interests of code simplicity, this memory operator is 
10
//      susceptible to unknown results should a new command be sent to it
11
//      before it completes the last one.  Unpredictable results might then
12
//      occurr.
13
//
14 36 dgisselq
//      20150919 -- Added support for handling BUS ERR's (i.e., the WB
15
//              error signal).
16
//
17 3 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
18 69 dgisselq
//              Gisselquist Technology, LLC
19 3 dgisselq
//
20
///////////////////////////////////////////////////////////////////////////
21
//
22
// Copyright (C) 2015, Gisselquist Technology, LLC
23
//
24
// This program is free software (firmware): you can redistribute it and/or
25
// modify it under the terms of  the GNU General Public License as published
26
// by the Free Software Foundation, either version 3 of the License, or (at
27
// your option) any later version.
28
//
29
// This program is distributed in the hope that it will be useful, but WITHOUT
30
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
31
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
32
// for more details.
33
//
34
// License:     GPL, v3, as defined and found on www.gnu.org,
35
//              http://www.gnu.org/licenses/gpl.html
36
//
37
//
38
///////////////////////////////////////////////////////////////////////////
39
//
40 69 dgisselq
module  memops(i_clk, i_rst, i_stb, i_lock,
41 2 dgisselq
                i_op, i_addr, i_data, i_oreg,
42 36 dgisselq
                        o_busy, o_valid, o_err, o_wreg, o_result,
43
                o_wb_cyc_gbl, o_wb_cyc_lcl,
44
                        o_wb_stb_gbl, o_wb_stb_lcl,
45
                        o_wb_we, o_wb_addr, o_wb_data,
46
                i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
47 69 dgisselq
        parameter       ADDRESS_WIDTH=24, IMPLEMENT_LOCK=0, AW=ADDRESS_WIDTH;
48 2 dgisselq
        input                   i_clk, i_rst;
49 69 dgisselq
        input                   i_stb, i_lock;
50 2 dgisselq
        // CPU interface
51
        input                   i_op;
52
        input           [31:0]   i_addr;
53
        input           [31:0]   i_data;
54
        input           [4:0]    i_oreg;
55
        // CPU outputs
56
        output  wire            o_busy;
57
        output  reg             o_valid;
58 36 dgisselq
        output  reg             o_err;
59 2 dgisselq
        output  reg     [4:0]    o_wreg;
60
        output  reg     [31:0]   o_result;
61
        // Wishbone outputs
62 69 dgisselq
        output  wire            o_wb_cyc_gbl;
63
        output  reg             o_wb_stb_gbl;
64
        output  wire            o_wb_cyc_lcl;
65
        output  reg             o_wb_stb_lcl;
66
        output  reg             o_wb_we;
67 48 dgisselq
        output  reg     [(AW-1):0]       o_wb_addr;
68
        output  reg     [31:0]   o_wb_data;
69 2 dgisselq
        // Wishbone inputs
70 36 dgisselq
        input                   i_wb_ack, i_wb_stall, i_wb_err;
71 2 dgisselq
        input           [31:0]   i_wb_data;
72
 
73 69 dgisselq
        reg     r_wb_cyc_gbl, r_wb_cyc_lcl;
74 36 dgisselq
        wire    gbl_stb, lcl_stb;
75
        assign  lcl_stb = (i_stb)&&(i_addr[31:8]==24'hc00000)&&(i_addr[7:5]==3'h0);
76
        assign  gbl_stb = (i_stb)&&((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
77
 
78 69 dgisselq
        initial r_wb_cyc_gbl = 1'b0;
79
        initial r_wb_cyc_lcl = 1'b0;
80 2 dgisselq
        always @(posedge i_clk)
81
                if (i_rst)
82 36 dgisselq
                begin
83 69 dgisselq
                        r_wb_cyc_gbl <= 1'b0;
84
                        r_wb_cyc_lcl <= 1'b0;
85
                end else if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl))
86 36 dgisselq
                begin
87
                        if ((i_wb_ack)||(i_wb_err))
88
                        begin
89 69 dgisselq
                                r_wb_cyc_gbl <= 1'b0;
90
                                r_wb_cyc_lcl <= 1'b0;
91 36 dgisselq
                        end
92
                end else if (i_stb) // New memory operation
93
                begin // Grab the wishbone
94 69 dgisselq
                        r_wb_cyc_lcl <= lcl_stb;
95
                        r_wb_cyc_gbl <= gbl_stb;
96 36 dgisselq
                end
97 3 dgisselq
        always @(posedge i_clk)
98 36 dgisselq
                if (o_wb_cyc_gbl)
99
                        o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall);
100 3 dgisselq
                else
101 36 dgisselq
                        o_wb_stb_gbl <= gbl_stb; // Grab wishbone on new operation
102 3 dgisselq
        always @(posedge i_clk)
103 36 dgisselq
                if (o_wb_cyc_lcl)
104
                        o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall);
105
                else
106
                        o_wb_stb_lcl  <= lcl_stb; // Grab wishbone on new operation
107
        always @(posedge i_clk)
108 3 dgisselq
                if (i_stb)
109
                begin
110 2 dgisselq
                        o_wb_we   <= i_op;
111
                        o_wb_data <= i_data;
112 48 dgisselq
                        o_wb_addr <= i_addr[(AW-1):0];
113 2 dgisselq
                end
114
 
115
        initial o_valid = 1'b0;
116
        always @(posedge i_clk)
117 36 dgisselq
                o_valid <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack)&&(~o_wb_we);
118
        initial o_err = 1'b0;
119
        always @(posedge i_clk)
120
                o_err <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_err);
121
        assign  o_busy = (o_wb_cyc_gbl)||(o_wb_cyc_lcl);
122 2 dgisselq
 
123
        always @(posedge i_clk)
124 3 dgisselq
                if (i_stb)
125 2 dgisselq
                        o_wreg    <= i_oreg;
126
        always @(posedge i_clk)
127 3 dgisselq
                if (i_wb_ack)
128 2 dgisselq
                        o_result <= i_wb_data;
129 69 dgisselq
 
130
        generate
131
        if (IMPLEMENT_LOCK != 0)
132
        begin
133
                reg     lock_gbl, lock_lcl;
134
 
135
                initial lock_gbl = 1'b0;
136
                initial lock_lcl = 1'b0;
137
 
138
                always @(posedge i_clk)
139
                begin
140
                        lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
141
                        lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl));
142
                end
143
 
144
                assign  o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
145
                assign  o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
146
        end else begin
147
                assign  o_wb_cyc_gbl = (r_wb_cyc_gbl);
148
                assign  o_wb_cyc_lcl = (r_wb_cyc_lcl);
149
        end endgenerate
150 2 dgisselq
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.