OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [memops.v] - Blame information for rev 3

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    memops.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A memory unit to support a CPU.
8
//
9
//      In the interests of code simplicity, this memory operator is 
10
//      susceptible to unknown results should a new command be sent to it
11
//      before it completes the last one.  Unpredictable results might then
12
//      occurr.
13
//
14
// Creator:     Dan Gisselquist, Ph.D.
15
//              Gisselquist Tecnology, LLC
16
//
17
///////////////////////////////////////////////////////////////////////////
18
//
19
// Copyright (C) 2015, Gisselquist Technology, LLC
20
//
21
// This program is free software (firmware): you can redistribute it and/or
22
// modify it under the terms of  the GNU General Public License as published
23
// by the Free Software Foundation, either version 3 of the License, or (at
24
// your option) any later version.
25
//
26
// This program is distributed in the hope that it will be useful, but WITHOUT
27
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
28
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
29
// for more details.
30
//
31
// License:     GPL, v3, as defined and found on www.gnu.org,
32
//              http://www.gnu.org/licenses/gpl.html
33
//
34
//
35
///////////////////////////////////////////////////////////////////////////
36
//
37 2 dgisselq
module  memops(i_clk, i_rst, i_stb,
38
                i_op, i_addr, i_data, i_oreg,
39
                        o_busy, o_valid, o_wreg, o_result,
40
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
41
                i_wb_ack, i_wb_stall, i_wb_data);
42
        input                   i_clk, i_rst;
43
        input                   i_stb;
44
        // CPU interface
45
        input                   i_op;
46
        input           [31:0]   i_addr;
47
        input           [31:0]   i_data;
48
        input           [4:0]    i_oreg;
49
        // CPU outputs
50
        output  wire            o_busy;
51
        output  reg             o_valid;
52
        output  reg     [4:0]    o_wreg;
53
        output  reg     [31:0]   o_result;
54
        // Wishbone outputs
55
        output  reg             o_wb_cyc, o_wb_stb, o_wb_we;
56
        output  reg     [31:0]   o_wb_addr, o_wb_data;
57
        // Wishbone inputs
58
        input                   i_wb_ack, i_wb_stall;
59
        input           [31:0]   i_wb_data;
60
 
61
        always @(posedge i_clk)
62
                if (i_rst)
63
                        o_wb_cyc <= 1'b0;
64
                else if (o_wb_cyc)
65
                        o_wb_cyc <= (~i_wb_ack);
66 3 dgisselq
                else if (i_stb) // New memory operation
67 2 dgisselq
                        // Grab the wishbone
68
                        o_wb_cyc  <= 1'b1;
69 3 dgisselq
        always @(posedge i_clk)
70
                if (o_wb_cyc)
71
                        o_wb_stb <= (o_wb_stb)&&(i_wb_stall);
72
                else
73
                        o_wb_stb  <= i_stb; // Grab wishbone on new operation
74
        always @(posedge i_clk)
75
                if (i_stb)
76
                begin
77 2 dgisselq
                        o_wb_we   <= i_op;
78
                        o_wb_data <= i_data;
79
                        o_wb_addr <= i_addr;
80
                end
81
 
82
        initial o_valid = 1'b0;
83
        always @(posedge i_clk)
84 3 dgisselq
                o_valid <= (o_wb_cyc)&&(i_wb_ack)&&(~o_wb_we);
85 2 dgisselq
        assign  o_busy = o_wb_cyc;
86
 
87
        always @(posedge i_clk)
88 3 dgisselq
                if (i_stb)
89 2 dgisselq
                        o_wreg    <= i_oreg;
90
        always @(posedge i_clk)
91 3 dgisselq
                if (i_wb_ack)
92 2 dgisselq
                        o_result <= i_wb_data;
93
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.