OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Blame information for rev 38

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3 3 dgisselq
// Filename:    pipefetch.v
4 2 dgisselq
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7 3 dgisselq
// Purpose:     Keeping our CPU fed with instructions, at one per clock and
8
//              with no stalls, can be quite a chore.  Worse, the Wishbone
9
//              takes a couple of cycles just to read one instruction from
10
//              the bus.  However, if we use pipeline accesses to the Wishbone
11
//              bus, then we can read more and faster.  Further, if we cache
12
//              these results so that we have them before we need them, then
13
//              we have a chance of keeping our CPU from stalling.  Those are
14
//              the purposes of this instruction fetch module: 1) Pipeline
15
//              wishbone accesses, and 2) an instruction cache.
16 2 dgisselq
//
17 36 dgisselq
//      20150919 -- Fixed a nasty race condition whereby the pipefetch routine
18
//              would produce either the same instruction twice, or skip
19
//              an instruction.  This condition was dependent on the CPU stall
20
//              condition, and would only take place if the pipeline wasn't 
21
//              completely full throughout the stall.
22
//
23
//              Interface support was also added for trapping on illegal
24
//              instructions (i.e., instruction fetches that cause bus errors),
25
//              however the internal interface has not caught up to supporting
26
//              these exceptions yet.
27
//
28 2 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
29
//              Gisselquist Tecnology, LLC
30
//
31
////////////////////////////////////////////////////////////////////////////////
32
//
33
// Copyright (C) 2015, Gisselquist Technology, LLC
34
//
35
// This program is free software (firmware): you can redistribute it and/or
36
// modify it under the terms of  the GNU General Public License as published
37
// by the Free Software Foundation, either version 3 of the License, or (at
38
// your option) any later version.
39
//
40
// This program is distributed in the hope that it will be useful, but WITHOUT
41
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
42
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
43
// for more details.
44
//
45
// License:     GPL, v3, as defined and found on www.gnu.org,
46
//              http://www.gnu.org/licenses/gpl.html
47
//
48
//
49
////////////////////////////////////////////////////////////////////////////////
50
//
51 18 dgisselq
module  pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
52 2 dgisselq
                        o_i, o_pc, o_v,
53
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
54 36 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
55
                        o_illegal);
56 3 dgisselq
        parameter       RESET_ADDRESS=32'h0010_0000,
57
                        LGCACHELEN = 6, CACHELEN=(1<<LGCACHELEN),
58
                        BUSW=32;
59 18 dgisselq
        input                           i_clk, i_rst, i_new_pc,
60
                                        i_clear_cache, i_stall_n;
61 2 dgisselq
        input           [(BUSW-1):0]     i_pc;
62
        output  reg     [(BUSW-1):0]     o_i;
63
        output  reg     [(BUSW-1):0]     o_pc;
64
        output  wire                    o_v;
65
        //
66
        output  reg             o_wb_cyc, o_wb_stb;
67
        output  wire            o_wb_we;
68
        output  reg     [(BUSW-1):0]     o_wb_addr;
69
        output  wire    [(BUSW-1):0]     o_wb_data;
70
        //
71 36 dgisselq
        input                   i_wb_ack, i_wb_stall, i_wb_err;
72 2 dgisselq
        input           [(BUSW-1):0]     i_wb_data;
73 3 dgisselq
        //
74
        // Is the (data) memory unit also requesting access to the bus?
75
        input                           i_wb_request;
76 36 dgisselq
        output  wire                    o_illegal;
77 2 dgisselq
 
78 36 dgisselq
        assign  o_illegal = 1'b0;
79
 
80 2 dgisselq
        // Fixed bus outputs: we read from the bus only, never write.
81
        // Thus the output data is ... irrelevant and don't care.  We set it
82
        // to zero just to set it to something.
83
        assign  o_wb_we = 1'b0;
84
        assign  o_wb_data = 0;
85
 
86 3 dgisselq
        reg     [(BUSW-1):0]             r_cache_base;
87 2 dgisselq
        reg     [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
88
        reg     [(BUSW-1):0]             cache[0:(CACHELEN-1)];
89
 
90 3 dgisselq
        reg     [(LGCACHELEN-1):0]       r_cache_offset;
91 2 dgisselq
 
92
        reg                     r_addr_set;
93
        reg     [(BUSW-1):0]     r_addr;
94
 
95
        wire    [(BUSW-1):0]     bus_nvalid;
96
        assign  bus_nvalid = { {(BUSW-LGCACHELEN-1){1'b0}}, r_nvalid };
97
 
98 3 dgisselq
        // What are some of the conditions for which we need to restart the
99
        // cache?
100
        wire    w_pc_out_of_bounds;
101
        assign  w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
102
                                        ||(i_pc < r_cache_base)
103
                                        ||(i_pc >= r_cache_base + CACHELEN)));
104
        wire    w_ran_off_end_of_cache;
105
        assign  w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
106
                                        ||(r_addr >= r_cache_base + CACHELEN)));
107
        wire    w_running_out_of_cache;
108
        assign  w_running_out_of_cache = (r_addr_set)
109
                        &&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
110
                                                + (1<<(LGCACHELEN-1)));
111
        initial r_cache_base = RESET_ADDRESS;
112 2 dgisselq
        always @(posedge i_clk)
113
        begin
114 18 dgisselq
                if ((i_rst)||(i_clear_cache))
115 3 dgisselq
                begin
116 2 dgisselq
                        o_wb_cyc <= 1'b0;
117 18 dgisselq
                        o_wb_stb <= 1'b0;
118 3 dgisselq
                        // r_cache_base <= RESET_ADDRESS;
119
                // end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
120
                //              &&(i_pc >= r_cache_base)
121
                //              &&(i_pc < r_cache_base + bus_nvalid))
122
                // begin
123 2 dgisselq
                        // The new instruction is in our cache, do nothing
124
                        // with the bus here.
125 3 dgisselq
                end else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
126 2 dgisselq
                begin
127
                        // We need to abandon our bus action to start over in
128
                        // a new region, setting up a new cache.  This may
129
                        // happen mid cycle while waiting for a result.  By
130
                        // dropping o_wb_cyc, we state that we are no longer
131
                        // interested in that result--whatever it might be.
132
                        o_wb_cyc <= 1'b0;
133
                        o_wb_stb <= 1'b0;
134 3 dgisselq
                end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set))
135
                begin
136
                        // Restart a bus cycle that was interrupted when the
137
                        // data section wanted access to our bus.
138
                        o_wb_cyc <= 1'b1;
139
                        o_wb_stb <= 1'b1;
140
                        // o_wb_addr <= r_cache_base + bus_nvalid;
141 2 dgisselq
                end else if ((~o_wb_cyc)&&(
142 3 dgisselq
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
143 2 dgisselq
                begin
144
                        // Start a bus transaction
145
                        o_wb_cyc <= 1'b1;
146
                        o_wb_stb <= 1'b1;
147 3 dgisselq
                        // o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
148
                        // r_nvalid <= 0;
149
                        // r_cache_base <= (i_new_pc) ? i_pc : r_addr;
150
                        // r_cache_offset <= 0;
151
                end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
152 2 dgisselq
                begin
153
                        // If we're using the last quarter of the cache, then
154
                        // let's start a bus transaction to extend the cache.
155
                        o_wb_cyc <= 1'b1;
156
                        o_wb_stb <= 1'b1;
157 3 dgisselq
                        // o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
158
                        // r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
159
                        // r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
160
                        // r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
161 2 dgisselq
                end else if (o_wb_cyc)
162
                begin
163
                        // This handles everything ... but the case where
164
                        // while reading we need to extend our cache.
165
                        if ((o_wb_stb)&&(~i_wb_stall))
166
                        begin
167 3 dgisselq
                                // o_wb_addr <= o_wb_addr + 1;
168
                                if ((o_wb_addr - r_cache_base >= CACHELEN-1)
169
                                        ||(i_wb_request))
170 2 dgisselq
                                        o_wb_stb <= 1'b0;
171
                        end
172
 
173
                        if (i_wb_ack)
174
                        begin
175 3 dgisselq
                                // r_nvalid <= r_nvalid + 1;
176 2 dgisselq
                                if ((r_acks_waiting == 1)&&(~o_wb_stb))
177
                                        o_wb_cyc <= 1'b0;
178 36 dgisselq
                        end else if ((r_acks_waiting == 0)&&(~o_wb_stb))
179
                                o_wb_cyc <= 1'b0;
180 2 dgisselq
                end
181
        end
182
 
183 36 dgisselq
        initial r_nvalid = 0;
184 3 dgisselq
        always @(posedge i_clk)
185 18 dgisselq
                if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
186 11 dgisselq
                        r_nvalid <= 0;
187
                else if ((~o_wb_cyc)&&(
188 3 dgisselq
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
189
                        r_nvalid <= 0;
190
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
191
                        r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
192
                else if ((o_wb_cyc)&&(i_wb_ack))
193
                        r_nvalid <= r_nvalid+1;
194
 
195
        always @(posedge i_clk)
196 18 dgisselq
                if (i_clear_cache)
197
                        r_cache_base <= i_pc;
198
                else if ((~o_wb_cyc)&&(
199
                                (w_pc_out_of_bounds)
200
                                ||(w_ran_off_end_of_cache)))
201 3 dgisselq
                        r_cache_base <= (i_new_pc) ? i_pc : r_addr;
202
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
203
                        r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
204
 
205
        always @(posedge i_clk)
206 18 dgisselq
                if (i_clear_cache)
207 3 dgisselq
                        r_cache_offset <= 0;
208 18 dgisselq
                else if ((~o_wb_cyc)&&(
209
                                (w_pc_out_of_bounds)
210
                                ||(w_ran_off_end_of_cache)))
211
                        r_cache_offset <= 0;
212 3 dgisselq
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
213
                        r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
214
 
215
        always @(posedge i_clk)
216 18 dgisselq
                if (i_clear_cache)
217
                        o_wb_addr <= i_pc;
218 38 dgisselq
                else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
219
                begin
220
                        if (i_wb_ack)
221
                                o_wb_addr <= r_cache_base + bus_nvalid+1;
222
                        else
223
                                o_wb_addr <= r_cache_base + bus_nvalid;
224
                end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
225 3 dgisselq
                                        ||(w_ran_off_end_of_cache)))
226
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
227
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
228
                        o_wb_addr <= o_wb_addr + 1;
229
 
230
        initial r_acks_waiting = 0;
231
        always @(posedge i_clk)
232
                if (~o_wb_cyc)
233
                        r_acks_waiting <= 0;
234 38 dgisselq
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
235 36 dgisselq
                        r_acks_waiting <= r_acks_waiting + 1;
236 38 dgisselq
                else if ((o_wb_cyc)&&(i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
237 36 dgisselq
                        r_acks_waiting <= r_acks_waiting - 1;
238 3 dgisselq
 
239
        always @(posedge i_clk)
240
                if ((o_wb_cyc)&&(i_wb_ack))
241
                        cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
242
                                        <= i_wb_data;
243
 
244 2 dgisselq
        initial r_addr_set = 1'b0;
245
        always @(posedge i_clk)
246 18 dgisselq
                if ((i_rst)||(i_clear_cache))
247 2 dgisselq
                        r_addr_set <= 1'b0;
248
                else if (i_new_pc)
249
                        r_addr_set <= 1'b1;
250
 
251
        // Now, read from the cache
252
        wire    w_cv;   // Cache valid, address is in the cache
253
        reg     r_cv;
254
        assign  w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
255
                        &&(r_addr-r_cache_base < bus_nvalid));
256
        always @(posedge i_clk)
257 36 dgisselq
                r_cv <= (~i_new_pc)&&((w_cv)||((~i_stall_n)&&(r_cv)));
258 2 dgisselq
        assign  o_v = (r_cv)&&(~i_new_pc);
259
 
260
        always @(posedge i_clk)
261
                if (i_new_pc)
262
                        r_addr <= i_pc;
263 36 dgisselq
                else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )
264 2 dgisselq
                        r_addr <= r_addr + 1;
265
 
266
        wire    [(LGCACHELEN-1):0]       c_rdaddr, c_cache_base;
267
        assign  c_cache_base   = r_cache_base[(LGCACHELEN-1):0];
268 3 dgisselq
        assign  c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;
269 2 dgisselq
        always @(posedge i_clk)
270 36 dgisselq
                if ((~o_v)||((i_stall_n)&&(o_v)))
271 2 dgisselq
                        o_i <= cache[c_rdaddr];
272
        always @(posedge i_clk)
273 36 dgisselq
                if ((~o_v)||((i_stall_n)&&(o_v)))
274 2 dgisselq
                        o_pc <= r_addr;
275
 
276
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.