OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [pipefetch.v] - Blame information for rev 48

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3 3 dgisselq
// Filename:    pipefetch.v
4 2 dgisselq
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7 3 dgisselq
// Purpose:     Keeping our CPU fed with instructions, at one per clock and
8
//              with no stalls, can be quite a chore.  Worse, the Wishbone
9
//              takes a couple of cycles just to read one instruction from
10
//              the bus.  However, if we use pipeline accesses to the Wishbone
11
//              bus, then we can read more and faster.  Further, if we cache
12
//              these results so that we have them before we need them, then
13
//              we have a chance of keeping our CPU from stalling.  Those are
14
//              the purposes of this instruction fetch module: 1) Pipeline
15
//              wishbone accesses, and 2) an instruction cache.
16 2 dgisselq
//
17 36 dgisselq
//      20150919 -- Fixed a nasty race condition whereby the pipefetch routine
18
//              would produce either the same instruction twice, or skip
19
//              an instruction.  This condition was dependent on the CPU stall
20
//              condition, and would only take place if the pipeline wasn't 
21
//              completely full throughout the stall.
22
//
23
//              Interface support was also added for trapping on illegal
24
//              instructions (i.e., instruction fetches that cause bus errors),
25
//              however the internal interface has not caught up to supporting
26
//              these exceptions yet.
27
//
28 2 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
29
//              Gisselquist Tecnology, LLC
30
//
31
////////////////////////////////////////////////////////////////////////////////
32
//
33
// Copyright (C) 2015, Gisselquist Technology, LLC
34
//
35
// This program is free software (firmware): you can redistribute it and/or
36
// modify it under the terms of  the GNU General Public License as published
37
// by the Free Software Foundation, either version 3 of the License, or (at
38
// your option) any later version.
39
//
40
// This program is distributed in the hope that it will be useful, but WITHOUT
41
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
42
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
43
// for more details.
44
//
45
// License:     GPL, v3, as defined and found on www.gnu.org,
46
//              http://www.gnu.org/licenses/gpl.html
47
//
48
//
49
////////////////////////////////////////////////////////////////////////////////
50
//
51 18 dgisselq
module  pipefetch(i_clk, i_rst, i_new_pc, i_clear_cache, i_stall_n, i_pc,
52 2 dgisselq
                        o_i, o_pc, o_v,
53
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
54 36 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_wb_request,
55
                        o_illegal);
56 3 dgisselq
        parameter       RESET_ADDRESS=32'h0010_0000,
57 48 dgisselq
                        LGCACHELEN = 6, ADDRESS_WIDTH=24,
58
                        CACHELEN=(1<<LGCACHELEN), BUSW=32, AW=ADDRESS_WIDTH;
59 18 dgisselq
        input                           i_clk, i_rst, i_new_pc,
60
                                        i_clear_cache, i_stall_n;
61 48 dgisselq
        input           [(AW-1):0]       i_pc;
62 2 dgisselq
        output  reg     [(BUSW-1):0]     o_i;
63 48 dgisselq
        output  reg     [(AW-1):0]       o_pc;
64 2 dgisselq
        output  wire                    o_v;
65
        //
66
        output  reg             o_wb_cyc, o_wb_stb;
67
        output  wire            o_wb_we;
68 48 dgisselq
        output  reg     [(AW-1):0]       o_wb_addr;
69 2 dgisselq
        output  wire    [(BUSW-1):0]     o_wb_data;
70
        //
71 36 dgisselq
        input                   i_wb_ack, i_wb_stall, i_wb_err;
72 2 dgisselq
        input           [(BUSW-1):0]     i_wb_data;
73 3 dgisselq
        //
74
        // Is the (data) memory unit also requesting access to the bus?
75
        input                           i_wb_request;
76 36 dgisselq
        output  wire                    o_illegal;
77 2 dgisselq
 
78 36 dgisselq
        assign  o_illegal = 1'b0;
79
 
80 2 dgisselq
        // Fixed bus outputs: we read from the bus only, never write.
81
        // Thus the output data is ... irrelevant and don't care.  We set it
82
        // to zero just to set it to something.
83
        assign  o_wb_we = 1'b0;
84
        assign  o_wb_data = 0;
85
 
86 48 dgisselq
        reg     [(AW-1):0]               r_cache_base;
87 2 dgisselq
        reg     [(LGCACHELEN):0] r_nvalid, r_acks_waiting;
88
        reg     [(BUSW-1):0]             cache[0:(CACHELEN-1)];
89
 
90 3 dgisselq
        reg     [(LGCACHELEN-1):0]       r_cache_offset;
91 2 dgisselq
 
92
        reg                     r_addr_set;
93 48 dgisselq
        reg     [(AW-1):0]       r_addr;
94 2 dgisselq
 
95 48 dgisselq
        wire    [(AW-1):0]       bus_nvalid;
96
        assign  bus_nvalid = { {(AW-LGCACHELEN-1){1'b0}}, r_nvalid };
97 2 dgisselq
 
98 3 dgisselq
        // What are some of the conditions for which we need to restart the
99
        // cache?
100
        wire    w_pc_out_of_bounds;
101
        assign  w_pc_out_of_bounds = ((i_new_pc)&&((r_nvalid == 0)
102
                                        ||(i_pc < r_cache_base)
103 48 dgisselq
                                        ||(i_pc >= r_cache_base + CACHELEN)
104
                                        ||(i_pc >= r_cache_base + bus_nvalid+5)));
105 3 dgisselq
        wire    w_ran_off_end_of_cache;
106
        assign  w_ran_off_end_of_cache =((r_addr_set)&&((r_addr < r_cache_base)
107 48 dgisselq
                                        ||(r_addr >= r_cache_base + CACHELEN)
108
                                        ||(r_addr >= r_cache_base + bus_nvalid+5)));
109 3 dgisselq
        wire    w_running_out_of_cache;
110
        assign  w_running_out_of_cache = (r_addr_set)
111
                        &&(r_addr >= r_cache_base + (1<<(LGCACHELEN-2))
112 48 dgisselq
                                                + (1<<(LGCACHELEN-1)))
113
                        &&(|r_nvalid[(LGCACHELEN):(LGCACHELEN-1)]);
114
 
115 3 dgisselq
        initial r_cache_base = RESET_ADDRESS;
116 2 dgisselq
        always @(posedge i_clk)
117
        begin
118 18 dgisselq
                if ((i_rst)||(i_clear_cache))
119 3 dgisselq
                begin
120 2 dgisselq
                        o_wb_cyc <= 1'b0;
121 18 dgisselq
                        o_wb_stb <= 1'b0;
122 3 dgisselq
                        // r_cache_base <= RESET_ADDRESS;
123
                // end else if ((~o_wb_cyc)&&(i_new_pc)&&(r_nvalid != 0)
124
                //              &&(i_pc >= r_cache_base)
125
                //              &&(i_pc < r_cache_base + bus_nvalid))
126
                // begin
127 2 dgisselq
                        // The new instruction is in our cache, do nothing
128
                        // with the bus here.
129 3 dgisselq
                end else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
130 2 dgisselq
                begin
131
                        // We need to abandon our bus action to start over in
132
                        // a new region, setting up a new cache.  This may
133
                        // happen mid cycle while waiting for a result.  By
134
                        // dropping o_wb_cyc, we state that we are no longer
135
                        // interested in that result--whatever it might be.
136
                        o_wb_cyc <= 1'b0;
137
                        o_wb_stb <= 1'b0;
138 3 dgisselq
                end else if ((~o_wb_cyc)&&(~r_nvalid[LGCACHELEN])&&(~i_wb_request)&&(r_addr_set))
139
                begin
140
                        // Restart a bus cycle that was interrupted when the
141
                        // data section wanted access to our bus.
142
                        o_wb_cyc <= 1'b1;
143
                        o_wb_stb <= 1'b1;
144
                        // o_wb_addr <= r_cache_base + bus_nvalid;
145 2 dgisselq
                end else if ((~o_wb_cyc)&&(
146 3 dgisselq
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
147 2 dgisselq
                begin
148
                        // Start a bus transaction
149
                        o_wb_cyc <= 1'b1;
150
                        o_wb_stb <= 1'b1;
151 3 dgisselq
                        // o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
152
                        // r_nvalid <= 0;
153
                        // r_cache_base <= (i_new_pc) ? i_pc : r_addr;
154
                        // r_cache_offset <= 0;
155
                end else if ((~o_wb_cyc)&&(w_running_out_of_cache))
156 2 dgisselq
                begin
157
                        // If we're using the last quarter of the cache, then
158
                        // let's start a bus transaction to extend the cache.
159
                        o_wb_cyc <= 1'b1;
160
                        o_wb_stb <= 1'b1;
161 3 dgisselq
                        // o_wb_addr <= r_cache_base + (1<<(LGCACHELEN));
162
                        // r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
163
                        // r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
164
                        // r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
165 2 dgisselq
                end else if (o_wb_cyc)
166
                begin
167
                        // This handles everything ... but the case where
168
                        // while reading we need to extend our cache.
169
                        if ((o_wb_stb)&&(~i_wb_stall))
170
                        begin
171 3 dgisselq
                                // o_wb_addr <= o_wb_addr + 1;
172
                                if ((o_wb_addr - r_cache_base >= CACHELEN-1)
173
                                        ||(i_wb_request))
174 2 dgisselq
                                        o_wb_stb <= 1'b0;
175
                        end
176
 
177
                        if (i_wb_ack)
178
                        begin
179 3 dgisselq
                                // r_nvalid <= r_nvalid + 1;
180 2 dgisselq
                                if ((r_acks_waiting == 1)&&(~o_wb_stb))
181
                                        o_wb_cyc <= 1'b0;
182 36 dgisselq
                        end else if ((r_acks_waiting == 0)&&(~o_wb_stb))
183
                                o_wb_cyc <= 1'b0;
184 2 dgisselq
                end
185
        end
186
 
187 36 dgisselq
        initial r_nvalid = 0;
188 3 dgisselq
        always @(posedge i_clk)
189 18 dgisselq
                if ((i_rst)||(i_clear_cache)) // Required, so we can reload memoy and then reset
190 11 dgisselq
                        r_nvalid <= 0;
191
                else if ((~o_wb_cyc)&&(
192 3 dgisselq
                                (w_pc_out_of_bounds)||(w_ran_off_end_of_cache)))
193
                        r_nvalid <= 0;
194
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
195
                        r_nvalid <= r_nvalid - (1<<(LGCACHELEN-2));
196
                else if ((o_wb_cyc)&&(i_wb_ack))
197
                        r_nvalid <= r_nvalid+1;
198
 
199
        always @(posedge i_clk)
200 18 dgisselq
                if (i_clear_cache)
201
                        r_cache_base <= i_pc;
202
                else if ((~o_wb_cyc)&&(
203
                                (w_pc_out_of_bounds)
204
                                ||(w_ran_off_end_of_cache)))
205 3 dgisselq
                        r_cache_base <= (i_new_pc) ? i_pc : r_addr;
206
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
207
                        r_cache_base <= r_cache_base + (1<<(LGCACHELEN-2));
208
 
209
        always @(posedge i_clk)
210 18 dgisselq
                if (i_clear_cache)
211 3 dgisselq
                        r_cache_offset <= 0;
212 18 dgisselq
                else if ((~o_wb_cyc)&&(
213
                                (w_pc_out_of_bounds)
214
                                ||(w_ran_off_end_of_cache)))
215
                        r_cache_offset <= 0;
216 3 dgisselq
                else if ((~o_wb_cyc)&&(w_running_out_of_cache))
217
                        r_cache_offset <= r_cache_offset + (1<<(LGCACHELEN-2));
218
 
219
        always @(posedge i_clk)
220 18 dgisselq
                if (i_clear_cache)
221
                        o_wb_addr <= i_pc;
222 38 dgisselq
                else if ((o_wb_cyc)&&(w_pc_out_of_bounds))
223
                begin
224
                        if (i_wb_ack)
225
                                o_wb_addr <= r_cache_base + bus_nvalid+1;
226
                        else
227
                                o_wb_addr <= r_cache_base + bus_nvalid;
228
                end else if ((~o_wb_cyc)&&((w_pc_out_of_bounds)
229 3 dgisselq
                                        ||(w_ran_off_end_of_cache)))
230
                        o_wb_addr <= (i_new_pc) ? i_pc : r_addr;
231
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
232
                        o_wb_addr <= o_wb_addr + 1;
233
 
234
        initial r_acks_waiting = 0;
235
        always @(posedge i_clk)
236
                if (~o_wb_cyc)
237
                        r_acks_waiting <= 0;
238 38 dgisselq
                else if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall)&&(~i_wb_ack))
239 36 dgisselq
                        r_acks_waiting <= r_acks_waiting + 1;
240 38 dgisselq
                else if ((o_wb_cyc)&&(i_wb_ack)&&((~o_wb_stb)||(i_wb_stall)))
241 36 dgisselq
                        r_acks_waiting <= r_acks_waiting - 1;
242 3 dgisselq
 
243
        always @(posedge i_clk)
244
                if ((o_wb_cyc)&&(i_wb_ack))
245
                        cache[r_nvalid[(LGCACHELEN-1):0]+r_cache_offset]
246
                                        <= i_wb_data;
247
 
248 2 dgisselq
        initial r_addr_set = 1'b0;
249
        always @(posedge i_clk)
250 18 dgisselq
                if ((i_rst)||(i_clear_cache))
251 2 dgisselq
                        r_addr_set <= 1'b0;
252
                else if (i_new_pc)
253
                        r_addr_set <= 1'b1;
254
 
255
        // Now, read from the cache
256
        wire    w_cv;   // Cache valid, address is in the cache
257
        reg     r_cv;
258
        assign  w_cv = ((r_nvalid != 0)&&(r_addr>=r_cache_base)
259
                        &&(r_addr-r_cache_base < bus_nvalid));
260
        always @(posedge i_clk)
261 36 dgisselq
                r_cv <= (~i_new_pc)&&((w_cv)||((~i_stall_n)&&(r_cv)));
262 2 dgisselq
        assign  o_v = (r_cv)&&(~i_new_pc);
263
 
264
        always @(posedge i_clk)
265
                if (i_new_pc)
266
                        r_addr <= i_pc;
267 36 dgisselq
                else if ( ((i_stall_n)&&(w_cv)) || ((~i_stall_n)&&(w_cv)&&(r_addr == o_pc)) )
268 2 dgisselq
                        r_addr <= r_addr + 1;
269
 
270
        wire    [(LGCACHELEN-1):0]       c_rdaddr, c_cache_base;
271
        assign  c_cache_base   = r_cache_base[(LGCACHELEN-1):0];
272 3 dgisselq
        assign  c_rdaddr = r_addr[(LGCACHELEN-1):0]-c_cache_base+r_cache_offset;
273 2 dgisselq
        always @(posedge i_clk)
274 36 dgisselq
                if ((~o_v)||((i_stall_n)&&(o_v)))
275 2 dgisselq
                        o_i <= cache[c_rdaddr];
276
        always @(posedge i_clk)
277 36 dgisselq
                if ((~o_v)||((i_stall_n)&&(o_v)))
278 2 dgisselq
                        o_pc <= r_addr;
279
 
280
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.