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[/] [zipcpu/] [trunk/] [rtl/] [core/] [prefetch.v] - Blame information for rev 130

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////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    prefetch.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is a very simple instruction fetch approach.  It gets
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//              one instruction at a time.  Future versions should pipeline
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//              fetches and perhaps even cache results--this doesn't do that.
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//              It should, however, be simple enough to get things running.
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//
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//              The interface is fascinating.  The 'i_pc' input wire is just
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//              a suggestion of what to load.  Other wires may be loaded
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//              instead. i_pc is what must be output, not necessarily input.
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//
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//      20150919 -- Added support for the WB error signal.  When reading an
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//              instruction results in this signal being raised, the pipefetch
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//              module will set an illegal instruction flag to be returned to
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//              the CPU together with the instruction.  Hence, the ZipCPU
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//              can trap on it if necessary.
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Flash requires a minimum of 4 clocks per byte to read, so that would be
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// 4*(4bytes/32bit word) = 16 clocks per word read---and that's in pipeline
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// mode which this prefetch does not support.  In non--pipelined mode, the
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// flash will require (16+6+6)*2 = 56 clocks plus 16 clocks per word read,
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// or 72 clocks to fetch one instruction.
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module  prefetch(i_clk, i_rst, i_ce, i_stalled_n, i_pc, i_aux,
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                        o_i, o_pc, o_aux, o_valid, o_illegal,
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                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
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                        i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
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        parameter               ADDRESS_WIDTH=32, AUX_WIDTH = 1, AW=ADDRESS_WIDTH;
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        input                           i_clk, i_rst, i_ce, i_stalled_n;
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        input           [(AW-1):0]       i_pc;
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        input   [(AUX_WIDTH-1):0]        i_aux;
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        output  reg     [31:0]           o_i;
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        output  reg     [(AW-1):0]       o_pc;
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        output  reg [(AUX_WIDTH-1):0]    o_aux;
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        output  reg                     o_valid, o_illegal;
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        // Wishbone outputs
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        output  reg                     o_wb_cyc, o_wb_stb;
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        output  wire                    o_wb_we;
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        output  reg     [(AW-1):0]       o_wb_addr;
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        output  wire    [31:0]           o_wb_data;
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        // And return inputs
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        input                   i_wb_ack, i_wb_stall, i_wb_err;
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        input           [31:0]   i_wb_data;
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        assign  o_wb_we = 1'b0;
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        assign  o_wb_data = 32'h0000;
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        // Let's build it simple and upgrade later: For each instruction
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        // we do one bus cycle to get the instruction.  Later we should
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        // pipeline this, but for now let's just do one at a time.
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        initial o_wb_cyc = 1'b0;
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        initial o_wb_stb = 1'b0;
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        initial o_wb_addr= 0;
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        always @(posedge i_clk)
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                if ((i_rst)||(i_wb_ack))
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                begin
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                        o_wb_cyc <= 1'b0;
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                        o_wb_stb <= 1'b0;
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                end else if ((i_ce)&&(~o_wb_cyc)) // Initiate a bus cycle
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                begin
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                        o_wb_cyc <= 1'b1;
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                        o_wb_stb <= 1'b1;
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                end else if (o_wb_cyc) // Independent of ce
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                begin
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                        if ((o_wb_cyc)&&(o_wb_stb)&&(~i_wb_stall))
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                                o_wb_stb <= 1'b0;
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                        if (i_wb_ack)
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                                o_wb_cyc <= 1'b0;
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                end
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        always @(posedge i_clk)
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                if (i_rst) // Set the address to guarantee the result is invalid
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                        o_wb_addr <= {(AW){1'b1}};
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                else if ((i_ce)&&(~o_wb_cyc))
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                        o_wb_addr <= i_pc;
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        always @(posedge i_clk)
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                if ((o_wb_cyc)&&(i_wb_ack))
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                        o_aux <= i_aux;
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        always @(posedge i_clk)
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                if ((o_wb_cyc)&&(i_wb_ack))
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                        o_i <= i_wb_data;
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        always @(posedge i_clk)
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                if ((o_wb_cyc)&&(i_wb_ack))
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                        o_pc <= o_wb_addr;
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        initial o_valid   = 1'b0;
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        initial o_illegal = 1'b0;
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        always @(posedge i_clk)
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                if ((o_wb_cyc)&&(i_wb_ack))
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                begin
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                        o_valid <= (i_pc == o_wb_addr)&&(~i_wb_err);
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                        o_illegal <= i_wb_err;
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                end else if (i_stalled_n)
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                begin
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                        o_valid <= 1'b0;
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                        o_illegal <= 1'b0;
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                end
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endmodule

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