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///////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipcpu.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is the top level module holding the core of the Zip CPU
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//              together.  The Zip CPU is designed to be as simple as possible.
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//      (actual implementation aside ...)  The instruction set is about as
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//      RISC as you can get, there are only 16 instruction types supported.
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//      Please see the accompanying spec.pdf file for a description of these
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//      instructions.
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//
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//      All instructions are 32-bits wide.  All bus accesses, both address and
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//      data, are 32-bits over a wishbone bus.
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//
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//      The Zip CPU is fully pipelined with the following pipeline stages:
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//
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//              1. Prefetch, returns the instruction from memory. 
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//
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//              2. Instruction Decode
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//
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//              3. Read Operands
24
//
25
//              4. Apply Instruction
26
//
27
//              4. Write-back Results
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//
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//      Further information about the inner workings of this CPU may be
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//      found in the spec.pdf file.  (The documentation within this file
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//      had become out of date and out of sync with the spec.pdf, so look
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//      to the spec.pdf for accurate and up to date information.)
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//
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//
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//      In general, the pipelining is controlled by three pieces of logic
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//      per stage: _ce, _stall, and _valid.  _valid means that the stage
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//      holds a valid instruction.  _ce means that the instruction from the
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//      previous stage is to move into this one, and _stall means that the
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//      instruction from the previous stage may not move into this one.
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//      The difference between these control signals allows individual stages
41
//      to propagate instructions independently.  In general, the logic works
42
//      as:
43
//
44
//
45
//      assign  (n)_ce = (n-1)_valid && (~(n)_stall)
46
//
47
//
48
//      always @(posedge i_clk)
49
//              if ((i_rst)||(clear_pipeline))
50
//                      (n)_valid = 0
51
//              else if (n)_ce
52
//                      (n)_valid = 1
53
//              else if (n+1)_ce
54
//                      (n)_valid = 0
55
//
56
//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )
57
//                      || (  (n)_valid && (n+1)_stall );
58
//
59
//      and ...
60
//
61
//      always @(posedge i_clk)
62
//              if (n)_ce
63
//                      (n)_variable = ... whatever logic for this stage
64
//
65
//      Note that a stage can stall even if no instruction is loaded into
66
//      it.
67
//
68
//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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///////////////////////////////////////////////////////////////////////////////
73
//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
85
//
86
// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
88
//
89
//
90
///////////////////////////////////////////////////////////////////////////////
91
//
92 36 dgisselq
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
93
// fetches are more complicated and therefore use more FPGA resources, while
94
// single fetches will cause the CPU to stall for about 5 stalls each 
95
// instruction cycle, effectively reducing the instruction count per clock to
96
// about 0.2.  However, the area cost may be worth it.  Consider:
97
//
98
//      Slice LUTs              ZipSystem       ZipCPU
99
//      Single Fetching         2521            1734
100
//      Pipelined fetching      2796            2046
101
//
102
//
103
//
104 25 dgisselq
`define CPU_CC_REG      4'he
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`define CPU_PC_REG      4'hf
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`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error
107
`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero
108
`define CPU_BUSERR_BIT  10      // Bus error flag, set on error
109
`define CPU_TRAP_BIT    9       // User TRAP has taken place
110
`define CPU_ILL_BIT     8       // Illegal instruction
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`define CPU_BREAK_BIT   7
112 69 dgisselq
`define CPU_STEP_BIT    6       // Will step one or two (VLIW) instructions
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`define CPU_GIE_BIT     5
114
`define CPU_SLEEP_BIT   4
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// Compile time defines
116 56 dgisselq
//
117
`include "cpudefs.v"
118
//
119 65 dgisselq
//
120 2 dgisselq
module  zipcpu(i_clk, i_rst, i_interrupt,
121
                // Debug interface
122 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
123
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
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                        o_break,
125
                // CPU interface to the wishbone bus
126 36 dgisselq
                o_wb_gbl_cyc, o_wb_gbl_stb,
127
                        o_wb_lcl_cyc, o_wb_lcl_stb,
128
                        o_wb_we, o_wb_addr, o_wb_data,
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                        i_wb_ack, i_wb_stall, i_wb_data,
130 36 dgisselq
                        i_wb_err,
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                // Accounting/CPU usage interface
132 65 dgisselq
                o_op_stall, o_pf_stall, o_i_count
133
`ifdef  DEBUG_SCOPE
134
                , o_debug
135
`endif
136
                );
137 48 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=24,
138 69 dgisselq
                        LGICACHE=6;
139 56 dgisselq
`ifdef  OPT_MULTIPLY
140
        parameter       IMPLEMENT_MPY = 1;
141
`else
142
        parameter       IMPLEMENT_MPY = 0;
143
`endif
144 71 dgisselq
`ifdef  OPT_DIVIDE
145
        parameter       IMPLEMENT_DIVIDE = 1;
146
`else
147
        parameter       IMPLEMENT_DIVIDE = 0;
148
`endif
149
`ifdef  OPT_IMPLEMENT_FPU
150
        parameter       IMPLEMENT_FPU = 1,
151
`else
152
        parameter       IMPLEMENT_FPU = 0,
153
`endif
154 69 dgisselq
                        IMPLEMENT_LOCK=1;
155
`ifdef  OPT_EARLY_BRANCHING
156
        parameter       EARLY_BRANCHING = 1;
157
`else
158
        parameter       EARLY_BRANCHING = 0;
159
`endif
160
        parameter       AW=ADDRESS_WIDTH;
161 2 dgisselq
        input                   i_clk, i_rst, i_interrupt;
162
        // Debug interface -- inputs
163 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
164 2 dgisselq
        input           [4:0]    i_dbg_reg;
165
        input                   i_dbg_we;
166
        input           [31:0]   i_dbg_data;
167
        // Debug interface -- outputs
168
        output  reg             o_dbg_stall;
169
        output  reg     [31:0]   o_dbg_reg;
170 56 dgisselq
        output  reg     [3:0]    o_dbg_cc;
171 2 dgisselq
        output  wire            o_break;
172
        // Wishbone interface -- outputs
173 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
174
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
175 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
176
        output  wire    [31:0]   o_wb_data;
177 2 dgisselq
        // Wishbone interface -- inputs
178
        input                   i_wb_ack, i_wb_stall;
179
        input           [31:0]   i_wb_data;
180 36 dgisselq
        input                   i_wb_err;
181 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
182 9 dgisselq
        output  wire            o_op_stall;
183 2 dgisselq
        output  wire            o_pf_stall;
184 9 dgisselq
        output  wire            o_i_count;
185 56 dgisselq
        //
186 65 dgisselq
`ifdef  DEBUG_SCOPE
187 56 dgisselq
        output  reg     [31:0]   o_debug;
188 65 dgisselq
`endif
189 2 dgisselq
 
190 25 dgisselq
 
191 2 dgisselq
        // Registers
192 56 dgisselq
        //
193
        //      The distributed RAM style comment is necessary on the
194
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
195
        // set and in the process ruining everything else.  It basically
196
        // optimizes logic away, to where it no longer works.  The logic
197
        // as described herein will work, this just makes sure XST implements
198
        // that logic.
199
        //
200
        (* ram_style = "distributed" *)
201 2 dgisselq
        reg     [31:0]   regset [0:31];
202 9 dgisselq
 
203
        // Condition codes
204 56 dgisselq
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
205
        reg     [3:0]    flags, iflags;
206 83 dgisselq
        wire    [13:0]   w_uflags, w_iflags;
207 25 dgisselq
        reg             trap, break_en, step, gie, sleep;
208 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
209 65 dgisselq
        reg             ill_err_u, ill_err_i;
210 38 dgisselq
`else
211 65 dgisselq
        wire            ill_err_u, ill_err_i;
212 36 dgisselq
`endif
213 65 dgisselq
        reg             ibus_err_flag, ubus_err_flag;
214 69 dgisselq
        wire            idiv_err_flag, udiv_err_flag;
215
        wire            ifpu_err_flag, ufpu_err_flag;
216
        wire            ihalt_phase, uhalt_phase;
217 2 dgisselq
 
218 9 dgisselq
        // The master chip enable
219
        wire            master_ce;
220 2 dgisselq
 
221
        //
222
        //
223
        //      PIPELINE STAGE #1 :: Prefetch
224
        //              Variable declarations
225
        //
226 48 dgisselq
        reg     [(AW-1):0]       pf_pc;
227 69 dgisselq
        reg     new_pc;
228 18 dgisselq
        wire    clear_pipeline;
229 69 dgisselq
        assign  clear_pipeline = new_pc || i_clear_pf_cache;
230 9 dgisselq
 
231
        wire            dcd_stalled;
232 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
233 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
234
        wire    [31:0]           pf_data;
235
        wire    [31:0]           instruction;
236
        wire    [(AW-1):0]       instruction_pc;
237 36 dgisselq
        wire    pf_valid, instruction_gie, pf_illegal;
238 2 dgisselq
 
239
        //
240
        //
241
        //      PIPELINE STAGE #2 :: Instruction Decode
242
        //              Variable declarations
243
        //
244
        //
245 83 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu;
246 69 dgisselq
        reg             opvalid_div, opvalid_fpu;
247
        wire            op_stall, dcd_ce, dcd_phase;
248
        wire    [3:0]    dcdOp;
249
        wire    [4:0]    dcdA, dcdB, dcdR;
250
        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
251
        wire    [3:0]    dcdF;
252
        wire            dcdR_wr, dcdA_rd, dcdB_rd,
253
                                dcdALU, dcdM, dcdDV, dcdFP,
254 71 dgisselq
                                dcdF_wr, dcd_gie, dcd_break, dcd_lock,
255 105 dgisselq
                                dcd_pipe, dcd_ljmp;
256 69 dgisselq
        reg             r_dcdvalid;
257
        wire            dcdvalid;
258
        wire    [(AW-1):0]       dcd_pc;
259
        wire    [31:0]   dcdI;
260
        wire            dcd_zI; // true if dcdI == 0
261 2 dgisselq
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
262
 
263 69 dgisselq
        wire    dcd_illegal;
264
        wire                    dcd_early_branch;
265 48 dgisselq
        wire    [(AW-1):0]       dcd_branch_pc;
266 2 dgisselq
 
267
 
268
        //
269
        //
270
        //      PIPELINE STAGE #3 :: Read Operands
271
        //              Variable declarations
272
        //
273
        //
274
        //
275
        // Now, let's read our operands
276
        reg     [4:0]    alu_reg;
277
        reg     [3:0]    opn;
278
        reg     [4:0]    opR;
279 48 dgisselq
        reg     [31:0]   r_opA, r_opB;
280
        reg     [(AW-1):0]       op_pc;
281 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
282 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
283 56 dgisselq
        reg             opR_wr, opR_cc, opF_wr, op_gie;
284 83 dgisselq
        wire    [13:0]   opFl;
285 56 dgisselq
        reg     [5:0]    r_opF;
286
        wire    [7:0]    opF;
287 69 dgisselq
        wire            op_ce, op_phase;
288 56 dgisselq
        // Some pipeline control wires
289 69 dgisselq
`ifdef  OPT_PIPELINED
290 56 dgisselq
        reg     opA_alu, opA_mem;
291
        reg     opB_alu, opB_mem;
292
`endif
293 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
294 36 dgisselq
        reg     op_illegal;
295
`endif
296 69 dgisselq
        reg     op_break;
297
        wire    op_lock;
298 2 dgisselq
 
299
 
300
        //
301
        //
302
        //      PIPELINE STAGE #4 :: ALU / Memory
303
        //              Variable declarations
304
        //
305
        //
306 48 dgisselq
        reg     [(AW-1):0]       alu_pc;
307 69 dgisselq
        reg             alu_pc_valid;
308
        wire            alu_phase;
309 2 dgisselq
        wire            alu_ce, alu_stall;
310
        wire    [31:0]   alu_result;
311
        wire    [3:0]    alu_flags;
312 71 dgisselq
        wire            alu_valid, alu_busy;
313 2 dgisselq
        wire            set_cond;
314
        reg             alu_wr, alF_wr, alu_gie;
315 56 dgisselq
        wire            alu_illegal_op;
316 38 dgisselq
        wire            alu_illegal;
317 2 dgisselq
 
318
 
319
 
320
        wire    mem_ce, mem_stalled;
321 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
322
        wire    mem_pipe_stalled;
323
`endif
324 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
325
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
326 48 dgisselq
        wire    [4:0]            mem_wreg;
327 9 dgisselq
 
328 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
329
        wire    [(AW-1):0]       mem_addr;
330
        wire    [31:0]           mem_data, mem_result;
331 2 dgisselq
 
332 69 dgisselq
        wire    div_ce, div_error, div_busy, div_valid;
333
        wire    [31:0]   div_result;
334
        wire    [3:0]    div_flags;
335 2 dgisselq
 
336 69 dgisselq
        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
337
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
338
                                &&(set_cond);
339 2 dgisselq
 
340 69 dgisselq
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
341
        wire    [31:0]   fpu_result;
342
        wire    [3:0]    fpu_flags;
343
 
344
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
345
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
346
                                &&(set_cond);
347
 
348
 
349 2 dgisselq
        //
350
        //
351
        //      PIPELINE STAGE #5 :: Write-back
352
        //              Variable declarations
353
        //
354 25 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
355 2 dgisselq
        wire    [4:0]    wr_reg_id;
356
        wire    [31:0]   wr_reg_vl;
357
        wire    w_switch_to_interrupt, w_release_from_interrupt;
358 48 dgisselq
        reg     [(AW-1):0]       upc, ipc;
359 2 dgisselq
 
360
 
361
 
362
        //
363
        //      MASTER: clock enable.
364
        //
365 38 dgisselq
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
366 2 dgisselq
 
367
 
368
        //
369
        //      PIPELINE STAGE #1 :: Prefetch
370
        //              Calculate stall conditions
371 65 dgisselq
        //
372
        //      These are calculated externally, within the prefetch module.
373
        //
374 2 dgisselq
 
375
        //
376
        //      PIPELINE STAGE #2 :: Instruction Decode
377
        //              Calculate stall conditions
378 69 dgisselq
`ifdef  OPT_PIPELINED
379
        assign          dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
380
`else
381
        assign          dcd_ce = 1'b1;
382
`endif
383
`ifdef  OPT_PIPELINED
384
        assign          dcd_stalled = (dcdvalid)&&(op_stall);
385
`else
386
        // If not pipelined, there will be no opvalid_ anything, and the
387
        // op_stall will be false, dcdX_stall will be false, thus we can simply
388
        // do a ...
389
        assign          dcd_stalled = 1'b0;
390
`endif
391 2 dgisselq
        //
392
        //      PIPELINE STAGE #3 :: Read Operands
393
        //              Calculate stall conditions
394 69 dgisselq
        wire    op_lock_stall;
395
`ifdef  OPT_PIPELINED
396
        assign  op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
397
                        // Stall if we're stopped, and not allowed to execute
398
                        // an instruction
399
                        // (~master_ce)         // Already captured in alu_stall
400
                        //
401 56 dgisselq
                        // Stall if going into the ALU and the ALU is stalled
402
                        //      i.e. if the memory is busy, or we are single
403 69 dgisselq
                        //      stepping.  This also includes our stalls for
404
                        //      op_break and op_lock, so we don't need to
405
                        //      include those as well here.
406 83 dgisselq
                        // This also includes whether or not the divide or
407
                        // floating point units are busy.
408
                        (alu_stall)
409 56 dgisselq
                        //
410
                        // Stall if we are going into memory with an operation
411
                        //      that cannot be pipelined, and the memory is
412
                        //      already busy
413 83 dgisselq
                        ||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
414 69 dgisselq
                        )
415
                        ||(dcdvalid)&&(
416 71 dgisselq
                                // Stall if we need to wait for an operand A
417 69 dgisselq
                                // to be ready to read
418 71 dgisselq
                                (dcdA_stall)
419 69 dgisselq
                                // Likewise for B, also includes logic
420
                                // regarding immediate offset (register must
421
                                // be in register file if we need to add to
422
                                // an immediate)
423
                                ||(dcdB_stall)
424
                                // Or if we need to wait on flags to work on the
425
                                // CC register
426
                                ||(dcdF_stall)
427
                        );
428 71 dgisselq
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
429 65 dgisselq
`else
430 69 dgisselq
        assign  op_stall = (opvalid)&&(~master_ce);
431 71 dgisselq
        assign  op_ce = ((dcdvalid)||(dcd_illegal));
432 65 dgisselq
`endif
433 2 dgisselq
 
434
        //
435
        //      PIPELINE STAGE #4 :: ALU / Memory
436
        //              Calculate stall conditions
437 36 dgisselq
        //
438
        // 1. Basic stall is if the previous stage is valid and the next is
439
        //      busy.  
440
        // 2. Also stall if the prior stage is valid and the master clock enable
441
        //      is de-selected
442 56 dgisselq
        // 3. Stall if someone on the other end is writing the CC register,
443
        //      since we don't know if it'll put us to sleep or not.
444 36 dgisselq
        // 4. Last case: Stall if we would otherwise move a break instruction
445
        //      through the ALU.  Break instructions are not allowed through
446
        //      the ALU.
447 69 dgisselq
`ifdef  OPT_PIPELINED
448 71 dgisselq
        assign  alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
449 56 dgisselq
                        // Old case #3--this isn't an ALU stall though ...
450
                        ||((opvalid_alu)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
451
                                &&(wr_write_cc)) // Case 3
452 69 dgisselq
                        ||((opvalid)&&(op_lock)&&(op_lock_stall))
453
                        ||((opvalid)&&(op_break))
454
                        ||(div_busy)||(fpu_busy);
455 71 dgisselq
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))
456 69 dgisselq
                                &&(~alu_stall)
457
                                &&(~clear_pipeline);
458
`else
459
        assign  alu_stall = ((~master_ce)&&(opvalid_alu))
460
                                ||((opvalid_alu)&&(op_break));
461 71 dgisselq
        assign  alu_ce = (master_ce)&&((opvalid_alu)||(op_illegal))&&(~alu_stall);
462 69 dgisselq
`endif
463 2 dgisselq
        //
464 65 dgisselq
 
465
        //
466
        // Note: if you change the conditions for mem_ce, you must also change
467
        // alu_pc_valid.
468
        //
469 69 dgisselq
`ifdef  OPT_PIPELINED
470
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
471 71 dgisselq
                        &&(~clear_pipeline);
472 69 dgisselq
`else
473
        // If we aren't pipelined, then no one will be changing what's in the
474
        // pipeline (i.e. clear_pipeline), while our only instruction goes
475
        // through the ... pipeline.
476 71 dgisselq
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled);
477 69 dgisselq
`endif
478 65 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
479 71 dgisselq
        assign  mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
480 38 dgisselq
                                (mem_pipe_stalled)
481
                                ||((~op_pipe)&&(mem_busy))
482 69 dgisselq
                                ||(div_busy)
483
                                ||(fpu_busy)
484 38 dgisselq
                                // Stall waiting for flags to be valid
485
                                // Or waiting for a write to the PC register
486
                                // Or CC register, since that can change the
487
                                //  PC as well
488
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
489
                                        &&((wr_write_pc)||(wr_write_cc)))));
490
`else
491 69 dgisselq
`ifdef  OPT_PIPELINED
492 25 dgisselq
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
493 2 dgisselq
                                (~master_ce)
494
                                // Stall waiting for flags to be valid
495
                                // Or waiting for a write to the PC register
496 25 dgisselq
                                // Or CC register, since that can change the
497
                                //  PC as well
498
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
499 69 dgisselq
`else
500
        assign  mem_stalled = (opvalid_mem)&&(~master_ce);
501 38 dgisselq
`endif
502 69 dgisselq
`endif
503 2 dgisselq
 
504
 
505
        //
506
        //
507
        //      PIPELINE STAGE #1 :: Prefetch
508
        //
509
        //
510 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
511 9 dgisselq
        wire            pf_ce;
512
 
513 69 dgisselq
        assign          pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_valid);
514 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
515 69 dgisselq
                        pf(i_clk, i_rst, (pf_ce), (~dcd_stalled), pf_pc, gie,
516 2 dgisselq
                                instruction, instruction_pc, instruction_gie,
517 36 dgisselq
                                        pf_valid, pf_illegal,
518
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
519
                                pf_ack, pf_stall, pf_err, i_wb_data);
520 69 dgisselq
 
521
        initial r_dcdvalid = 1'b0;
522
        always @(posedge i_clk)
523
                if (i_rst)
524
                        r_dcdvalid <= 1'b0;
525
                else if (dcd_ce)
526 105 dgisselq
                        r_dcdvalid <= (pf_valid);
527
                else if (op_ce)
528 69 dgisselq
                        r_dcdvalid <= 1'b0;
529
        assign  dcdvalid = r_dcdvalid;
530
 
531 2 dgisselq
`else // Pipe fetch
532 69 dgisselq
 
533
`ifdef  OPT_TRADITIONAL_PFCACHE
534
        pfcache #(LGICACHE, ADDRESS_WIDTH)
535 105 dgisselq
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
536 69 dgisselq
                                        i_clear_pf_cache,
537
                                // dcd_pc,
538
                                ~dcd_stalled,
539 105 dgisselq
                                ((dcd_early_branch)&&(~clear_pipeline))
540 69 dgisselq
                                        ? dcd_branch_pc:pf_pc,
541
                                instruction, instruction_pc, pf_valid,
542
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
543
                                        pf_ack, pf_stall, pf_err, i_wb_data,
544
                                pf_illegal);
545
`else
546 48 dgisselq
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
547 105 dgisselq
                        pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
548 36 dgisselq
                                        i_clear_pf_cache, ~dcd_stalled,
549
                                        (new_pc)?pf_pc:dcd_branch_pc,
550 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
551
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
552 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
553 69 dgisselq
//`ifdef        OPT_PRECLEAR_BUS
554
                                //((dcd_clear_bus)&&(dcdvalid))
555
                                //||((op_clear_bus)&&(opvalid))
556
                                //||
557
//`endif
558 36 dgisselq
                                (mem_cyc_lcl)||(mem_cyc_gbl),
559
                                pf_illegal);
560 69 dgisselq
`endif
561 2 dgisselq
        assign  instruction_gie = gie;
562
 
563 69 dgisselq
        initial r_dcdvalid = 1'b0;
564 2 dgisselq
        always @(posedge i_clk)
565 69 dgisselq
                if ((i_rst)||(clear_pipeline))
566
                        r_dcdvalid <= 1'b0;
567 2 dgisselq
                else if (dcd_ce)
568 105 dgisselq
                        r_dcdvalid <= (pf_valid)&&(~clear_pipeline)&&(~dcd_ljmp)&&((~r_dcdvalid)||(~dcd_early_branch));
569 69 dgisselq
                else if (op_ce)
570
                        r_dcdvalid <= 1'b0;
571
        assign  dcdvalid = r_dcdvalid;
572 36 dgisselq
`endif
573 2 dgisselq
 
574 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
575
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
576
                        IMPLEMENT_FPU)
577
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
578
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
579
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
580
                        dcd_illegal, dcd_pc, dcd_gie,
581
                        { dcdR_cc, dcdR_pc, dcdR },
582
                        { dcdA_cc, dcdA_pc, dcdA },
583
                        { dcdB_cc, dcdB_pc, dcdB },
584
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
585
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
586
                        dcdR_wr,dcdA_rd, dcdB_rd,
587
                        dcd_early_branch,
588 105 dgisselq
                        dcd_branch_pc, dcd_ljmp,
589 71 dgisselq
                        dcd_pipe);
590 36 dgisselq
`else
591 69 dgisselq
        idecode_deprecated
592
                #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
593
                        IMPLEMENT_FPU)
594
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
595
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
596
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
597
                        dcd_illegal, dcd_pc, dcd_gie,
598
                        { dcdR_cc, dcdR_pc, dcdR },
599
                        { dcdA_cc, dcdA_pc, dcdA },
600
                        { dcdB_cc, dcdB_pc, dcdB },
601
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
602
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
603
                        dcdR_wr,dcdA_rd, dcdB_rd,
604
                        dcd_early_branch,
605 71 dgisselq
                        dcd_branch_pc,
606
                        dcd_pipe);
607 105 dgisselq
        assign  dcd_ljmp = 1'b0;
608 36 dgisselq
`endif
609 2 dgisselq
 
610 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
611
        reg             op_pipe;
612 2 dgisselq
 
613 38 dgisselq
        initial op_pipe = 1'b0;
614
        // To be a pipeable operation, there must be 
615
        //      two valid adjacent instructions
616
        //      Both must be memory instructions
617
        //      Both must be writes, or both must be reads
618
        //      Both operations must be to the same identical address,
619
        //              or at least a single (one) increment above that address
620 71 dgisselq
        //
621
        // However ... we need to know this before this clock, hence this is
622
        // calculated in the instruction decoder.
623 38 dgisselq
        always @(posedge i_clk)
624
                if (op_ce)
625 71 dgisselq
                        op_pipe <= dcd_pipe;
626 38 dgisselq
`endif
627
 
628 2 dgisselq
        //
629
        //
630
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
631
        //
632
        //
633 25 dgisselq
        assign  w_opA = regset[dcdA];
634
        assign  w_opB = regset[dcdB];
635 56 dgisselq
 
636
        wire    [31:0]   w_pcA_v;
637
        generate
638
        if (AW < 32)
639
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
640
        else
641
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
642
        endgenerate
643 71 dgisselq
 
644
`ifdef  OPT_PIPELINED
645
        reg     [4:0]    opA_id, opB_id;
646
        reg             opA_rd, opB_rd;
647 2 dgisselq
        always @(posedge i_clk)
648 71 dgisselq
                if (op_ce)
649
                begin
650
                        opA_id <= dcdA;
651
                        opB_id <= dcdB;
652
                        opA_rd <= dcdA_rd;
653
                        opB_rd <= dcdB_rd;
654
                end
655
`endif
656
 
657
        always @(posedge i_clk)
658 2 dgisselq
                if (op_ce) // &&(dcdvalid))
659
                begin
660
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
661
                                r_opA <= wr_reg_vl;
662 25 dgisselq
                        else if (dcdA_pc)
663 56 dgisselq
                                r_opA <= w_pcA_v;
664 25 dgisselq
                        else if (dcdA_cc)
665 83 dgisselq
                                r_opA <= { w_opA[31:14], (dcdA[4])?w_uflags:w_iflags };
666 2 dgisselq
                        else
667 25 dgisselq
                                r_opA <= w_opA;
668 69 dgisselq
`ifdef  OPT_PIPELINED
669 71 dgisselq
                end else
670 48 dgisselq
                begin // We were going to pick these up when they became valid,
671
                        // but for some reason we're stuck here as they became
672
                        // valid.  Pick them up now anyway
673 71 dgisselq
                        // if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
674
                                // r_opA <= wr_reg_vl;
675
                        if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))
676 48 dgisselq
                                r_opA <= wr_reg_vl;
677 56 dgisselq
`endif
678 2 dgisselq
                end
679 56 dgisselq
 
680 69 dgisselq
        wire    [31:0]   w_opBnI, w_pcB_v;
681 56 dgisselq
        generate
682
        if (AW < 32)
683
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
684
        else
685
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
686
        endgenerate
687
 
688 36 dgisselq
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
689 56 dgisselq
                : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
690
                : ((dcdB_pc) ? w_pcB_v
691 83 dgisselq
                : ((dcdB_cc) ? { w_opB[31:14], (dcdB[4])?w_uflags:w_iflags}
692 56 dgisselq
                : w_opB)));
693
 
694 2 dgisselq
        always @(posedge i_clk)
695
                if (op_ce) // &&(dcdvalid))
696 36 dgisselq
                        r_opB <= w_opBnI + dcdI;
697 69 dgisselq
`ifdef  OPT_PIPELINED
698 71 dgisselq
                else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
699 48 dgisselq
                        r_opB <= wr_reg_vl;
700 56 dgisselq
`endif
701 2 dgisselq
 
702
        // The logic here has become more complex than it should be, no thanks
703
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
704
        // be two sets of four bits: the top bits specify what bits matter, the
705
        // bottom specify what those top bits must equal.  However, two of
706
        // conditions check whether bits are on, and those are the only two
707
        // conditions checking those bits.  Therefore, Vivado complains that
708
        // these two bits are redundant.  Hence the convoluted expression
709
        // below, arriving at what we finally want in the (now wire net)
710
        // opF.
711
        always @(posedge i_clk)
712
                if (op_ce)
713 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
714 2 dgisselq
                        case(dcdF[2:0])
715 56 dgisselq
                        3'h0:   r_opF <= 6'h00; // Always
716 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
717
                        // These were remapped as part of the new instruction
718
                        // set in order to make certain that the low order
719
                        // two bits contained the most commonly used 
720
                        // conditions: Always, LT, Z, and NZ.
721
                        3'h1:   r_opF <= 6'h24; // LT
722
                        3'h2:   r_opF <= 6'h11; // Z
723
                        3'h3:   r_opF <= 6'h10; // NE
724
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
725
                        3'h5:   r_opF <= 6'h20; // GE (!N)
726
`else
727 56 dgisselq
                        3'h1:   r_opF <= 6'h11; // Z
728
                        3'h2:   r_opF <= 6'h10; // NE
729
                        3'h3:   r_opF <= 6'h20; // GE (!N)
730
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
731
                        3'h5:   r_opF <= 6'h24; // LT
732 69 dgisselq
`endif
733 56 dgisselq
                        3'h6:   r_opF <= 6'h02; // C
734
                        3'h7:   r_opF <= 6'h08; // V
735 2 dgisselq
                        endcase
736 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
737 56 dgisselq
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
738 2 dgisselq
 
739 69 dgisselq
        wire    w_opvalid;
740 105 dgisselq
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp);
741 36 dgisselq
        initial opvalid     = 1'b0;
742
        initial opvalid_alu = 1'b0;
743
        initial opvalid_mem = 1'b0;
744 91 dgisselq
        initial opvalid_div = 1'b0;
745
        initial opvalid_fpu = 1'b0;
746 2 dgisselq
        always @(posedge i_clk)
747
                if (i_rst)
748 25 dgisselq
                begin
749
                        opvalid     <= 1'b0;
750
                        opvalid_alu <= 1'b0;
751
                        opvalid_mem <= 1'b0;
752
                end else if (op_ce)
753
                begin
754 2 dgisselq
                        // Do we have a valid instruction?
755
                        //   The decoder may vote to stall one of its
756
                        //   instructions based upon something we currently
757
                        //   have in our queue.  This instruction must then
758
                        //   move forward, and get a stall cycle inserted.
759
                        //   Hence, the test on dcd_stalled here.  If we must
760
                        //   wait until our operands are valid, then we aren't
761
                        //   valid yet until then.
762 69 dgisselq
                        opvalid<= w_opvalid;
763 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
764 69 dgisselq
                        opvalid_alu <= ((dcdALU)||(dcd_illegal))&&(w_opvalid);
765
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
766
                        opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
767
                        opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
768 36 dgisselq
`else
769 69 dgisselq
                        opvalid_alu <= (dcdALU)&&(w_opvalid);
770
                        opvalid_mem <= (dcdM)&&(w_opvalid);
771
                        opvalid_div <= (dcdDV)&&(w_opvalid);
772
                        opvalid_fpu <= (dcdFP)&&(w_opvalid);
773 36 dgisselq
`endif
774 69 dgisselq
                end else if ((clear_pipeline)||(alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
775 25 dgisselq
                begin
776
                        opvalid     <= 1'b0;
777
                        opvalid_alu <= 1'b0;
778
                        opvalid_mem <= 1'b0;
779 69 dgisselq
                        opvalid_div <= 1'b0;
780
                        opvalid_fpu <= 1'b0;
781 25 dgisselq
                end
782 2 dgisselq
 
783
        // Here's part of our debug interface.  When we recognize a break
784
        // instruction, we set the op_break flag.  That'll prevent this
785
        // instruction from entering the ALU, and cause an interrupt before
786
        // this instruction.  Thus, returning to this code will cause the
787
        // break to repeat and continue upon return.  To get out of this
788
        // condition, replace the break instruction with what it is supposed
789
        // to be, step through it, and then replace it back.  In this fashion,
790
        // a debugger can step through code.
791 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
792
        initial op_break = 1'b0;
793 2 dgisselq
        always @(posedge i_clk)
794 25 dgisselq
                if (i_rst)      op_break <= 1'b0;
795
                else if (op_ce) op_break <= (dcd_break);
796
                else if ((clear_pipeline)||(~opvalid))
797
                                op_break <= 1'b0;
798 2 dgisselq
 
799 69 dgisselq
`ifdef  OPT_PIPELINED
800
        generate
801
        if (IMPLEMENT_LOCK != 0)
802
        begin
803
                reg     r_op_lock, r_op_lock_stall;
804
 
805
                initial r_op_lock_stall = 1'b0;
806
                always @(posedge i_clk)
807
                        if (i_rst)
808
                                r_op_lock_stall <= 1'b0;
809
                        else
810
                                r_op_lock_stall <= (~opvalid)||(~op_lock)
811
                                                ||(~dcdvalid)||(~pf_valid);
812
 
813
                assign  op_lock_stall = r_op_lock_stall;
814
 
815
                initial r_op_lock = 1'b0;
816
                always @(posedge i_clk)
817
                        if (i_rst)
818
                                r_op_lock <= 1'b0;
819
                        else if ((op_ce)&&(dcd_lock))
820
                                r_op_lock <= 1'b1;
821
                        else if ((op_ce)||(clear_pipeline))
822
                                r_op_lock <= 1'b0;
823
                assign  op_lock = r_op_lock;
824
 
825
        end else begin
826
                assign  op_lock_stall = 1'b0;
827
                assign  op_lock = 1'b0;
828
        end endgenerate
829
 
830
`else
831
        assign op_lock_stall = 1'b0;
832
        assign op_lock       = 1'b0;
833
`endif
834
 
835 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
836 71 dgisselq
        initial op_illegal = 1'b0;
837 2 dgisselq
        always @(posedge i_clk)
838 71 dgisselq
                if ((i_rst)||(clear_pipeline))
839
                        op_illegal <= 1'b0;
840
                else if(op_ce)
841 69 dgisselq
`ifdef  OPT_PIPELINED
842
                        op_illegal <=(dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0));
843
`else
844
                        op_illegal <= (dcd_illegal)||(dcd_lock);
845 36 dgisselq
`endif
846 69 dgisselq
`endif
847 36 dgisselq
 
848 71 dgisselq
        // No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
849
        // set, dcd_early_branch will simply be a wire connected to zero and
850
        // this logic should just optimize.
851
        always @(posedge i_clk)
852
                if (op_ce)
853
                begin
854 83 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
855
                                &&(~dcd_early_branch)&&(~dcd_illegal);
856
                        opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
857 71 dgisselq
                end
858 69 dgisselq
 
859 36 dgisselq
        always @(posedge i_clk)
860 2 dgisselq
                if (op_ce)
861
                begin
862
                        opn    <= dcdOp;        // Which ALU operation?
863 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
864 2 dgisselq
                        // What register will these results be written into?
865 69 dgisselq
                        opR    <= dcdR;
866
                        opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
867 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
868
                        op_gie <= dcd_gie;
869
 
870 69 dgisselq
 
871 2 dgisselq
                        //
872 48 dgisselq
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
873 2 dgisselq
                end
874
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
875
 
876 69 dgisselq
`ifdef  OPT_VLIW
877
        reg     r_op_phase;
878
        initial r_op_phase = 1'b0;
879
        always @(posedge i_clk)
880
                if ((i_rst)||(clear_pipeline))
881
                        r_op_phase <= 1'b0;
882
                else if (op_ce)
883
                        r_op_phase <= dcd_phase;
884
        assign  op_phase = r_op_phase;
885
`else
886
        assign  op_phase = 1'b0;
887
`endif
888
 
889 2 dgisselq
        // This is tricky.  First, the PC and Flags registers aren't kept in
890
        // register set but in special registers of their own.  So step one
891
        // is to select the right register.  Step to is to replace that
892
        // register with the results of an ALU or memory operation, if such
893
        // results are now available.  Otherwise, we'd need to insert a wait
894
        // state of some type.
895
        //
896
        // The alternative approach would be to define some sort of
897
        // op_stall wire, which would stall any upstream stage.
898
        // We'll create a flag here to start our coordination.  Once we
899
        // define this flag to something other than just plain zero, then
900
        // the stalls will already be in place.
901 69 dgisselq
`ifdef  OPT_PIPELINED
902 83 dgisselq
        assign  opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))
903 71 dgisselq
                        ?  wr_reg_vl : r_opA;
904 56 dgisselq
`else
905
        assign  opA = r_opA;
906
`endif
907 48 dgisselq
 
908 69 dgisselq
`ifdef  OPT_PIPELINED
909 83 dgisselq
        // Stall if we have decoded an instruction that will read register A
910
        //      AND ... something that may write a register is running
911
        //      AND (series of conditions here ...)
912
        //              The operation might set flags, and we wish to read the
913
        //                      CC register
914
        //              OR ... (No other conditions)
915
        assign  dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere
916
                                &&((opvalid)||(mem_rdbusy)
917
                                        ||(div_busy)||(fpu_busy))
918
                                &&((opF_wr)&&(dcdA_cc));
919 56 dgisselq
`else
920 69 dgisselq
        // There are no pipeline hazards, if we aren't pipelined
921
        assign  dcdA_stall = 1'b0;
922 56 dgisselq
`endif
923 36 dgisselq
 
924 69 dgisselq
`ifdef  OPT_PIPELINED
925 71 dgisselq
        assign  opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))
926
                        ? wr_reg_vl: r_opB;
927 56 dgisselq
`else
928
        assign  opB = r_opB;
929
`endif
930
 
931 69 dgisselq
`ifdef  OPT_PIPELINED
932 83 dgisselq
        // Stall if we have decoded an instruction that will read register B
933
        //      AND ... something that may write a (unknown) register is running
934
        //      AND (series of conditions here ...)
935
        //              The operation might set flags, and we wish to read the
936
        //                      CC register
937
        //              OR the operation might set register B, and we still need
938
        //                      a clock to add the offset to it
939
        assign  dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere
940
                                // If the op stage isn't valid, yet something
941
                                // is running, then it must have been valid.
942
                                // We'll use the last values from that stage
943
                                // (opR_wr, opF_wr, opR) in our logic below.
944
                                &&((opvalid)||(mem_rdbusy)
945
                                        ||(div_busy)||(fpu_busy))
946
                                &&(
947 38 dgisselq
                                // Stall on memory ops writing to my register
948
                                //      (i.e. loads), or on any write to my
949
                                //      register if I have an immediate offset
950
                                // Note the exception for writing to the PC:
951
                                //      if I write to the PC, the whole next
952
                                //      instruction is invalid, not just the
953
                                //      operand.  That'll get wiped in the
954
                                //      next operation anyway, so don't stall
955 83 dgisselq
                                //      here.  This keeps a BC X, BNZ Y from
956
                                //      stalling between the two branches.
957
                                //      BC X, BRA Y is still clear, since BRA Y
958
                                //      is an early branch instruction.
959
                                //      (This exception is commented out in
960
                                //      order to help keep our logic simple, and
961
                                //      because multiple conditional branches
962
                                //      following each other constitutes a
963
                                //      fairly unusualy code structure.)
964
                                //      
965
                                ((~dcd_zI)&&(opR == dcdB)&&(opR_wr))
966
                                        // &&(opR != { op_gie, `CPU_PC_REG } )
967
                                // Stall following any instruction that will
968
                                // set the flags, if we're going to need the
969
                                // flags (CC) register for opB.
970
                                ||((opF_wr)&&(dcdB_cc))
971 38 dgisselq
                                // Stall on any ongoing memory operation that
972 71 dgisselq
                                // will write to opB -- captured above
973
                                // ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
974
                                );
975 91 dgisselq
        assign  dcdF_stall = ((~dcdF[3])
976
                                        ||((dcdA_rd)&&(dcdA_cc))
977
                                        ||((dcdB_rd)&&(dcdB_cc)))
978
                                        &&(opvalid)&&(opR_cc);
979
                                // &&(dcdvalid) is checked for elsewhere
980 56 dgisselq
`else
981 69 dgisselq
        // No stalls without pipelining, 'cause how can you have a pipeline
982
        // hazard without the pipeline?
983
        assign  dcdB_stall = 1'b0;
984 91 dgisselq
        assign  dcdF_stall = 1'b0;
985 56 dgisselq
`endif
986 2 dgisselq
        //
987
        //
988
        //      PIPELINE STAGE #4 :: Apply Instruction
989
        //
990
        //
991 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
992 56 dgisselq
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
993 25 dgisselq
                        (opvalid_alu), opn, opA, opB,
994 71 dgisselq
                        alu_result, alu_flags, alu_valid, alu_illegal_op,
995
                        alu_busy);
996 69 dgisselq
`else
997
        cpuops_deprecated       #(IMPLEMENT_MPY) doalu(i_clk, i_rst, alu_ce,
998
                        (opvalid_alu), opn, opA, opB,
999
                        alu_result, alu_flags, alu_valid, alu_illegal_op);
1000 71 dgisselq
        assign  alu_busy = 1'b0;
1001 69 dgisselq
`endif
1002 2 dgisselq
 
1003 69 dgisselq
        generate
1004
        if (IMPLEMENT_DIVIDE != 0)
1005
        begin
1006 83 dgisselq
                div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0],
1007 69 dgisselq
                        opA, opB, div_busy, div_valid, div_error, div_result,
1008
                        div_flags);
1009
        end else begin
1010
                assign  div_error = 1'b1;
1011
                assign  div_busy  = 1'b0;
1012
                assign  div_valid = 1'b0;
1013
                assign  div_result= 32'h00;
1014
                assign  div_flags = 4'h0;
1015
        end endgenerate
1016
 
1017
        generate
1018
        if (IMPLEMENT_FPU != 0)
1019
        begin
1020
                //
1021
                // sfpu thefpu(i_clk, i_rst, fpu_ce,
1022
                //      opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
1023
                //      fpu_flags);
1024
                //
1025
                assign  fpu_error = 1'b1;
1026
                assign  fpu_busy  = 1'b0;
1027
                assign  fpu_valid = 1'b0;
1028
                assign  fpu_result= 32'h00;
1029
                assign  fpu_flags = 4'h0;
1030
        end else begin
1031
                assign  fpu_error = 1'b1;
1032
                assign  fpu_busy  = 1'b0;
1033
                assign  fpu_valid = 1'b0;
1034
                assign  fpu_result= 32'h00;
1035
                assign  fpu_flags = 4'h0;
1036
        end endgenerate
1037
 
1038
 
1039 2 dgisselq
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
1040
        initial alF_wr   = 1'b0;
1041
        initial alu_wr   = 1'b0;
1042
        always @(posedge i_clk)
1043
                if (i_rst)
1044
                begin
1045
                        alu_wr   <= 1'b0;
1046
                        alF_wr   <= 1'b0;
1047
                end else if (alu_ce)
1048
                begin
1049 65 dgisselq
                        // alu_reg <= opR;
1050 2 dgisselq
                        alu_wr  <= (opR_wr)&&(set_cond);
1051
                        alF_wr  <= (opF_wr)&&(set_cond);
1052 71 dgisselq
                end else if (~alu_busy) begin
1053 2 dgisselq
                        // These are strobe signals, so clear them if not
1054
                        // set for any particular clock
1055 65 dgisselq
                        alu_wr <= (i_halt)&&(i_dbg_we);
1056 2 dgisselq
                        alF_wr <= 1'b0;
1057
                end
1058 69 dgisselq
 
1059
`ifdef  OPT_VLIW
1060
        reg     r_alu_phase;
1061
        initial r_alu_phase = 1'b0;
1062 2 dgisselq
        always @(posedge i_clk)
1063 69 dgisselq
                if (i_rst)
1064
                        r_alu_phase <= 1'b0;
1065
                else if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce))
1066
                        r_alu_phase <= op_phase;
1067
        assign  alu_phase = r_alu_phase;
1068
`else
1069
        assign  alu_phase = 1'b0;
1070
`endif
1071
 
1072
        always @(posedge i_clk)
1073
                if ((alu_ce)||(div_ce)||(fpu_ce))
1074 65 dgisselq
                        alu_reg <= opR;
1075
                else if ((i_halt)&&(i_dbg_we))
1076
                        alu_reg <= i_dbg_reg;
1077 69 dgisselq
 
1078 65 dgisselq
        reg     [31:0]   dbg_val;
1079
        reg             dbgv;
1080
        always @(posedge i_clk)
1081
                dbg_val <= i_dbg_data;
1082
        initial dbgv = 1'b0;
1083
        always @(posedge i_clk)
1084
                dbgv <= (~i_rst)&&(~alu_ce)&&((i_halt)&&(i_dbg_we));
1085
        always @(posedge i_clk)
1086 2 dgisselq
                if ((alu_ce)||(mem_ce))
1087
                        alu_gie  <= op_gie;
1088
        always @(posedge i_clk)
1089 65 dgisselq
                if ((alu_ce)||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
1090
                                &&(~mem_stalled)))
1091 2 dgisselq
                        alu_pc  <= op_pc;
1092 65 dgisselq
 
1093 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1094 56 dgisselq
        reg     r_alu_illegal;
1095
        initial r_alu_illegal = 0;
1096 38 dgisselq
        always @(posedge i_clk)
1097 71 dgisselq
                if (clear_pipeline)
1098
                        r_alu_illegal <= 1'b0;
1099
                else if ((alu_ce)||(mem_ce))
1100 56 dgisselq
                        r_alu_illegal <= op_illegal;
1101
        assign  alu_illegal = (alu_illegal_op)||(r_alu_illegal);
1102 38 dgisselq
`endif
1103
 
1104 65 dgisselq
        // This _almost_ is equal to (alu_ce)||(mem_ce).  The only
1105
        // problem is that mem_ce is gated by the set_cond, and
1106
        // the PC will be valid independent of the set condition.  Hence, this
1107
        // equals (alu_ce)||(everything in mem_ce but the set condition)
1108 2 dgisselq
        initial alu_pc_valid = 1'b0;
1109
        always @(posedge i_clk)
1110 65 dgisselq
                alu_pc_valid <= ((alu_ce)
1111
                        ||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)&&(~mem_stalled)));
1112 2 dgisselq
 
1113 69 dgisselq
        wire    bus_lock;
1114
`ifdef  OPT_PIPELINED
1115
        generate
1116
        if (IMPLEMENT_LOCK != 0)
1117
        begin
1118
                reg     r_bus_lock;
1119
                initial r_bus_lock = 1'b0;
1120
                always @(posedge i_clk)
1121
                        if (i_rst)
1122
                                r_bus_lock <= 1'b0;
1123
                        else if ((op_ce)&&(op_lock))
1124
                                r_bus_lock <= 1'b1;
1125
                        else if (~opvalid_mem)
1126
                                r_bus_lock <= 1'b0;
1127
                assign  bus_lock = r_bus_lock;
1128
        end else begin
1129
                assign  bus_lock = 1'b0;
1130
        end endgenerate
1131
`else
1132
        assign  bus_lock = 1'b0;
1133
`endif
1134
 
1135 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
1136 71 dgisselq
        pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1137 38 dgisselq
                                (opn[0]), opB, opA, opR,
1138
                                mem_busy, mem_pipe_stalled,
1139
                                mem_valid, bus_err, mem_wreg, mem_result,
1140
                        mem_cyc_gbl, mem_cyc_lcl,
1141
                                mem_stb_gbl, mem_stb_lcl,
1142
                                mem_we, mem_addr, mem_data,
1143
                                mem_ack, mem_stall, mem_err, i_wb_data);
1144
 
1145
`else // PIPELINED_BUS_ACCESS
1146 71 dgisselq
        memops  #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1147 2 dgisselq
                                (opn[0]), opB, opA, opR,
1148 38 dgisselq
                                mem_busy,
1149
                                mem_valid, bus_err, mem_wreg, mem_result,
1150 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
1151
                                mem_stb_gbl, mem_stb_lcl,
1152
                                mem_we, mem_addr, mem_data,
1153
                                mem_ack, mem_stall, mem_err, i_wb_data);
1154 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
1155 65 dgisselq
        assign  mem_rdbusy = ((mem_busy)&&(~mem_we));
1156 2 dgisselq
 
1157
        // Either the prefetch or the instruction gets the memory bus, but 
1158
        // never both.
1159 48 dgisselq
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
1160 36 dgisselq
                // Memory access to the arbiter, priority position
1161
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1162
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
1163 2 dgisselq
                // Prefetch access to the arbiter
1164 36 dgisselq
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
1165
                        pf_ack, pf_stall, pf_err,
1166 2 dgisselq
                // Common wires, in and out, of the arbiter
1167 36 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1168
                        o_wb_we, o_wb_addr, o_wb_data,
1169
                        i_wb_ack, i_wb_stall, i_wb_err);
1170 2 dgisselq
 
1171
        //
1172
        //
1173
        //      PIPELINE STAGE #5 :: Write-back results
1174
        //
1175
        //
1176
        // This stage is not allowed to stall.  If results are ready to be
1177
        // written back, they are written back at all cost.  Sleepy CPU's
1178
        // won't prevent write back, nor debug modes, halting the CPU, nor
1179
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1180
        // as knowinig something is available for writeback.
1181
 
1182
        //
1183
        // Write back to our generic register set ...
1184
        // When shall we write back?  On one of two conditions
1185
        //      Note that the flags needed to be checked before issuing the
1186
        //      bus instruction, so they don't need to be checked here.
1187
        //      Further, alu_wr includes (set_cond), so we don't need to
1188
        //      check for that here either.
1189 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1190 83 dgisselq
        assign  wr_reg_ce = (~alu_illegal)&&
1191
                        (((alu_wr)&&(~clear_pipeline)
1192
                                &&((alu_valid)||(div_valid)||(fpu_valid)))
1193
                        ||(mem_valid));
1194 36 dgisselq
`else
1195 69 dgisselq
        assign  wr_reg_ce = ((alu_wr)&&(~clear_pipeline))||(mem_valid)||(div_valid)||(fpu_valid);
1196 36 dgisselq
`endif
1197 2 dgisselq
        // Which register shall be written?
1198 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1199
        //              One or PC, one for CC, and one for GIE match
1200 69 dgisselq
        //      Note that the alu_reg is the register to write on a divide or
1201
        //      FPU operation.
1202 2 dgisselq
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
1203 25 dgisselq
        // Are we writing to the CC register?
1204
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1205 2 dgisselq
        // Are we writing to the PC?
1206
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1207
        // What value to write?
1208 71 dgisselq
        assign  wr_reg_vl = ((mem_valid) ? mem_result
1209
                                :((div_valid|fpu_valid))
1210
                                        ? ((div_valid) ? div_result:fpu_result)
1211
                                :((dbgv) ? dbg_val : alu_result));
1212 2 dgisselq
        always @(posedge i_clk)
1213
                if (wr_reg_ce)
1214
                        regset[wr_reg_id] <= wr_reg_vl;
1215
 
1216
        //
1217
        // Write back to the condition codes/flags register ...
1218
        // When shall we write to our flags register?  alF_wr already
1219
        // includes the set condition ...
1220 69 dgisselq
        assign  wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
1221 83 dgisselq
        assign  w_uflags = { uhalt_phase, ufpu_err_flag,
1222 71 dgisselq
                        udiv_err_flag, ubus_err_flag, trap, ill_err_u,
1223
                        1'b0, step, 1'b1, sleep,
1224
                        ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1225 83 dgisselq
        assign  w_iflags = { ihalt_phase, ifpu_err_flag,
1226 71 dgisselq
                        idiv_err_flag, ibus_err_flag, trap, ill_err_i,
1227
                        break_en, 1'b0, 1'b0, sleep,
1228
                        ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1229 69 dgisselq
 
1230
 
1231 2 dgisselq
        // What value to write?
1232
        always @(posedge i_clk)
1233
                // If explicitly writing the register itself
1234 25 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
1235 2 dgisselq
                        flags <= wr_reg_vl[3:0];
1236
                // Otherwise if we're setting the flags from an ALU operation
1237
                else if ((wr_flags_ce)&&(alu_gie))
1238 69 dgisselq
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1239
                                : alu_flags);
1240 2 dgisselq
 
1241
        always @(posedge i_clk)
1242 25 dgisselq
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1243 2 dgisselq
                        iflags <= wr_reg_vl[3:0];
1244
                else if ((wr_flags_ce)&&(~alu_gie))
1245 69 dgisselq
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1246
                                : alu_flags);
1247 2 dgisselq
 
1248
        // The 'break' enable  bit.  This bit can only be set from supervisor
1249
        // mode.  It control what the CPU does upon encountering a break
1250
        // instruction.
1251
        //
1252
        // The goal, upon encountering a break is that the CPU should stop and
1253
        // not execute the break instruction, choosing instead to enter into
1254
        // either interrupt mode or halt first.  
1255
        //      if ((break_en) AND (break_instruction)) // user mode or not
1256
        //              HALT CPU
1257
        //      else if (break_instruction) // only in user mode
1258
        //              set an interrupt flag, go to supervisor mode
1259
        //              allow supervisor to step the CPU.
1260
        //      Upon a CPU halt, any break condition will be reset.  The
1261
        //      external debugger will then need to deal with whatever
1262
        //      condition has taken place.
1263
        initial break_en = 1'b0;
1264
        always @(posedge i_clk)
1265
                if ((i_rst)||(i_halt))
1266
                        break_en <= 1'b0;
1267 25 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1268 2 dgisselq
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
1269 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1270 36 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
1271
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1272 69 dgisselq
                                &&(~div_busy)&&(~fpu_busy)
1273 36 dgisselq
                                &&(~clear_pipeline)
1274
                        ||((~alu_gie)&&(bus_err))
1275 69 dgisselq
                        ||((~alu_gie)&&(div_valid)&&(div_error))
1276
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error))
1277 71 dgisselq
                        ||((~alu_gie)&&(alu_pc_valid)&&(alu_illegal));
1278 36 dgisselq
`else
1279
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
1280
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1281
                                &&(~clear_pipeline))
1282 118 dgisselq
                        ||((~alu_gie)&&(bus_err))
1283
                        ||((~alu_gie)&&(div_valid)&&(div_error))
1284
                        ||((~alu_gie)&&(fpu_valid)&&(fpu_error));
1285 36 dgisselq
`endif
1286 2 dgisselq
 
1287
 
1288
        // The sleep register.  Setting the sleep register causes the CPU to
1289
        // sleep until the next interrupt.  Setting the sleep register within
1290
        // interrupt mode causes the processor to halt until a reset.  This is
1291 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1292
        // set the sleep bit and switch to supervisor mode in the same 
1293
        // instruction: users are not allowed to halt the CPU.
1294 2 dgisselq
        always @(posedge i_clk)
1295 69 dgisselq
                if ((i_rst)||(w_switch_to_interrupt))
1296 2 dgisselq
                        sleep <= 1'b0;
1297 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1298
                        // In supervisor mode, we have no protections.  The
1299
                        // supervisor can set the sleep bit however he wants.
1300 69 dgisselq
                        // Well ... not quite.  Switching to user mode and
1301
                        // sleep mode shouold only be possible if the interrupt
1302
                        // flag isn't set.
1303
                        //      Thus: if (i_interrupt)&&(wr_reg_vl[GIE])
1304
                        //              don't set the sleep bit
1305
                        //      otherwise however it would o.w. be set
1306
                        sleep <= (wr_reg_vl[`CPU_SLEEP_BIT])
1307
                                &&((~i_interrupt)||(~wr_reg_vl[`CPU_GIE_BIT]));
1308 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
1309
                        // In user mode, however, you can only set the sleep
1310
                        // mode while remaining in user mode.  You can't switch
1311
                        // to sleep mode *and* supervisor mode at the same
1312
                        // time, lest you halt the CPU.
1313
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1314 2 dgisselq
 
1315
        always @(posedge i_clk)
1316
                if ((i_rst)||(w_switch_to_interrupt))
1317
                        step <= 1'b0;
1318 25 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
1319 2 dgisselq
                        step <= wr_reg_vl[`CPU_STEP_BIT];
1320 38 dgisselq
                else if ((alu_pc_valid)&&(step)&&(gie))
1321 2 dgisselq
                        step <= 1'b0;
1322
 
1323
        // The GIE register.  Only interrupts can disable the interrupt register
1324
        assign  w_switch_to_interrupt = (gie)&&(
1325
                        // On interrupt (obviously)
1326 69 dgisselq
                        ((i_interrupt)&&(~alu_phase)&&(~bus_lock))
1327 2 dgisselq
                        // If we are stepping the CPU
1328 69 dgisselq
                        ||((alu_pc_valid)&&(step)&&(~alu_phase)&&(~bus_lock))
1329 2 dgisselq
                        // If we encounter a break instruction, if the break
1330 36 dgisselq
                        //      enable isn't set.
1331 69 dgisselq
                        ||((master_ce)&&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
1332
                                &&(op_break)&&(~break_en))
1333 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1334 36 dgisselq
                        // On an illegal instruction
1335 71 dgisselq
                        ||((alu_pc_valid)&&(alu_illegal))
1336 36 dgisselq
`endif
1337 71 dgisselq
                        // On division by zero.  If the divide isn't
1338
                        // implemented, div_valid and div_error will be short
1339
                        // circuited and that logic will be bypassed
1340
                        ||((div_valid)&&(div_error))
1341
                        // Same thing on a floating point error.
1342
                        ||((fpu_valid)&&(fpu_error))
1343
                        //      
1344 69 dgisselq
                        ||(bus_err)
1345 2 dgisselq
                        // If we write to the CC register
1346
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1347 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1348 2 dgisselq
                        );
1349
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1350
                        // Then if we write the CC register
1351
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
1352 25 dgisselq
                                &&(~wr_reg_id[4])&&(wr_write_cc))
1353 2 dgisselq
                        );
1354
        always @(posedge i_clk)
1355
                if (i_rst)
1356
                        gie <= 1'b0;
1357
                else if (w_switch_to_interrupt)
1358
                        gie <= 1'b0;
1359
                else if (w_release_from_interrupt)
1360
                        gie <= 1'b1;
1361
 
1362 25 dgisselq
        initial trap = 1'b0;
1363
        always @(posedge i_clk)
1364
                if (i_rst)
1365
                        trap <= 1'b0;
1366 69 dgisselq
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1367
                                &&(wr_write_cc)) // &&(wr_reg_id[4]) implied
1368 25 dgisselq
                        trap <= 1'b1;
1369
                else if (w_release_from_interrupt)
1370
                        trap <= 1'b0;
1371
 
1372 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1373 65 dgisselq
        initial ill_err_i = 1'b0;
1374 36 dgisselq
        always @(posedge i_clk)
1375
                if (i_rst)
1376 65 dgisselq
                        ill_err_i <= 1'b0;
1377
                // The debug interface can clear this bit
1378
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1379
                                &&(~wr_reg_vl[`CPU_ILL_BIT]))
1380
                        ill_err_i <= 1'b0;
1381 71 dgisselq
                else if ((alu_pc_valid)&&(alu_illegal)&&(~alu_gie))
1382 65 dgisselq
                        ill_err_i <= 1'b1;
1383
        initial ill_err_u = 1'b0;
1384
        always @(posedge i_clk)
1385
                if (i_rst)
1386
                        ill_err_u <= 1'b0;
1387
                // The bit is automatically cleared on release from interrupt
1388 36 dgisselq
                else if (w_release_from_interrupt)
1389 65 dgisselq
                        ill_err_u <= 1'b0;
1390
                // If the supervisor writes to this register, clearing the
1391
                // bit, then clear it
1392
                else if (((~alu_gie)||(dbgv))
1393
                                &&(wr_reg_ce)&&(~wr_reg_vl[`CPU_ILL_BIT])
1394
                                &&(wr_reg_id[4])&&(wr_write_cc))
1395
                        ill_err_u <= 1'b0;
1396 71 dgisselq
                else if ((alu_pc_valid)&&(alu_illegal)&&(alu_gie))
1397 65 dgisselq
                        ill_err_u <= 1'b1;
1398 38 dgisselq
`else
1399 65 dgisselq
        assign ill_err_u = 1'b0;
1400
        assign ill_err_i = 1'b0;
1401 36 dgisselq
`endif
1402 65 dgisselq
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
1403
        // ever set.
1404
        initial ibus_err_flag = 1'b0;
1405 36 dgisselq
        always @(posedge i_clk)
1406
                if (i_rst)
1407 65 dgisselq
                        ibus_err_flag <= 1'b0;
1408
                else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1409
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT]))
1410
                        ibus_err_flag <= 1'b0;
1411
                else if ((bus_err)&&(~alu_gie))
1412
                        ibus_err_flag <= 1'b1;
1413
        // User bus error flag -- if ever set, it will cause an interrupt to
1414
        // supervisor mode.  
1415
        initial ubus_err_flag = 1'b0;
1416
        always @(posedge i_clk)
1417
                if (i_rst)
1418
                        ubus_err_flag <= 1'b0;
1419 36 dgisselq
                else if (w_release_from_interrupt)
1420 65 dgisselq
                        ubus_err_flag <= 1'b0;
1421
                // else if ((i_halt)&&(i_dbg_we)&&(~i_dbg_reg[4])
1422
                                // &&(i_dbg_reg == {1'b1, `CPU_CC_REG})
1423
                                // &&(~i_dbg_data[`CPU_BUSERR_BIT]))
1424
                        // ubus_err_flag <= 1'b0;
1425
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1426
                                &&(~wr_reg_vl[`CPU_BUSERR_BIT])
1427
                                &&(wr_reg_id[4])&&(wr_write_cc))
1428
                        ubus_err_flag <= 1'b0;
1429 36 dgisselq
                else if ((bus_err)&&(alu_gie))
1430 65 dgisselq
                        ubus_err_flag <= 1'b1;
1431 36 dgisselq
 
1432 69 dgisselq
        generate
1433
        if (IMPLEMENT_DIVIDE != 0)
1434
        begin
1435
                reg     r_idiv_err_flag, r_udiv_err_flag;
1436
 
1437
                // Supervisor/interrupt divide (by zero) error flag -- this will
1438
                // crash the CPU if ever set.  This bit is thus available for us
1439
                // to be able to tell if/why the CPU crashed.
1440
                initial r_idiv_err_flag = 1'b0;
1441
                always @(posedge i_clk)
1442
                        if (i_rst)
1443
                                r_idiv_err_flag <= 1'b0;
1444
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1445
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT]))
1446
                                r_idiv_err_flag <= 1'b0;
1447
                        else if ((div_error)&&(div_valid)&&(~alu_gie))
1448
                                r_idiv_err_flag <= 1'b1;
1449
                // User divide (by zero) error flag -- if ever set, it will
1450
                // cause a sudden switch interrupt to supervisor mode.  
1451
                initial r_udiv_err_flag = 1'b0;
1452
                always @(posedge i_clk)
1453
                        if (i_rst)
1454
                                r_udiv_err_flag <= 1'b0;
1455
                        else if (w_release_from_interrupt)
1456
                                r_udiv_err_flag <= 1'b0;
1457
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1458
                                        &&(~wr_reg_vl[`CPU_DIVERR_BIT])
1459
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1460
                                r_udiv_err_flag <= 1'b0;
1461
                        else if ((div_error)&&(alu_gie)&&(div_valid))
1462
                                r_udiv_err_flag <= 1'b1;
1463
 
1464
                assign  idiv_err_flag = r_idiv_err_flag;
1465
                assign  udiv_err_flag = r_udiv_err_flag;
1466
        end else begin
1467
                assign  idiv_err_flag = 1'b0;
1468
                assign  udiv_err_flag = 1'b0;
1469
        end endgenerate
1470
 
1471
        generate
1472
        if (IMPLEMENT_FPU !=0)
1473
        begin
1474
                // Supervisor/interrupt floating point error flag -- this will
1475
                // crash the CPU if ever set.
1476
                reg             r_ifpu_err_flag, r_ufpu_err_flag;
1477
                initial r_ifpu_err_flag = 1'b0;
1478
                always @(posedge i_clk)
1479
                        if (i_rst)
1480
                                r_ifpu_err_flag <= 1'b0;
1481
                        else if ((dbgv)&&(wr_reg_id == {1'b0, `CPU_CC_REG})
1482
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT]))
1483
                                r_ifpu_err_flag <= 1'b0;
1484
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
1485
                                r_ifpu_err_flag <= 1'b1;
1486
                // User floating point error flag -- if ever set, it will cause
1487
                // a sudden switch interrupt to supervisor mode.  
1488
                initial r_ufpu_err_flag = 1'b0;
1489
                always @(posedge i_clk)
1490
                        if (i_rst)
1491
                                r_ufpu_err_flag <= 1'b0;
1492
                        else if (w_release_from_interrupt)
1493
                                r_ufpu_err_flag <= 1'b0;
1494
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1495
                                        &&(~wr_reg_vl[`CPU_FPUERR_BIT])
1496
                                        &&(wr_reg_id[4])&&(wr_write_cc))
1497
                                r_ufpu_err_flag <= 1'b0;
1498
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
1499
                                r_ufpu_err_flag <= 1'b1;
1500
 
1501
                assign  ifpu_err_flag = r_ifpu_err_flag;
1502
                assign  ufpu_err_flag = r_ufpu_err_flag;
1503
        end else begin
1504
                assign  ifpu_err_flag = 1'b0;
1505
                assign  ufpu_err_flag = 1'b0;
1506
        end endgenerate
1507
 
1508
`ifdef  OPT_VLIW
1509
        reg             r_ihalt_phase, r_uhalt_phase;
1510
 
1511
        initial r_ihalt_phase = 0;
1512
        initial r_uhalt_phase = 0;
1513
        always @(posedge i_clk)
1514
                if (~alu_gie)
1515
                        r_ihalt_phase <= alu_phase;
1516
        always @(posedge i_clk)
1517
                if (alu_gie)
1518
                        r_uhalt_phase <= alu_phase;
1519
                else if (w_release_from_interrupt)
1520
                        r_uhalt_phase <= 1'b0;
1521
 
1522
        assign  ihalt_phase = r_ihalt_phase;
1523
        assign  uhalt_phase = r_uhalt_phase;
1524
`else
1525
        assign  ihalt_phase = 1'b0;
1526
        assign  uhalt_phase = 1'b0;
1527
`endif
1528
 
1529 2 dgisselq
        //
1530
        // Write backs to the PC register, and general increments of it
1531
        //      We support two: upc and ipc.  If the instruction is normal,
1532
        // we increment upc, if interrupt level we increment ipc.  If
1533
        // the instruction writes the PC, we write whichever PC is appropriate.
1534
        //
1535
        // Do we need to all our partial results from the pipeline?
1536
        // What happens when the pipeline has gie and ~gie instructions within
1537
        // it?  Do we clear both?  What if a gie instruction tries to clear
1538
        // a non-gie instruction?
1539
        always @(posedge i_clk)
1540 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1541 48 dgisselq
                        upc <= wr_reg_vl[(AW-1):0];
1542 36 dgisselq
                else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1543 2 dgisselq
                        upc <= alu_pc;
1544
 
1545
        always @(posedge i_clk)
1546
                if (i_rst)
1547
                        ipc <= RESET_ADDRESS;
1548
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1549 48 dgisselq
                        ipc <= wr_reg_vl[(AW-1):0];
1550 36 dgisselq
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1551 2 dgisselq
                        ipc <= alu_pc;
1552
 
1553
        always @(posedge i_clk)
1554
                if (i_rst)
1555
                        pf_pc <= RESET_ADDRESS;
1556
                else if (w_switch_to_interrupt)
1557
                        pf_pc <= ipc;
1558
                else if (w_release_from_interrupt)
1559
                        pf_pc <= upc;
1560
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1561 48 dgisselq
                        pf_pc <= wr_reg_vl[(AW-1):0];
1562 69 dgisselq
`ifdef  OPT_PIPELINED
1563 105 dgisselq
                else if ((dcd_early_branch)&&(~clear_pipeline))
1564 69 dgisselq
                        pf_pc <= dcd_branch_pc + 1;
1565
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
1566 56 dgisselq
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
1567 69 dgisselq
`else
1568
                else if ((alu_pc_valid)&&(~clear_pipeline))
1569
                        pf_pc <= alu_pc;
1570
`endif
1571 2 dgisselq
 
1572
        initial new_pc = 1'b1;
1573
        always @(posedge i_clk)
1574 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
1575 2 dgisselq
                        new_pc <= 1'b1;
1576
                else if (w_switch_to_interrupt)
1577
                        new_pc <= 1'b1;
1578
                else if (w_release_from_interrupt)
1579
                        new_pc <= 1'b1;
1580
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1581
                        new_pc <= 1'b1;
1582
                else
1583
                        new_pc <= 1'b0;
1584
 
1585
        //
1586
        // The debug interface
1587 56 dgisselq
        generate
1588
        if (AW<32)
1589
        begin
1590
                always @(posedge i_clk)
1591 2 dgisselq
                begin
1592
                        o_dbg_reg <= regset[i_dbg_reg];
1593
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1594 48 dgisselq
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
1595 2 dgisselq
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1596 56 dgisselq
                        begin
1597 83 dgisselq
                                o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1598 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1599
                        end
1600 2 dgisselq
                end
1601 56 dgisselq
        end else begin
1602
                always @(posedge i_clk)
1603
                begin
1604
                        o_dbg_reg <= regset[i_dbg_reg];
1605
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1606
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
1607
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1608
                        begin
1609 83 dgisselq
                                o_dbg_reg[13:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1610 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1611
                        end
1612
                end
1613
        end endgenerate
1614
 
1615 2 dgisselq
        always @(posedge i_clk)
1616 56 dgisselq
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
1617 18 dgisselq
 
1618
        always @(posedge i_clk)
1619 25 dgisselq
                o_dbg_stall <= (i_halt)&&(
1620 36 dgisselq
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
1621 2 dgisselq
                        ||((~opvalid)&&(~i_rst))
1622 25 dgisselq
                        ||((~dcdvalid)&&(~i_rst)));
1623 2 dgisselq
 
1624
        //
1625
        //
1626
        // Produce accounting outputs: Account for any CPU stalls, so we can
1627
        // later evaluate how well we are doing.
1628
        //
1629
        //
1630 71 dgisselq
        assign  o_op_stall = (master_ce)&&(op_stall);
1631 9 dgisselq
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1632 38 dgisselq
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1633 56 dgisselq
 
1634 65 dgisselq
`ifdef  DEBUG_SCOPE
1635 56 dgisselq
        always @(posedge i_clk)
1636 65 dgisselq
                o_debug <= {
1637 118 dgisselq
                        i_wb_err, pf_pc[2:0], flags,
1638 56 dgisselq
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
1639
                        op_ce, alu_ce, mem_ce,
1640 65 dgisselq
                        //
1641
                        master_ce, opvalid_alu, opvalid_mem,
1642
                        //
1643
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
1644
                        mem_we,
1645
                        // ((opvalid_alu)&&(alu_stall))
1646
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
1647
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
1648
                        // opA[23:20], opA[3:0],
1649
                        gie, sleep,
1650 71 dgisselq
                        wr_reg_ce, wr_reg_vl[4:0]
1651
                /*
1652 69 dgisselq
                        i_rst, master_ce, (new_pc),
1653
                        ((dcd_early_branch)&&(dcdvalid)),
1654
                        pf_valid, pf_illegal,
1655
                        op_ce, dcd_ce, dcdvalid, dcd_stalled,
1656
                        pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
1657
                        pf_pc[7:0], pf_addr[7:0]
1658 71 dgisselq
                */
1659 56 dgisselq
                        };
1660 65 dgisselq
`endif
1661 56 dgisselq
 
1662 2 dgisselq
endmodule

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