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///////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipcpu.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is the top level module holding the core of the Zip CPU
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//              together.  The Zip CPU is designed to be as simple as possible.
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//      (actual implementation aside ...)  The instruction set is about as
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//      RISC as you can get, with only 26 instruction types currently supported.
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//      (There are still 8-instruction Op-Codes reserved for floating point,
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//      and 5 which can be used for transactions not requiring registers.)
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//      Please see the accompanying spec.pdf file for a description of these
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//      instructions.
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//
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//      All instructions are 32-bits wide.  All bus accesses, both address and
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//      data, are 32-bits over a wishbone bus.
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//
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//      The Zip CPU is fully pipelined with the following pipeline stages:
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//
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//              1. Prefetch, returns the instruction from memory. 
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//
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//              2. Instruction Decode
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//
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//              3. Read Operands
26
//
27
//              4. Apply Instruction
28
//
29
//              4. Write-back Results
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//
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//      Further information about the inner workings of this CPU, such as
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//      what causes pipeline stalls, may be found in the spec.pdf file.  (The
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//      documentation within this file had become out of date and out of sync
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//      with the spec.pdf, so look to the spec.pdf for accurate and up to date
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//      information.)
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//
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//
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//      In general, the pipelining is controlled by three pieces of logic
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//      per stage: _ce, _stall, and _valid.  _valid means that the stage
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//      holds a valid instruction.  _ce means that the instruction from the
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//      previous stage is to move into this one, and _stall means that the
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//      instruction from the previous stage may not move into this one.
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//      The difference between these control signals allows individual stages
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//      to propagate instructions independently.  In general, the logic works
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//      as:
46
//
47
//
48
//      assign  (n)_ce = (n-1)_valid && (~(n)_stall)
49
//
50
//
51
//      always @(posedge i_clk)
52
//              if ((i_rst)||(clear_pipeline))
53
//                      (n)_valid = 0
54
//              else if (n)_ce
55
//                      (n)_valid = 1
56
//              else if (n+1)_ce
57
//                      (n)_valid = 0
58
//
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//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )
60
//                      || (  (n)_valid && (n+1)_stall );
61
//
62
//      and ...
63
//
64
//      always @(posedge i_clk)
65
//              if (n)_ce
66
//                      (n)_variable = ... whatever logic for this stage
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//
68
//      Note that a stage can stall even if no instruction is loaded into
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//      it.
70
//
71
//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
75
///////////////////////////////////////////////////////////////////////////////
76
//
77 160 dgisselq
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
92
//
93
///////////////////////////////////////////////////////////////////////////////
94
//
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// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
96
// fetches are more complicated and therefore use more FPGA resources, while
97
// single fetches will cause the CPU to stall for about 5 stalls each 
98
// instruction cycle, effectively reducing the instruction count per clock to
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// about 0.2.  However, the area cost may be worth it.  Consider:
100
//
101
//      Slice LUTs              ZipSystem       ZipCPU
102
//      Single Fetching         2521            1734
103
//      Pipelined fetching      2796            2046
104
//
105
//
106
//
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`define CPU_CC_REG      4'he
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`define CPU_PC_REG      4'hf
109 193 dgisselq
`define CPU_CLRCACHE_BIT 14     // Set to clear the I-cache, automatically clears
110
`define CPU_PHASE_BIT   13      // Set if we are executing the latter half of a VLIW
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`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error
112
`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero
113
`define CPU_BUSERR_BIT  10      // Bus error flag, set on error
114
`define CPU_TRAP_BIT    9       // User TRAP has taken place
115
`define CPU_ILL_BIT     8       // Illegal instruction
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`define CPU_BREAK_BIT   7
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`define CPU_STEP_BIT    6       // Will step one or two (VLIW) instructions
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`define CPU_GIE_BIT     5
119
`define CPU_SLEEP_BIT   4
120 36 dgisselq
// Compile time defines
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//
122
`include "cpudefs.v"
123
//
124 65 dgisselq
//
125 2 dgisselq
module  zipcpu(i_clk, i_rst, i_interrupt,
126
                // Debug interface
127 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
128
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
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                        o_break,
130
                // CPU interface to the wishbone bus
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                o_wb_gbl_cyc, o_wb_gbl_stb,
132
                        o_wb_lcl_cyc, o_wb_lcl_stb,
133
                        o_wb_we, o_wb_addr, o_wb_data,
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                        i_wb_ack, i_wb_stall, i_wb_data,
135 36 dgisselq
                        i_wb_err,
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                // Accounting/CPU usage interface
137 65 dgisselq
                o_op_stall, o_pf_stall, o_i_count
138
`ifdef  DEBUG_SCOPE
139
                , o_debug
140
`endif
141
                );
142 193 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=32,
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                        LGICACHE=8;
144 56 dgisselq
`ifdef  OPT_MULTIPLY
145 132 dgisselq
        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;
146 56 dgisselq
`else
147
        parameter       IMPLEMENT_MPY = 0;
148
`endif
149 71 dgisselq
`ifdef  OPT_DIVIDE
150
        parameter       IMPLEMENT_DIVIDE = 1;
151
`else
152
        parameter       IMPLEMENT_DIVIDE = 0;
153
`endif
154
`ifdef  OPT_IMPLEMENT_FPU
155
        parameter       IMPLEMENT_FPU = 1,
156
`else
157
        parameter       IMPLEMENT_FPU = 0,
158
`endif
159 69 dgisselq
                        IMPLEMENT_LOCK=1;
160
`ifdef  OPT_EARLY_BRANCHING
161
        parameter       EARLY_BRANCHING = 1;
162
`else
163
        parameter       EARLY_BRANCHING = 0;
164
`endif
165 193 dgisselq
        localparam      AW=ADDRESS_WIDTH;
166 2 dgisselq
        input                   i_clk, i_rst, i_interrupt;
167
        // Debug interface -- inputs
168 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
169 2 dgisselq
        input           [4:0]    i_dbg_reg;
170
        input                   i_dbg_we;
171
        input           [31:0]   i_dbg_data;
172
        // Debug interface -- outputs
173 160 dgisselq
        output  wire            o_dbg_stall;
174 2 dgisselq
        output  reg     [31:0]   o_dbg_reg;
175 56 dgisselq
        output  reg     [3:0]    o_dbg_cc;
176 2 dgisselq
        output  wire            o_break;
177
        // Wishbone interface -- outputs
178 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
179
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
180 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
181
        output  wire    [31:0]   o_wb_data;
182 2 dgisselq
        // Wishbone interface -- inputs
183
        input                   i_wb_ack, i_wb_stall;
184
        input           [31:0]   i_wb_data;
185 36 dgisselq
        input                   i_wb_err;
186 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
187 9 dgisselq
        output  wire            o_op_stall;
188 2 dgisselq
        output  wire            o_pf_stall;
189 9 dgisselq
        output  wire            o_i_count;
190 56 dgisselq
        //
191 65 dgisselq
`ifdef  DEBUG_SCOPE
192 56 dgisselq
        output  reg     [31:0]   o_debug;
193 65 dgisselq
`endif
194 2 dgisselq
 
195 25 dgisselq
 
196 2 dgisselq
        // Registers
197 56 dgisselq
        //
198
        //      The distributed RAM style comment is necessary on the
199
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
200
        // set and in the process ruining everything else.  It basically
201
        // optimizes logic away, to where it no longer works.  The logic
202
        // as described herein will work, this just makes sure XST implements
203
        // that logic.
204
        //
205
        (* ram_style = "distributed" *)
206 2 dgisselq
        reg     [31:0]   regset [0:31];
207 9 dgisselq
 
208
        // Condition codes
209 56 dgisselq
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
210
        reg     [3:0]    flags, iflags;
211 179 dgisselq
        wire    [14:0]   w_uflags, w_iflags;
212 160 dgisselq
        reg             trap, break_en, step, gie, sleep, r_halted;
213 179 dgisselq
        wire            break_pending;
214
        wire            w_clear_icache;
215 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
216 65 dgisselq
        reg             ill_err_u, ill_err_i;
217 38 dgisselq
`else
218 65 dgisselq
        wire            ill_err_u, ill_err_i;
219 36 dgisselq
`endif
220 179 dgisselq
        reg             ubreak;
221 65 dgisselq
        reg             ibus_err_flag, ubus_err_flag;
222 69 dgisselq
        wire            idiv_err_flag, udiv_err_flag;
223
        wire            ifpu_err_flag, ufpu_err_flag;
224
        wire            ihalt_phase, uhalt_phase;
225 2 dgisselq
 
226 9 dgisselq
        // The master chip enable
227
        wire            master_ce;
228 2 dgisselq
 
229
        //
230
        //
231
        //      PIPELINE STAGE #1 :: Prefetch
232
        //              Variable declarations
233
        //
234 48 dgisselq
        reg     [(AW-1):0]       pf_pc;
235 69 dgisselq
        reg     new_pc;
236 18 dgisselq
        wire    clear_pipeline;
237 179 dgisselq
        assign  clear_pipeline = new_pc;
238 9 dgisselq
 
239
        wire            dcd_stalled;
240 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
241 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
242
        wire    [31:0]           pf_data;
243
        wire    [31:0]           instruction;
244
        wire    [(AW-1):0]       instruction_pc;
245 36 dgisselq
        wire    pf_valid, instruction_gie, pf_illegal;
246 2 dgisselq
 
247
        //
248
        //
249
        //      PIPELINE STAGE #2 :: Instruction Decode
250
        //              Variable declarations
251
        //
252
        //
253 83 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu;
254 69 dgisselq
        reg             opvalid_div, opvalid_fpu;
255
        wire            op_stall, dcd_ce, dcd_phase;
256
        wire    [3:0]    dcdOp;
257
        wire    [4:0]    dcdA, dcdB, dcdR;
258
        wire            dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc, dcdR_cc, dcdR_pc;
259
        wire    [3:0]    dcdF;
260
        wire            dcdR_wr, dcdA_rd, dcdB_rd,
261
                                dcdALU, dcdM, dcdDV, dcdFP,
262 71 dgisselq
                                dcdF_wr, dcd_gie, dcd_break, dcd_lock,
263 105 dgisselq
                                dcd_pipe, dcd_ljmp;
264 69 dgisselq
        reg             r_dcdvalid;
265
        wire            dcdvalid;
266
        wire    [(AW-1):0]       dcd_pc;
267
        wire    [31:0]   dcdI;
268
        wire            dcd_zI; // true if dcdI == 0
269 2 dgisselq
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
270
 
271 69 dgisselq
        wire    dcd_illegal;
272
        wire                    dcd_early_branch;
273 48 dgisselq
        wire    [(AW-1):0]       dcd_branch_pc;
274 2 dgisselq
 
275
 
276
        //
277
        //
278
        //      PIPELINE STAGE #3 :: Read Operands
279
        //              Variable declarations
280
        //
281
        //
282
        //
283
        // Now, let's read our operands
284
        reg     [4:0]    alu_reg;
285 179 dgisselq
        wire    [3:0]    opn;
286
        wire    [4:0]    opR;
287 48 dgisselq
        reg     [31:0]   r_opA, r_opB;
288
        reg     [(AW-1):0]       op_pc;
289 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
290 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
291 179 dgisselq
        reg             opR_wr, opF_wr;
292
        wire            op_gie, opR_cc;
293
        wire    [14:0]   opFl;
294 56 dgisselq
        reg     [5:0]    r_opF;
295
        wire    [7:0]    opF;
296 160 dgisselq
        wire            op_ce, op_phase, op_pipe, op_change_data_ce;
297 56 dgisselq
        // Some pipeline control wires
298 69 dgisselq
`ifdef  OPT_PIPELINED
299 56 dgisselq
        reg     opA_alu, opA_mem;
300
        reg     opB_alu, opB_mem;
301
`endif
302 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
303 36 dgisselq
        reg     op_illegal;
304 160 dgisselq
`else
305
        wire    op_illegal;
306
        assign  op_illegal = 1'b0;
307 36 dgisselq
`endif
308 179 dgisselq
        wire    op_break;
309 69 dgisselq
        wire    op_lock;
310 2 dgisselq
 
311
 
312
        //
313
        //
314
        //      PIPELINE STAGE #4 :: ALU / Memory
315
        //              Variable declarations
316
        //
317
        //
318 179 dgisselq
        wire    [(AW-1):0]       alu_pc;
319 145 dgisselq
        reg             r_alu_pc_valid, mem_pc_valid;
320
        wire            alu_pc_valid;
321 69 dgisselq
        wire            alu_phase;
322 2 dgisselq
        wire            alu_ce, alu_stall;
323
        wire    [31:0]   alu_result;
324
        wire    [3:0]    alu_flags;
325 71 dgisselq
        wire            alu_valid, alu_busy;
326 2 dgisselq
        wire            set_cond;
327 179 dgisselq
        reg             alu_wr, alF_wr;
328 193 dgisselq
        wire            alu_gie, alu_illegal;
329 2 dgisselq
 
330
 
331
 
332
        wire    mem_ce, mem_stalled;
333 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
334
        wire    mem_pipe_stalled;
335
`endif
336 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
337
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
338 48 dgisselq
        wire    [4:0]            mem_wreg;
339 9 dgisselq
 
340 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
341
        wire    [(AW-1):0]       mem_addr;
342
        wire    [31:0]           mem_data, mem_result;
343 2 dgisselq
 
344 69 dgisselq
        wire    div_ce, div_error, div_busy, div_valid;
345
        wire    [31:0]   div_result;
346
        wire    [3:0]    div_flags;
347 2 dgisselq
 
348 69 dgisselq
        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_div)
349
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
350
                                &&(set_cond);
351 2 dgisselq
 
352 69 dgisselq
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
353
        wire    [31:0]   fpu_result;
354
        wire    [3:0]    fpu_flags;
355
 
356
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(opvalid_fpu)
357
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
358
                                &&(set_cond);
359
 
360 179 dgisselq
        wire    adf_ce_unconditional;
361 69 dgisselq
 
362 2 dgisselq
        //
363
        //
364
        //      PIPELINE STAGE #5 :: Write-back
365
        //              Variable declarations
366
        //
367 179 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc,
368
                        wr_write_scc, wr_write_ucc;
369 2 dgisselq
        wire    [4:0]    wr_reg_id;
370 160 dgisselq
        wire    [31:0]   wr_gpreg_vl, wr_spreg_vl;
371 2 dgisselq
        wire    w_switch_to_interrupt, w_release_from_interrupt;
372 48 dgisselq
        reg     [(AW-1):0]       upc, ipc;
373 2 dgisselq
 
374
 
375
 
376
        //
377
        //      MASTER: clock enable.
378
        //
379 38 dgisselq
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
380 2 dgisselq
 
381
 
382
        //
383
        //      PIPELINE STAGE #1 :: Prefetch
384
        //              Calculate stall conditions
385 65 dgisselq
        //
386
        //      These are calculated externally, within the prefetch module.
387
        //
388 2 dgisselq
 
389
        //
390
        //      PIPELINE STAGE #2 :: Instruction Decode
391
        //              Calculate stall conditions
392 69 dgisselq
        assign          dcd_ce = ((~dcdvalid)||(~dcd_stalled))&&(~clear_pipeline);
393 145 dgisselq
 
394 69 dgisselq
`ifdef  OPT_PIPELINED
395
        assign          dcd_stalled = (dcdvalid)&&(op_stall);
396
`else
397
        // If not pipelined, there will be no opvalid_ anything, and the
398
        // op_stall will be false, dcdX_stall will be false, thus we can simply
399
        // do a ...
400
        assign          dcd_stalled = 1'b0;
401
`endif
402 2 dgisselq
        //
403
        //      PIPELINE STAGE #3 :: Read Operands
404
        //              Calculate stall conditions
405 69 dgisselq
        wire    op_lock_stall;
406
`ifdef  OPT_PIPELINED
407 179 dgisselq
        reg     cc_invalid_for_dcd;
408
        always @(posedge i_clk)
409
                cc_invalid_for_dcd <= (wr_flags_ce)
410
                        ||(wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG)
411
                        ||(opvalid)&&((opF_wr)||((opR_wr)&&(opR[3:0] == `CPU_CC_REG)))
412
                        ||((alF_wr)||((alu_wr)&&(alu_reg[3:0] == `CPU_CC_REG)))
413
                        ||(mem_busy)||(div_busy)||(fpu_busy);
414
 
415 69 dgisselq
        assign  op_stall = (opvalid)&&( // Only stall if we're loaded w/validins
416
                        // Stall if we're stopped, and not allowed to execute
417
                        // an instruction
418
                        // (~master_ce)         // Already captured in alu_stall
419
                        //
420 56 dgisselq
                        // Stall if going into the ALU and the ALU is stalled
421
                        //      i.e. if the memory is busy, or we are single
422 69 dgisselq
                        //      stepping.  This also includes our stalls for
423
                        //      op_break and op_lock, so we don't need to
424
                        //      include those as well here.
425 83 dgisselq
                        // This also includes whether or not the divide or
426
                        // floating point units are busy.
427
                        (alu_stall)
428 56 dgisselq
                        //
429
                        // Stall if we are going into memory with an operation
430
                        //      that cannot be pipelined, and the memory is
431
                        //      already busy
432 83 dgisselq
                        ||(mem_stalled) // &&(opvalid_mem) part of mem_stalled
433 179 dgisselq
                        ||(opR_cc)
434 69 dgisselq
                        )
435
                        ||(dcdvalid)&&(
436 71 dgisselq
                                // Stall if we need to wait for an operand A
437 69 dgisselq
                                // to be ready to read
438 71 dgisselq
                                (dcdA_stall)
439 69 dgisselq
                                // Likewise for B, also includes logic
440
                                // regarding immediate offset (register must
441
                                // be in register file if we need to add to
442
                                // an immediate)
443
                                ||(dcdB_stall)
444
                                // Or if we need to wait on flags to work on the
445
                                // CC register
446
                                ||(dcdF_stall)
447
                        );
448 71 dgisselq
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~op_stall)&&(~clear_pipeline);
449 179 dgisselq
 
450
 
451 160 dgisselq
        // BUT ... op_ce is too complex for many of the data operations.  So
452
        // let's make their circuit enable code simpler.  In particular, if
453
        // op_ doesn't need to be preserved, we can change it all we want
454
        // ... right?  The clear_pipeline code, for example, really only needs
455
        // to determine whether opvalid is true.
456
        assign  op_change_data_ce = (~op_stall);
457 65 dgisselq
`else
458 69 dgisselq
        assign  op_stall = (opvalid)&&(~master_ce);
459 145 dgisselq
        assign  op_ce = ((dcdvalid)||(dcd_illegal))&&(~clear_pipeline);
460 160 dgisselq
        assign  op_change_data_ce = 1'b1;
461 65 dgisselq
`endif
462 2 dgisselq
 
463
        //
464
        //      PIPELINE STAGE #4 :: ALU / Memory
465
        //              Calculate stall conditions
466 36 dgisselq
        //
467
        // 1. Basic stall is if the previous stage is valid and the next is
468
        //      busy.  
469
        // 2. Also stall if the prior stage is valid and the master clock enable
470
        //      is de-selected
471 56 dgisselq
        // 3. Stall if someone on the other end is writing the CC register,
472
        //      since we don't know if it'll put us to sleep or not.
473 36 dgisselq
        // 4. Last case: Stall if we would otherwise move a break instruction
474
        //      through the ALU.  Break instructions are not allowed through
475
        //      the ALU.
476 69 dgisselq
`ifdef  OPT_PIPELINED
477 71 dgisselq
        assign  alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(opvalid_alu)) //Case 1&2
478 69 dgisselq
                        ||((opvalid)&&(op_lock)&&(op_lock_stall))
479 193 dgisselq
                        ||((opvalid)&&(op_break))       // || op_illegal
480 179 dgisselq
                        ||(wr_reg_ce)&&(wr_write_cc)
481 69 dgisselq
                        ||(div_busy)||(fpu_busy);
482 160 dgisselq
        assign  alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)
483 69 dgisselq
                                &&(~clear_pipeline);
484
`else
485 179 dgisselq
        assign  alu_stall = (opvalid_alu)&&((~master_ce)||(op_break));
486 193 dgisselq
        assign  alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
487 69 dgisselq
`endif
488 2 dgisselq
        //
489 65 dgisselq
 
490
        //
491
        // Note: if you change the conditions for mem_ce, you must also change
492
        // alu_pc_valid.
493
        //
494 69 dgisselq
`ifdef  OPT_PIPELINED
495
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
496 71 dgisselq
                        &&(~clear_pipeline);
497 69 dgisselq
`else
498
        // If we aren't pipelined, then no one will be changing what's in the
499
        // pipeline (i.e. clear_pipeline), while our only instruction goes
500
        // through the ... pipeline.
501 145 dgisselq
        //
502
        // However, in hind sight this logic didn't work.  What happens when
503
        // something gets in the pipeline and then (due to interrupt or some
504
        // such) needs to be voided?  Thus we avoid simplification and keep
505
        // what worked here.
506
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)
507
                        &&(~clear_pipeline);
508 69 dgisselq
`endif
509 65 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
510 71 dgisselq
        assign  mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&(
511 38 dgisselq
                                (mem_pipe_stalled)
512
                                ||((~op_pipe)&&(mem_busy))
513 69 dgisselq
                                ||(div_busy)
514
                                ||(fpu_busy)
515 38 dgisselq
                                // Stall waiting for flags to be valid
516
                                // Or waiting for a write to the PC register
517
                                // Or CC register, since that can change the
518
                                //  PC as well
519
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
520
                                        &&((wr_write_pc)||(wr_write_cc)))));
521
`else
522 69 dgisselq
`ifdef  OPT_PIPELINED
523 25 dgisselq
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
524 2 dgisselq
                                (~master_ce)
525
                                // Stall waiting for flags to be valid
526
                                // Or waiting for a write to the PC register
527 25 dgisselq
                                // Or CC register, since that can change the
528
                                //  PC as well
529
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
530 69 dgisselq
`else
531
        assign  mem_stalled = (opvalid_mem)&&(~master_ce);
532 38 dgisselq
`endif
533 69 dgisselq
`endif
534 2 dgisselq
 
535 179 dgisselq
        // ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
536
        assign  adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(opvalid)
537
                                &&(~opvalid_mem)&&(~mem_rdbusy)
538
                                &&((~opvalid_alu)||(~alu_stall))&&(~op_break)
539
                                &&(~div_busy)&&(~fpu_busy)&&(~clear_pipeline);
540 2 dgisselq
 
541
        //
542
        //
543
        //      PIPELINE STAGE #1 :: Prefetch
544
        //
545
        //
546 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
547 9 dgisselq
        wire            pf_ce;
548
 
549 145 dgisselq
        assign          pf_ce = (~pf_valid)&&(~dcdvalid)&&(~opvalid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid);
550 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
551 145 dgisselq
                        pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc, gie,
552 2 dgisselq
                                instruction, instruction_pc, instruction_gie,
553 36 dgisselq
                                        pf_valid, pf_illegal,
554
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
555
                                pf_ack, pf_stall, pf_err, i_wb_data);
556 69 dgisselq
 
557
        initial r_dcdvalid = 1'b0;
558
        always @(posedge i_clk)
559 145 dgisselq
                if ((i_rst)||(clear_pipeline))
560 69 dgisselq
                        r_dcdvalid <= 1'b0;
561
                else if (dcd_ce)
562 179 dgisselq
                        r_dcdvalid <= (pf_valid)||(pf_illegal);
563 105 dgisselq
                else if (op_ce)
564 69 dgisselq
                        r_dcdvalid <= 1'b0;
565
        assign  dcdvalid = r_dcdvalid;
566
 
567 2 dgisselq
`else // Pipe fetch
568 69 dgisselq
 
569
`ifdef  OPT_TRADITIONAL_PFCACHE
570
        pfcache #(LGICACHE, ADDRESS_WIDTH)
571 105 dgisselq
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
572 179 dgisselq
                                        w_clear_icache,
573 69 dgisselq
                                // dcd_pc,
574
                                ~dcd_stalled,
575 105 dgisselq
                                ((dcd_early_branch)&&(~clear_pipeline))
576 69 dgisselq
                                        ? dcd_branch_pc:pf_pc,
577
                                instruction, instruction_pc, pf_valid,
578
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
579
                                        pf_ack, pf_stall, pf_err, i_wb_data,
580
                                pf_illegal);
581
`else
582 48 dgisselq
        pipefetch       #(RESET_ADDRESS, LGICACHE, ADDRESS_WIDTH)
583 179 dgisselq
                        pf(i_clk, i_rst, (new_pc)||(dcd_early_branch),
584
                                        w_clear_icache, ~dcd_stalled,
585 36 dgisselq
                                        (new_pc)?pf_pc:dcd_branch_pc,
586 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
587
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
588 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
589 69 dgisselq
//`ifdef        OPT_PRECLEAR_BUS
590
                                //((dcd_clear_bus)&&(dcdvalid))
591
                                //||((op_clear_bus)&&(opvalid))
592
                                //||
593
//`endif
594 36 dgisselq
                                (mem_cyc_lcl)||(mem_cyc_gbl),
595
                                pf_illegal);
596 69 dgisselq
`endif
597 2 dgisselq
        assign  instruction_gie = gie;
598
 
599 69 dgisselq
        initial r_dcdvalid = 1'b0;
600 2 dgisselq
        always @(posedge i_clk)
601 179 dgisselq
                if ((i_rst)||(clear_pipeline)||(w_clear_icache))
602 69 dgisselq
                        r_dcdvalid <= 1'b0;
603 2 dgisselq
                else if (dcd_ce)
604 179 dgisselq
                        r_dcdvalid <= (pf_valid)&&(~dcd_ljmp)&&(~dcd_early_branch);
605 69 dgisselq
                else if (op_ce)
606
                        r_dcdvalid <= 1'b0;
607
        assign  dcdvalid = r_dcdvalid;
608 36 dgisselq
`endif
609 2 dgisselq
 
610 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
611 179 dgisselq
 
612
        // If not pipelined, there will be no opvalid_ anything, and the
613 69 dgisselq
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
614
                        IMPLEMENT_FPU)
615
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
616 179 dgisselq
                        (~dcdvalid)||(~op_stall), dcd_stalled, instruction, instruction_gie,
617 69 dgisselq
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
618
                        dcd_illegal, dcd_pc, dcd_gie,
619
                        { dcdR_cc, dcdR_pc, dcdR },
620
                        { dcdA_cc, dcdA_pc, dcdA },
621
                        { dcdB_cc, dcdB_pc, dcdB },
622
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
623
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
624
                        dcdR_wr,dcdA_rd, dcdB_rd,
625
                        dcd_early_branch,
626 105 dgisselq
                        dcd_branch_pc, dcd_ljmp,
627 71 dgisselq
                        dcd_pipe);
628 36 dgisselq
`else
629 69 dgisselq
        idecode_deprecated
630
                #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
631
                        IMPLEMENT_FPU)
632
                instruction_decoder(i_clk, (i_rst)||(clear_pipeline),
633
                        dcd_ce, dcd_stalled, instruction, instruction_gie,
634
                        instruction_pc, pf_valid, pf_illegal, dcd_phase,
635
                        dcd_illegal, dcd_pc, dcd_gie,
636
                        { dcdR_cc, dcdR_pc, dcdR },
637
                        { dcdA_cc, dcdA_pc, dcdA },
638
                        { dcdB_cc, dcdB_pc, dcdB },
639
                        dcdI, dcd_zI, dcdF, dcdF_wr, dcdOp,
640
                        dcdALU, dcdM, dcdDV, dcdFP, dcd_break, dcd_lock,
641
                        dcdR_wr,dcdA_rd, dcdB_rd,
642
                        dcd_early_branch,
643 71 dgisselq
                        dcd_branch_pc,
644
                        dcd_pipe);
645 105 dgisselq
        assign  dcd_ljmp = 1'b0;
646 36 dgisselq
`endif
647 2 dgisselq
 
648 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
649 132 dgisselq
        reg             r_op_pipe;
650 2 dgisselq
 
651 132 dgisselq
        initial r_op_pipe = 1'b0;
652 38 dgisselq
        // To be a pipeable operation, there must be 
653
        //      two valid adjacent instructions
654
        //      Both must be memory instructions
655
        //      Both must be writes, or both must be reads
656
        //      Both operations must be to the same identical address,
657
        //              or at least a single (one) increment above that address
658 71 dgisselq
        //
659
        // However ... we need to know this before this clock, hence this is
660
        // calculated in the instruction decoder.
661 38 dgisselq
        always @(posedge i_clk)
662
                if (op_ce)
663 132 dgisselq
                        r_op_pipe <= dcd_pipe;
664 145 dgisselq
                else if (mem_ce) // Clear us any time an op_ is clocked in
665
                        r_op_pipe <= 1'b0;
666 132 dgisselq
        assign  op_pipe = r_op_pipe;
667
`else
668
        assign  op_pipe = 1'b0;
669 38 dgisselq
`endif
670
 
671 2 dgisselq
        //
672
        //
673
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
674
        //
675
        //
676 25 dgisselq
        assign  w_opA = regset[dcdA];
677
        assign  w_opB = regset[dcdB];
678 56 dgisselq
 
679 132 dgisselq
        wire    [8:0]    w_cpu_info;
680
        assign  w_cpu_info = {
681
`ifdef  OPT_ILLEGAL_INSTRUCTION
682
        1'b1,
683
`else
684
        1'b0,
685
`endif
686
`ifdef  OPT_MULTIPLY
687
        1'b1,
688
`else
689
        1'b0,
690
`endif
691
`ifdef  OPT_DIVIDE
692
        1'b1,
693
`else
694
        1'b0,
695
`endif
696
`ifdef  OPT_IMPLEMENT_FPU
697
        1'b1,
698
`else
699
        1'b0,
700
`endif
701
`ifdef  OPT_PIPELINED
702
        1'b1,
703
`else
704
        1'b0,
705
`endif
706
`ifdef  OPT_TRADITIONAL_CACHE
707
        1'b1,
708
`else
709
        1'b0,
710
`endif
711
`ifdef  OPT_EARLY_BRANCHING
712
        1'b1,
713
`else
714
        1'b0,
715
`endif
716
`ifdef  OPT_PIPELINED_BUS_ACCESS
717
        1'b1,
718
`else
719
        1'b0,
720
`endif
721
`ifdef  OPT_VLIW
722
        1'b1
723
`else
724
        1'b0
725
`endif
726
        };
727
 
728 56 dgisselq
        wire    [31:0]   w_pcA_v;
729
        generate
730
        if (AW < 32)
731
                assign  w_pcA_v = {{(32-AW){1'b0}}, (dcdA[4] == dcd_gie)?dcd_pc:upc };
732
        else
733
                assign  w_pcA_v = (dcdA[4] == dcd_gie)?dcd_pc:upc;
734
        endgenerate
735 71 dgisselq
 
736
`ifdef  OPT_PIPELINED
737
        reg     [4:0]    opA_id, opB_id;
738
        reg             opA_rd, opB_rd;
739 2 dgisselq
        always @(posedge i_clk)
740 71 dgisselq
                if (op_ce)
741
                begin
742
                        opA_id <= dcdA;
743
                        opB_id <= dcdB;
744
                        opA_rd <= dcdA_rd;
745
                        opB_rd <= dcdB_rd;
746
                end
747
`endif
748
 
749
        always @(posedge i_clk)
750 179 dgisselq
`ifdef  OPT_PIPELINED
751 160 dgisselq
                if (op_change_data_ce)
752 179 dgisselq
`endif
753 2 dgisselq
                begin
754 179 dgisselq
`ifdef  OPT_PIPELINED
755 2 dgisselq
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
756 160 dgisselq
                                r_opA <= wr_gpreg_vl;
757 179 dgisselq
                        else
758
`endif
759
                        if (dcdA_pc)
760 56 dgisselq
                                r_opA <= w_pcA_v;
761 25 dgisselq
                        else if (dcdA_cc)
762 179 dgisselq
                                r_opA <= { w_cpu_info, w_opA[22:16], 1'b0, (dcdA[4])?w_uflags:w_iflags };
763 2 dgisselq
                        else
764 25 dgisselq
                                r_opA <= w_opA;
765 69 dgisselq
`ifdef  OPT_PIPELINED
766 71 dgisselq
                end else
767 48 dgisselq
                begin // We were going to pick these up when they became valid,
768
                        // but for some reason we're stuck here as they became
769
                        // valid.  Pick them up now anyway
770 71 dgisselq
                        // if (((opA_alu)&&(alu_wr))||((opA_mem)&&(mem_valid)))
771 160 dgisselq
                                // r_opA <= wr_gpreg_vl;
772 71 dgisselq
                        if ((wr_reg_ce)&&(wr_reg_id == opA_id)&&(opA_rd))
773 160 dgisselq
                                r_opA <= wr_gpreg_vl;
774 56 dgisselq
`endif
775 2 dgisselq
                end
776 56 dgisselq
 
777 69 dgisselq
        wire    [31:0]   w_opBnI, w_pcB_v;
778 56 dgisselq
        generate
779
        if (AW < 32)
780
                assign  w_pcB_v = {{(32-AW){1'b0}}, (dcdB[4] == dcd_gie)?dcd_pc:upc };
781
        else
782
                assign  w_pcB_v = (dcdB[4] == dcd_gie)?dcd_pc:upc;
783
        endgenerate
784
 
785 36 dgisselq
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
786 179 dgisselq
`ifdef  OPT_PIPELINED
787
                : ((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_gpreg_vl
788
`endif
789 56 dgisselq
                : ((dcdB_pc) ? w_pcB_v
790 179 dgisselq
                : ((dcdB_cc) ? { w_cpu_info, w_opB[22:16], // w_opB[31:14],
791
                        1'b0, (dcdB[4])?w_uflags:w_iflags}
792
                : w_opB));
793 56 dgisselq
 
794 2 dgisselq
        always @(posedge i_clk)
795 179 dgisselq
`ifdef  OPT_PIPELINED
796 160 dgisselq
                if (op_change_data_ce)
797 36 dgisselq
                        r_opB <= w_opBnI + dcdI;
798 71 dgisselq
                else if ((wr_reg_ce)&&(opB_id == wr_reg_id)&&(opB_rd))
799 160 dgisselq
                        r_opB <= wr_gpreg_vl;
800 179 dgisselq
`else
801
                r_opB <= w_opBnI + dcdI;
802 56 dgisselq
`endif
803 2 dgisselq
 
804
        // The logic here has become more complex than it should be, no thanks
805
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
806
        // be two sets of four bits: the top bits specify what bits matter, the
807
        // bottom specify what those top bits must equal.  However, two of
808
        // conditions check whether bits are on, and those are the only two
809
        // conditions checking those bits.  Therefore, Vivado complains that
810
        // these two bits are redundant.  Hence the convoluted expression
811
        // below, arriving at what we finally want in the (now wire net)
812
        // opF.
813
        always @(posedge i_clk)
814 179 dgisselq
`ifdef  OPT_PIPELINED
815 160 dgisselq
                if (op_ce) // Cannot do op_change_data_ce here since opF depends
816
                        // upon being either correct for a valid op, or correct
817
                        // for the last valid op
818 179 dgisselq
`endif
819 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
820 2 dgisselq
                        case(dcdF[2:0])
821 56 dgisselq
                        3'h0:   r_opF <= 6'h00; // Always
822 69 dgisselq
`ifdef  OPT_NEW_INSTRUCTION_SET
823
                        // These were remapped as part of the new instruction
824
                        // set in order to make certain that the low order
825
                        // two bits contained the most commonly used 
826
                        // conditions: Always, LT, Z, and NZ.
827
                        3'h1:   r_opF <= 6'h24; // LT
828
                        3'h2:   r_opF <= 6'h11; // Z
829
                        3'h3:   r_opF <= 6'h10; // NE
830
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
831
                        3'h5:   r_opF <= 6'h20; // GE (!N)
832
`else
833 56 dgisselq
                        3'h1:   r_opF <= 6'h11; // Z
834
                        3'h2:   r_opF <= 6'h10; // NE
835
                        3'h3:   r_opF <= 6'h20; // GE (!N)
836
                        3'h4:   r_opF <= 6'h30; // GT (!N&!Z)
837
                        3'h5:   r_opF <= 6'h24; // LT
838 69 dgisselq
`endif
839 56 dgisselq
                        3'h6:   r_opF <= 6'h02; // C
840
                        3'h7:   r_opF <= 6'h08; // V
841 2 dgisselq
                        endcase
842 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
843 56 dgisselq
        assign  opF = { r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
844 2 dgisselq
 
845 69 dgisselq
        wire    w_opvalid;
846 105 dgisselq
        assign  w_opvalid = (~clear_pipeline)&&(dcdvalid)&&(~dcd_ljmp);
847 36 dgisselq
        initial opvalid     = 1'b0;
848
        initial opvalid_alu = 1'b0;
849
        initial opvalid_mem = 1'b0;
850 91 dgisselq
        initial opvalid_div = 1'b0;
851
        initial opvalid_fpu = 1'b0;
852 2 dgisselq
        always @(posedge i_clk)
853 193 dgisselq
                if ((i_rst)||(clear_pipeline))
854 25 dgisselq
                begin
855
                        opvalid     <= 1'b0;
856
                        opvalid_alu <= 1'b0;
857
                        opvalid_mem <= 1'b0;
858 179 dgisselq
                        opvalid_div <= 1'b0;
859
                        opvalid_fpu <= 1'b0;
860 25 dgisselq
                end else if (op_ce)
861
                begin
862 2 dgisselq
                        // Do we have a valid instruction?
863
                        //   The decoder may vote to stall one of its
864
                        //   instructions based upon something we currently
865
                        //   have in our queue.  This instruction must then
866
                        //   move forward, and get a stall cycle inserted.
867
                        //   Hence, the test on dcd_stalled here.  If we must
868
                        //   wait until our operands are valid, then we aren't
869
                        //   valid yet until then.
870 179 dgisselq
                        opvalid<= (w_opvalid)||(dcd_illegal)&&(dcdvalid);
871 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
872 179 dgisselq
                        opvalid_alu <= (w_opvalid)&&((dcdALU)||(dcd_illegal));
873 69 dgisselq
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(w_opvalid);
874
                        opvalid_div <= (dcdDV)&&(~dcd_illegal)&&(w_opvalid);
875
                        opvalid_fpu <= (dcdFP)&&(~dcd_illegal)&&(w_opvalid);
876 36 dgisselq
`else
877 69 dgisselq
                        opvalid_alu <= (dcdALU)&&(w_opvalid);
878
                        opvalid_mem <= (dcdM)&&(w_opvalid);
879
                        opvalid_div <= (dcdDV)&&(w_opvalid);
880
                        opvalid_fpu <= (dcdFP)&&(w_opvalid);
881 36 dgisselq
`endif
882 193 dgisselq
                end else if ((adf_ce_unconditional)||(mem_ce))
883 25 dgisselq
                begin
884
                        opvalid     <= 1'b0;
885
                        opvalid_alu <= 1'b0;
886
                        opvalid_mem <= 1'b0;
887 69 dgisselq
                        opvalid_div <= 1'b0;
888
                        opvalid_fpu <= 1'b0;
889 25 dgisselq
                end
890 2 dgisselq
 
891
        // Here's part of our debug interface.  When we recognize a break
892
        // instruction, we set the op_break flag.  That'll prevent this
893
        // instruction from entering the ALU, and cause an interrupt before
894
        // this instruction.  Thus, returning to this code will cause the
895
        // break to repeat and continue upon return.  To get out of this
896
        // condition, replace the break instruction with what it is supposed
897
        // to be, step through it, and then replace it back.  In this fashion,
898
        // a debugger can step through code.
899 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
900 179 dgisselq
`ifdef  OPT_PIPELINED
901
        reg     r_op_break;
902
 
903
        initial r_op_break = 1'b0;
904 2 dgisselq
        always @(posedge i_clk)
905 179 dgisselq
                if (i_rst)      r_op_break <= 1'b0;
906 193 dgisselq
                else if (op_ce) r_op_break <= (dcd_break); //||dcd_illegal &&(dcdvalid)
907 25 dgisselq
                else if ((clear_pipeline)||(~opvalid))
908 179 dgisselq
                                r_op_break <= 1'b0;
909
        assign  op_break = r_op_break;
910
`else
911
        assign  op_break = dcd_break;
912
`endif
913 2 dgisselq
 
914 69 dgisselq
`ifdef  OPT_PIPELINED
915
        generate
916
        if (IMPLEMENT_LOCK != 0)
917
        begin
918
                reg     r_op_lock, r_op_lock_stall;
919
 
920
                initial r_op_lock_stall = 1'b0;
921
                always @(posedge i_clk)
922
                        if (i_rst)
923
                                r_op_lock_stall <= 1'b0;
924
                        else
925
                                r_op_lock_stall <= (~opvalid)||(~op_lock)
926
                                                ||(~dcdvalid)||(~pf_valid);
927
 
928
                assign  op_lock_stall = r_op_lock_stall;
929
 
930
                initial r_op_lock = 1'b0;
931
                always @(posedge i_clk)
932 160 dgisselq
                        if ((i_rst)||(clear_pipeline))
933 69 dgisselq
                                r_op_lock <= 1'b0;
934 132 dgisselq
                        else if (op_ce)
935
                                r_op_lock <= (dcd_lock)&&(~clear_pipeline);
936 69 dgisselq
                assign  op_lock = r_op_lock;
937
 
938
        end else begin
939
                assign  op_lock_stall = 1'b0;
940
                assign  op_lock = 1'b0;
941
        end endgenerate
942
 
943
`else
944
        assign op_lock_stall = 1'b0;
945
        assign op_lock       = 1'b0;
946
`endif
947
 
948 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
949 71 dgisselq
        initial op_illegal = 1'b0;
950 2 dgisselq
        always @(posedge i_clk)
951 71 dgisselq
                if ((i_rst)||(clear_pipeline))
952
                        op_illegal <= 1'b0;
953
                else if(op_ce)
954 69 dgisselq
`ifdef  OPT_PIPELINED
955 179 dgisselq
                        op_illegal <= (dcdvalid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0)));
956 69 dgisselq
`else
957 179 dgisselq
                        op_illegal <= (dcdvalid)&&((dcd_illegal)||(dcd_lock));
958 36 dgisselq
`endif
959 179 dgisselq
                else if(alu_ce)
960
                        op_illegal <= 1'b0;
961 69 dgisselq
`endif
962 36 dgisselq
 
963 71 dgisselq
        // No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
964
        // set, dcd_early_branch will simply be a wire connected to zero and
965
        // this logic should just optimize.
966 179 dgisselq
`ifdef  OPT_PIPELINED
967 71 dgisselq
        always @(posedge i_clk)
968
                if (op_ce)
969
                begin
970 83 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
971
                                &&(~dcd_early_branch)&&(~dcd_illegal);
972
                        opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
973 71 dgisselq
                end
974 179 dgisselq
`else
975
        always @(posedge i_clk)
976
        begin
977
                opF_wr <= (dcdF_wr)&&((~dcdR_cc)||(~dcdR_wr))
978
                        &&(~dcd_early_branch)&&(~dcd_illegal);
979
                opR_wr <= (dcdR_wr)&&(~dcd_early_branch)&&(~dcd_illegal);
980
        end
981
`endif
982 69 dgisselq
 
983 179 dgisselq
`ifdef  OPT_PIPELINED
984
        reg     [3:0]    r_opn;
985
        reg     [4:0]    r_opR;
986
        reg             r_opR_cc;
987
        reg             r_op_gie;
988 36 dgisselq
        always @(posedge i_clk)
989 160 dgisselq
                if (op_change_data_ce)
990 2 dgisselq
                begin
991 179 dgisselq
                        r_opn    <= dcdOp;      // Which ALU operation?
992 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
993 2 dgisselq
                        // What register will these results be written into?
994 179 dgisselq
                        r_opR    <= dcdR;
995
                        r_opR_cc <= (dcdR_cc)&&(dcdR_wr)&&(dcdR[4]==dcd_gie);
996 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
997 179 dgisselq
                        r_op_gie <= dcd_gie;
998 2 dgisselq
 
999 69 dgisselq
 
1000 2 dgisselq
                        //
1001 48 dgisselq
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
1002 2 dgisselq
                end
1003 179 dgisselq
        assign  opn = r_opn;
1004
        assign  opR = r_opR;
1005
        assign  op_gie = r_op_gie;
1006
        assign  opR_cc = r_opR_cc;
1007
`else
1008
        assign  opn = dcdOp;
1009
        assign  opR = dcdR;
1010
        assign  op_gie = dcd_gie;
1011
        // With no pipelining, there is no early branching.  We keep it
1012
        always @(posedge i_clk)
1013
                op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
1014
`endif
1015 2 dgisselq
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
1016
 
1017 69 dgisselq
`ifdef  OPT_VLIW
1018
        reg     r_op_phase;
1019
        initial r_op_phase = 1'b0;
1020
        always @(posedge i_clk)
1021
                if ((i_rst)||(clear_pipeline))
1022
                        r_op_phase <= 1'b0;
1023 160 dgisselq
                else if (op_change_data_ce)
1024 69 dgisselq
                        r_op_phase <= dcd_phase;
1025
        assign  op_phase = r_op_phase;
1026
`else
1027
        assign  op_phase = 1'b0;
1028
`endif
1029
 
1030 2 dgisselq
        // This is tricky.  First, the PC and Flags registers aren't kept in
1031
        // register set but in special registers of their own.  So step one
1032
        // is to select the right register.  Step to is to replace that
1033
        // register with the results of an ALU or memory operation, if such
1034
        // results are now available.  Otherwise, we'd need to insert a wait
1035
        // state of some type.
1036
        //
1037
        // The alternative approach would be to define some sort of
1038
        // op_stall wire, which would stall any upstream stage.
1039
        // We'll create a flag here to start our coordination.  Once we
1040
        // define this flag to something other than just plain zero, then
1041
        // the stalls will already be in place.
1042 69 dgisselq
`ifdef  OPT_PIPELINED
1043 83 dgisselq
        assign  opA = ((wr_reg_ce)&&(wr_reg_id == opA_id)) // &&(opA_rd))
1044 160 dgisselq
                        ?  wr_gpreg_vl : r_opA;
1045 56 dgisselq
`else
1046
        assign  opA = r_opA;
1047
`endif
1048 48 dgisselq
 
1049 69 dgisselq
`ifdef  OPT_PIPELINED
1050 83 dgisselq
        // Stall if we have decoded an instruction that will read register A
1051
        //      AND ... something that may write a register is running
1052
        //      AND (series of conditions here ...)
1053
        //              The operation might set flags, and we wish to read the
1054
        //                      CC register
1055
        //              OR ... (No other conditions)
1056
        assign  dcdA_stall = (dcdA_rd) // &&(dcdvalid) is checked for elsewhere
1057
                                &&((opvalid)||(mem_rdbusy)
1058
                                        ||(div_busy)||(fpu_busy))
1059 179 dgisselq
                                &&(((opF_wr)||(cc_invalid_for_dcd))&&(dcdA_cc))
1060
                        ||((dcdA_rd)&&(dcdA_cc)&&(cc_invalid_for_dcd));
1061 56 dgisselq
`else
1062 69 dgisselq
        // There are no pipeline hazards, if we aren't pipelined
1063
        assign  dcdA_stall = 1'b0;
1064 56 dgisselq
`endif
1065 36 dgisselq
 
1066 69 dgisselq
`ifdef  OPT_PIPELINED
1067 71 dgisselq
        assign  opB = ((wr_reg_ce)&&(wr_reg_id == opB_id)&&(opB_rd))
1068 160 dgisselq
                        ? wr_gpreg_vl: r_opB;
1069 56 dgisselq
`else
1070
        assign  opB = r_opB;
1071
`endif
1072
 
1073 69 dgisselq
`ifdef  OPT_PIPELINED
1074 83 dgisselq
        // Stall if we have decoded an instruction that will read register B
1075
        //      AND ... something that may write a (unknown) register is running
1076
        //      AND (series of conditions here ...)
1077
        //              The operation might set flags, and we wish to read the
1078
        //                      CC register
1079
        //              OR the operation might set register B, and we still need
1080
        //                      a clock to add the offset to it
1081
        assign  dcdB_stall = (dcdB_rd) // &&(dcdvalid) is checked for elsewhere
1082
                                // If the op stage isn't valid, yet something
1083
                                // is running, then it must have been valid.
1084
                                // We'll use the last values from that stage
1085
                                // (opR_wr, opF_wr, opR) in our logic below.
1086
                                &&((opvalid)||(mem_rdbusy)
1087 132 dgisselq
                                        ||(div_busy)||(fpu_busy)||(alu_busy))
1088 83 dgisselq
                                &&(
1089 145 dgisselq
                                // Okay, what happens if the result register
1090
                                // from instruction 1 becomes the input for
1091
                                // instruction two, *and* there's an immediate
1092
                                // offset in instruction two?  In that case, we
1093
                                // need an extra clock between the two 
1094
                                // instructions to calculate the base plus 
1095
                                // offset.
1096
                                //
1097
                                // What if instruction 1 (or before) is in a
1098
                                // memory pipeline?  We may no longer know what
1099
                                // the register was!  We will then need  to 
1100
                                // blindly wait.  We'll temper this only waiting
1101
                                // if we're not piping this new instruction.
1102
                                // If we were piping, the pipe logic in the
1103
                                // decode circuit has told us that the hazard
1104
                                // is clear, so we're okay then.
1105
                                //
1106 132 dgisselq
                                ((~dcd_zI)&&(
1107
                                        ((opR == dcdB)&&(opR_wr))
1108 145 dgisselq
                                        ||((mem_rdbusy)&&(~dcd_pipe))
1109
                                        ))
1110 83 dgisselq
                                // Stall following any instruction that will
1111
                                // set the flags, if we're going to need the
1112
                                // flags (CC) register for opB.
1113 179 dgisselq
                                ||(((opF_wr)||(cc_invalid_for_dcd))&&(dcdB_cc))
1114 38 dgisselq
                                // Stall on any ongoing memory operation that
1115 71 dgisselq
                                // will write to opB -- captured above
1116
                                // ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcdB)&&(~dcd_zI))
1117 179 dgisselq
                                )
1118
                        ||((dcdB_rd)&&(dcdB_cc)&&(cc_invalid_for_dcd));
1119 91 dgisselq
        assign  dcdF_stall = ((~dcdF[3])
1120
                                        ||((dcdA_rd)&&(dcdA_cc))
1121
                                        ||((dcdB_rd)&&(dcdB_cc)))
1122
                                        &&(opvalid)&&(opR_cc);
1123
                                // &&(dcdvalid) is checked for elsewhere
1124 56 dgisselq
`else
1125 69 dgisselq
        // No stalls without pipelining, 'cause how can you have a pipeline
1126
        // hazard without the pipeline?
1127
        assign  dcdB_stall = 1'b0;
1128 91 dgisselq
        assign  dcdF_stall = 1'b0;
1129 56 dgisselq
`endif
1130 2 dgisselq
        //
1131
        //
1132
        //      PIPELINE STAGE #4 :: Apply Instruction
1133
        //
1134
        //
1135 193 dgisselq
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, (i_rst)||(clear_pipeline),
1136
                        alu_ce, opn, opA, opB,
1137
                        alu_result, alu_flags, alu_valid, alu_busy);
1138 2 dgisselq
 
1139 69 dgisselq
        generate
1140
        if (IMPLEMENT_DIVIDE != 0)
1141
        begin
1142 83 dgisselq
                div thedivide(i_clk, (i_rst)||(clear_pipeline), div_ce, opn[0],
1143 69 dgisselq
                        opA, opB, div_busy, div_valid, div_error, div_result,
1144
                        div_flags);
1145
        end else begin
1146 179 dgisselq
                assign  div_error = 1'b0; // Can't be high unless div_valid
1147 69 dgisselq
                assign  div_busy  = 1'b0;
1148
                assign  div_valid = 1'b0;
1149
                assign  div_result= 32'h00;
1150
                assign  div_flags = 4'h0;
1151
        end endgenerate
1152
 
1153
        generate
1154
        if (IMPLEMENT_FPU != 0)
1155
        begin
1156
                //
1157
                // sfpu thefpu(i_clk, i_rst, fpu_ce,
1158
                //      opA, opB, fpu_busy, fpu_valid, fpu_err, fpu_result,
1159
                //      fpu_flags);
1160
                //
1161 179 dgisselq
                assign  fpu_error = 1'b0; // Must only be true if fpu_valid
1162 69 dgisselq
                assign  fpu_busy  = 1'b0;
1163
                assign  fpu_valid = 1'b0;
1164
                assign  fpu_result= 32'h00;
1165
                assign  fpu_flags = 4'h0;
1166
        end else begin
1167 179 dgisselq
                assign  fpu_error = 1'b0;
1168 69 dgisselq
                assign  fpu_busy  = 1'b0;
1169
                assign  fpu_valid = 1'b0;
1170
                assign  fpu_result= 32'h00;
1171
                assign  fpu_flags = 4'h0;
1172
        end endgenerate
1173
 
1174
 
1175 2 dgisselq
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
1176
        initial alF_wr   = 1'b0;
1177
        initial alu_wr   = 1'b0;
1178
        always @(posedge i_clk)
1179
                if (i_rst)
1180
                begin
1181
                        alu_wr   <= 1'b0;
1182
                        alF_wr   <= 1'b0;
1183
                end else if (alu_ce)
1184
                begin
1185 65 dgisselq
                        // alu_reg <= opR;
1186 2 dgisselq
                        alu_wr  <= (opR_wr)&&(set_cond);
1187
                        alF_wr  <= (opF_wr)&&(set_cond);
1188 71 dgisselq
                end else if (~alu_busy) begin
1189 2 dgisselq
                        // These are strobe signals, so clear them if not
1190
                        // set for any particular clock
1191 65 dgisselq
                        alu_wr <= (i_halt)&&(i_dbg_we);
1192 2 dgisselq
                        alF_wr <= 1'b0;
1193
                end
1194 69 dgisselq
 
1195
`ifdef  OPT_VLIW
1196
        reg     r_alu_phase;
1197
        initial r_alu_phase = 1'b0;
1198 2 dgisselq
        always @(posedge i_clk)
1199 69 dgisselq
                if (i_rst)
1200
                        r_alu_phase <= 1'b0;
1201 160 dgisselq
                else if ((adf_ce_unconditional)||(mem_ce))
1202 69 dgisselq
                        r_alu_phase <= op_phase;
1203
        assign  alu_phase = r_alu_phase;
1204
`else
1205
        assign  alu_phase = 1'b0;
1206
`endif
1207
 
1208 179 dgisselq
`ifdef  OPT_PIPELINED
1209 69 dgisselq
        always @(posedge i_clk)
1210 160 dgisselq
                if (adf_ce_unconditional)
1211 65 dgisselq
                        alu_reg <= opR;
1212
                else if ((i_halt)&&(i_dbg_we))
1213
                        alu_reg <= i_dbg_reg;
1214 179 dgisselq
`else
1215
        always @(posedge i_clk)
1216
                if ((i_halt)&&(i_dbg_we))
1217
                        alu_reg <= i_dbg_reg;
1218
                else
1219
                        alu_reg <= opR;
1220
`endif
1221 69 dgisselq
 
1222 132 dgisselq
        //
1223
        // DEBUG Register write access starts here
1224
        //
1225 65 dgisselq
        reg             dbgv;
1226
        initial dbgv = 1'b0;
1227
        always @(posedge i_clk)
1228 160 dgisselq
                dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
1229 132 dgisselq
        reg     [31:0]   dbg_val;
1230 65 dgisselq
        always @(posedge i_clk)
1231 132 dgisselq
                dbg_val <= i_dbg_data;
1232 179 dgisselq
`ifdef  OPT_PIPELINED
1233
        reg     r_alu_gie;
1234
 
1235 132 dgisselq
        always @(posedge i_clk)
1236 160 dgisselq
                if ((adf_ce_unconditional)||(mem_ce))
1237 179 dgisselq
                        r_alu_gie  <= op_gie;
1238
        assign  alu_gie = r_alu_gie;
1239
 
1240
        reg     [(AW-1):0]       r_alu_pc;
1241 2 dgisselq
        always @(posedge i_clk)
1242 160 dgisselq
                if ((adf_ce_unconditional)
1243
                        ||((master_ce)&&(opvalid_mem)&&(~clear_pipeline)
1244 65 dgisselq
                                &&(~mem_stalled)))
1245 179 dgisselq
                        r_alu_pc  <= op_pc;
1246
        assign  alu_pc = r_alu_pc;
1247
`else
1248
        assign  alu_gie = op_gie;
1249
        assign  alu_pc = op_pc;
1250
`endif
1251 65 dgisselq
 
1252 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1253 56 dgisselq
        reg     r_alu_illegal;
1254
        initial r_alu_illegal = 0;
1255 38 dgisselq
        always @(posedge i_clk)
1256 179 dgisselq
                if ((i_rst)||(clear_pipeline))
1257 71 dgisselq
                        r_alu_illegal <= 1'b0;
1258 179 dgisselq
                else if (alu_ce)
1259 56 dgisselq
                        r_alu_illegal <= op_illegal;
1260 179 dgisselq
                else
1261
                        r_alu_illegal <= 1'b0;
1262 193 dgisselq
        assign  alu_illegal = (r_alu_illegal);
1263 179 dgisselq
`else
1264
        assign  alu_illegal = 1'b0;
1265 38 dgisselq
`endif
1266
 
1267 145 dgisselq
        initial r_alu_pc_valid = 1'b0;
1268 132 dgisselq
        initial mem_pc_valid = 1'b0;
1269 2 dgisselq
        always @(posedge i_clk)
1270 132 dgisselq
                if (i_rst)
1271 145 dgisselq
                        r_alu_pc_valid <= 1'b0;
1272 160 dgisselq
                else if (adf_ce_unconditional)//Includes&&(~alu_clear_pipeline)
1273 145 dgisselq
                        r_alu_pc_valid <= 1'b1;
1274 160 dgisselq
                else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
1275 145 dgisselq
                        r_alu_pc_valid <= 1'b0;
1276 160 dgisselq
        assign  alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
1277 132 dgisselq
        always @(posedge i_clk)
1278
                if (i_rst)
1279
                        mem_pc_valid <= 1'b0;
1280
                else
1281
                        mem_pc_valid <= (mem_ce);
1282 2 dgisselq
 
1283 69 dgisselq
        wire    bus_lock;
1284
`ifdef  OPT_PIPELINED
1285
        generate
1286
        if (IMPLEMENT_LOCK != 0)
1287
        begin
1288 132 dgisselq
                reg     [1:0]    r_bus_lock;
1289
                initial r_bus_lock = 2'b00;
1290 69 dgisselq
                always @(posedge i_clk)
1291
                        if (i_rst)
1292 132 dgisselq
                                r_bus_lock <= 2'b00;
1293 69 dgisselq
                        else if ((op_ce)&&(op_lock))
1294 132 dgisselq
                                r_bus_lock <= 2'b11;
1295
                        else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce)))
1296
                                r_bus_lock <= r_bus_lock + 2'b11;
1297
                assign  bus_lock = |r_bus_lock;
1298 69 dgisselq
        end else begin
1299
                assign  bus_lock = 1'b0;
1300
        end endgenerate
1301
`else
1302
        assign  bus_lock = 1'b0;
1303
`endif
1304
 
1305 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
1306 71 dgisselq
        pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1307 38 dgisselq
                                (opn[0]), opB, opA, opR,
1308
                                mem_busy, mem_pipe_stalled,
1309
                                mem_valid, bus_err, mem_wreg, mem_result,
1310
                        mem_cyc_gbl, mem_cyc_lcl,
1311
                                mem_stb_gbl, mem_stb_lcl,
1312
                                mem_we, mem_addr, mem_data,
1313
                                mem_ack, mem_stall, mem_err, i_wb_data);
1314
 
1315
`else // PIPELINED_BUS_ACCESS
1316 71 dgisselq
        memops  #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1317 2 dgisselq
                                (opn[0]), opB, opA, opR,
1318 38 dgisselq
                                mem_busy,
1319
                                mem_valid, bus_err, mem_wreg, mem_result,
1320 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
1321
                                mem_stb_gbl, mem_stb_lcl,
1322
                                mem_we, mem_addr, mem_data,
1323
                                mem_ack, mem_stall, mem_err, i_wb_data);
1324 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
1325 65 dgisselq
        assign  mem_rdbusy = ((mem_busy)&&(~mem_we));
1326 2 dgisselq
 
1327
        // Either the prefetch or the instruction gets the memory bus, but 
1328
        // never both.
1329 48 dgisselq
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
1330 36 dgisselq
                // Memory access to the arbiter, priority position
1331
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1332
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
1333 2 dgisselq
                // Prefetch access to the arbiter
1334 36 dgisselq
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
1335
                        pf_ack, pf_stall, pf_err,
1336 2 dgisselq
                // Common wires, in and out, of the arbiter
1337 36 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1338
                        o_wb_we, o_wb_addr, o_wb_data,
1339
                        i_wb_ack, i_wb_stall, i_wb_err);
1340 2 dgisselq
 
1341 132 dgisselq
 
1342
 
1343 2 dgisselq
        //
1344
        //
1345 132 dgisselq
        //
1346
        //
1347
        //
1348
        //
1349
        //
1350
        //
1351 2 dgisselq
        //      PIPELINE STAGE #5 :: Write-back results
1352
        //
1353
        //
1354
        // This stage is not allowed to stall.  If results are ready to be
1355
        // written back, they are written back at all cost.  Sleepy CPU's
1356
        // won't prevent write back, nor debug modes, halting the CPU, nor
1357
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1358
        // as knowinig something is available for writeback.
1359
 
1360
        //
1361
        // Write back to our generic register set ...
1362
        // When shall we write back?  On one of two conditions
1363
        //      Note that the flags needed to be checked before issuing the
1364
        //      bus instruction, so they don't need to be checked here.
1365
        //      Further, alu_wr includes (set_cond), so we don't need to
1366
        //      check for that here either.
1367 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1368 160 dgisselq
        assign  wr_reg_ce = (dbgv)||(mem_valid)
1369
                                ||((~clear_pipeline)&&(~alu_illegal)
1370
                                        &&(((alu_wr)&&(alu_valid))
1371
                                                ||(div_valid)||(fpu_valid)));
1372 36 dgisselq
`else
1373 160 dgisselq
        assign  wr_reg_ce = (dbgv)||(mem_valid)
1374
                                ||((~clear_pipeline)
1375
                                        &&(((alu_wr)&&(alu_valid))
1376
                                                ||(div_valid)||(fpu_valid)));
1377 36 dgisselq
`endif
1378 2 dgisselq
        // Which register shall be written?
1379 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1380
        //              One or PC, one for CC, and one for GIE match
1381 69 dgisselq
        //      Note that the alu_reg is the register to write on a divide or
1382
        //      FPU operation.
1383 160 dgisselq
        assign  wr_reg_id = (alu_wr|div_valid|fpu_valid)?alu_reg:mem_wreg;
1384 25 dgisselq
        // Are we writing to the CC register?
1385
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1386 179 dgisselq
        assign  wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
1387
        assign  wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
1388 2 dgisselq
        // Are we writing to the PC?
1389
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1390 179 dgisselq
 
1391 2 dgisselq
        // What value to write?
1392 160 dgisselq
        assign  wr_gpreg_vl = ((mem_valid) ? mem_result
1393 71 dgisselq
                                :((div_valid|fpu_valid))
1394
                                        ? ((div_valid) ? div_result:fpu_result)
1395
                                :((dbgv) ? dbg_val : alu_result));
1396 160 dgisselq
        assign  wr_spreg_vl = ((mem_valid) ? mem_result
1397
                                :((dbgv) ? dbg_val : alu_result));
1398 2 dgisselq
        always @(posedge i_clk)
1399
                if (wr_reg_ce)
1400 160 dgisselq
                        regset[wr_reg_id] <= wr_gpreg_vl;
1401 2 dgisselq
 
1402
        //
1403
        // Write back to the condition codes/flags register ...
1404
        // When shall we write to our flags register?  alF_wr already
1405
        // includes the set condition ...
1406 69 dgisselq
        assign  wr_flags_ce = ((alF_wr)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
1407 179 dgisselq
        assign  w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag,
1408 71 dgisselq
                        udiv_err_flag, ubus_err_flag, trap, ill_err_u,
1409 179 dgisselq
                        ubreak, step, 1'b1, sleep,
1410 71 dgisselq
                        ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1411 179 dgisselq
        assign  w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag,
1412 71 dgisselq
                        idiv_err_flag, ibus_err_flag, trap, ill_err_i,
1413
                        break_en, 1'b0, 1'b0, sleep,
1414
                        ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1415 69 dgisselq
 
1416
 
1417 2 dgisselq
        // What value to write?
1418
        always @(posedge i_clk)
1419
                // If explicitly writing the register itself
1420 179 dgisselq
                if ((wr_reg_ce)&&(wr_write_ucc))
1421 160 dgisselq
                        flags <= wr_gpreg_vl[3:0];
1422 2 dgisselq
                // Otherwise if we're setting the flags from an ALU operation
1423
                else if ((wr_flags_ce)&&(alu_gie))
1424 69 dgisselq
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1425
                                : alu_flags);
1426 2 dgisselq
 
1427
        always @(posedge i_clk)
1428 179 dgisselq
                if ((wr_reg_ce)&&(wr_write_scc))
1429 160 dgisselq
                        iflags <= wr_gpreg_vl[3:0];
1430 2 dgisselq
                else if ((wr_flags_ce)&&(~alu_gie))
1431 69 dgisselq
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1432
                                : alu_flags);
1433 2 dgisselq
 
1434
        // The 'break' enable  bit.  This bit can only be set from supervisor
1435
        // mode.  It control what the CPU does upon encountering a break
1436
        // instruction.
1437
        //
1438
        // The goal, upon encountering a break is that the CPU should stop and
1439
        // not execute the break instruction, choosing instead to enter into
1440
        // either interrupt mode or halt first.  
1441
        //      if ((break_en) AND (break_instruction)) // user mode or not
1442
        //              HALT CPU
1443
        //      else if (break_instruction) // only in user mode
1444 179 dgisselq
        //              set an interrupt flag, set the user break bit,
1445
        //              go to supervisor mode, allow supervisor to step the CPU.
1446 2 dgisselq
        //      Upon a CPU halt, any break condition will be reset.  The
1447
        //      external debugger will then need to deal with whatever
1448
        //      condition has taken place.
1449
        initial break_en = 1'b0;
1450
        always @(posedge i_clk)
1451
                if ((i_rst)||(i_halt))
1452
                        break_en <= 1'b0;
1453 179 dgisselq
                else if ((wr_reg_ce)&&(wr_write_scc))
1454 160 dgisselq
                        break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
1455 179 dgisselq
 
1456
`ifdef  OPT_PIPELINED
1457
        reg     r_break_pending;
1458
 
1459
        initial r_break_pending = 1'b0;
1460
        always @(posedge i_clk)
1461
                if ((i_rst)||(clear_pipeline)||(~opvalid))
1462
                        r_break_pending <= 1'b0;
1463
                else if (op_break)
1464 193 dgisselq
                        r_break_pending <= (~alu_busy)&&(~div_busy)&&(~fpu_busy)&&(~mem_busy)&&(!wr_reg_ce);
1465 179 dgisselq
                else
1466
                        r_break_pending <= 1'b0;
1467
        assign  break_pending = r_break_pending;
1468 36 dgisselq
`else
1469 179 dgisselq
        assign  break_pending = op_break;
1470 36 dgisselq
`endif
1471 2 dgisselq
 
1472
 
1473 179 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(break_pending)
1474
                                &&(~clear_pipeline)
1475
                        ||((~alu_gie)&&(bus_err))
1476
                        ||((~alu_gie)&&(div_error))
1477
                        ||((~alu_gie)&&(fpu_error))
1478 193 dgisselq
                        ||((~alu_gie)&&(alu_illegal)&&(!clear_pipeline));
1479 179 dgisselq
 
1480 2 dgisselq
        // The sleep register.  Setting the sleep register causes the CPU to
1481
        // sleep until the next interrupt.  Setting the sleep register within
1482
        // interrupt mode causes the processor to halt until a reset.  This is
1483 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1484
        // set the sleep bit and switch to supervisor mode in the same 
1485
        // instruction: users are not allowed to halt the CPU.
1486 2 dgisselq
        always @(posedge i_clk)
1487 69 dgisselq
                if ((i_rst)||(w_switch_to_interrupt))
1488 2 dgisselq
                        sleep <= 1'b0;
1489 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1490
                        // In supervisor mode, we have no protections.  The
1491
                        // supervisor can set the sleep bit however he wants.
1492 69 dgisselq
                        // Well ... not quite.  Switching to user mode and
1493
                        // sleep mode shouold only be possible if the interrupt
1494
                        // flag isn't set.
1495 160 dgisselq
                        //      Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
1496 69 dgisselq
                        //              don't set the sleep bit
1497
                        //      otherwise however it would o.w. be set
1498 160 dgisselq
                        sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
1499
                                &&((~i_interrupt)||(~wr_spreg_vl[`CPU_GIE_BIT]));
1500
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
1501 25 dgisselq
                        // In user mode, however, you can only set the sleep
1502
                        // mode while remaining in user mode.  You can't switch
1503
                        // to sleep mode *and* supervisor mode at the same
1504
                        // time, lest you halt the CPU.
1505 160 dgisselq
                        sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
1506 2 dgisselq
 
1507
        always @(posedge i_clk)
1508 193 dgisselq
                if (i_rst)
1509 2 dgisselq
                        step <= 1'b0;
1510 179 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_write_ucc))
1511 160 dgisselq
                        step <= wr_spreg_vl[`CPU_STEP_BIT];
1512 2 dgisselq
 
1513
        // The GIE register.  Only interrupts can disable the interrupt register
1514
        assign  w_switch_to_interrupt = (gie)&&(
1515
                        // On interrupt (obviously)
1516 69 dgisselq
                        ((i_interrupt)&&(~alu_phase)&&(~bus_lock))
1517 2 dgisselq
                        // If we are stepping the CPU
1518 132 dgisselq
                        ||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
1519 2 dgisselq
                        // If we encounter a break instruction, if the break
1520 36 dgisselq
                        //      enable isn't set.
1521 179 dgisselq
                        ||((master_ce)&&(break_pending)&&(~break_en))
1522 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1523 36 dgisselq
                        // On an illegal instruction
1524 193 dgisselq
                        ||((alu_illegal)&&(!clear_pipeline))
1525 36 dgisselq
`endif
1526 71 dgisselq
                        // On division by zero.  If the divide isn't
1527
                        // implemented, div_valid and div_error will be short
1528
                        // circuited and that logic will be bypassed
1529 179 dgisselq
                        ||(div_error)
1530
                        // Same thing on a floating point error.  Note that
1531
                        // fpu_error must *never* be set unless fpu_valid is
1532
                        // also set as well, else this will fail.
1533
                        ||(fpu_error)
1534 71 dgisselq
                        //      
1535 69 dgisselq
                        ||(bus_err)
1536 2 dgisselq
                        // If we write to the CC register
1537 160 dgisselq
                        ||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
1538 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1539 2 dgisselq
                        );
1540
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1541 179 dgisselq
                        // Then if we write the sCC register
1542 160 dgisselq
                        &&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
1543 179 dgisselq
                                &&(wr_write_scc))
1544 2 dgisselq
                        );
1545
        always @(posedge i_clk)
1546
                if (i_rst)
1547
                        gie <= 1'b0;
1548
                else if (w_switch_to_interrupt)
1549
                        gie <= 1'b0;
1550
                else if (w_release_from_interrupt)
1551
                        gie <= 1'b1;
1552
 
1553 25 dgisselq
        initial trap = 1'b0;
1554
        always @(posedge i_clk)
1555 179 dgisselq
                if ((i_rst)||(w_release_from_interrupt))
1556 25 dgisselq
                        trap <= 1'b0;
1557 160 dgisselq
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
1558 179 dgisselq
                                &&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
1559 25 dgisselq
                        trap <= 1'b1;
1560 179 dgisselq
                else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie))
1561
                        trap <= (trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
1562 25 dgisselq
 
1563 179 dgisselq
        initial ubreak = 1'b0;
1564
        always @(posedge i_clk)
1565
                if ((i_rst)||(w_release_from_interrupt))
1566
                        ubreak <= 1'b0;
1567
                else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
1568
                        ubreak <= 1'b1;
1569
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
1570
                        ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
1571
 
1572
 
1573 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1574 65 dgisselq
        initial ill_err_i = 1'b0;
1575 36 dgisselq
        always @(posedge i_clk)
1576
                if (i_rst)
1577 65 dgisselq
                        ill_err_i <= 1'b0;
1578 132 dgisselq
                // Only the debug interface can clear this bit
1579 179 dgisselq
                else if ((dbgv)&&(wr_write_scc))
1580
                        ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
1581 193 dgisselq
                else if ((alu_illegal)&&(~alu_gie)&&(!clear_pipeline))
1582 65 dgisselq
                        ill_err_i <= 1'b1;
1583
        initial ill_err_u = 1'b0;
1584
        always @(posedge i_clk)
1585
                // The bit is automatically cleared on release from interrupt
1586 179 dgisselq
                // or reset
1587
                if ((i_rst)||(w_release_from_interrupt))
1588 65 dgisselq
                        ill_err_u <= 1'b0;
1589 179 dgisselq
                // If the supervisor (or debugger) writes to this register,
1590
                // clearing the bit, then clear it
1591
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
1592
                        ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
1593 193 dgisselq
                else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline))
1594 65 dgisselq
                        ill_err_u <= 1'b1;
1595 38 dgisselq
`else
1596 65 dgisselq
        assign ill_err_u = 1'b0;
1597
        assign ill_err_i = 1'b0;
1598 36 dgisselq
`endif
1599 65 dgisselq
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
1600
        // ever set.
1601
        initial ibus_err_flag = 1'b0;
1602 36 dgisselq
        always @(posedge i_clk)
1603
                if (i_rst)
1604 65 dgisselq
                        ibus_err_flag <= 1'b0;
1605 179 dgisselq
                else if ((dbgv)&&(wr_write_scc))
1606
                        ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
1607 65 dgisselq
                else if ((bus_err)&&(~alu_gie))
1608
                        ibus_err_flag <= 1'b1;
1609
        // User bus error flag -- if ever set, it will cause an interrupt to
1610
        // supervisor mode.  
1611
        initial ubus_err_flag = 1'b0;
1612
        always @(posedge i_clk)
1613 179 dgisselq
                if ((i_rst)||(w_release_from_interrupt))
1614 65 dgisselq
                        ubus_err_flag <= 1'b0;
1615 179 dgisselq
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
1616
                        ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
1617 36 dgisselq
                else if ((bus_err)&&(alu_gie))
1618 65 dgisselq
                        ubus_err_flag <= 1'b1;
1619 36 dgisselq
 
1620 69 dgisselq
        generate
1621
        if (IMPLEMENT_DIVIDE != 0)
1622
        begin
1623
                reg     r_idiv_err_flag, r_udiv_err_flag;
1624
 
1625
                // Supervisor/interrupt divide (by zero) error flag -- this will
1626
                // crash the CPU if ever set.  This bit is thus available for us
1627
                // to be able to tell if/why the CPU crashed.
1628
                initial r_idiv_err_flag = 1'b0;
1629
                always @(posedge i_clk)
1630
                        if (i_rst)
1631
                                r_idiv_err_flag <= 1'b0;
1632 179 dgisselq
                        else if ((dbgv)&&(wr_write_scc))
1633
                                r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
1634
                        else if ((div_error)&&(~alu_gie))
1635 69 dgisselq
                                r_idiv_err_flag <= 1'b1;
1636
                // User divide (by zero) error flag -- if ever set, it will
1637
                // cause a sudden switch interrupt to supervisor mode.  
1638
                initial r_udiv_err_flag = 1'b0;
1639
                always @(posedge i_clk)
1640 179 dgisselq
                        if ((i_rst)||(w_release_from_interrupt))
1641 69 dgisselq
                                r_udiv_err_flag <= 1'b0;
1642
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1643 179 dgisselq
                                        &&(wr_write_ucc))
1644
                                r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
1645
                        else if ((div_error)&&(alu_gie))
1646 69 dgisselq
                                r_udiv_err_flag <= 1'b1;
1647
 
1648
                assign  idiv_err_flag = r_idiv_err_flag;
1649
                assign  udiv_err_flag = r_udiv_err_flag;
1650
        end else begin
1651
                assign  idiv_err_flag = 1'b0;
1652
                assign  udiv_err_flag = 1'b0;
1653
        end endgenerate
1654
 
1655
        generate
1656
        if (IMPLEMENT_FPU !=0)
1657
        begin
1658
                // Supervisor/interrupt floating point error flag -- this will
1659
                // crash the CPU if ever set.
1660
                reg             r_ifpu_err_flag, r_ufpu_err_flag;
1661
                initial r_ifpu_err_flag = 1'b0;
1662
                always @(posedge i_clk)
1663
                        if (i_rst)
1664
                                r_ifpu_err_flag <= 1'b0;
1665 179 dgisselq
                        else if ((dbgv)&&(wr_write_scc))
1666
                                r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
1667 69 dgisselq
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
1668
                                r_ifpu_err_flag <= 1'b1;
1669
                // User floating point error flag -- if ever set, it will cause
1670
                // a sudden switch interrupt to supervisor mode.  
1671
                initial r_ufpu_err_flag = 1'b0;
1672
                always @(posedge i_clk)
1673 179 dgisselq
                        if ((i_rst)&&(w_release_from_interrupt))
1674 69 dgisselq
                                r_ufpu_err_flag <= 1'b0;
1675
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1676 179 dgisselq
                                        &&(wr_write_ucc))
1677
                                r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
1678 69 dgisselq
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
1679
                                r_ufpu_err_flag <= 1'b1;
1680
 
1681
                assign  ifpu_err_flag = r_ifpu_err_flag;
1682
                assign  ufpu_err_flag = r_ufpu_err_flag;
1683
        end else begin
1684
                assign  ifpu_err_flag = 1'b0;
1685
                assign  ufpu_err_flag = 1'b0;
1686
        end endgenerate
1687
 
1688
`ifdef  OPT_VLIW
1689
        reg             r_ihalt_phase, r_uhalt_phase;
1690
 
1691
        initial r_ihalt_phase = 0;
1692
        initial r_uhalt_phase = 0;
1693
        always @(posedge i_clk)
1694 179 dgisselq
                if (i_rst)
1695
                        r_ihalt_phase <= 1'b0;
1696
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1697 69 dgisselq
                        r_ihalt_phase <= alu_phase;
1698
        always @(posedge i_clk)
1699 179 dgisselq
                if ((i_rst)||(w_release_from_interrupt))
1700
                        r_uhalt_phase <= 1'b0;
1701
                else if ((alu_gie)&&(alu_pc_valid))
1702 69 dgisselq
                        r_uhalt_phase <= alu_phase;
1703 179 dgisselq
                else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc))
1704
                        r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT];
1705 69 dgisselq
 
1706
        assign  ihalt_phase = r_ihalt_phase;
1707
        assign  uhalt_phase = r_uhalt_phase;
1708
`else
1709
        assign  ihalt_phase = 1'b0;
1710
        assign  uhalt_phase = 1'b0;
1711
`endif
1712
 
1713 2 dgisselq
        //
1714
        // Write backs to the PC register, and general increments of it
1715
        //      We support two: upc and ipc.  If the instruction is normal,
1716
        // we increment upc, if interrupt level we increment ipc.  If
1717
        // the instruction writes the PC, we write whichever PC is appropriate.
1718
        //
1719
        // Do we need to all our partial results from the pipeline?
1720
        // What happens when the pipeline has gie and ~gie instructions within
1721
        // it?  Do we clear both?  What if a gie instruction tries to clear
1722
        // a non-gie instruction?
1723
        always @(posedge i_clk)
1724 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1725 160 dgisselq
                        upc <= wr_spreg_vl[(AW-1):0];
1726 132 dgisselq
                else if ((alu_gie)&&
1727 193 dgisselq
                                (((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal))
1728 132 dgisselq
                                ||(mem_pc_valid)))
1729 2 dgisselq
                        upc <= alu_pc;
1730
 
1731
        always @(posedge i_clk)
1732
                if (i_rst)
1733
                        ipc <= RESET_ADDRESS;
1734
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1735 160 dgisselq
                        ipc <= wr_spreg_vl[(AW-1):0];
1736 132 dgisselq
                else if ((~alu_gie)&&
1737
                                (((alu_pc_valid)&&(~clear_pipeline))
1738
                                ||(mem_pc_valid)))
1739 2 dgisselq
                        ipc <= alu_pc;
1740
 
1741
        always @(posedge i_clk)
1742
                if (i_rst)
1743
                        pf_pc <= RESET_ADDRESS;
1744 179 dgisselq
                else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache)))
1745 2 dgisselq
                        pf_pc <= ipc;
1746 179 dgisselq
                else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache)))
1747 2 dgisselq
                        pf_pc <= upc;
1748
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1749 160 dgisselq
                        pf_pc <= wr_spreg_vl[(AW-1):0];
1750 69 dgisselq
`ifdef  OPT_PIPELINED
1751 105 dgisselq
                else if ((dcd_early_branch)&&(~clear_pipeline))
1752 69 dgisselq
                        pf_pc <= dcd_branch_pc + 1;
1753
                else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
1754 56 dgisselq
                        pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
1755 69 dgisselq
`else
1756 145 dgisselq
                else if ((alu_gie==gie)&&(
1757
                                ((alu_pc_valid)&&(~clear_pipeline))
1758
                                ||(mem_pc_valid)))
1759 69 dgisselq
                        pf_pc <= alu_pc;
1760
`endif
1761 2 dgisselq
 
1762
        initial new_pc = 1'b1;
1763
        always @(posedge i_clk)
1764 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
1765 2 dgisselq
                        new_pc <= 1'b1;
1766
                else if (w_switch_to_interrupt)
1767
                        new_pc <= 1'b1;
1768
                else if (w_release_from_interrupt)
1769
                        new_pc <= 1'b1;
1770
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1771
                        new_pc <= 1'b1;
1772
                else
1773
                        new_pc <= 1'b0;
1774
 
1775 179 dgisselq
`ifdef  OPT_PIPELINED
1776
        reg     r_clear_icache;
1777
        initial r_clear_icache = 1'b1;
1778
        always @(posedge i_clk)
1779
                if ((i_rst)||(i_clear_pf_cache))
1780
                        r_clear_icache <= 1'b1;
1781
                else if ((wr_reg_ce)&&(wr_write_scc))
1782
                        r_clear_icache <=  wr_spreg_vl[`CPU_CLRCACHE_BIT];
1783
                else
1784
                        r_clear_icache <= 1'b0;
1785
        assign  w_clear_icache = r_clear_icache;
1786
`else
1787
        assign  w_clear_icache = 1'b0;
1788
`endif
1789
 
1790 2 dgisselq
        //
1791
        // The debug interface
1792 56 dgisselq
        generate
1793
        if (AW<32)
1794
        begin
1795
                always @(posedge i_clk)
1796 2 dgisselq
                begin
1797
                        o_dbg_reg <= regset[i_dbg_reg];
1798
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1799 48 dgisselq
                                o_dbg_reg <= {{(32-AW){1'b0}},(i_dbg_reg[4])?upc:ipc};
1800 2 dgisselq
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1801 56 dgisselq
                        begin
1802 179 dgisselq
                                o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1803
                                o_dbg_reg[15] <= 1'b0;
1804
                                o_dbg_reg[31:23] <= w_cpu_info;
1805 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1806
                        end
1807 2 dgisselq
                end
1808 56 dgisselq
        end else begin
1809
                always @(posedge i_clk)
1810
                begin
1811
                        o_dbg_reg <= regset[i_dbg_reg];
1812
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1813
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
1814
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1815
                        begin
1816 179 dgisselq
                                o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1817
                                o_dbg_reg[15] <= 1'b0;
1818
                                o_dbg_reg[31:23] <= w_cpu_info;
1819 56 dgisselq
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
1820
                        end
1821
                end
1822
        end endgenerate
1823
 
1824 2 dgisselq
        always @(posedge i_clk)
1825 56 dgisselq
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
1826 18 dgisselq
 
1827 179 dgisselq
`ifdef  OPT_PIPELINED
1828 18 dgisselq
        always @(posedge i_clk)
1829 160 dgisselq
                r_halted <= (i_halt)&&(
1830 179 dgisselq
                        // To be halted, any long lasting instruction must
1831
                        // be completed.
1832
                        (~pf_cyc)&&(~mem_busy)&&(~alu_busy)
1833
                                &&(~div_busy)&&(~fpu_busy)
1834
                        // Operations must either be valid, or illegal
1835
                        &&((opvalid)||(i_rst)||(dcd_illegal))
1836
                        // Decode stage must be either valid, in reset, or ill
1837
                        &&((dcdvalid)||(i_rst)||(pf_illegal)));
1838
`else
1839
        always @(posedge i_clk)
1840
                r_halted <= (i_halt)&&((opvalid)||(i_rst));
1841
`endif
1842
        assign  o_dbg_stall = ~r_halted;
1843 2 dgisselq
 
1844
        //
1845
        //
1846
        // Produce accounting outputs: Account for any CPU stalls, so we can
1847
        // later evaluate how well we are doing.
1848
        //
1849
        //
1850 71 dgisselq
        assign  o_op_stall = (master_ce)&&(op_stall);
1851 9 dgisselq
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1852 38 dgisselq
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1853 56 dgisselq
 
1854 65 dgisselq
`ifdef  DEBUG_SCOPE
1855 56 dgisselq
        always @(posedge i_clk)
1856 65 dgisselq
                o_debug <= {
1857 179 dgisselq
                /*
1858 132 dgisselq
                        o_break, i_wb_err, pf_pc[1:0],
1859
                        flags,
1860 56 dgisselq
                        pf_valid, dcdvalid, opvalid, alu_valid, mem_valid,
1861
                        op_ce, alu_ce, mem_ce,
1862 65 dgisselq
                        //
1863
                        master_ce, opvalid_alu, opvalid_mem,
1864
                        //
1865
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
1866
                        mem_we,
1867
                        // ((opvalid_alu)&&(alu_stall))
1868
                        // ||((opvalid_mem)&&(~op_pipe)&&(mem_busy))
1869
                        // ||((opvalid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
1870
                        // opA[23:20], opA[3:0],
1871 160 dgisselq
                        gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
1872 179 dgisselq
                */
1873 71 dgisselq
                /*
1874 69 dgisselq
                        i_rst, master_ce, (new_pc),
1875
                        ((dcd_early_branch)&&(dcdvalid)),
1876
                        pf_valid, pf_illegal,
1877
                        op_ce, dcd_ce, dcdvalid, dcd_stalled,
1878
                        pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
1879
                        pf_pc[7:0], pf_addr[7:0]
1880 71 dgisselq
                */
1881 179 dgisselq
 
1882 132 dgisselq
                        i_wb_err, gie, alu_illegal,
1883
                              (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
1884
                        mem_busy,
1885
                                (mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
1886
                                        o_wb_addr[8:0] }
1887
                                        : { instruction[31:21] },
1888
                        pf_valid, (pf_valid) ? alu_pc[14:0]
1889
                                :{ pf_cyc, pf_stb, pf_pc[12:0] }
1890 179 dgisselq
 
1891 132 dgisselq
                /*
1892
                        i_wb_err, gie, new_pc, dcd_early_branch,        // 4
1893
                        pf_valid, pf_cyc, pf_stb, instruction_pc[0],    // 4
1894
                        instruction[30:27],                             // 4
1895
                        dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb,  // 4
1896
                        dcdvalid,
1897
                        ((dcd_early_branch)&&(~clear_pipeline))         // 15
1898
                                        ? dcd_branch_pc[14:0]:pf_pc[14:0]
1899
                */
1900 56 dgisselq
                        };
1901 65 dgisselq
`endif
1902 56 dgisselq
 
1903 2 dgisselq
endmodule

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