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1 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipcpu.v
4
//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This is the top level module holding the core of the Zip CPU
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//              together.  The Zip CPU is designed to be as simple as possible.
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//      (actual implementation aside ...)  The instruction set is about as
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//      RISC as you can get, with only 26 instruction types currently supported.
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//      (There are still 8-instruction Op-Codes reserved for floating point,
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//      and 5 which can be used for transactions not requiring registers.)
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//      Please see the accompanying spec.pdf file for a description of these
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//      instructions.
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//
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//      All instructions are 32-bits wide.  All bus accesses, both address and
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//      data, are 32-bits over a wishbone bus.
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//
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//      The Zip CPU is fully pipelined with the following pipeline stages:
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//
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//              1. Prefetch, returns the instruction from memory.
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//
23
//              2. Instruction Decode
24
//
25
//              3. Read Operands
26
//
27
//              4. Apply Instruction
28
//
29
//              4. Write-back Results
30
//
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//      Further information about the inner workings of this CPU, such as
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//      what causes pipeline stalls, may be found in the spec.pdf file.  (The
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//      documentation within this file had become out of date and out of sync
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//      with the spec.pdf, so look to the spec.pdf for accurate and up to date
35
//      information.)
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//
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//
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//      In general, the pipelining is controlled by three pieces of logic
39
//      per stage: _ce, _stall, and _valid.  _valid means that the stage
40
//      holds a valid instruction.  _ce means that the instruction from the
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//      previous stage is to move into this one, and _stall means that the
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//      instruction from the previous stage may not move into this one.
43
//      The difference between these control signals allows individual stages
44
//      to propagate instructions independently.  In general, the logic works
45
//      as:
46
//
47
//
48
//      assign  (n)_ce = (n-1)_valid && (~(n)_stall)
49
//
50
//
51
//      always @(posedge i_clk)
52
//              if ((i_rst)||(clear_pipeline))
53
//                      (n)_valid = 0
54
//              else if (n)_ce
55
//                      (n)_valid = 1
56
//              else if (n+1)_ce
57
//                      (n)_valid = 0
58
//
59
//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )
60
//                      || (  (n)_valid && (n+1)_stall );
61
//
62
//      and ...
63
//
64
//      always @(posedge i_clk)
65
//              if (n)_ce
66
//                      (n)_variable = ... whatever logic for this stage
67
//
68
//      Note that a stage can stall even if no instruction is loaded into
69
//      it.
70
//
71
//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
75 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
76 2 dgisselq
//
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// Copyright (C) 2015-2017, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
83
//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
87
// for more details.
88
//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
93
//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
96
//
97
//
98 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
99 2 dgisselq
//
100 36 dgisselq
//
101
//
102 25 dgisselq
`define CPU_CC_REG      4'he
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`define CPU_PC_REG      4'hf
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`define CPU_CLRCACHE_BIT 14     // Set to clear the I-cache, automatically clears
105 201 dgisselq
`define CPU_PHASE_BIT   13      // Set if we are executing the latter half of a CIS
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`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error
107
`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero
108
`define CPU_BUSERR_BIT  10      // Bus error flag, set on error
109
`define CPU_TRAP_BIT    9       // User TRAP has taken place
110
`define CPU_ILL_BIT     8       // Illegal instruction
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`define CPU_BREAK_BIT   7
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`define CPU_STEP_BIT    6       // Will step one (or two CIS) instructions
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`define CPU_GIE_BIT     5
114
`define CPU_SLEEP_BIT   4
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// Compile time defines
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//
117
`include "cpudefs.v"
118
//
119 65 dgisselq
//
120 2 dgisselq
module  zipcpu(i_clk, i_rst, i_interrupt,
121
                // Debug interface
122 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
123
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
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                        o_break,
125
                // CPU interface to the wishbone bus
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                o_wb_gbl_cyc, o_wb_gbl_stb,
127
                        o_wb_lcl_cyc, o_wb_lcl_stb,
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                        o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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                        i_wb_ack, i_wb_stall, i_wb_data,
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                        i_wb_err,
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                // Accounting/CPU usage interface
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                o_op_stall, o_pf_stall, o_i_count
133
`ifdef  DEBUG_SCOPE
134
                , o_debug
135
`endif
136
                );
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        parameter [31:0] RESET_ADDRESS=32'h0100000;
138
        parameter       ADDRESS_WIDTH=30,
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                        LGICACHE=8;
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`ifdef  OPT_MULTIPLY
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        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;
142 56 dgisselq
`else
143
        parameter       IMPLEMENT_MPY = 0;
144
`endif
145 71 dgisselq
`ifdef  OPT_DIVIDE
146
        parameter       IMPLEMENT_DIVIDE = 1;
147
`else
148
        parameter       IMPLEMENT_DIVIDE = 0;
149
`endif
150
`ifdef  OPT_IMPLEMENT_FPU
151
        parameter       IMPLEMENT_FPU = 1,
152
`else
153
        parameter       IMPLEMENT_FPU = 0,
154
`endif
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                        IMPLEMENT_LOCK=1;
156
`ifdef  OPT_EARLY_BRANCHING
157
        parameter       EARLY_BRANCHING = 1;
158
`else
159
        parameter       EARLY_BRANCHING = 0;
160
`endif
161 201 dgisselq
        parameter       WITH_LOCAL_BUS = 1;
162 193 dgisselq
        localparam      AW=ADDRESS_WIDTH;
163 201 dgisselq
        localparam      [(AW-1):0]       RESET_BUS_ADDRESS = RESET_ADDRESS[(AW+1):2];
164 2 dgisselq
        input                   i_clk, i_rst, i_interrupt;
165
        // Debug interface -- inputs
166 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
167 2 dgisselq
        input           [4:0]    i_dbg_reg;
168
        input                   i_dbg_we;
169
        input           [31:0]   i_dbg_data;
170
        // Debug interface -- outputs
171 160 dgisselq
        output  wire            o_dbg_stall;
172 2 dgisselq
        output  reg     [31:0]   o_dbg_reg;
173 56 dgisselq
        output  reg     [3:0]    o_dbg_cc;
174 2 dgisselq
        output  wire            o_break;
175
        // Wishbone interface -- outputs
176 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
177
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
178 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
179
        output  wire    [31:0]   o_wb_data;
180 201 dgisselq
        output  wire    [3:0]    o_wb_sel;
181 2 dgisselq
        // Wishbone interface -- inputs
182
        input                   i_wb_ack, i_wb_stall;
183
        input           [31:0]   i_wb_data;
184 36 dgisselq
        input                   i_wb_err;
185 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
186 9 dgisselq
        output  wire            o_op_stall;
187 2 dgisselq
        output  wire            o_pf_stall;
188 9 dgisselq
        output  wire            o_i_count;
189 56 dgisselq
        //
190 65 dgisselq
`ifdef  DEBUG_SCOPE
191 56 dgisselq
        output  reg     [31:0]   o_debug;
192 65 dgisselq
`endif
193 2 dgisselq
 
194 25 dgisselq
 
195 2 dgisselq
        // Registers
196 56 dgisselq
        //
197
        //      The distributed RAM style comment is necessary on the
198
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
199
        // set and in the process ruining everything else.  It basically
200
        // optimizes logic away, to where it no longer works.  The logic
201
        // as described herein will work, this just makes sure XST implements
202
        // that logic.
203
        //
204
        (* ram_style = "distributed" *)
205 201 dgisselq
`ifdef  OPT_NO_USERMODE
206
        reg     [31:0]   regset [0:15];
207
`else
208 2 dgisselq
        reg     [31:0]   regset [0:31];
209 201 dgisselq
`endif
210 9 dgisselq
 
211
        // Condition codes
212 56 dgisselq
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
213
        reg     [3:0]    flags, iflags;
214 179 dgisselq
        wire    [14:0]   w_uflags, w_iflags;
215 201 dgisselq
        reg             break_en, step, sleep, r_halted;
216
        wire            break_pending, trap, gie, ubreak;
217
        wire            w_clear_icache, ill_err_u;
218
        reg             ill_err_i;
219
        reg             ibus_err_flag;
220
        wire            ubus_err_flag;
221 69 dgisselq
        wire            idiv_err_flag, udiv_err_flag;
222
        wire            ifpu_err_flag, ufpu_err_flag;
223
        wire            ihalt_phase, uhalt_phase;
224 2 dgisselq
 
225 9 dgisselq
        // The master chip enable
226
        wire            master_ce;
227 2 dgisselq
 
228
        //
229
        //
230
        //      PIPELINE STAGE #1 :: Prefetch
231
        //              Variable declarations
232
        //
233 201 dgisselq
        reg     [(AW+1):0]       pf_pc;
234 69 dgisselq
        reg     new_pc;
235 18 dgisselq
        wire    clear_pipeline;
236 179 dgisselq
        assign  clear_pipeline = new_pc;
237 9 dgisselq
 
238
        wire            dcd_stalled;
239 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
240 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
241
        wire    [31:0]           pf_data;
242 201 dgisselq
        wire    [31:0]           pf_instruction;
243
        wire    [(AW-1):0]       pf_instruction_pc;
244
        wire    pf_valid, pf_gie, pf_illegal;
245 2 dgisselq
 
246
        //
247
        //
248
        //      PIPELINE STAGE #2 :: Instruction Decode
249
        //              Variable declarations
250
        //
251
        //
252 201 dgisselq
        reg             op_valid /* verilator public_flat */,
253
                        op_valid_mem, op_valid_alu;
254
        reg             op_valid_div, op_valid_fpu;
255 69 dgisselq
        wire            op_stall, dcd_ce, dcd_phase;
256 201 dgisselq
        wire    [3:0]    dcd_opn;
257
        wire    [4:0]    dcd_A, dcd_B, dcd_R;
258
        wire            dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc;
259
        wire    [3:0]    dcd_F;
260
        wire            dcd_wR, dcd_rA, dcd_rB,
261
                                dcd_ALU, dcd_M, dcd_DIV, dcd_FP,
262
                                dcd_wF, dcd_gie, dcd_break, dcd_lock,
263 105 dgisselq
                                dcd_pipe, dcd_ljmp;
264 201 dgisselq
        reg             r_dcd_valid;
265
        wire            dcd_valid;
266
        wire    [AW:0]   dcd_pc /* verilator public_flat */;
267
        wire    [31:0]   dcd_I;
268
        wire            dcd_zI; // true if dcd_I == 0
269
        wire    dcd_A_stall, dcd_B_stall, dcd_F_stall;
270 2 dgisselq
 
271 69 dgisselq
        wire    dcd_illegal;
272
        wire                    dcd_early_branch;
273 48 dgisselq
        wire    [(AW-1):0]       dcd_branch_pc;
274 2 dgisselq
 
275 201 dgisselq
        wire            dcd_sim;
276
        wire    [22:0]   dcd_sim_immv;
277 2 dgisselq
 
278 201 dgisselq
 
279 2 dgisselq
        //
280
        //
281
        //      PIPELINE STAGE #3 :: Read Operands
282
        //              Variable declarations
283
        //
284
        //
285
        //
286
        // Now, let's read our operands
287
        reg     [4:0]    alu_reg;
288 201 dgisselq
        wire    [3:0]    op_opn;
289
        wire    [4:0]    op_R;
290
        reg     [31:0]   r_op_Av, r_op_Bv;
291 48 dgisselq
        reg     [(AW-1):0]       op_pc;
292 201 dgisselq
        wire    [31:0]   w_op_Av, w_op_Bv;
293
        wire    [31:0]   op_A_nowait, op_B_nowait, op_Av, op_Bv;
294
        reg             op_wR, op_wF;
295
        wire            op_gie, op_Rcc;
296
        wire    [14:0]   op_Fl;
297
        reg     [6:0]    r_op_F;
298
        wire    [7:0]    op_F;
299 160 dgisselq
        wire            op_ce, op_phase, op_pipe, op_change_data_ce;
300 56 dgisselq
        // Some pipeline control wires
301 69 dgisselq
`ifdef  OPT_PIPELINED
302 201 dgisselq
        reg     op_A_alu, op_A_mem;
303
        reg     op_B_alu, op_B_mem;
304 56 dgisselq
`endif
305 36 dgisselq
        reg     op_illegal;
306 179 dgisselq
        wire    op_break;
307 69 dgisselq
        wire    op_lock;
308 2 dgisselq
 
309 201 dgisselq
`ifdef  VERILATOR
310
        reg             op_sim          /* verilator public_flat */;
311
        reg     [22:0]   op_sim_immv     /* verilator public_flat */;
312
`endif
313 2 dgisselq
 
314 201 dgisselq
 
315 2 dgisselq
        //
316
        //
317
        //      PIPELINE STAGE #4 :: ALU / Memory
318
        //              Variable declarations
319
        //
320
        //
321 179 dgisselq
        wire    [(AW-1):0]       alu_pc;
322 145 dgisselq
        reg             r_alu_pc_valid, mem_pc_valid;
323
        wire            alu_pc_valid;
324 69 dgisselq
        wire            alu_phase;
325 201 dgisselq
        wire            alu_ce /* verilator public_flat */, alu_stall;
326 2 dgisselq
        wire    [31:0]   alu_result;
327
        wire    [3:0]    alu_flags;
328 71 dgisselq
        wire            alu_valid, alu_busy;
329 2 dgisselq
        wire            set_cond;
330 201 dgisselq
        reg             alu_wR, alu_wF;
331 193 dgisselq
        wire            alu_gie, alu_illegal;
332 2 dgisselq
 
333
 
334
 
335
        wire    mem_ce, mem_stalled;
336 38 dgisselq
        wire    mem_pipe_stalled;
337 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
338
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
339 48 dgisselq
        wire    [4:0]            mem_wreg;
340 9 dgisselq
 
341 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
342
        wire    [(AW-1):0]       mem_addr;
343
        wire    [31:0]           mem_data, mem_result;
344 201 dgisselq
        wire    [3:0]            mem_sel;
345 2 dgisselq
 
346 69 dgisselq
        wire    div_ce, div_error, div_busy, div_valid;
347
        wire    [31:0]   div_result;
348
        wire    [3:0]    div_flags;
349 2 dgisselq
 
350 201 dgisselq
        assign  div_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_div)
351 69 dgisselq
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
352
                                &&(set_cond);
353 2 dgisselq
 
354 69 dgisselq
        wire    fpu_ce, fpu_error, fpu_busy, fpu_valid;
355
        wire    [31:0]   fpu_result;
356
        wire    [3:0]    fpu_flags;
357
 
358 201 dgisselq
        assign  fpu_ce = (master_ce)&&(~clear_pipeline)&&(op_valid_fpu)
359 69 dgisselq
                                &&(~mem_rdbusy)&&(~div_busy)&&(~fpu_busy)
360
                                &&(set_cond);
361
 
362 179 dgisselq
        wire    adf_ce_unconditional;
363 69 dgisselq
 
364 2 dgisselq
        //
365
        //
366
        //      PIPELINE STAGE #5 :: Write-back
367
        //              Variable declarations
368
        //
369 179 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc,
370
                        wr_write_scc, wr_write_ucc;
371 2 dgisselq
        wire    [4:0]    wr_reg_id;
372 160 dgisselq
        wire    [31:0]   wr_gpreg_vl, wr_spreg_vl;
373 2 dgisselq
        wire    w_switch_to_interrupt, w_release_from_interrupt;
374 201 dgisselq
        reg     [(AW+1):0]       ipc;
375
        wire    [(AW+1):0]       upc;
376 2 dgisselq
 
377
 
378
 
379
        //
380
        //      MASTER: clock enable.
381
        //
382 201 dgisselq
        assign  master_ce = ((~i_halt)||(alu_phase))&&(~o_break)&&(~sleep);
383 2 dgisselq
 
384
 
385
        //
386
        //      PIPELINE STAGE #1 :: Prefetch
387
        //              Calculate stall conditions
388 65 dgisselq
        //
389
        //      These are calculated externally, within the prefetch module.
390
        //
391 2 dgisselq
 
392
        //
393
        //      PIPELINE STAGE #2 :: Instruction Decode
394
        //              Calculate stall conditions
395 201 dgisselq
        assign          dcd_ce = ((~dcd_valid)||(~dcd_stalled))&&(~clear_pipeline);
396 145 dgisselq
 
397 69 dgisselq
`ifdef  OPT_PIPELINED
398 201 dgisselq
        assign          dcd_stalled = (dcd_valid)&&(op_stall);
399 69 dgisselq
`else
400 201 dgisselq
        // If not pipelined, there will be no op_valid_ anything, and the
401
        // op_stall will be false, dcd_X_stall will be false, thus we can simply
402 69 dgisselq
        // do a ...
403
        assign          dcd_stalled = 1'b0;
404
`endif
405 2 dgisselq
        //
406
        //      PIPELINE STAGE #3 :: Read Operands
407
        //              Calculate stall conditions
408 201 dgisselq
        wire    prelock_stall;
409 69 dgisselq
`ifdef  OPT_PIPELINED
410 179 dgisselq
        reg     cc_invalid_for_dcd;
411
        always @(posedge i_clk)
412
                cc_invalid_for_dcd <= (wr_flags_ce)
413
                        ||(wr_reg_ce)&&(wr_reg_id[3:0] == `CPU_CC_REG)
414 201 dgisselq
                        ||(op_valid)&&((op_wF)||((op_wR)&&(op_R[3:0] == `CPU_CC_REG)))
415
                        ||((alu_wF)||((alu_wR)&&(alu_reg[3:0] == `CPU_CC_REG)))
416 179 dgisselq
                        ||(mem_busy)||(div_busy)||(fpu_busy);
417
 
418 201 dgisselq
        assign  op_stall = (op_valid)&&( // Only stall if we're loaded w/validins
419 69 dgisselq
                        // Stall if we're stopped, and not allowed to execute
420
                        // an instruction
421
                        // (~master_ce)         // Already captured in alu_stall
422
                        //
423 56 dgisselq
                        // Stall if going into the ALU and the ALU is stalled
424
                        //      i.e. if the memory is busy, or we are single
425 69 dgisselq
                        //      stepping.  This also includes our stalls for
426
                        //      op_break and op_lock, so we don't need to
427
                        //      include those as well here.
428 83 dgisselq
                        // This also includes whether or not the divide or
429
                        // floating point units are busy.
430
                        (alu_stall)
431 201 dgisselq
                        ||(((op_valid_div)||(op_valid_fpu))
432
                                &&(!adf_ce_unconditional))
433 56 dgisselq
                        //
434
                        // Stall if we are going into memory with an operation
435
                        //      that cannot be pipelined, and the memory is
436
                        //      already busy
437 201 dgisselq
                        ||(mem_stalled) // &&(op_valid_mem) part of mem_stalled
438
                        ||(op_Rcc)
439 69 dgisselq
                        )
440 201 dgisselq
                        ||(dcd_valid)&&(
441 71 dgisselq
                                // Stall if we need to wait for an operand A
442 69 dgisselq
                                // to be ready to read
443 201 dgisselq
                                (dcd_A_stall)
444 69 dgisselq
                                // Likewise for B, also includes logic
445
                                // regarding immediate offset (register must
446
                                // be in register file if we need to add to
447
                                // an immediate)
448 201 dgisselq
                                ||(dcd_B_stall)
449 69 dgisselq
                                // Or if we need to wait on flags to work on the
450
                                // CC register
451 201 dgisselq
                                ||(dcd_F_stall)
452 69 dgisselq
                        );
453 201 dgisselq
        assign  op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);
454 179 dgisselq
 
455
 
456 160 dgisselq
        // BUT ... op_ce is too complex for many of the data operations.  So
457
        // let's make their circuit enable code simpler.  In particular, if
458
        // op_ doesn't need to be preserved, we can change it all we want
459
        // ... right?  The clear_pipeline code, for example, really only needs
460 201 dgisselq
        // to determine whether op_valid is true.
461 160 dgisselq
        assign  op_change_data_ce = (~op_stall);
462 65 dgisselq
`else
463 201 dgisselq
        assign  op_stall = (op_valid)&&(~master_ce);
464
        assign  op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(~clear_pipeline);
465 160 dgisselq
        assign  op_change_data_ce = 1'b1;
466 65 dgisselq
`endif
467 2 dgisselq
 
468
        //
469
        //      PIPELINE STAGE #4 :: ALU / Memory
470
        //              Calculate stall conditions
471 36 dgisselq
        //
472
        // 1. Basic stall is if the previous stage is valid and the next is
473 201 dgisselq
        //      busy.
474 36 dgisselq
        // 2. Also stall if the prior stage is valid and the master clock enable
475
        //      is de-selected
476 56 dgisselq
        // 3. Stall if someone on the other end is writing the CC register,
477
        //      since we don't know if it'll put us to sleep or not.
478 36 dgisselq
        // 4. Last case: Stall if we would otherwise move a break instruction
479
        //      through the ALU.  Break instructions are not allowed through
480
        //      the ALU.
481 69 dgisselq
`ifdef  OPT_PIPELINED
482 201 dgisselq
        assign  alu_stall = (((~master_ce)||(mem_rdbusy)||(alu_busy))&&(op_valid_alu)) //Case 1&2
483
                        ||(prelock_stall)
484
                        ||((op_valid)&&(op_break))
485 179 dgisselq
                        ||(wr_reg_ce)&&(wr_write_cc)
486 69 dgisselq
                        ||(div_busy)||(fpu_busy);
487 201 dgisselq
        assign  alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall)
488 69 dgisselq
                                &&(~clear_pipeline);
489
`else
490 201 dgisselq
        assign  alu_stall = (op_valid_alu)&&((~master_ce)||(op_break));
491
        assign  alu_ce = (master_ce)&&(op_valid_alu)&&(~alu_stall)&&(~clear_pipeline);
492 69 dgisselq
`endif
493 2 dgisselq
        //
494 65 dgisselq
 
495
        //
496
        // Note: if you change the conditions for mem_ce, you must also change
497
        // alu_pc_valid.
498
        //
499 69 dgisselq
`ifdef  OPT_PIPELINED
500 201 dgisselq
        assign  mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled)
501 71 dgisselq
                        &&(~clear_pipeline);
502 69 dgisselq
`else
503
        // If we aren't pipelined, then no one will be changing what's in the
504
        // pipeline (i.e. clear_pipeline), while our only instruction goes
505
        // through the ... pipeline.
506 145 dgisselq
        //
507
        // However, in hind sight this logic didn't work.  What happens when
508
        // something gets in the pipeline and then (due to interrupt or some
509
        // such) needs to be voided?  Thus we avoid simplification and keep
510
        // what worked here.
511 201 dgisselq
        assign  mem_ce = (master_ce)&&(op_valid_mem)&&(~mem_stalled)
512 145 dgisselq
                        &&(~clear_pipeline);
513 69 dgisselq
`endif
514 65 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
515 201 dgisselq
        assign  mem_stalled = (~master_ce)||(alu_busy)||((op_valid_mem)&&(
516 38 dgisselq
                                (mem_pipe_stalled)
517 201 dgisselq
                                ||(prelock_stall)
518 38 dgisselq
                                ||((~op_pipe)&&(mem_busy))
519 69 dgisselq
                                ||(div_busy)
520
                                ||(fpu_busy)
521 38 dgisselq
                                // Stall waiting for flags to be valid
522
                                // Or waiting for a write to the PC register
523
                                // Or CC register, since that can change the
524
                                //  PC as well
525
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
526
                                        &&((wr_write_pc)||(wr_write_cc)))));
527
`else
528 69 dgisselq
`ifdef  OPT_PIPELINED
529 201 dgisselq
        assign  mem_stalled = (mem_busy)||((op_valid_mem)&&(
530 2 dgisselq
                                (~master_ce)
531
                                // Stall waiting for flags to be valid
532
                                // Or waiting for a write to the PC register
533 25 dgisselq
                                // Or CC register, since that can change the
534
                                //  PC as well
535
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
536 69 dgisselq
`else
537 201 dgisselq
        assign  mem_stalled = (op_valid_mem)&&(~master_ce);
538 38 dgisselq
`endif
539 69 dgisselq
`endif
540 2 dgisselq
 
541 179 dgisselq
        // ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
542 201 dgisselq
        assign  adf_ce_unconditional = (master_ce)&&(~clear_pipeline)&&(op_valid)
543
                                &&(~op_valid_mem)&&(~mem_rdbusy)
544
                                &&((~op_valid_alu)||(~alu_stall))&&(~op_break)
545 179 dgisselq
                                &&(~div_busy)&&(~fpu_busy)&&(~clear_pipeline);
546 2 dgisselq
 
547
        //
548
        //
549
        //      PIPELINE STAGE #1 :: Prefetch
550
        //
551
        //
552 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
553 9 dgisselq
        wire            pf_ce;
554
 
555 201 dgisselq
        assign          pf_ce = (~pf_valid)&&(~dcd_valid)&&(~op_valid)&&(~alu_busy)&&(~mem_busy)&&(~alu_pc_valid)&&(~mem_pc_valid);
556 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
557 201 dgisselq
                        pf(i_clk, (i_rst), (pf_ce), (~dcd_stalled), pf_pc[(AW+1):2], gie,
558
                                pf_instruction, pf_instruction_pc, pf_gie,
559 36 dgisselq
                                        pf_valid, pf_illegal,
560
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
561
                                pf_ack, pf_stall, pf_err, i_wb_data);
562 69 dgisselq
 
563 201 dgisselq
        initial r_dcd_valid = 1'b0;
564 69 dgisselq
        always @(posedge i_clk)
565 201 dgisselq
                if (clear_pipeline)
566
                        r_dcd_valid <= 1'b0;
567 69 dgisselq
                else if (dcd_ce)
568 201 dgisselq
                        r_dcd_valid <= (pf_valid)||(pf_illegal);
569 105 dgisselq
                else if (op_ce)
570 201 dgisselq
                        r_dcd_valid <= 1'b0;
571
        assign  dcd_valid = r_dcd_valid;
572 69 dgisselq
 
573 2 dgisselq
`else // Pipe fetch
574 69 dgisselq
 
575 201 dgisselq
        wire    pf_stalled;
576
        assign  pf_stalled = (dcd_stalled)||(dcd_phase);
577 69 dgisselq
`ifdef  OPT_TRADITIONAL_PFCACHE
578 201 dgisselq
        wire    [(AW-1):0]       pf_request_address;
579
        assign  pf_request_address = ((dcd_early_branch)&&(!clear_pipeline))
580
                                ? dcd_branch_pc:pf_pc[(AW+1):2];
581 69 dgisselq
        pfcache #(LGICACHE, ADDRESS_WIDTH)
582 105 dgisselq
                pf(i_clk, i_rst, (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
583 179 dgisselq
                                        w_clear_icache,
584 69 dgisselq
                                // dcd_pc,
585 201 dgisselq
                                (!pf_stalled),
586
                                pf_request_address,
587
                                pf_instruction, pf_instruction_pc, pf_valid,
588 69 dgisselq
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
589
                                        pf_ack, pf_stall, pf_err, i_wb_data,
590
                                pf_illegal);
591
`else
592 201 dgisselq
        pipefetch       #(RESET_BUS_ADDRESS, LGICACHE, ADDRESS_WIDTH)
593 179 dgisselq
                        pf(i_clk, i_rst, (new_pc)||(dcd_early_branch),
594 201 dgisselq
                                        w_clear_icache, (!pf_stalled),
595
                                        (new_pc)?pf_pc[(AW+1):2]:dcd_branch_pc,
596
                                        pf_instruction, pf_instruction_pc, pf_valid,
597 2 dgisselq
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
598 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
599
                                (mem_cyc_lcl)||(mem_cyc_gbl),
600
                                pf_illegal);
601 69 dgisselq
`endif
602 201 dgisselq
`ifdef  OPT_NO_USERMODE
603
        assign  pf_gie = 1'b0;
604
`else
605
        assign  pf_gie = gie;
606
`endif
607 2 dgisselq
 
608 201 dgisselq
        initial r_dcd_valid = 1'b0;
609 2 dgisselq
        always @(posedge i_clk)
610 201 dgisselq
                if ((clear_pipeline)||(w_clear_icache))
611
                        r_dcd_valid <= 1'b0;
612 2 dgisselq
                else if (dcd_ce)
613 201 dgisselq
                        r_dcd_valid <= ((dcd_phase)||(pf_valid))
614
                                        &&(~dcd_ljmp)&&(~dcd_early_branch);
615 69 dgisselq
                else if (op_ce)
616 201 dgisselq
                        r_dcd_valid <= 1'b0;
617
        assign  dcd_valid = r_dcd_valid;
618 36 dgisselq
`endif
619 2 dgisselq
 
620 201 dgisselq
        // If not pipelined, there will be no op_valid_ anything, and the
621 69 dgisselq
        idecode #(AW, IMPLEMENT_MPY, EARLY_BRANCHING, IMPLEMENT_DIVIDE,
622
                        IMPLEMENT_FPU)
623 201 dgisselq
                instruction_decoder(i_clk, (clear_pipeline),
624
                        (~dcd_valid)||(~op_stall), dcd_stalled, pf_instruction, pf_gie,
625
                        pf_instruction_pc, pf_valid, pf_illegal, dcd_phase,
626
                        dcd_illegal, dcd_pc, dcd_gie,
627
                        { dcd_Rcc, dcd_Rpc, dcd_R },
628
                        { dcd_Acc, dcd_Apc, dcd_A },
629
                        { dcd_Bcc, dcd_Bpc, dcd_B },
630
                        dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn,
631
                        dcd_ALU, dcd_M, dcd_DIV, dcd_FP, dcd_break, dcd_lock,
632
                        dcd_wR,dcd_rA, dcd_rB,
633 69 dgisselq
                        dcd_early_branch,
634 105 dgisselq
                        dcd_branch_pc, dcd_ljmp,
635 201 dgisselq
                        dcd_pipe,
636
                        dcd_sim, dcd_sim_immv);
637 2 dgisselq
 
638 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
639 132 dgisselq
        reg             r_op_pipe;
640 2 dgisselq
 
641 132 dgisselq
        initial r_op_pipe = 1'b0;
642 201 dgisselq
        // To be a pipeable operation, there must be
643 38 dgisselq
        //      two valid adjacent instructions
644
        //      Both must be memory instructions
645
        //      Both must be writes, or both must be reads
646
        //      Both operations must be to the same identical address,
647
        //              or at least a single (one) increment above that address
648 71 dgisselq
        //
649
        // However ... we need to know this before this clock, hence this is
650
        // calculated in the instruction decoder.
651 38 dgisselq
        always @(posedge i_clk)
652 201 dgisselq
                if (clear_pipeline)
653
                        r_op_pipe <= 1'b0;
654
                else if (op_ce)
655 132 dgisselq
                        r_op_pipe <= dcd_pipe;
656 145 dgisselq
                else if (mem_ce) // Clear us any time an op_ is clocked in
657
                        r_op_pipe <= 1'b0;
658 132 dgisselq
        assign  op_pipe = r_op_pipe;
659
`else
660
        assign  op_pipe = 1'b0;
661 38 dgisselq
`endif
662
 
663 2 dgisselq
        //
664
        //
665
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
666
        //
667
        //
668 201 dgisselq
`ifdef  OPT_NO_USERMODE
669
        assign  w_op_Av = regset[dcd_A[3:0]];
670
        assign  w_op_Bv = regset[dcd_B[3:0]];
671
`else
672
        assign  w_op_Av = regset[dcd_A];
673
        assign  w_op_Bv = regset[dcd_B];
674
`endif
675 56 dgisselq
 
676 132 dgisselq
        wire    [8:0]    w_cpu_info;
677
        assign  w_cpu_info = {
678
        1'b1,
679 201 dgisselq
        (IMPLEMENT_MPY    >0)? 1'b1:1'b0,
680
        (IMPLEMENT_DIVIDE >0)? 1'b1:1'b0,
681
        (IMPLEMENT_FPU    >0)? 1'b1:1'b0,
682 132 dgisselq
`ifdef  OPT_PIPELINED
683
        1'b1,
684
`else
685
        1'b0,
686
`endif
687
`ifdef  OPT_TRADITIONAL_CACHE
688
        1'b1,
689
`else
690
        1'b0,
691
`endif
692
`ifdef  OPT_EARLY_BRANCHING
693
        1'b1,
694
`else
695
        1'b0,
696
`endif
697
`ifdef  OPT_PIPELINED_BUS_ACCESS
698
        1'b1,
699
`else
700
        1'b0,
701
`endif
702 201 dgisselq
`ifdef  OPT_CIS
703 132 dgisselq
        1'b1
704
`else
705
        1'b0
706
`endif
707
        };
708
 
709 56 dgisselq
        wire    [31:0]   w_pcA_v;
710 201 dgisselq
        assign  w_pcA_v[(AW+1):0] = { (dcd_A[4] == dcd_gie)
711
                                ? { dcd_pc[AW:1], 2'b00 }
712
                                : { upc[(AW+1):2], uhalt_phase, 1'b0 } };
713 56 dgisselq
        generate
714 201 dgisselq
        if (AW < 30)
715
                assign  w_pcA_v[31:(AW+2)] = 0;
716 56 dgisselq
        endgenerate
717 71 dgisselq
 
718
`ifdef  OPT_PIPELINED
719 201 dgisselq
        reg     [4:0]    op_Aid, op_Bid;
720
        reg             op_rA, op_rB;
721 2 dgisselq
        always @(posedge i_clk)
722 71 dgisselq
                if (op_ce)
723
                begin
724 201 dgisselq
                        op_Aid <= dcd_A;
725
                        op_Bid <= dcd_B;
726
                        op_rA <= dcd_rA;
727
                        op_rB <= dcd_rB;
728 71 dgisselq
                end
729
`endif
730
 
731
        always @(posedge i_clk)
732 179 dgisselq
`ifdef  OPT_PIPELINED
733 201 dgisselq
                if (op_ce)
734 179 dgisselq
`endif
735 2 dgisselq
                begin
736 179 dgisselq
`ifdef  OPT_PIPELINED
737 201 dgisselq
                        if ((wr_reg_ce)&&(wr_reg_id == dcd_A))
738
                                r_op_Av <= wr_gpreg_vl;
739 179 dgisselq
                        else
740
`endif
741 201 dgisselq
                        if (dcd_Apc)
742
                                r_op_Av <= w_pcA_v;
743
                        else if (dcd_Acc)
744
                                r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags };
745 2 dgisselq
                        else
746 201 dgisselq
                                r_op_Av <= w_op_Av;
747 69 dgisselq
`ifdef  OPT_PIPELINED
748 71 dgisselq
                end else
749 48 dgisselq
                begin // We were going to pick these up when they became valid,
750
                        // but for some reason we're stuck here as they became
751
                        // valid.  Pick them up now anyway
752 201 dgisselq
                        // if (((op_A_alu)&&(alu_wR))||((op_A_mem)&&(mem_valid)))
753
                                // r_op_Av <= wr_gpreg_vl;
754
                        if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA))
755
                                r_op_Av <= wr_gpreg_vl;
756 56 dgisselq
`endif
757 2 dgisselq
                end
758 56 dgisselq
 
759 201 dgisselq
        wire    [31:0]   w_op_BnI, w_pcB_v;
760
        assign  w_pcB_v[(AW+1):0] = { (dcd_B[4] == dcd_gie)
761
                                        ? { dcd_pc[AW:1], 2'b00 }
762
                                        : { upc[(AW+1):2], uhalt_phase, 1'b0 } };
763 56 dgisselq
        generate
764 201 dgisselq
        if (AW < 30)
765
                assign  w_pcB_v[31:(AW+2)] = 0;
766 56 dgisselq
        endgenerate
767
 
768 201 dgisselq
        assign  w_op_BnI = (!dcd_rB) ? 32'h00
769 179 dgisselq
`ifdef  OPT_PIPELINED
770 201 dgisselq
                : ((wr_reg_ce)&&(wr_reg_id == dcd_B)) ? wr_gpreg_vl
771 179 dgisselq
`endif
772 201 dgisselq
                : ((dcd_Bcc) ? { w_cpu_info, w_op_Bv[22:16], // w_op_B[31:14],
773
                        1'b0, (dcd_B[4])?w_uflags:w_iflags}
774
                : w_op_Bv);
775 56 dgisselq
 
776 2 dgisselq
        always @(posedge i_clk)
777 179 dgisselq
`ifdef  OPT_PIPELINED
778 201 dgisselq
                if ((op_ce)&&(dcd_Bpc)&&(dcd_rB))
779
                        r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 };
780
                else if (op_ce)
781
                        r_op_Bv <= w_op_BnI + dcd_I;
782
                else if ((wr_reg_ce)&&(op_Bid == wr_reg_id)&&(op_rB))
783
                        r_op_Bv <= wr_gpreg_vl;
784 179 dgisselq
`else
785 201 dgisselq
                if ((dcd_Bpc)&&(dcd_rB))
786
                        r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 };
787
                else
788
                        r_op_Bv <= w_op_BnI + dcd_I;
789 56 dgisselq
`endif
790 2 dgisselq
 
791
        // The logic here has become more complex than it should be, no thanks
792
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
793
        // be two sets of four bits: the top bits specify what bits matter, the
794
        // bottom specify what those top bits must equal.  However, two of
795
        // conditions check whether bits are on, and those are the only two
796
        // conditions checking those bits.  Therefore, Vivado complains that
797
        // these two bits are redundant.  Hence the convoluted expression
798
        // below, arriving at what we finally want in the (now wire net)
799 201 dgisselq
        // op_F.
800 2 dgisselq
        always @(posedge i_clk)
801 179 dgisselq
`ifdef  OPT_PIPELINED
802 201 dgisselq
                if (op_ce) // Cannot do op_change_data_ce here since op_F depends
803 160 dgisselq
                        // upon being either correct for a valid op, or correct
804
                        // for the last valid op
805 179 dgisselq
`endif
806 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
807 201 dgisselq
                        case(dcd_F[2:0])
808
                        3'h0:   r_op_F <= 7'h00;        // Always
809
                        3'h1:   r_op_F <= 7'h11;        // Z
810
                        3'h2:   r_op_F <= 7'h44;        // LT
811
                        3'h3:   r_op_F <= 7'h22;        // C
812
                        3'h4:   r_op_F <= 7'h08;        // V
813
                        3'h5:   r_op_F <= 7'h10;        // NE
814
                        3'h6:   r_op_F <= 7'h40;        // GE (!N)
815
                        3'h7:   r_op_F <= 7'h20;        // NC
816 2 dgisselq
                        endcase
817 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
818 201 dgisselq
        assign  op_F = { r_op_F[3], r_op_F[6:0] };
819 2 dgisselq
 
820 201 dgisselq
        wire    w_op_valid;
821
        assign  w_op_valid = (~clear_pipeline)&&(dcd_valid)&&(~dcd_ljmp)&&(!dcd_early_branch);
822
        initial op_valid     = 1'b0;
823
        initial op_valid_alu = 1'b0;
824
        initial op_valid_mem = 1'b0;
825
        initial op_valid_div = 1'b0;
826
        initial op_valid_fpu = 1'b0;
827 2 dgisselq
        always @(posedge i_clk)
828 201 dgisselq
                if (clear_pipeline)
829 25 dgisselq
                begin
830 201 dgisselq
                        op_valid     <= 1'b0;
831
                        op_valid_alu <= 1'b0;
832
                        op_valid_mem <= 1'b0;
833
                        op_valid_div <= 1'b0;
834
                        op_valid_fpu <= 1'b0;
835 25 dgisselq
                end else if (op_ce)
836
                begin
837 2 dgisselq
                        // Do we have a valid instruction?
838
                        //   The decoder may vote to stall one of its
839
                        //   instructions based upon something we currently
840
                        //   have in our queue.  This instruction must then
841
                        //   move forward, and get a stall cycle inserted.
842
                        //   Hence, the test on dcd_stalled here.  If we must
843
                        //   wait until our operands are valid, then we aren't
844
                        //   valid yet until then.
845 201 dgisselq
                        op_valid<= (w_op_valid)||(dcd_illegal)&&(dcd_valid)||(dcd_early_branch);
846
                        op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal)
847
                                        ||(dcd_early_branch));
848
                        op_valid_mem <= (dcd_M)&&(~dcd_illegal)&&(w_op_valid);
849
                        op_valid_div <= (dcd_DIV)&&(~dcd_illegal)&&(w_op_valid);
850
                        op_valid_fpu <= (dcd_FP)&&(~dcd_illegal)&&(w_op_valid);
851 193 dgisselq
                end else if ((adf_ce_unconditional)||(mem_ce))
852 25 dgisselq
                begin
853 201 dgisselq
                        op_valid     <= 1'b0;
854
                        op_valid_alu <= 1'b0;
855
                        op_valid_mem <= 1'b0;
856
                        op_valid_div <= 1'b0;
857
                        op_valid_fpu <= 1'b0;
858 25 dgisselq
                end
859 2 dgisselq
 
860
        // Here's part of our debug interface.  When we recognize a break
861
        // instruction, we set the op_break flag.  That'll prevent this
862
        // instruction from entering the ALU, and cause an interrupt before
863
        // this instruction.  Thus, returning to this code will cause the
864
        // break to repeat and continue upon return.  To get out of this
865
        // condition, replace the break instruction with what it is supposed
866
        // to be, step through it, and then replace it back.  In this fashion,
867
        // a debugger can step through code.
868 201 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001);
869 179 dgisselq
`ifdef  OPT_PIPELINED
870
        reg     r_op_break;
871
 
872
        initial r_op_break = 1'b0;
873 2 dgisselq
        always @(posedge i_clk)
874 201 dgisselq
                if ((i_rst)||(clear_pipeline))  r_op_break <= 1'b0;
875
                else if (op_ce)
876
                        r_op_break <= (dcd_break);
877
                else if (!op_valid)
878
                        r_op_break <= 1'b0;
879 179 dgisselq
        assign  op_break = r_op_break;
880
`else
881
        assign  op_break = dcd_break;
882
`endif
883 2 dgisselq
 
884 69 dgisselq
`ifdef  OPT_PIPELINED
885
        generate
886
        if (IMPLEMENT_LOCK != 0)
887
        begin
888 201 dgisselq
                reg     r_op_lock;
889 69 dgisselq
 
890
                initial r_op_lock = 1'b0;
891
                always @(posedge i_clk)
892 201 dgisselq
                        if (clear_pipeline)
893 69 dgisselq
                                r_op_lock <= 1'b0;
894 132 dgisselq
                        else if (op_ce)
895 201 dgisselq
                                r_op_lock <= (dcd_valid)&&(dcd_lock)&&(~clear_pipeline);
896 69 dgisselq
                assign  op_lock = r_op_lock;
897
 
898
        end else begin
899
                assign  op_lock = 1'b0;
900
        end endgenerate
901
 
902
`else
903
        assign op_lock       = 1'b0;
904
`endif
905
 
906 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
907 71 dgisselq
        initial op_illegal = 1'b0;
908 2 dgisselq
        always @(posedge i_clk)
909 201 dgisselq
                if (clear_pipeline)
910 71 dgisselq
                        op_illegal <= 1'b0;
911
                else if(op_ce)
912 69 dgisselq
`ifdef  OPT_PIPELINED
913 201 dgisselq
                        op_illegal <= (dcd_valid)&&((dcd_illegal)||((dcd_lock)&&(IMPLEMENT_LOCK == 0)));
914 69 dgisselq
`else
915 201 dgisselq
                        op_illegal <= (dcd_valid)&&((dcd_illegal)||(dcd_lock));
916 36 dgisselq
`endif
917 179 dgisselq
                else if(alu_ce)
918
                        op_illegal <= 1'b0;
919 69 dgisselq
`endif
920 36 dgisselq
 
921 71 dgisselq
        // No generate on EARLY_BRANCHING here, since if EARLY_BRANCHING is not
922
        // set, dcd_early_branch will simply be a wire connected to zero and
923
        // this logic should just optimize.
924 179 dgisselq
`ifdef  OPT_PIPELINED
925 71 dgisselq
        always @(posedge i_clk)
926
                if (op_ce)
927
                begin
928 201 dgisselq
                        op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR))
929 83 dgisselq
                                &&(~dcd_early_branch)&&(~dcd_illegal);
930 201 dgisselq
                        op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal);
931 71 dgisselq
                end
932 179 dgisselq
`else
933
        always @(posedge i_clk)
934
        begin
935 201 dgisselq
                op_wF <= (dcd_wF)&&((~dcd_Rcc)||(~dcd_wR))
936 179 dgisselq
                        &&(~dcd_early_branch)&&(~dcd_illegal);
937 201 dgisselq
                op_wR <= (dcd_wR)&&(~dcd_early_branch)&&(~dcd_illegal);
938 179 dgisselq
        end
939
`endif
940 69 dgisselq
 
941 201 dgisselq
`ifdef  VERILATOR
942 179 dgisselq
`ifdef  OPT_PIPELINED
943 201 dgisselq
        always @(posedge i_clk)
944
                if (op_change_data_ce)
945
                begin
946
                        op_sim      <= dcd_sim;
947
                        op_sim_immv <= dcd_sim_immv;
948
                end
949
`else
950
        always @(*)
951
        begin
952
                op_sim      = dcd_sim;
953
                op_sim_immv = dcd_sim_immv;
954
        end
955
`endif
956
`endif
957
 
958
`ifdef  OPT_PIPELINED
959
        reg     [3:0]    r_op_opn;
960
        reg     [4:0]    r_op_R;
961
        reg             r_op_Rcc;
962 179 dgisselq
        reg             r_op_gie;
963 36 dgisselq
        always @(posedge i_clk)
964 160 dgisselq
                if (op_change_data_ce)
965 2 dgisselq
                begin
966 201 dgisselq
                        // Which ALU operation?  Early branches are
967
                        // unimplemented moves
968
                        r_op_opn    <= (dcd_early_branch) ? 4'hf : dcd_opn;
969
                        // opM  <= dcd_M;       // Is this a memory operation?
970 2 dgisselq
                        // What register will these results be written into?
971 201 dgisselq
                        r_op_R    <= dcd_R;
972
                        r_op_Rcc <= (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie);
973 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
974 179 dgisselq
                        r_op_gie <= dcd_gie;
975 2 dgisselq
 
976
                        //
977 201 dgisselq
                        op_pc  <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1];
978 2 dgisselq
                end
979 201 dgisselq
        assign  op_opn = r_op_opn;
980
        assign  op_R = r_op_R;
981
`ifdef  OPT_NO_USERMODE
982
        assign  op_gie = 1'b0;
983
`else
984 179 dgisselq
        assign  op_gie = r_op_gie;
985 201 dgisselq
`endif
986
        assign  op_Rcc = r_op_Rcc;
987 179 dgisselq
`else
988 201 dgisselq
        assign  op_opn = dcd_opn;
989
        assign  op_R = dcd_R;
990
`ifdef  OPT_NO_USERMODE
991
        assign  op_gie = 1'b0;
992
`else
993 179 dgisselq
        assign  op_gie = dcd_gie;
994 201 dgisselq
`endif
995 179 dgisselq
        // With no pipelining, there is no early branching.  We keep it
996
        always @(posedge i_clk)
997 201 dgisselq
                op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc[AW:1];
998 179 dgisselq
`endif
999 201 dgisselq
        assign  op_Fl = (op_gie)?(w_uflags):(w_iflags);
1000 2 dgisselq
 
1001 201 dgisselq
`ifdef  OPT_CIS
1002 69 dgisselq
        reg     r_op_phase;
1003
        initial r_op_phase = 1'b0;
1004
        always @(posedge i_clk)
1005 201 dgisselq
                if (clear_pipeline)
1006 69 dgisselq
                        r_op_phase <= 1'b0;
1007 160 dgisselq
                else if (op_change_data_ce)
1008 201 dgisselq
                        r_op_phase <= (dcd_phase)&&((!dcd_wR)||(!dcd_Rpc));
1009 69 dgisselq
        assign  op_phase = r_op_phase;
1010
`else
1011
        assign  op_phase = 1'b0;
1012
`endif
1013
 
1014 2 dgisselq
        // This is tricky.  First, the PC and Flags registers aren't kept in
1015
        // register set but in special registers of their own.  So step one
1016
        // is to select the right register.  Step to is to replace that
1017
        // register with the results of an ALU or memory operation, if such
1018
        // results are now available.  Otherwise, we'd need to insert a wait
1019
        // state of some type.
1020
        //
1021
        // The alternative approach would be to define some sort of
1022
        // op_stall wire, which would stall any upstream stage.
1023
        // We'll create a flag here to start our coordination.  Once we
1024
        // define this flag to something other than just plain zero, then
1025
        // the stalls will already be in place.
1026 69 dgisselq
`ifdef  OPT_PIPELINED
1027 201 dgisselq
        assign  op_Av = ((wr_reg_ce)&&(wr_reg_id == op_Aid)) // &&(op_rA))
1028
                        ?  wr_gpreg_vl : r_op_Av;
1029 56 dgisselq
`else
1030 201 dgisselq
        assign  op_Av = r_op_Av;
1031 56 dgisselq
`endif
1032 48 dgisselq
 
1033 69 dgisselq
`ifdef  OPT_PIPELINED
1034 83 dgisselq
        // Stall if we have decoded an instruction that will read register A
1035
        //      AND ... something that may write a register is running
1036
        //      AND (series of conditions here ...)
1037
        //              The operation might set flags, and we wish to read the
1038
        //                      CC register
1039
        //              OR ... (No other conditions)
1040 201 dgisselq
        assign  dcd_A_stall = (dcd_rA) // &&(dcd_valid) is checked for elsewhere
1041
                                &&((op_valid)||(mem_rdbusy)
1042 83 dgisselq
                                        ||(div_busy)||(fpu_busy))
1043 201 dgisselq
                                &&(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Acc))
1044
                        ||((dcd_rA)&&(dcd_Acc)&&(cc_invalid_for_dcd));
1045 56 dgisselq
`else
1046 69 dgisselq
        // There are no pipeline hazards, if we aren't pipelined
1047 201 dgisselq
        assign  dcd_A_stall = 1'b0;
1048 56 dgisselq
`endif
1049 36 dgisselq
 
1050 69 dgisselq
`ifdef  OPT_PIPELINED
1051 201 dgisselq
        assign  op_Bv = ((wr_reg_ce)&&(wr_reg_id == op_Bid)&&(op_rB))
1052
                        ? wr_gpreg_vl: r_op_Bv;
1053 56 dgisselq
`else
1054 201 dgisselq
        assign  op_Bv = r_op_Bv;
1055 56 dgisselq
`endif
1056
 
1057 69 dgisselq
`ifdef  OPT_PIPELINED
1058 83 dgisselq
        // Stall if we have decoded an instruction that will read register B
1059
        //      AND ... something that may write a (unknown) register is running
1060
        //      AND (series of conditions here ...)
1061
        //              The operation might set flags, and we wish to read the
1062
        //                      CC register
1063
        //              OR the operation might set register B, and we still need
1064
        //                      a clock to add the offset to it
1065 201 dgisselq
        assign  dcd_B_stall = (dcd_rB) // &&(dcd_valid) is checked for elsewhere
1066 83 dgisselq
                                // If the op stage isn't valid, yet something
1067
                                // is running, then it must have been valid.
1068
                                // We'll use the last values from that stage
1069 201 dgisselq
                                // (op_wR, op_wF, op_R) in our logic below.
1070
                                &&((op_valid)||(mem_rdbusy)
1071 132 dgisselq
                                        ||(div_busy)||(fpu_busy)||(alu_busy))
1072 83 dgisselq
                                &&(
1073 145 dgisselq
                                // Okay, what happens if the result register
1074
                                // from instruction 1 becomes the input for
1075
                                // instruction two, *and* there's an immediate
1076
                                // offset in instruction two?  In that case, we
1077 201 dgisselq
                                // need an extra clock between the two
1078
                                // instructions to calculate the base plus
1079 145 dgisselq
                                // offset.
1080
                                //
1081
                                // What if instruction 1 (or before) is in a
1082
                                // memory pipeline?  We may no longer know what
1083 201 dgisselq
                                // the register was!  We will then need  to
1084 145 dgisselq
                                // blindly wait.  We'll temper this only waiting
1085
                                // if we're not piping this new instruction.
1086
                                // If we were piping, the pipe logic in the
1087
                                // decode circuit has told us that the hazard
1088
                                // is clear, so we're okay then.
1089
                                //
1090 132 dgisselq
                                ((~dcd_zI)&&(
1091 201 dgisselq
                                        ((op_R == dcd_B)&&(op_wR))
1092 145 dgisselq
                                        ||((mem_rdbusy)&&(~dcd_pipe))
1093
                                        ))
1094 83 dgisselq
                                // Stall following any instruction that will
1095
                                // set the flags, if we're going to need the
1096 201 dgisselq
                                // flags (CC) register for op_B.
1097
                                ||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc))
1098 38 dgisselq
                                // Stall on any ongoing memory operation that
1099 201 dgisselq
                                // will write to op_B -- captured above
1100
                                // ||((mem_busy)&&(~mem_we)&&(mem_last_reg==dcd_B)&&(~dcd_zI))
1101 179 dgisselq
                                )
1102 201 dgisselq
                        ||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd));
1103
        assign  dcd_F_stall = ((~dcd_F[3])
1104
                                        ||((dcd_rA)&&(dcd_Acc))
1105
                                        ||((dcd_rB)&&(dcd_Bcc)))
1106
                                        &&(op_valid)&&(op_Rcc);
1107
                                // &&(dcd_valid) is checked for elsewhere
1108 56 dgisselq
`else
1109 69 dgisselq
        // No stalls without pipelining, 'cause how can you have a pipeline
1110
        // hazard without the pipeline?
1111 201 dgisselq
        assign  dcd_B_stall = 1'b0;
1112
        assign  dcd_F_stall = 1'b0;
1113 56 dgisselq
`endif
1114 2 dgisselq
        //
1115
        //
1116
        //      PIPELINE STAGE #4 :: Apply Instruction
1117
        //
1118
        //
1119 201 dgisselq
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, (clear_pipeline),
1120
                        alu_ce, op_opn, op_Av, op_Bv,
1121 193 dgisselq
                        alu_result, alu_flags, alu_valid, alu_busy);
1122 2 dgisselq
 
1123 69 dgisselq
        generate
1124
        if (IMPLEMENT_DIVIDE != 0)
1125
        begin
1126 201 dgisselq
                div thedivide(i_clk, (clear_pipeline), div_ce, op_opn[0],
1127
                        op_Av, op_Bv, div_busy, div_valid, div_error, div_result,
1128 69 dgisselq
                        div_flags);
1129
        end else begin
1130 179 dgisselq
                assign  div_error = 1'b0; // Can't be high unless div_valid
1131 69 dgisselq
                assign  div_busy  = 1'b0;
1132
                assign  div_valid = 1'b0;
1133
                assign  div_result= 32'h00;
1134
                assign  div_flags = 4'h0;
1135
        end endgenerate
1136
 
1137
        generate
1138
        if (IMPLEMENT_FPU != 0)
1139
        begin
1140
                //
1141
                // sfpu thefpu(i_clk, i_rst, fpu_ce,
1142 201 dgisselq
                //      op_Av, op_Bv, fpu_busy, fpu_valid, fpu_err, fpu_result,
1143 69 dgisselq
                //      fpu_flags);
1144
                //
1145 179 dgisselq
                assign  fpu_error = 1'b0; // Must only be true if fpu_valid
1146 69 dgisselq
                assign  fpu_busy  = 1'b0;
1147
                assign  fpu_valid = 1'b0;
1148
                assign  fpu_result= 32'h00;
1149
                assign  fpu_flags = 4'h0;
1150
        end else begin
1151 179 dgisselq
                assign  fpu_error = 1'b0;
1152 69 dgisselq
                assign  fpu_busy  = 1'b0;
1153
                assign  fpu_valid = 1'b0;
1154
                assign  fpu_result= 32'h00;
1155
                assign  fpu_flags = 4'h0;
1156
        end endgenerate
1157
 
1158
 
1159 201 dgisselq
        assign  set_cond = ((op_F[7:4]&op_Fl[3:0])==op_F[3:0]);
1160
        initial alu_wF   = 1'b0;
1161
        initial alu_wR   = 1'b0;
1162 2 dgisselq
        always @(posedge i_clk)
1163
                if (i_rst)
1164
                begin
1165 201 dgisselq
                        alu_wR   <= 1'b0;
1166
                        alu_wF   <= 1'b0;
1167 2 dgisselq
                end else if (alu_ce)
1168
                begin
1169 201 dgisselq
                        // alu_reg <= op_R;
1170
                        alu_wR  <= (op_wR)&&(set_cond);
1171
                        alu_wF  <= (op_wF)&&(set_cond);
1172 71 dgisselq
                end else if (~alu_busy) begin
1173 2 dgisselq
                        // These are strobe signals, so clear them if not
1174
                        // set for any particular clock
1175 201 dgisselq
                        alu_wR <= (i_halt)&&(i_dbg_we);
1176
                        alu_wF <= 1'b0;
1177 2 dgisselq
                end
1178 69 dgisselq
 
1179 201 dgisselq
`ifdef  OPT_CIS
1180 69 dgisselq
        reg     r_alu_phase;
1181
        initial r_alu_phase = 1'b0;
1182 2 dgisselq
        always @(posedge i_clk)
1183 69 dgisselq
                if (i_rst)
1184
                        r_alu_phase <= 1'b0;
1185 160 dgisselq
                else if ((adf_ce_unconditional)||(mem_ce))
1186 69 dgisselq
                        r_alu_phase <= op_phase;
1187
        assign  alu_phase = r_alu_phase;
1188
`else
1189
        assign  alu_phase = 1'b0;
1190
`endif
1191
 
1192 179 dgisselq
`ifdef  OPT_PIPELINED
1193 69 dgisselq
        always @(posedge i_clk)
1194 160 dgisselq
                if (adf_ce_unconditional)
1195 201 dgisselq
                        alu_reg <= op_R;
1196 65 dgisselq
                else if ((i_halt)&&(i_dbg_we))
1197
                        alu_reg <= i_dbg_reg;
1198 179 dgisselq
`else
1199
        always @(posedge i_clk)
1200
                if ((i_halt)&&(i_dbg_we))
1201
                        alu_reg <= i_dbg_reg;
1202
                else
1203 201 dgisselq
                        alu_reg <= op_R;
1204 179 dgisselq
`endif
1205 69 dgisselq
 
1206 132 dgisselq
        //
1207
        // DEBUG Register write access starts here
1208
        //
1209 65 dgisselq
        reg             dbgv;
1210
        initial dbgv = 1'b0;
1211
        always @(posedge i_clk)
1212 160 dgisselq
                dbgv <= (~i_rst)&&(i_halt)&&(i_dbg_we)&&(r_halted);
1213 132 dgisselq
        reg     [31:0]   dbg_val;
1214 65 dgisselq
        always @(posedge i_clk)
1215 132 dgisselq
                dbg_val <= i_dbg_data;
1216 201 dgisselq
`ifdef  OPT_NO_USERMODE
1217
        assign  alu_gie = 1'b0;
1218
`else
1219 179 dgisselq
`ifdef  OPT_PIPELINED
1220
        reg     r_alu_gie;
1221
 
1222 132 dgisselq
        always @(posedge i_clk)
1223 160 dgisselq
                if ((adf_ce_unconditional)||(mem_ce))
1224 179 dgisselq
                        r_alu_gie  <= op_gie;
1225
        assign  alu_gie = r_alu_gie;
1226 201 dgisselq
`else
1227
        assign  alu_gie = op_gie;
1228
`endif
1229
`endif
1230 179 dgisselq
 
1231 201 dgisselq
`ifdef  OPT_PIPELINED
1232 179 dgisselq
        reg     [(AW-1):0]       r_alu_pc;
1233 2 dgisselq
        always @(posedge i_clk)
1234 160 dgisselq
                if ((adf_ce_unconditional)
1235 201 dgisselq
                        ||((master_ce)&&(op_valid_mem)&&(~clear_pipeline)
1236 65 dgisselq
                                &&(~mem_stalled)))
1237 179 dgisselq
                        r_alu_pc  <= op_pc;
1238
        assign  alu_pc = r_alu_pc;
1239
`else
1240
        assign  alu_pc = op_pc;
1241
`endif
1242 65 dgisselq
 
1243 56 dgisselq
        reg     r_alu_illegal;
1244
        initial r_alu_illegal = 0;
1245 38 dgisselq
        always @(posedge i_clk)
1246 201 dgisselq
                if (clear_pipeline)
1247 71 dgisselq
                        r_alu_illegal <= 1'b0;
1248 179 dgisselq
                else if (alu_ce)
1249 56 dgisselq
                        r_alu_illegal <= op_illegal;
1250 179 dgisselq
                else
1251
                        r_alu_illegal <= 1'b0;
1252 193 dgisselq
        assign  alu_illegal = (r_alu_illegal);
1253 38 dgisselq
 
1254 145 dgisselq
        initial r_alu_pc_valid = 1'b0;
1255 132 dgisselq
        initial mem_pc_valid = 1'b0;
1256 2 dgisselq
        always @(posedge i_clk)
1257 201 dgisselq
                if (clear_pipeline)
1258 145 dgisselq
                        r_alu_pc_valid <= 1'b0;
1259 201 dgisselq
                else if ((adf_ce_unconditional)&&(!op_phase)) //Includes&&(~alu_clear_pipeline)
1260 145 dgisselq
                        r_alu_pc_valid <= 1'b1;
1261 160 dgisselq
                else if (((~alu_busy)&&(~div_busy)&&(~fpu_busy))||(clear_pipeline))
1262 145 dgisselq
                        r_alu_pc_valid <= 1'b0;
1263 160 dgisselq
        assign  alu_pc_valid = (r_alu_pc_valid)&&((~alu_busy)&&(~div_busy)&&(~fpu_busy));
1264 132 dgisselq
        always @(posedge i_clk)
1265
                if (i_rst)
1266
                        mem_pc_valid <= 1'b0;
1267
                else
1268
                        mem_pc_valid <= (mem_ce);
1269 2 dgisselq
 
1270 69 dgisselq
        wire    bus_lock;
1271
`ifdef  OPT_PIPELINED
1272
        generate
1273
        if (IMPLEMENT_LOCK != 0)
1274
        begin
1275 201 dgisselq
                reg     r_prelock_stall;
1276
 
1277
                initial r_prelock_stall = 1'b0;
1278
                always @(posedge i_clk)
1279
                        if (clear_pipeline)
1280
                                r_prelock_stall <= 1'b0;
1281
                        else if ((op_valid)&&(op_lock)&&(op_ce))
1282
                                r_prelock_stall <= 1'b1;
1283
                        else if ((op_valid)&&(dcd_valid)&&(pf_valid))
1284
                                r_prelock_stall <= 1'b0;
1285
 
1286
                assign  prelock_stall = r_prelock_stall;
1287
 
1288
                reg     r_prelock_primed;
1289
                always @(posedge i_clk)
1290
                        if (clear_pipeline)
1291
                                r_prelock_primed <= 1'b0;
1292
                        else if (r_prelock_stall)
1293
                                r_prelock_primed <= 1'b1;
1294
                        else if ((adf_ce_unconditional)||(mem_ce))
1295
                                r_prelock_primed <= 1'b0;
1296
 
1297 132 dgisselq
                reg     [1:0]    r_bus_lock;
1298
                initial r_bus_lock = 2'b00;
1299 69 dgisselq
                always @(posedge i_clk)
1300 201 dgisselq
                        if (clear_pipeline)
1301 132 dgisselq
                                r_bus_lock <= 2'b00;
1302 201 dgisselq
                        else if ((op_valid)&&((adf_ce_unconditional)||(mem_ce)))
1303
                        begin
1304
                                if (r_prelock_primed)
1305
                                        r_bus_lock <= 2'b10;
1306
                                else if (r_bus_lock != 2'h0)
1307
                                        r_bus_lock <= r_bus_lock + 2'b11;
1308
                        end
1309 132 dgisselq
                assign  bus_lock = |r_bus_lock;
1310 69 dgisselq
        end else begin
1311 201 dgisselq
                assign  prelock_stall = 1'b0;
1312 69 dgisselq
                assign  bus_lock = 1'b0;
1313
        end endgenerate
1314
`else
1315
        assign  bus_lock = 1'b0;
1316
`endif
1317
 
1318 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
1319 71 dgisselq
        pipemem #(AW,IMPLEMENT_LOCK) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1320 201 dgisselq
                                (op_opn[2:0]), op_Bv, op_Av, op_R,
1321 38 dgisselq
                                mem_busy, mem_pipe_stalled,
1322
                                mem_valid, bus_err, mem_wreg, mem_result,
1323
                        mem_cyc_gbl, mem_cyc_lcl,
1324
                                mem_stb_gbl, mem_stb_lcl,
1325 201 dgisselq
                                mem_we, mem_addr, mem_data, mem_sel,
1326 38 dgisselq
                                mem_ack, mem_stall, mem_err, i_wb_data);
1327 201 dgisselq
 
1328 38 dgisselq
`else // PIPELINED_BUS_ACCESS
1329 201 dgisselq
        memops  #(AW,IMPLEMENT_LOCK,WITH_LOCAL_BUS) domem(i_clk, i_rst,(mem_ce)&&(set_cond), bus_lock,
1330
                                (op_opn[2:0]), op_Bv, op_Av, op_R,
1331 38 dgisselq
                                mem_busy,
1332
                                mem_valid, bus_err, mem_wreg, mem_result,
1333 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
1334
                                mem_stb_gbl, mem_stb_lcl,
1335 201 dgisselq
                                mem_we, mem_addr, mem_data, mem_sel,
1336 36 dgisselq
                                mem_ack, mem_stall, mem_err, i_wb_data);
1337 201 dgisselq
        assign  mem_pipe_stalled = 1'b0;
1338 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
1339 65 dgisselq
        assign  mem_rdbusy = ((mem_busy)&&(~mem_we));
1340 2 dgisselq
 
1341 201 dgisselq
        // Either the prefetch or the instruction gets the memory bus, but
1342 2 dgisselq
        // never both.
1343 48 dgisselq
        wbdblpriarb     #(32,AW) pformem(i_clk, i_rst,
1344 36 dgisselq
                // Memory access to the arbiter, priority position
1345
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1346 201 dgisselq
                        mem_we, mem_addr, mem_data, mem_sel,
1347
                        mem_ack, mem_stall, mem_err,
1348 2 dgisselq
                // Prefetch access to the arbiter
1349 201 dgisselq
                //
1350
                // At a first glance, we might want something like:
1351
                //
1352
                // pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, 4'hf,
1353
                //
1354
                // However, we know that the prefetch will not generate any
1355
                // writes.  Therefore, the write specific lines (mem_data and
1356
                // mem_sel) can be shared with the memory in order to ease
1357
                // timing and LUT usage.
1358
                pf_cyc,1'b0,pf_stb, 1'b0, pf_we, pf_addr, mem_data, mem_sel,
1359 36 dgisselq
                        pf_ack, pf_stall, pf_err,
1360 2 dgisselq
                // Common wires, in and out, of the arbiter
1361 201 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1362
                        o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
1363 36 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_err);
1364 2 dgisselq
 
1365 132 dgisselq
 
1366
 
1367 2 dgisselq
        //
1368
        //
1369 132 dgisselq
        //
1370
        //
1371
        //
1372
        //
1373
        //
1374
        //
1375 2 dgisselq
        //      PIPELINE STAGE #5 :: Write-back results
1376
        //
1377
        //
1378
        // This stage is not allowed to stall.  If results are ready to be
1379
        // written back, they are written back at all cost.  Sleepy CPU's
1380
        // won't prevent write back, nor debug modes, halting the CPU, nor
1381
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1382
        // as knowinig something is available for writeback.
1383
 
1384
        //
1385
        // Write back to our generic register set ...
1386
        // When shall we write back?  On one of two conditions
1387
        //      Note that the flags needed to be checked before issuing the
1388
        //      bus instruction, so they don't need to be checked here.
1389 201 dgisselq
        //      Further, alu_wR includes (set_cond), so we don't need to
1390 2 dgisselq
        //      check for that here either.
1391 160 dgisselq
        assign  wr_reg_ce = (dbgv)||(mem_valid)
1392
                                ||((~clear_pipeline)&&(~alu_illegal)
1393 201 dgisselq
                                        &&(((alu_wR)&&(alu_valid))
1394 160 dgisselq
                                                ||(div_valid)||(fpu_valid)));
1395 2 dgisselq
        // Which register shall be written?
1396 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1397
        //              One or PC, one for CC, and one for GIE match
1398 69 dgisselq
        //      Note that the alu_reg is the register to write on a divide or
1399
        //      FPU operation.
1400 201 dgisselq
`ifdef  OPT_NO_USERMODE
1401
        assign  wr_reg_id[3:0] = (alu_wR|div_valid|fpu_valid)
1402
                                ? alu_reg[3:0]:mem_wreg[3:0];
1403
        assign  wr_reg_id[4] = 1'b0;
1404
`else
1405
        assign  wr_reg_id = (alu_wR|div_valid|fpu_valid)?alu_reg:mem_wreg;
1406
`endif
1407
 
1408 25 dgisselq
        // Are we writing to the CC register?
1409
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1410 179 dgisselq
        assign  wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
1411
        assign  wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
1412 2 dgisselq
        // Are we writing to the PC?
1413
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1414 179 dgisselq
 
1415 2 dgisselq
        // What value to write?
1416 160 dgisselq
        assign  wr_gpreg_vl = ((mem_valid) ? mem_result
1417 71 dgisselq
                                :((div_valid|fpu_valid))
1418
                                        ? ((div_valid) ? div_result:fpu_result)
1419
                                :((dbgv) ? dbg_val : alu_result));
1420 160 dgisselq
        assign  wr_spreg_vl = ((mem_valid) ? mem_result
1421
                                :((dbgv) ? dbg_val : alu_result));
1422 2 dgisselq
        always @(posedge i_clk)
1423
                if (wr_reg_ce)
1424 201 dgisselq
`ifdef  OPT_NO_USERMODE
1425
                        regset[wr_reg_id[3:0]] <= wr_gpreg_vl;
1426
`else
1427
                        regset[wr_reg_id] <= wr_gpreg_vl;
1428
`endif
1429 2 dgisselq
 
1430
        //
1431
        // Write back to the condition codes/flags register ...
1432 201 dgisselq
        // When shall we write to our flags register?  alu_wF already
1433 2 dgisselq
        // includes the set condition ...
1434 201 dgisselq
        assign  wr_flags_ce = ((alu_wF)||(div_valid)||(fpu_valid))&&(~clear_pipeline)&&(~alu_illegal);
1435 179 dgisselq
        assign  w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag,
1436 71 dgisselq
                        udiv_err_flag, ubus_err_flag, trap, ill_err_u,
1437 179 dgisselq
                        ubreak, step, 1'b1, sleep,
1438 71 dgisselq
                        ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1439 179 dgisselq
        assign  w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag,
1440 71 dgisselq
                        idiv_err_flag, ibus_err_flag, trap, ill_err_i,
1441
                        break_en, 1'b0, 1'b0, sleep,
1442
                        ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
1443 69 dgisselq
 
1444
 
1445 2 dgisselq
        // What value to write?
1446
        always @(posedge i_clk)
1447
                // If explicitly writing the register itself
1448 179 dgisselq
                if ((wr_reg_ce)&&(wr_write_ucc))
1449 160 dgisselq
                        flags <= wr_gpreg_vl[3:0];
1450 2 dgisselq
                // Otherwise if we're setting the flags from an ALU operation
1451
                else if ((wr_flags_ce)&&(alu_gie))
1452 69 dgisselq
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1453
                                : alu_flags);
1454 2 dgisselq
 
1455
        always @(posedge i_clk)
1456 179 dgisselq
                if ((wr_reg_ce)&&(wr_write_scc))
1457 160 dgisselq
                        iflags <= wr_gpreg_vl[3:0];
1458 2 dgisselq
                else if ((wr_flags_ce)&&(~alu_gie))
1459 69 dgisselq
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1460
                                : alu_flags);
1461 2 dgisselq
 
1462
        // The 'break' enable  bit.  This bit can only be set from supervisor
1463
        // mode.  It control what the CPU does upon encountering a break
1464
        // instruction.
1465
        //
1466
        // The goal, upon encountering a break is that the CPU should stop and
1467
        // not execute the break instruction, choosing instead to enter into
1468 201 dgisselq
        // either interrupt mode or halt first.
1469 2 dgisselq
        //      if ((break_en) AND (break_instruction)) // user mode or not
1470
        //              HALT CPU
1471
        //      else if (break_instruction) // only in user mode
1472 179 dgisselq
        //              set an interrupt flag, set the user break bit,
1473
        //              go to supervisor mode, allow supervisor to step the CPU.
1474 2 dgisselq
        //      Upon a CPU halt, any break condition will be reset.  The
1475
        //      external debugger will then need to deal with whatever
1476
        //      condition has taken place.
1477
        initial break_en = 1'b0;
1478
        always @(posedge i_clk)
1479
                if ((i_rst)||(i_halt))
1480
                        break_en <= 1'b0;
1481 179 dgisselq
                else if ((wr_reg_ce)&&(wr_write_scc))
1482 160 dgisselq
                        break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
1483 179 dgisselq
 
1484
`ifdef  OPT_PIPELINED
1485
        reg     r_break_pending;
1486
 
1487
        initial r_break_pending = 1'b0;
1488
        always @(posedge i_clk)
1489 201 dgisselq
                if ((clear_pipeline)||(~op_valid))
1490 179 dgisselq
                        r_break_pending <= 1'b0;
1491
                else if (op_break)
1492 193 dgisselq
                        r_break_pending <= (~alu_busy)&&(~div_busy)&&(~fpu_busy)&&(~mem_busy)&&(!wr_reg_ce);
1493 179 dgisselq
                else
1494
                        r_break_pending <= 1'b0;
1495
        assign  break_pending = r_break_pending;
1496 36 dgisselq
`else
1497 179 dgisselq
        assign  break_pending = op_break;
1498 36 dgisselq
`endif
1499 2 dgisselq
 
1500
 
1501 179 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(break_pending)
1502
                                &&(~clear_pipeline)
1503
                        ||((~alu_gie)&&(bus_err))
1504
                        ||((~alu_gie)&&(div_error))
1505
                        ||((~alu_gie)&&(fpu_error))
1506 193 dgisselq
                        ||((~alu_gie)&&(alu_illegal)&&(!clear_pipeline));
1507 179 dgisselq
 
1508 2 dgisselq
        // The sleep register.  Setting the sleep register causes the CPU to
1509
        // sleep until the next interrupt.  Setting the sleep register within
1510
        // interrupt mode causes the processor to halt until a reset.  This is
1511 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1512 201 dgisselq
        // set the sleep bit and switch to supervisor mode in the same
1513 25 dgisselq
        // instruction: users are not allowed to halt the CPU.
1514 201 dgisselq
        initial sleep = 1'b0;
1515
`ifdef  OPT_NO_USERMODE
1516
        reg     r_sleep_is_halt;
1517
        initial r_sleep_is_halt = 1'b0;
1518 2 dgisselq
        always @(posedge i_clk)
1519 201 dgisselq
                if (i_rst)
1520
                        r_sleep_is_halt <= 1'b0;
1521
                else if ((wr_reg_ce)&&(wr_write_cc)
1522
                                &&(wr_spreg_vl[`CPU_SLEEP_BIT])
1523
                                &&(~wr_spreg_vl[`CPU_GIE_BIT]))
1524
                        r_sleep_is_halt <= 1'b1;
1525
 
1526
        // Trying to switch to user mode, either via a WAIT or an RTU
1527
        // instruction will cause the CPU to sleep until an interrupt, in
1528
        // the NO-USERMODE build.
1529
        always @(posedge i_clk)
1530
                if ((i_rst)||((i_interrupt)&&(!r_sleep_is_halt)))
1531
                        sleep <= 1'b0;
1532
                else if ((wr_reg_ce)&&(wr_write_cc)
1533
                                &&(wr_spreg_vl[`CPU_GIE_BIT]))
1534
                        sleep <= 1'b1;
1535
`else
1536
        always @(posedge i_clk)
1537 69 dgisselq
                if ((i_rst)||(w_switch_to_interrupt))
1538 2 dgisselq
                        sleep <= 1'b0;
1539 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1540
                        // In supervisor mode, we have no protections.  The
1541
                        // supervisor can set the sleep bit however he wants.
1542 69 dgisselq
                        // Well ... not quite.  Switching to user mode and
1543
                        // sleep mode shouold only be possible if the interrupt
1544
                        // flag isn't set.
1545 160 dgisselq
                        //      Thus: if (i_interrupt)&&(wr_spreg_vl[GIE])
1546 69 dgisselq
                        //              don't set the sleep bit
1547
                        //      otherwise however it would o.w. be set
1548 160 dgisselq
                        sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
1549
                                &&((~i_interrupt)||(~wr_spreg_vl[`CPU_GIE_BIT]));
1550
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_spreg_vl[`CPU_GIE_BIT]))
1551 25 dgisselq
                        // In user mode, however, you can only set the sleep
1552
                        // mode while remaining in user mode.  You can't switch
1553
                        // to sleep mode *and* supervisor mode at the same
1554
                        // time, lest you halt the CPU.
1555 160 dgisselq
                        sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
1556 201 dgisselq
`endif
1557 2 dgisselq
 
1558
        always @(posedge i_clk)
1559 193 dgisselq
                if (i_rst)
1560 2 dgisselq
                        step <= 1'b0;
1561 179 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_write_ucc))
1562 160 dgisselq
                        step <= wr_spreg_vl[`CPU_STEP_BIT];
1563 2 dgisselq
 
1564
        // The GIE register.  Only interrupts can disable the interrupt register
1565 201 dgisselq
`ifdef  OPT_NO_USERMODE
1566
        assign  w_switch_to_interrupt    = 1'b0;
1567
        assign  w_release_from_interrupt = 1'b0;
1568
`else
1569 2 dgisselq
        assign  w_switch_to_interrupt = (gie)&&(
1570
                        // On interrupt (obviously)
1571 69 dgisselq
                        ((i_interrupt)&&(~alu_phase)&&(~bus_lock))
1572 2 dgisselq
                        // If we are stepping the CPU
1573 132 dgisselq
                        ||(((alu_pc_valid)||(mem_pc_valid))&&(step)&&(~alu_phase)&&(~bus_lock))
1574 2 dgisselq
                        // If we encounter a break instruction, if the break
1575 36 dgisselq
                        //      enable isn't set.
1576 179 dgisselq
                        ||((master_ce)&&(break_pending)&&(~break_en))
1577 36 dgisselq
                        // On an illegal instruction
1578 193 dgisselq
                        ||((alu_illegal)&&(!clear_pipeline))
1579 71 dgisselq
                        // On division by zero.  If the divide isn't
1580
                        // implemented, div_valid and div_error will be short
1581
                        // circuited and that logic will be bypassed
1582 179 dgisselq
                        ||(div_error)
1583
                        // Same thing on a floating point error.  Note that
1584
                        // fpu_error must *never* be set unless fpu_valid is
1585
                        // also set as well, else this will fail.
1586
                        ||(fpu_error)
1587 201 dgisselq
                        //
1588 69 dgisselq
                        ||(bus_err)
1589 2 dgisselq
                        // If we write to the CC register
1590 160 dgisselq
                        ||((wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
1591 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1592 2 dgisselq
                        );
1593
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1594 179 dgisselq
                        // Then if we write the sCC register
1595 160 dgisselq
                        &&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
1596 179 dgisselq
                                &&(wr_write_scc))
1597 2 dgisselq
                        );
1598 201 dgisselq
`endif
1599
 
1600
`ifdef  OPT_NO_USERMODE
1601
        assign  gie = 1'b0;
1602
`else
1603
        reg     r_gie;
1604
 
1605
        initial r_gie = 1'b0;
1606 2 dgisselq
        always @(posedge i_clk)
1607
                if (i_rst)
1608 201 dgisselq
                        r_gie <= 1'b0;
1609 2 dgisselq
                else if (w_switch_to_interrupt)
1610 201 dgisselq
                        r_gie <= 1'b0;
1611 2 dgisselq
                else if (w_release_from_interrupt)
1612 201 dgisselq
                        r_gie <= 1'b1;
1613
        assign  gie = r_gie;
1614
`endif
1615 2 dgisselq
 
1616 201 dgisselq
`ifdef  OPT_NO_USERMODE
1617
        assign  trap   = 1'b0;
1618
        assign  ubreak = 1'b0;
1619
`else
1620
        reg     r_trap;
1621
 
1622
        initial r_trap = 1'b0;
1623 25 dgisselq
        always @(posedge i_clk)
1624 179 dgisselq
                if ((i_rst)||(w_release_from_interrupt))
1625 201 dgisselq
                        r_trap <= 1'b0;
1626 160 dgisselq
                else if ((alu_gie)&&(wr_reg_ce)&&(~wr_spreg_vl[`CPU_GIE_BIT])
1627 179 dgisselq
                                &&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
1628 201 dgisselq
                        r_trap <= 1'b1;
1629 179 dgisselq
                else if ((wr_reg_ce)&&(wr_write_ucc)&&(~alu_gie))
1630 201 dgisselq
                        r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
1631 25 dgisselq
 
1632 201 dgisselq
        reg     r_ubreak;
1633
 
1634
        initial r_ubreak = 1'b0;
1635 179 dgisselq
        always @(posedge i_clk)
1636
                if ((i_rst)||(w_release_from_interrupt))
1637 201 dgisselq
                        r_ubreak <= 1'b0;
1638 179 dgisselq
                else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
1639 201 dgisselq
                        r_ubreak <= 1'b1;
1640 179 dgisselq
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
1641 201 dgisselq
                        r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
1642 179 dgisselq
 
1643 201 dgisselq
        assign  trap = r_trap;
1644
        assign  ubreak = r_ubreak;
1645
`endif
1646 179 dgisselq
 
1647 201 dgisselq
 
1648 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1649 65 dgisselq
        initial ill_err_i = 1'b0;
1650 36 dgisselq
        always @(posedge i_clk)
1651
                if (i_rst)
1652 65 dgisselq
                        ill_err_i <= 1'b0;
1653 132 dgisselq
                // Only the debug interface can clear this bit
1654 179 dgisselq
                else if ((dbgv)&&(wr_write_scc))
1655
                        ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
1656 193 dgisselq
                else if ((alu_illegal)&&(~alu_gie)&&(!clear_pipeline))
1657 65 dgisselq
                        ill_err_i <= 1'b1;
1658 201 dgisselq
 
1659
`ifdef  OPT_NO_USERMODE
1660
        assign  ill_err_u = 1'b0;
1661
`else
1662
        reg     r_ill_err_u;
1663
 
1664
        initial r_ill_err_u = 1'b0;
1665 65 dgisselq
        always @(posedge i_clk)
1666
                // The bit is automatically cleared on release from interrupt
1667 179 dgisselq
                // or reset
1668
                if ((i_rst)||(w_release_from_interrupt))
1669 201 dgisselq
                        r_ill_err_u <= 1'b0;
1670 179 dgisselq
                // If the supervisor (or debugger) writes to this register,
1671
                // clearing the bit, then clear it
1672
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
1673 201 dgisselq
                        r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
1674 193 dgisselq
                else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline))
1675 201 dgisselq
                        r_ill_err_u <= 1'b1;
1676
 
1677
        assign  ill_err_u = r_ill_err_u;
1678
`endif
1679 38 dgisselq
`else
1680 65 dgisselq
        assign ill_err_u = 1'b0;
1681
        assign ill_err_i = 1'b0;
1682 36 dgisselq
`endif
1683 65 dgisselq
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
1684
        // ever set.
1685
        initial ibus_err_flag = 1'b0;
1686 36 dgisselq
        always @(posedge i_clk)
1687
                if (i_rst)
1688 65 dgisselq
                        ibus_err_flag <= 1'b0;
1689 179 dgisselq
                else if ((dbgv)&&(wr_write_scc))
1690
                        ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
1691 65 dgisselq
                else if ((bus_err)&&(~alu_gie))
1692
                        ibus_err_flag <= 1'b1;
1693
        // User bus error flag -- if ever set, it will cause an interrupt to
1694 201 dgisselq
        // supervisor mode.
1695
`ifdef  OPT_NO_USERMODE
1696
        assign  ubus_err_flag = 1'b0;
1697
`else
1698
        reg     r_ubus_err_flag;
1699
 
1700
        initial r_ubus_err_flag = 1'b0;
1701 65 dgisselq
        always @(posedge i_clk)
1702 179 dgisselq
                if ((i_rst)||(w_release_from_interrupt))
1703 201 dgisselq
                        r_ubus_err_flag <= 1'b0;
1704 179 dgisselq
                else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
1705 201 dgisselq
                        r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
1706 36 dgisselq
                else if ((bus_err)&&(alu_gie))
1707 201 dgisselq
                        r_ubus_err_flag <= 1'b1;
1708 36 dgisselq
 
1709 201 dgisselq
        assign  ubus_err_flag = r_ubus_err_flag;
1710
`endif
1711
 
1712 69 dgisselq
        generate
1713
        if (IMPLEMENT_DIVIDE != 0)
1714
        begin
1715
                reg     r_idiv_err_flag, r_udiv_err_flag;
1716
 
1717
                // Supervisor/interrupt divide (by zero) error flag -- this will
1718
                // crash the CPU if ever set.  This bit is thus available for us
1719
                // to be able to tell if/why the CPU crashed.
1720
                initial r_idiv_err_flag = 1'b0;
1721
                always @(posedge i_clk)
1722
                        if (i_rst)
1723
                                r_idiv_err_flag <= 1'b0;
1724 179 dgisselq
                        else if ((dbgv)&&(wr_write_scc))
1725
                                r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
1726
                        else if ((div_error)&&(~alu_gie))
1727 69 dgisselq
                                r_idiv_err_flag <= 1'b1;
1728 201 dgisselq
 
1729
                assign  idiv_err_flag = r_idiv_err_flag;
1730
`ifdef  OPT_NO_USERMODE
1731
                assign  udiv_err_flag = 1'b0;
1732
`else
1733 69 dgisselq
                // User divide (by zero) error flag -- if ever set, it will
1734 201 dgisselq
                // cause a sudden switch interrupt to supervisor mode.
1735 69 dgisselq
                initial r_udiv_err_flag = 1'b0;
1736
                always @(posedge i_clk)
1737 179 dgisselq
                        if ((i_rst)||(w_release_from_interrupt))
1738 69 dgisselq
                                r_udiv_err_flag <= 1'b0;
1739
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1740 179 dgisselq
                                        &&(wr_write_ucc))
1741
                                r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
1742
                        else if ((div_error)&&(alu_gie))
1743 69 dgisselq
                                r_udiv_err_flag <= 1'b1;
1744
 
1745
                assign  udiv_err_flag = r_udiv_err_flag;
1746 201 dgisselq
`endif
1747 69 dgisselq
        end else begin
1748
                assign  idiv_err_flag = 1'b0;
1749
                assign  udiv_err_flag = 1'b0;
1750
        end endgenerate
1751
 
1752
        generate
1753
        if (IMPLEMENT_FPU !=0)
1754
        begin
1755
                // Supervisor/interrupt floating point error flag -- this will
1756
                // crash the CPU if ever set.
1757
                reg             r_ifpu_err_flag, r_ufpu_err_flag;
1758
                initial r_ifpu_err_flag = 1'b0;
1759
                always @(posedge i_clk)
1760
                        if (i_rst)
1761
                                r_ifpu_err_flag <= 1'b0;
1762 179 dgisselq
                        else if ((dbgv)&&(wr_write_scc))
1763
                                r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
1764 69 dgisselq
                        else if ((fpu_error)&&(fpu_valid)&&(~alu_gie))
1765
                                r_ifpu_err_flag <= 1'b1;
1766
                // User floating point error flag -- if ever set, it will cause
1767 201 dgisselq
                // a sudden switch interrupt to supervisor mode.
1768 69 dgisselq
                initial r_ufpu_err_flag = 1'b0;
1769
                always @(posedge i_clk)
1770 179 dgisselq
                        if ((i_rst)&&(w_release_from_interrupt))
1771 69 dgisselq
                                r_ufpu_err_flag <= 1'b0;
1772
                        else if (((~alu_gie)||(dbgv))&&(wr_reg_ce)
1773 179 dgisselq
                                        &&(wr_write_ucc))
1774
                                r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
1775 69 dgisselq
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
1776
                                r_ufpu_err_flag <= 1'b1;
1777
 
1778
                assign  ifpu_err_flag = r_ifpu_err_flag;
1779
                assign  ufpu_err_flag = r_ufpu_err_flag;
1780
        end else begin
1781
                assign  ifpu_err_flag = 1'b0;
1782
                assign  ufpu_err_flag = 1'b0;
1783
        end endgenerate
1784
 
1785 201 dgisselq
`ifdef  OPT_CIS
1786
        reg             r_ihalt_phase;
1787 69 dgisselq
 
1788
        initial r_ihalt_phase = 0;
1789
        always @(posedge i_clk)
1790 179 dgisselq
                if (i_rst)
1791
                        r_ihalt_phase <= 1'b0;
1792
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1793 69 dgisselq
                        r_ihalt_phase <= alu_phase;
1794 201 dgisselq
 
1795
        assign  ihalt_phase = r_ihalt_phase;
1796
 
1797
`ifdef  OPT_NO_USERMODE
1798
        assign  uhalt_phase = 1'b0;
1799
`else
1800
        reg             r_uhalt_phase;
1801
 
1802
        initial r_uhalt_phase = 0;
1803 69 dgisselq
        always @(posedge i_clk)
1804 179 dgisselq
                if ((i_rst)||(w_release_from_interrupt))
1805
                        r_uhalt_phase <= 1'b0;
1806
                else if ((alu_gie)&&(alu_pc_valid))
1807 69 dgisselq
                        r_uhalt_phase <= alu_phase;
1808 179 dgisselq
                else if ((~alu_gie)&&(wr_reg_ce)&&(wr_write_ucc))
1809
                        r_uhalt_phase <= wr_spreg_vl[`CPU_PHASE_BIT];
1810 69 dgisselq
 
1811
        assign  uhalt_phase = r_uhalt_phase;
1812 201 dgisselq
`endif
1813 69 dgisselq
`else
1814
        assign  ihalt_phase = 1'b0;
1815
        assign  uhalt_phase = 1'b0;
1816
`endif
1817
 
1818 2 dgisselq
        //
1819
        // Write backs to the PC register, and general increments of it
1820
        //      We support two: upc and ipc.  If the instruction is normal,
1821
        // we increment upc, if interrupt level we increment ipc.  If
1822
        // the instruction writes the PC, we write whichever PC is appropriate.
1823
        //
1824
        // Do we need to all our partial results from the pipeline?
1825
        // What happens when the pipeline has gie and ~gie instructions within
1826
        // it?  Do we clear both?  What if a gie instruction tries to clear
1827
        // a non-gie instruction?
1828 201 dgisselq
`ifdef  OPT_NO_USERMODE
1829
        assign  upc = {(AW+2){1'b0}};
1830
`else
1831
        reg     [(AW+1):0]       r_upc;
1832
 
1833 2 dgisselq
        always @(posedge i_clk)
1834 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1835 201 dgisselq
                        r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
1836 132 dgisselq
                else if ((alu_gie)&&
1837 193 dgisselq
                                (((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal))
1838 132 dgisselq
                                ||(mem_pc_valid)))
1839 201 dgisselq
                        r_upc <= { alu_pc, 2'b00 };
1840
        assign  upc = r_upc;
1841
`endif
1842 2 dgisselq
 
1843
        always @(posedge i_clk)
1844
                if (i_rst)
1845 201 dgisselq
                        ipc <= { RESET_BUS_ADDRESS, 2'b00 };
1846 2 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1847 201 dgisselq
                        ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
1848
                else if ((!alu_gie)&&(!alu_phase)&&
1849
                                (((alu_pc_valid)&&(~clear_pipeline)&&(!alu_illegal))
1850 132 dgisselq
                                ||(mem_pc_valid)))
1851 201 dgisselq
                        ipc <= { alu_pc, 2'b00 };
1852 2 dgisselq
 
1853
        always @(posedge i_clk)
1854
                if (i_rst)
1855 201 dgisselq
                        pf_pc <= { RESET_BUS_ADDRESS, 2'b00 };
1856 179 dgisselq
                else if ((w_switch_to_interrupt)||((~gie)&&(w_clear_icache)))
1857 201 dgisselq
                        pf_pc <= { ipc[(AW+1):2], 2'b00 };
1858 179 dgisselq
                else if ((w_release_from_interrupt)||((gie)&&(w_clear_icache)))
1859 201 dgisselq
                        pf_pc <= { upc[(AW+1):2], 2'b00 };
1860 2 dgisselq
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1861 201 dgisselq
                        pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
1862 69 dgisselq
`ifdef  OPT_PIPELINED
1863 105 dgisselq
                else if ((dcd_early_branch)&&(~clear_pipeline))
1864 201 dgisselq
                        pf_pc <= { dcd_branch_pc + 1'b1, 2'b00 };
1865
                else if ((new_pc)||((!pf_stalled)&&(pf_valid)))
1866
                        pf_pc <= { pf_pc[(AW+1):2] + {{(AW-1){1'b0}},1'b1}, 2'b00 };
1867 69 dgisselq
`else
1868 145 dgisselq
                else if ((alu_gie==gie)&&(
1869
                                ((alu_pc_valid)&&(~clear_pipeline))
1870
                                ||(mem_pc_valid)))
1871 201 dgisselq
                        pf_pc <= { alu_pc[(AW-1):0], 2'b00 };
1872 69 dgisselq
`endif
1873 2 dgisselq
 
1874 179 dgisselq
`ifdef  OPT_PIPELINED
1875
        reg     r_clear_icache;
1876
        initial r_clear_icache = 1'b1;
1877
        always @(posedge i_clk)
1878
                if ((i_rst)||(i_clear_pf_cache))
1879
                        r_clear_icache <= 1'b1;
1880
                else if ((wr_reg_ce)&&(wr_write_scc))
1881
                        r_clear_icache <=  wr_spreg_vl[`CPU_CLRCACHE_BIT];
1882
                else
1883
                        r_clear_icache <= 1'b0;
1884
        assign  w_clear_icache = r_clear_icache;
1885
`else
1886 201 dgisselq
        assign  w_clear_icache = i_clear_pf_cache;
1887 179 dgisselq
`endif
1888
 
1889 201 dgisselq
        initial new_pc = 1'b1;
1890
        always @(posedge i_clk)
1891
                if ((i_rst)||(w_clear_icache))
1892
                        new_pc <= 1'b1;
1893
                else if (w_switch_to_interrupt)
1894
                        new_pc <= 1'b1;
1895
                else if (w_release_from_interrupt)
1896
                        new_pc <= 1'b1;
1897
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1898
                        new_pc <= 1'b1;
1899
                else
1900
                        new_pc <= 1'b0;
1901
 
1902 2 dgisselq
        //
1903
        // The debug interface
1904 201 dgisselq
        wire    [31:0]   w_debug_pc;
1905
`ifdef  OPT_NO_USERMODE
1906
        assign  w_debug_pc[(AW+1):0] = { ipc, 2'b00 };
1907
`else
1908
        assign  w_debug_pc[(AW+1):0] = { (i_dbg_reg[4])
1909
                                ? { upc[(AW+1):2], uhalt_phase, 1'b0 }
1910
                                : { ipc[(AW+1):2], ihalt_phase, 1'b0 } };
1911
`endif
1912 56 dgisselq
        generate
1913 201 dgisselq
        if (AW<30)
1914
                assign  w_debug_pc[31:(AW+2)] = 0;
1915
        endgenerate
1916
 
1917
        always @(posedge i_clk)
1918 56 dgisselq
        begin
1919 201 dgisselq
`ifdef  OPT_NO_USERMODE
1920
                o_dbg_reg <= regset[i_dbg_reg[3:0]];
1921
                if (i_dbg_reg[3:0] == `CPU_PC_REG)
1922
                        o_dbg_reg <= w_debug_pc;
1923
                else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1924 2 dgisselq
                begin
1925 201 dgisselq
                        o_dbg_reg[14:0] <= w_iflags;
1926
                        o_dbg_reg[15] <= 1'b0;
1927
                        o_dbg_reg[31:23] <= w_cpu_info;
1928
                        o_dbg_reg[`CPU_GIE_BIT] <= gie;
1929 2 dgisselq
                end
1930 201 dgisselq
`else
1931
                o_dbg_reg <= regset[i_dbg_reg];
1932
                if (i_dbg_reg[3:0] == `CPU_PC_REG)
1933
                        o_dbg_reg <= w_debug_pc;
1934
                else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1935 56 dgisselq
                begin
1936 201 dgisselq
                        o_dbg_reg[14:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1937
                        o_dbg_reg[15] <= 1'b0;
1938
                        o_dbg_reg[31:23] <= w_cpu_info;
1939
                        o_dbg_reg[`CPU_GIE_BIT] <= gie;
1940 56 dgisselq
                end
1941 201 dgisselq
`endif
1942
        end
1943 56 dgisselq
 
1944 2 dgisselq
        always @(posedge i_clk)
1945 56 dgisselq
                o_dbg_cc <= { o_break, bus_err, gie, sleep };
1946 18 dgisselq
 
1947 179 dgisselq
`ifdef  OPT_PIPELINED
1948 18 dgisselq
        always @(posedge i_clk)
1949 160 dgisselq
                r_halted <= (i_halt)&&(
1950 179 dgisselq
                        // To be halted, any long lasting instruction must
1951
                        // be completed.
1952
                        (~pf_cyc)&&(~mem_busy)&&(~alu_busy)
1953
                                &&(~div_busy)&&(~fpu_busy)
1954
                        // Operations must either be valid, or illegal
1955 201 dgisselq
                        &&((op_valid)||(i_rst)||(dcd_illegal))
1956 179 dgisselq
                        // Decode stage must be either valid, in reset, or ill
1957 201 dgisselq
                        &&((dcd_valid)||(i_rst)||(pf_illegal)));
1958 179 dgisselq
`else
1959
        always @(posedge i_clk)
1960 201 dgisselq
                r_halted <= (i_halt)&&((op_valid)||(i_rst));
1961 179 dgisselq
`endif
1962
        assign  o_dbg_stall = ~r_halted;
1963 2 dgisselq
 
1964
        //
1965
        //
1966
        // Produce accounting outputs: Account for any CPU stalls, so we can
1967
        // later evaluate how well we are doing.
1968
        //
1969
        //
1970 71 dgisselq
        assign  o_op_stall = (master_ce)&&(op_stall);
1971 9 dgisselq
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1972 38 dgisselq
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1973 56 dgisselq
 
1974 65 dgisselq
`ifdef  DEBUG_SCOPE
1975 56 dgisselq
        always @(posedge i_clk)
1976 65 dgisselq
                o_debug <= {
1977 179 dgisselq
                /*
1978 132 dgisselq
                        o_break, i_wb_err, pf_pc[1:0],
1979
                        flags,
1980 201 dgisselq
                        pf_valid, dcd_valid, op_valid, alu_valid, mem_valid,
1981 56 dgisselq
                        op_ce, alu_ce, mem_ce,
1982 65 dgisselq
                        //
1983 201 dgisselq
                        master_ce, op_valid_alu, op_valid_mem,
1984 65 dgisselq
                        //
1985
                        alu_stall, mem_busy, op_pipe, mem_pipe_stalled,
1986
                        mem_we,
1987 201 dgisselq
                        // ((op_valid_alu)&&(alu_stall))
1988
                        // ||((op_valid_mem)&&(~op_pipe)&&(mem_busy))
1989
                        // ||((op_valid_mem)&&( op_pipe)&&(mem_pipe_stalled)));
1990
                        // op_Av[23:20], op_Av[3:0],
1991 160 dgisselq
                        gie, sleep, wr_reg_ce, wr_gpreg_vl[4:0]
1992 179 dgisselq
                */
1993 71 dgisselq
                /*
1994 69 dgisselq
                        i_rst, master_ce, (new_pc),
1995 201 dgisselq
                        ((dcd_early_branch)&&(dcd_valid)),
1996 69 dgisselq
                        pf_valid, pf_illegal,
1997 201 dgisselq
                        op_ce, dcd_ce, dcd_valid, dcd_stalled,
1998 69 dgisselq
                        pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err,
1999
                        pf_pc[7:0], pf_addr[7:0]
2000 71 dgisselq
                */
2001 179 dgisselq
 
2002 132 dgisselq
                        i_wb_err, gie, alu_illegal,
2003
                              (new_pc)||((dcd_early_branch)&&(~clear_pipeline)),
2004
                        mem_busy,
2005
                                (mem_busy)?{ (o_wb_gbl_stb|o_wb_lcl_stb), o_wb_we,
2006
                                        o_wb_addr[8:0] }
2007 201 dgisselq
                                        : { pf_instruction[31:21] },
2008 132 dgisselq
                        pf_valid, (pf_valid) ? alu_pc[14:0]
2009 201 dgisselq
                                :{ pf_cyc, pf_stb, pf_pc[14:2] }
2010 179 dgisselq
 
2011 132 dgisselq
                /*
2012
                        i_wb_err, gie, new_pc, dcd_early_branch,        // 4
2013 201 dgisselq
                        pf_valid, pf_cyc, pf_stb, pf_instruction_pc[0], // 4
2014
                        pf_instruction[30:27],                          // 4
2015 132 dgisselq
                        dcd_gie, mem_busy, o_wb_gbl_cyc, o_wb_gbl_stb,  // 4
2016 201 dgisselq
                        dcd_valid,
2017 132 dgisselq
                        ((dcd_early_branch)&&(~clear_pipeline))         // 15
2018
                                        ? dcd_branch_pc[14:0]:pf_pc[14:0]
2019
                */
2020 56 dgisselq
                        };
2021 65 dgisselq
`endif
2022 201 dgisselq
 
2023 2 dgisselq
endmodule

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