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[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Blame information for rev 209

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1 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
3
// Filename:    zipcpu.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//{{{
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// Purpose:     This is the top level module holding the core of the Zip CPU
8
//              together.  The Zip CPU is designed to be as simple as possible.
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//      (actual implementation aside ...)  The instruction set is about as
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//      RISC as you can get, with only 26 instruction types currently supported.
11
//      (There are still 8-instruction Op-Codes reserved for floating point,
12
//      and 5 which can be used for transactions not requiring registers.)
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//      Please see the accompanying spec.pdf file for a description of these
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//      instructions.
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//
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//      All instructions are 32-bits wide.  All bus accesses, both address and
17
//      data, are 32-bits over a wishbone bus.
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//
19
//      The Zip CPU is fully pipelined with the following pipeline stages:
20
//
21 201 dgisselq
//              1. Prefetch, returns the instruction from memory.
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//
23
//              2. Instruction Decode
24
//
25
//              3. Read Operands
26
//
27
//              4. Apply Instruction
28
//
29
//              4. Write-back Results
30
//
31 179 dgisselq
//      Further information about the inner workings of this CPU, such as
32
//      what causes pipeline stalls, may be found in the spec.pdf file.  (The
33
//      documentation within this file had become out of date and out of sync
34
//      with the spec.pdf, so look to the spec.pdf for accurate and up to date
35
//      information.)
36 2 dgisselq
//
37
//
38 69 dgisselq
//      In general, the pipelining is controlled by three pieces of logic
39
//      per stage: _ce, _stall, and _valid.  _valid means that the stage
40
//      holds a valid instruction.  _ce means that the instruction from the
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//      previous stage is to move into this one, and _stall means that the
42
//      instruction from the previous stage may not move into this one.
43
//      The difference between these control signals allows individual stages
44
//      to propagate instructions independently.  In general, the logic works
45
//      as:
46
//
47
//
48 205 dgisselq
//      assign  (n)_ce = (n-1)_valid && (!(n)_stall)
49 69 dgisselq
//
50
//
51
//      always @(posedge i_clk)
52 209 dgisselq
//              if ((i_reset)||(clear_pipeline))
53 69 dgisselq
//                      (n)_valid = 0
54
//              else if (n)_ce
55
//                      (n)_valid = 1
56
//              else if (n+1)_ce
57
//                      (n)_valid = 0
58
//
59
//      assign (n)_stall = (  (n-1)_valid && ( pipeline hazard detection )  )
60
//                      || (  (n)_valid && (n+1)_stall );
61
//
62
//      and ...
63
//
64
//      always @(posedge i_clk)
65
//              if (n)_ce
66
//                      (n)_variable = ... whatever logic for this stage
67
//
68
//      Note that a stage can stall even if no instruction is loaded into
69
//      it.
70
//
71 209 dgisselq
//}}}
72 2 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
73 69 dgisselq
//              Gisselquist Technology, LLC
74 2 dgisselq
//
75 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
76 2 dgisselq
//
77 209 dgisselq
// Copyright (C) 2015-2019, Gisselquist Technology, LLC
78
//{{{
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// This program is free software (firmware): you can redistribute it and/or
80
// modify it under the terms of  the GNU General Public License as published
81
// by the Free Software Foundation, either version 3 of the License, or (at
82
// your option) any later version.
83
//
84
// This program is distributed in the hope that it will be useful, but WITHOUT
85
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
86
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
87
// for more details.
88
//
89 201 dgisselq
// You should have received a copy of the GNU General Public License along
90
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
91
// target there if the PDF file isn't present.)  If not, see
92
// <http://www.gnu.org/licenses/> for a copy.
93 209 dgisselq
//}}}
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
96
//
97
//
98 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
99 2 dgisselq
//
100 36 dgisselq
//
101 209 dgisselq
`default_nettype        none
102 36 dgisselq
//
103 209 dgisselq
`define CPU_SUB_OP      4'h0 // also a compare instruction
104
`define CPU_AND_OP      4'h1 // also a test instruction
105
`define CPU_BREV_OP     4'h8
106
`define CPU_MOV_OP      4'hd
107
//
108 25 dgisselq
`define CPU_CC_REG      4'he
109 2 dgisselq
`define CPU_PC_REG      4'hf
110 193 dgisselq
`define CPU_CLRCACHE_BIT 14     // Set to clear the I-cache, automatically clears
111 201 dgisselq
`define CPU_PHASE_BIT   13      // Set if we are executing the latter half of a CIS
112 69 dgisselq
`define CPU_FPUERR_BIT  12      // Floating point error flag, set on error
113
`define CPU_DIVERR_BIT  11      // Divide error flag, set on divide by zero
114
`define CPU_BUSERR_BIT  10      // Bus error flag, set on error
115
`define CPU_TRAP_BIT    9       // User TRAP has taken place
116
`define CPU_ILL_BIT     8       // Illegal instruction
117 2 dgisselq
`define CPU_BREAK_BIT   7
118 201 dgisselq
`define CPU_STEP_BIT    6       // Will step one (or two CIS) instructions
119 2 dgisselq
`define CPU_GIE_BIT     5
120
`define CPU_SLEEP_BIT   4
121 36 dgisselq
// Compile time defines
122 56 dgisselq
//
123
`include "cpudefs.v"
124
//
125 65 dgisselq
//
126 209 dgisselq
module  zipcpu(i_clk, i_reset, i_interrupt,
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                // Debug interface
128 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
129
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
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                        o_break,
131
                // CPU interface to the wishbone bus
132 36 dgisselq
                o_wb_gbl_cyc, o_wb_gbl_stb,
133
                        o_wb_lcl_cyc, o_wb_lcl_stb,
134 201 dgisselq
                        o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
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                        i_wb_ack, i_wb_stall, i_wb_data,
136 36 dgisselq
                        i_wb_err,
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                // Accounting/CPU usage interface
138 65 dgisselq
                o_op_stall, o_pf_stall, o_i_count
139
`ifdef  DEBUG_SCOPE
140 209 dgisselq
                , o_debug // , o_dcache_debug
141 65 dgisselq
`endif
142
                );
143 209 dgisselq
        // Parameters
144
        //{{{
145 201 dgisselq
        parameter [31:0] RESET_ADDRESS=32'h0100000;
146
        parameter       ADDRESS_WIDTH=30,
147 209 dgisselq
                        LGICACHE=12;
148 56 dgisselq
`ifdef  OPT_MULTIPLY
149 132 dgisselq
        parameter       IMPLEMENT_MPY = `OPT_MULTIPLY;
150 56 dgisselq
`else
151
        parameter       IMPLEMENT_MPY = 0;
152
`endif
153 71 dgisselq
`ifdef  OPT_DIVIDE
154 209 dgisselq
        parameter [0:0]   IMPLEMENT_DIVIDE = 1;
155 71 dgisselq
`else
156 209 dgisselq
        parameter [0:0]   IMPLEMENT_DIVIDE = 0;
157 71 dgisselq
`endif
158
`ifdef  OPT_IMPLEMENT_FPU
159 209 dgisselq
        parameter [0:0]   IMPLEMENT_FPU = 1;
160 71 dgisselq
`else
161 209 dgisselq
        parameter [0:0]   IMPLEMENT_FPU = 0;
162 71 dgisselq
`endif
163 69 dgisselq
`ifdef  OPT_EARLY_BRANCHING
164 209 dgisselq
        parameter [0:0]   EARLY_BRANCHING = 1;
165 69 dgisselq
`else
166 209 dgisselq
        parameter [0:0]   EARLY_BRANCHING = 0;
167 69 dgisselq
`endif
168 209 dgisselq
`ifdef  OPT_CIS
169
        parameter [0:0]   OPT_CIS = 1'b1;
170
`else
171
        parameter [0:0]   OPT_CIS = 1'b0;
172
`endif
173
`ifdef  OPT_NO_USERMODE
174
        localparam      [0:0]     OPT_NO_USERMODE = 1'b1;
175
`else
176
        localparam      [0:0]     OPT_NO_USERMODE = 1'b0;
177
`endif
178
`ifdef  OPT_PIPELINED
179
        parameter       [0:0]     OPT_PIPELINED = 1'b1;
180
`else
181
        parameter       [0:0]     OPT_PIPELINED = 1'b0;
182
`endif
183
`ifdef  OPT_PIPELINED_BUS_ACCESS
184
        localparam      [0:0]     OPT_PIPELINED_BUS_ACCESS = (OPT_PIPELINED);
185
`else
186
        localparam      [0:0]     OPT_PIPELINED_BUS_ACCESS = 1'b0;
187
`endif
188
        localparam      [0:0]     OPT_MEMPIPE = OPT_PIPELINED_BUS_ACCESS;
189
        parameter       [0:0]     IMPLEMENT_LOCK=1;
190
        localparam      [0:0]     OPT_LOCK=(IMPLEMENT_LOCK)&&(OPT_PIPELINED);
191
`ifdef  OPT_DCACHE
192
        parameter               OPT_LGDCACHE = 10;
193
`else
194
        parameter               OPT_LGDCACHE = 0;
195
`endif
196
        localparam      [0:0]     OPT_DCACHE = (OPT_LGDCACHE > 0);
197
 
198
        parameter [0:0]   WITH_LOCAL_BUS = 1'b1;
199 193 dgisselq
        localparam      AW=ADDRESS_WIDTH;
200 201 dgisselq
        localparam      [(AW-1):0]       RESET_BUS_ADDRESS = RESET_ADDRESS[(AW+1):2];
201 209 dgisselq
        parameter       F_LGDEPTH=8;
202
 
203
        //}}}
204
        // I/O declarations
205
        //{{{
206
        input   wire            i_clk, i_reset, i_interrupt;
207 2 dgisselq
        // Debug interface -- inputs
208 209 dgisselq
        input   wire            i_halt, i_clear_pf_cache;
209
        input   wire    [4:0]    i_dbg_reg;
210
        input   wire            i_dbg_we;
211
        input   wire    [31:0]   i_dbg_data;
212 2 dgisselq
        // Debug interface -- outputs
213 160 dgisselq
        output  wire            o_dbg_stall;
214 2 dgisselq
        output  reg     [31:0]   o_dbg_reg;
215 56 dgisselq
        output  reg     [3:0]    o_dbg_cc;
216 2 dgisselq
        output  wire            o_break;
217
        // Wishbone interface -- outputs
218 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
219
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
220 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
221
        output  wire    [31:0]   o_wb_data;
222 201 dgisselq
        output  wire    [3:0]    o_wb_sel;
223 2 dgisselq
        // Wishbone interface -- inputs
224 209 dgisselq
        input   wire            i_wb_ack, i_wb_stall;
225
        input   wire    [31:0]   i_wb_data;
226
        input   wire            i_wb_err;
227 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
228 9 dgisselq
        output  wire            o_op_stall;
229 2 dgisselq
        output  wire            o_pf_stall;
230 9 dgisselq
        output  wire            o_i_count;
231 56 dgisselq
        //
232 65 dgisselq
`ifdef  DEBUG_SCOPE
233 56 dgisselq
        output  reg     [31:0]   o_debug;
234 209 dgisselq
        // output       wire    [31:0]  o_dcache_debug;
235 65 dgisselq
`endif
236 209 dgisselq
        //}}}
237 2 dgisselq
 
238 25 dgisselq
 
239 2 dgisselq
        // Registers
240 56 dgisselq
        //
241
        //      The distributed RAM style comment is necessary on the
242
        // SPARTAN6 with XST to prevent XST from oversimplifying the register
243
        // set and in the process ruining everything else.  It basically
244
        // optimizes logic away, to where it no longer works.  The logic
245
        // as described herein will work, this just makes sure XST implements
246
        // that logic.
247
        //
248
        (* ram_style = "distributed" *)
249 209 dgisselq
        reg     [31:0]   regset  [0:(OPT_NO_USERMODE)? 15:31];
250 9 dgisselq
 
251
        // Condition codes
252 56 dgisselq
        // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
253
        reg     [3:0]    flags, iflags;
254 179 dgisselq
        wire    [14:0]   w_uflags, w_iflags;
255 201 dgisselq
        reg             break_en, step, sleep, r_halted;
256 209 dgisselq
        wire            break_pending, trap, gie, ubreak, pending_interrupt;
257 201 dgisselq
        wire            w_clear_icache, ill_err_u;
258
        reg             ill_err_i;
259
        reg             ibus_err_flag;
260
        wire            ubus_err_flag;
261 69 dgisselq
        wire            idiv_err_flag, udiv_err_flag;
262
        wire            ifpu_err_flag, ufpu_err_flag;
263
        wire            ihalt_phase, uhalt_phase;
264 2 dgisselq
 
265 9 dgisselq
        // The master chip enable
266 209 dgisselq
        wire            master_ce, master_stall;
267 2 dgisselq
 
268
        //
269
        //
270
        //      PIPELINE STAGE #1 :: Prefetch
271
        //              Variable declarations
272
        //
273 209 dgisselq
        //{{{
274 201 dgisselq
        reg     [(AW+1):0]       pf_pc;
275 209 dgisselq
        wire    [(AW+1):0]       pf_request_address, pf_instruction_pc;
276 69 dgisselq
        reg     new_pc;
277 18 dgisselq
        wire    clear_pipeline;
278 9 dgisselq
 
279 209 dgisselq
        reg                     dcd_stalled;
280
        wire                    pf_cyc, pf_stb, pf_we, pf_ack, pf_stall, pf_err;
281 48 dgisselq
        wire    [(AW-1):0]       pf_addr;
282
        wire    [31:0]           pf_data;
283 201 dgisselq
        wire    [31:0]           pf_instruction;
284 209 dgisselq
        wire                    pf_valid, pf_gie, pf_illegal;
285
        wire                    pf_stalled;
286
        wire                    pf_new_pc;
287
`ifdef  FORMAL
288
        wire    [31:0]           f_dcd_insn_word;
289
        wire                    f_dcd_insn_gie;
290
        reg     [31:0]           f_op_insn_word;
291
        reg     [31:0]           f_alu_insn_word;
292
`endif
293 2 dgisselq
 
294 209 dgisselq
        assign  clear_pipeline = new_pc;
295
        //}}}
296
 
297 2 dgisselq
        //
298
        //
299
        //      PIPELINE STAGE #2 :: Instruction Decode
300
        //              Variable declarations
301
        //
302
        //
303 209 dgisselq
        //{{{
304 201 dgisselq
        reg             op_valid /* verilator public_flat */,
305
                        op_valid_mem, op_valid_alu;
306
        reg             op_valid_div, op_valid_fpu;
307 69 dgisselq
        wire            op_stall, dcd_ce, dcd_phase;
308 201 dgisselq
        wire    [3:0]    dcd_opn;
309 209 dgisselq
        wire    [4:0]    dcd_A, dcd_B, dcd_R, dcd_preA, dcd_preB;
310 201 dgisselq
        wire            dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc;
311
        wire    [3:0]    dcd_F;
312
        wire            dcd_wR, dcd_rA, dcd_rB,
313
                                dcd_ALU, dcd_M, dcd_DIV, dcd_FP,
314
                                dcd_wF, dcd_gie, dcd_break, dcd_lock,
315 105 dgisselq
                                dcd_pipe, dcd_ljmp;
316 201 dgisselq
        wire            dcd_valid;
317 209 dgisselq
        wire    [AW+1:0] dcd_pc /* verilator public_flat */;
318 201 dgisselq
        wire    [31:0]   dcd_I;
319
        wire            dcd_zI; // true if dcd_I == 0
320
        wire    dcd_A_stall, dcd_B_stall, dcd_F_stall;
321 2 dgisselq
 
322 69 dgisselq
        wire    dcd_illegal;
323 209 dgisselq
        wire                    dcd_early_branch, dcd_early_branch_stb;
324
        wire    [(AW+1):0]       dcd_branch_pc;
325 2 dgisselq
 
326 201 dgisselq
        wire            dcd_sim;
327
        wire    [22:0]   dcd_sim_immv;
328 209 dgisselq
        wire            prelock_stall;
329
        wire            cc_invalid_for_dcd;
330
        wire            pending_sreg_write;
331
        //}}}
332 2 dgisselq
 
333 201 dgisselq
 
334 2 dgisselq
        //
335
        //
336
        //      PIPELINE STAGE #3 :: Read Operands
337
        //              Variable declarations
338
        //
339
        //
340
        //
341 209 dgisselq
        //{{{
342 2 dgisselq
        // Now, let's read our operands
343
        reg     [4:0]    alu_reg;
344 201 dgisselq
        wire    [3:0]    op_opn;
345 209 dgisselq
        reg     [4:0]    op_R;
346
        reg             op_Rcc;
347
        reg     [4:0]    op_Aid, op_Bid;
348
        reg             op_rA, op_rB;
349 201 dgisselq
        reg     [31:0]   r_op_Av, r_op_Bv;
350 209 dgisselq
        reg     [(AW+1):0]       op_pc;
351
        wire    [31:0]   w_op_Av, w_op_Bv, op_Av, op_Bv;
352
        reg     [31:0]   w_pcB_v, w_pcA_v;
353
        reg     [31:0]   w_op_BnI;
354 201 dgisselq
        reg             op_wR, op_wF;
355 209 dgisselq
        wire            op_gie;
356
        wire    [3:0]    op_Fl;
357 201 dgisselq
        reg     [6:0]    r_op_F;
358
        wire    [7:0]    op_F;
359 209 dgisselq
        wire            op_ce, op_phase, op_pipe;
360
        reg             r_op_break;
361
        reg     [3:0]    r_op_opn;
362
        wire    w_op_valid;
363
        wire    [8:0]    w_cpu_info;
364 56 dgisselq
        // Some pipeline control wires
365 36 dgisselq
        reg     op_illegal;
366 179 dgisselq
        wire    op_break;
367 69 dgisselq
        wire    op_lock;
368 2 dgisselq
 
369 201 dgisselq
`ifdef  VERILATOR
370
        reg             op_sim          /* verilator public_flat */;
371
        reg     [22:0]   op_sim_immv     /* verilator public_flat */;
372 209 dgisselq
`else
373
        wire    op_sim = 1'b0;
374 201 dgisselq
`endif
375 209 dgisselq
        //}}}
376 2 dgisselq
 
377 201 dgisselq
 
378 2 dgisselq
        //
379
        //
380
        //      PIPELINE STAGE #4 :: ALU / Memory
381
        //              Variable declarations
382
        //
383
        //
384 209 dgisselq
        //{{{
385
        wire    [(AW+1):0]       alu_pc;
386 145 dgisselq
        reg             r_alu_pc_valid, mem_pc_valid;
387
        wire            alu_pc_valid;
388 69 dgisselq
        wire            alu_phase;
389 201 dgisselq
        wire            alu_ce /* verilator public_flat */, alu_stall;
390 2 dgisselq
        wire    [31:0]   alu_result;
391
        wire    [3:0]    alu_flags;
392 71 dgisselq
        wire            alu_valid, alu_busy;
393 2 dgisselq
        wire            set_cond;
394 201 dgisselq
        reg             alu_wR, alu_wF;
395 193 dgisselq
        wire            alu_gie, alu_illegal;
396 2 dgisselq
 
397
 
398 209 dgisselq
        wire                    mem_ce, mem_stalled;
399
        wire                    mem_pipe_stalled;
400
        wire                    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
401
                                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
402 48 dgisselq
        wire    [4:0]            mem_wreg;
403 9 dgisselq
 
404 48 dgisselq
        wire                    mem_busy, mem_rdbusy;
405
        wire    [(AW-1):0]       mem_addr;
406
        wire    [31:0]           mem_data, mem_result;
407 201 dgisselq
        wire    [3:0]            mem_sel;
408 2 dgisselq
 
409 209 dgisselq
        wire            div_ce, div_error, div_busy, div_valid;
410 69 dgisselq
        wire    [31:0]   div_result;
411
        wire    [3:0]    div_flags;
412 2 dgisselq
 
413 209 dgisselq
        wire            fpu_ce, fpu_error, fpu_busy, fpu_valid;
414 69 dgisselq
        wire    [31:0]   fpu_result;
415
        wire    [3:0]    fpu_flags;
416 209 dgisselq
        reg             adf_ce_unconditional;
417 69 dgisselq
 
418 209 dgisselq
        wire            bus_lock;
419 69 dgisselq
 
420 209 dgisselq
        reg             dbgv, dbg_clear_pipe;
421
        reg     [31:0]   dbg_val;
422 69 dgisselq
 
423 209 dgisselq
        assign  div_ce = (op_valid_div)&&(adf_ce_unconditional)&&(set_cond);
424
        assign  fpu_ce = (IMPLEMENT_FPU)&&(op_valid_fpu)&&(adf_ce_unconditional)&&(set_cond);
425
 
426
        //}}}
427
 
428 2 dgisselq
        //
429
        //
430
        //      PIPELINE STAGE #5 :: Write-back
431
        //              Variable declarations
432
        //
433 209 dgisselq
        //{{{
434 179 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc,
435
                        wr_write_scc, wr_write_ucc;
436 2 dgisselq
        wire    [4:0]    wr_reg_id;
437 160 dgisselq
        wire    [31:0]   wr_gpreg_vl, wr_spreg_vl;
438 209 dgisselq
        wire            w_switch_to_interrupt, w_release_from_interrupt;
439 201 dgisselq
        reg     [(AW+1):0]       ipc;
440
        wire    [(AW+1):0]       upc;
441 209 dgisselq
        reg             last_write_to_cc;
442
        wire            cc_write_hold;
443
        reg             r_clear_icache;
444
        //}}}
445 2 dgisselq
 
446 209 dgisselq
`ifdef  FORMAL
447
        wire    [F_LGDEPTH-1:0]
448
                f_gbl_arb_nreqs, f_gbl_arb_nacks, f_gbl_arb_outstanding,
449
                f_lcl_arb_nreqs, f_lcl_arb_nacks, f_lcl_arb_outstanding,
450
                f_gbl_mem_nreqs, f_gbl_mem_nacks, f_gbl_mem_outstanding,
451
                f_lcl_mem_nreqs, f_lcl_mem_nacks, f_lcl_mem_outstanding,
452
                f_gbl_pf_nreqs, f_gbl_pf_nacks, f_gbl_pf_outstanding,
453
                f_lcl_pf_nreqs, f_lcl_pf_nacks, f_lcl_pf_outstanding,
454
                f_mem_nreqs, f_mem_nacks, f_mem_outstanding;
455
        reg     f_pf_nreqs, f_pf_nacks, f_pf_outstanding;
456
        wire    f_mem_pc;
457
`endif
458 2 dgisselq
 
459
 
460
        //
461
        //      MASTER: clock enable.
462
        //
463 209 dgisselq
        assign  master_ce = ((!i_halt)||(alu_phase))
464
                                &&(!cc_write_hold)&&(!o_break)&&(!sleep);
465 2 dgisselq
 
466
 
467
        //
468
        //      PIPELINE STAGE #1 :: Prefetch
469
        //              Calculate stall conditions
470 65 dgisselq
        //
471
        //      These are calculated externally, within the prefetch module.
472
        //
473 2 dgisselq
 
474
        //
475
        //      PIPELINE STAGE #2 :: Instruction Decode
476
        //              Calculate stall conditions
477 145 dgisselq
 
478 209 dgisselq
        always @(*)
479
        if (OPT_PIPELINED)
480
                dcd_stalled = (dcd_valid)&&(op_stall);
481
        else
482
                dcd_stalled = (!master_ce)||(ill_err_i)||(dcd_valid)||(op_valid)
483
                        ||(ibus_err_flag)||(idiv_err_flag)
484
                        ||(alu_busy)||(div_busy)||(fpu_busy)||(mem_busy);
485 2 dgisselq
        //
486
        //      PIPELINE STAGE #3 :: Read Operands
487
        //              Calculate stall conditions
488 209 dgisselq
        //{{{
489
        generate if (OPT_PIPELINED)
490
        begin : GEN_OP_STALL
491
                reg     r_cc_invalid_for_dcd;
492
                always @(posedge i_clk)
493
                        r_cc_invalid_for_dcd <=
494
                                (set_cond)&&(op_valid)
495
                                        &&((op_wF)||((op_wR)&&(op_R[4:0] == { op_gie, `CPU_CC_REG })))
496
                                ||((r_cc_invalid_for_dcd)
497
                                        &&((alu_busy)||(mem_rdbusy)||(div_busy)||(fpu_busy)));
498 179 dgisselq
 
499 209 dgisselq
                assign  cc_invalid_for_dcd = r_cc_invalid_for_dcd;
500
 
501
                reg     r_pending_sreg_write;
502
                initial r_pending_sreg_write = 1'b0;
503
                always @(posedge i_clk)
504
                if (clear_pipeline)
505
                        r_pending_sreg_write <= 1'b0;
506
                else if (((adf_ce_unconditional)||(mem_ce))
507
                                &&(set_cond)&&(!op_illegal)
508
                                &&(op_wR)
509
                                &&(op_R[3:1] == 3'h7)
510
                                &&(op_R[4:0] != { gie, 4'hf }))
511
                        r_pending_sreg_write <= 1'b1;
512
                else if ((!mem_rdbusy)&&(!alu_busy))
513
                        r_pending_sreg_write <= 1'b0;
514
 
515
                assign  pending_sreg_write = r_pending_sreg_write;
516
 
517
                assign  op_stall = (op_valid)&&(
518
                //{{{
519
                        // Only stall if we're loaded w/validins and the
520
                        // next stage is accepting our instruction
521
                        (!adf_ce_unconditional)&&(!mem_ce)
522 69 dgisselq
                        )
523 201 dgisselq
                        ||(dcd_valid)&&(
524 71 dgisselq
                                // Stall if we need to wait for an operand A
525 69 dgisselq
                                // to be ready to read
526 201 dgisselq
                                (dcd_A_stall)
527 69 dgisselq
                                // Likewise for B, also includes logic
528
                                // regarding immediate offset (register must
529
                                // be in register file if we need to add to
530
                                // an immediate)
531 201 dgisselq
                                ||(dcd_B_stall)
532 69 dgisselq
                                // Or if we need to wait on flags to work on the
533
                                // CC register
534 201 dgisselq
                                ||(dcd_F_stall)
535 69 dgisselq
                        );
536 209 dgisselq
                //}}}
537
                assign  op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall);
538 179 dgisselq
 
539 209 dgisselq
        end else begin // !OPT_PIPELINED
540 179 dgisselq
 
541 209 dgisselq
                assign  op_stall = 1'b0; // (o_break)||(pending_interrupt);
542
                assign  op_ce = ((dcd_valid)||(dcd_early_branch))&&(!op_stall);
543
                assign  pending_sreg_write = 1'b0;
544
                assign  cc_invalid_for_dcd = 1'b0;
545
 
546
                // Verilator lint_off UNUSED
547
                wire    [1:0]    pipe_unused;
548
                assign          pipe_unused = { cc_invalid_for_dcd,
549
                                        pending_sreg_write };
550
                // Verilator lint_on UNUSED
551
        end endgenerate
552
 
553 160 dgisselq
        // BUT ... op_ce is too complex for many of the data operations.  So
554
        // let's make their circuit enable code simpler.  In particular, if
555
        // op_ doesn't need to be preserved, we can change it all we want
556
        // ... right?  The clear_pipeline code, for example, really only needs
557 201 dgisselq
        // to determine whether op_valid is true.
558 209 dgisselq
        // assign       op_change_data_ce = (!op_stall);
559
        //}}}
560 2 dgisselq
 
561
        //
562
        //      PIPELINE STAGE #4 :: ALU / Memory
563
        //              Calculate stall conditions
564 36 dgisselq
        //
565 209 dgisselq
        //{{{
566 36 dgisselq
        // 1. Basic stall is if the previous stage is valid and the next is
567 201 dgisselq
        //      busy.
568 36 dgisselq
        // 2. Also stall if the prior stage is valid and the master clock enable
569
        //      is de-selected
570 56 dgisselq
        // 3. Stall if someone on the other end is writing the CC register,
571
        //      since we don't know if it'll put us to sleep or not.
572 36 dgisselq
        // 4. Last case: Stall if we would otherwise move a break instruction
573
        //      through the ALU.  Break instructions are not allowed through
574
        //      the ALU.
575 209 dgisselq
        generate if (OPT_PIPELINED)
576
        begin : GEN_ALU_STALL
577
                assign  alu_stall = (((master_stall)||(mem_rdbusy))&&(op_valid_alu)) //Case 1&2
578
                        ||(wr_reg_ce)&&(wr_write_cc);
579
                // assign // alu_ce = (master_ce)&&(op_valid_alu)&&(!alu_stall)
580
                //      &&(!clear_pipeline)&&(!op_illegal)
581
                //      &&(!pending_sreg_write)
582
                //      &&(!alu_sreg_stall);
583
                assign  alu_ce = (adf_ce_unconditional)&&(op_valid_alu);
584
 
585
                // Verilator lint_off unused
586
                wire    unused_alu_stall = alu_stall;
587
                // Verilator lint_on  unused
588
        end else begin
589
 
590
                assign  alu_stall = (master_stall);
591
                //assign        alu_ce = (master_ce)&&(op_valid_alu)
592
                //                      &&(!clear_pipeline)
593
                //                      &&(!alu_stall);
594
                assign  alu_ce = (adf_ce_unconditional)&&(op_valid_alu);
595
 
596
                // Verilator lint_off unused
597
                wire    unused_alu_stall = alu_stall;
598
                // Verilator lint_on  unused
599
        end endgenerate
600 2 dgisselq
        //
601 65 dgisselq
 
602
        //
603
        // Note: if you change the conditions for mem_ce, you must also change
604
        // alu_pc_valid.
605
        //
606 205 dgisselq
        assign  mem_ce = (master_ce)&&(op_valid_mem)&&(!mem_stalled)
607
                        &&(!clear_pipeline);
608
 
609 209 dgisselq
        generate if (OPT_PIPELINED_BUS_ACCESS)
610
        begin
611
 
612
                assign  mem_stalled = (master_stall)||((op_valid_mem)&&(
613 38 dgisselq
                                (mem_pipe_stalled)
614 209 dgisselq
                                ||(bus_err)||(div_error)
615 205 dgisselq
                                ||((!op_pipe)&&(mem_busy))
616 38 dgisselq
                                // Stall waiting for flags to be valid
617
                                // Or waiting for a write to the PC register
618
                                // Or CC register, since that can change the
619
                                //  PC as well
620 209 dgisselq
                                ||((wr_reg_ce)
621 38 dgisselq
                                        &&((wr_write_pc)||(wr_write_cc)))));
622 209 dgisselq
        end else if (OPT_PIPELINED)
623
        begin
624
                assign  mem_stalled = (master_stall)||((op_valid_mem)&&(
625
                                (bus_err)||(div_error)||(mem_busy)
626 2 dgisselq
                                // Stall waiting for flags to be valid
627
                                // Or waiting for a write to the PC register
628 25 dgisselq
                                // Or CC register, since that can change the
629
                                //  PC as well
630 209 dgisselq
                                ||((wr_reg_ce)
631
                                        &&((wr_write_pc)||(wr_write_cc)))));
632
        end else begin
633 2 dgisselq
 
634 209 dgisselq
                assign  mem_stalled = (master_stall);
635
 
636
        end endgenerate
637
        //}}}
638
 
639
        assign  master_stall = (!master_ce)||(!op_valid)||(ill_err_i)
640
                        ||(ibus_err_flag)||(idiv_err_flag)
641
                        ||(pending_interrupt)&&(!alu_phase)
642
                        ||(alu_busy)||(div_busy)||(fpu_busy)||(op_break)
643
                        ||((OPT_PIPELINED)&&(
644
                                ((OPT_LOCK)&&(prelock_stall))
645
                                ||((mem_busy)&&(op_illegal))
646
                                ||((mem_busy)&&(op_valid_div))
647
                                ||(alu_illegal)||(o_break)));
648
 
649
 
650 179 dgisselq
        // ALU, DIV, or FPU CE ... equivalent to the OR of all three of these
651 209 dgisselq
        always @(*)
652
        if (OPT_PIPELINED)
653
                adf_ce_unconditional =
654
                        (!master_stall)&&(!op_valid_mem)&&(!mem_rdbusy)
655
                        &&((!mem_busy)||(!op_wR)||(op_R[4:1] != { gie, 3'h7}));
656
        else
657
                adf_ce_unconditional = (!master_stall)&&(op_valid)&&(!op_valid_mem);
658 2 dgisselq
 
659
        //
660
        //
661
        //      PIPELINE STAGE #1 :: Prefetch
662
        //
663
        //
664 209 dgisselq
        //{{{
665 205 dgisselq
        assign  pf_stalled = (dcd_stalled)||(dcd_phase);
666
 
667 209 dgisselq
        assign  pf_new_pc = (new_pc)||((dcd_early_branch_stb)&&(!clear_pipeline));
668 205 dgisselq
 
669 209 dgisselq
        assign  pf_request_address = ((dcd_early_branch_stb)&&(!clear_pipeline))
670
                                ? dcd_branch_pc:pf_pc;
671 205 dgisselq
        assign  pf_gie = gie;
672 209 dgisselq
`ifdef  FORMAL
673
        abs_prefetch    #(ADDRESS_WIDTH)
674
        //{{{
675
                        pf(i_clk, (i_reset), pf_new_pc, w_clear_icache,
676
                                (!pf_stalled),
677
                                pf_request_address,
678
                                pf_instruction, pf_instruction_pc,
679
                                        pf_valid,
680
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
681
                                pf_ack, pf_stall, pf_err, i_wb_data,
682
                                        pf_illegal);
683
                always @(*)
684
                begin
685
                        f_pf_nreqs = 0;
686
                        f_pf_nacks = 0;
687
                        f_pf_outstanding = 0;
688
                end
689
        //}}}
690
`else
691 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
692 48 dgisselq
        prefetch        #(ADDRESS_WIDTH)
693 209 dgisselq
        //{{{
694
                        pf(i_clk, (i_reset), pf_new_pc, w_clear_icache,
695 205 dgisselq
                                (!pf_stalled),
696
                                pf_request_address,
697
                                pf_instruction, pf_instruction_pc,
698 36 dgisselq
                                        pf_valid, pf_illegal,
699
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
700
                                pf_ack, pf_stall, pf_err, i_wb_data);
701 209 dgisselq
        //}}}
702 205 dgisselq
`else
703
`ifdef  OPT_DOUBLE_FETCH
704 69 dgisselq
 
705 205 dgisselq
        dblfetch #(ADDRESS_WIDTH)
706 209 dgisselq
        //{{{
707
                pf(i_clk, i_reset, pf_new_pc, w_clear_icache,
708 205 dgisselq
                                (!pf_stalled),
709
                                pf_request_address,
710
                                pf_instruction, pf_instruction_pc,
711
                                        pf_valid,
712
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
713
                                        pf_ack, pf_stall, pf_err, i_wb_data,
714
                                pf_illegal);
715 209 dgisselq
        //}}}
716 69 dgisselq
 
717 205 dgisselq
`else // Not single fetch and not double fetch
718
 
719 69 dgisselq
`ifdef  OPT_TRADITIONAL_PFCACHE
720
        pfcache #(LGICACHE, ADDRESS_WIDTH)
721 209 dgisselq
        //{{{
722
                pf(i_clk, i_reset, pf_new_pc, w_clear_icache,
723 69 dgisselq
                                // dcd_pc,
724 201 dgisselq
                                (!pf_stalled),
725
                                pf_request_address,
726
                                pf_instruction, pf_instruction_pc, pf_valid,
727 69 dgisselq
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
728
                                        pf_ack, pf_stall, pf_err, i_wb_data,
729
                                pf_illegal);
730 209 dgisselq
        //}}}
731 69 dgisselq
`else
732 209 dgisselq
        pipefetch       #({RESET_BUS_ADDRESS, 2'b00}, LGICACHE, ADDRESS_WIDTH)
733
        //{{{
734
                        pf(i_clk, i_reset, pf_new_pc,
735 201 dgisselq
                                        w_clear_icache, (!pf_stalled),
736 209 dgisselq
                                        (new_pc)?pf_pc:dcd_branch_pc,
737 201 dgisselq
                                        pf_instruction, pf_instruction_pc, pf_valid,
738 2 dgisselq
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
739 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
740
                                (mem_cyc_lcl)||(mem_cyc_gbl),
741
                                pf_illegal);
742 209 dgisselq
        //}}}
743 205 dgisselq
`endif  // OPT_TRADITIONAL_CACHE
744
`endif  // OPT_DOUBLE_FETCH
745
`endif  // OPT_SINGLE_FETCH
746 209 dgisselq
`endif  // FORMAL
747
        //}}}
748 2 dgisselq
 
749 209 dgisselq
        //
750
        //
751
        //      PIPELINE STAGE #2 :: Instruction Decode
752
        //
753
        //
754
        //{{{
755
        assign          dcd_ce =((OPT_PIPELINED)&&(!dcd_valid))||(!dcd_stalled);
756
        idecode #(.ADDRESS_WIDTH(AW),
757
                .OPT_MPY((IMPLEMENT_MPY!=0)? 1'b1:1'b0),
758
                .OPT_PIPELINED(OPT_PIPELINED),
759
                .OPT_EARLY_BRANCHING(EARLY_BRANCHING),
760
                .OPT_DIVIDE(IMPLEMENT_DIVIDE),
761
                .OPT_FPU(IMPLEMENT_FPU),
762
                .OPT_LOCK(OPT_LOCK),
763
                .OPT_OPIPE(OPT_PIPELINED_BUS_ACCESS),
764
                .OPT_NO_USERMODE(OPT_NO_USERMODE),
765
`ifdef  VERILATOR
766
                .OPT_SIM(1'b1),
767
`else
768
                .OPT_SIM(1'b0),
769
`endif
770
                .OPT_CIS(OPT_CIS))
771
                instruction_decoder(i_clk,
772
                        (i_reset)||(clear_pipeline)||(w_clear_icache),
773 205 dgisselq
                        dcd_ce,
774
                        dcd_stalled, pf_instruction, pf_gie,
775 209 dgisselq
                        pf_instruction_pc, pf_valid, pf_illegal,
776 205 dgisselq
                        dcd_valid, dcd_phase,
777 209 dgisselq
                        dcd_illegal, dcd_pc,
778 201 dgisselq
                        { dcd_Rcc, dcd_Rpc, dcd_R },
779
                        { dcd_Acc, dcd_Apc, dcd_A },
780
                        { dcd_Bcc, dcd_Bpc, dcd_B },
781 209 dgisselq
                        dcd_preA, dcd_preB,
782 201 dgisselq
                        dcd_I, dcd_zI, dcd_F, dcd_wF, dcd_opn,
783
                        dcd_ALU, dcd_M, dcd_DIV, dcd_FP, dcd_break, dcd_lock,
784
                        dcd_wR,dcd_rA, dcd_rB,
785 209 dgisselq
                        dcd_early_branch, dcd_early_branch_stb,
786 105 dgisselq
                        dcd_branch_pc, dcd_ljmp,
787 201 dgisselq
                        dcd_pipe,
788 209 dgisselq
                        dcd_sim, dcd_sim_immv
789
`ifdef  FORMAL
790
                        , f_dcd_insn_word, f_dcd_insn_gie
791
`endif
792
                        );
793
        assign  dcd_gie = pf_gie;
794
        //}}}
795 2 dgisselq
 
796 209 dgisselq
        //
797
        //
798
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
799
        //
800
        //
801
        //{{{
802
        generate if (OPT_PIPELINED_BUS_ACCESS)
803
        begin : GEN_OP_PIPE
804
                reg             r_op_pipe;
805 2 dgisselq
 
806 209 dgisselq
                initial r_op_pipe = 1'b0;
807
                // To be a pipeable operation, there must be
808
                //      two valid adjacent instructions
809
                //      Both must be memory instructions
810
                //      Both must be writes, or both must be reads
811
                //      Both operations must be to the same identical address,
812
                //              or at least a single (one) increment above that
813
                //              address
814
                //
815
                // However ... we need to know this before this clock, hence
816
                // this is calculated in the instruction decoder.
817
                always @(posedge i_clk)
818
                if ((clear_pipeline)||(i_halt))
819 201 dgisselq
                        r_op_pipe <= 1'b0;
820
                else if (op_ce)
821 209 dgisselq
                        r_op_pipe <= (dcd_pipe)&&(op_valid_mem);
822
                else if ((wr_reg_ce)&&(wr_reg_id == op_Bid[4:0]))
823
                        r_op_pipe <= 1'b0;
824 145 dgisselq
                else if (mem_ce) // Clear us any time an op_ is clocked in
825
                        r_op_pipe <= 1'b0;
826 209 dgisselq
 
827
                assign  op_pipe = r_op_pipe;
828
        end else begin
829
 
830
                assign  op_pipe = 1'b0;
831
 
832
        end endgenerate
833
 
834
// `define      NO_DISTRIBUTED_RAM
835
`ifdef  NO_DISTRIBUTED_RAM
836
        reg     [31:0]   pre_rewrite_value, pre_op_Av, pre_op_Bv;
837
        reg             pre_rewrite_flag_A, pre_rewrite_flag_B;
838
 
839
        always @(posedge i_clk)
840
        if (dcd_ce)
841
        begin
842
                pre_rewrite_flag_A <= (wr_reg_ce)&&(dcd_preA == wr_reg_id);
843
                pre_rewrite_flag_B <= (wr_reg_ce)&&(dcd_preB == wr_reg_id);
844
                pre_rewrite_value  <= wr_gpreg_vl;
845
        end
846
 
847
        generate if (OPT_NO_USERMODE)
848
        begin
849
                always @(posedge i_clk)
850
                if (dcd_ce)
851
                begin
852
                        pre_op_Av <= regset[dcd_preA[3:0]];
853
                        pre_op_Bv <= regset[dcd_preB[3:0]];
854
                end
855
        end else begin
856
 
857
                always @(posedge i_clk)
858
                if (dcd_ce)
859
                begin
860
                        pre_op_Av <= regset[dcd_preA];
861
                        pre_op_Bv <= regset[dcd_preB];
862
                end
863
 
864
        end endgenerate
865
 
866
        assign  w_op_Av = (pre_rewrite_flag_A) ? pre_rewrite_value : pre_op_Av;
867
        assign  w_op_Bv = (pre_rewrite_flag_B) ? pre_rewrite_value : pre_op_Bv;
868 132 dgisselq
`else
869 209 dgisselq
        generate if (OPT_NO_USERMODE)
870
        begin
871
                assign  w_op_Av = regset[dcd_A[3:0]];
872
                assign  w_op_Bv = regset[dcd_B[3:0]];
873
        end else begin
874 38 dgisselq
 
875 209 dgisselq
                assign  w_op_Av = regset[dcd_A];
876
                assign  w_op_Bv = regset[dcd_B];
877
 
878
        end endgenerate
879
 
880
        // verilator lint_off UNUSED
881
        wire    [9:0]    unused_prereg_addrs;
882
        assign  unused_prereg_addrs = { dcd_preA, dcd_preB };
883
        // verilator lint_on  UNUSED
884 201 dgisselq
`endif
885 56 dgisselq
 
886 132 dgisselq
        assign  w_cpu_info = {
887 209 dgisselq
        //{{{
888 132 dgisselq
        1'b1,
889 201 dgisselq
        (IMPLEMENT_MPY    >0)? 1'b1:1'b0,
890
        (IMPLEMENT_DIVIDE >0)? 1'b1:1'b0,
891
        (IMPLEMENT_FPU    >0)? 1'b1:1'b0,
892 209 dgisselq
        OPT_PIPELINED,
893 132 dgisselq
`ifdef  OPT_TRADITIONAL_CACHE
894
        1'b1,
895
`else
896
        1'b0,
897
`endif
898 209 dgisselq
        (EARLY_BRANCHING > 0)? 1'b1:1'b0,
899
        OPT_PIPELINED_BUS_ACCESS,
900
        OPT_CIS
901 132 dgisselq
        };
902 209 dgisselq
        //}}}
903 132 dgisselq
 
904 209 dgisselq
        always @(*)
905
        if ((OPT_NO_USERMODE)||(dcd_A[4] == dcd_gie))
906
                w_pcA_v[(AW+1):0] = { dcd_pc[AW+1:2], 2'b00 };
907
        else
908
                w_pcA_v[(AW+1):0] = { upc[(AW+1):2], uhalt_phase, 1'b0 };
909
 
910 56 dgisselq
        generate
911 201 dgisselq
        if (AW < 30)
912 209 dgisselq
                always @(*)
913
                        w_pcA_v[31:(AW+2)] = 0;
914 56 dgisselq
        endgenerate
915 71 dgisselq
 
916 209 dgisselq
        generate if (OPT_PIPELINED)
917
        begin : OPV
918
                initial op_R   = 0;
919
                initial op_Aid = 0;
920
                initial op_Bid = 0;
921
                initial op_rA  = 0;
922
                initial op_rB  = 0;
923
                initial op_Rcc = 0;
924
                always @(posedge i_clk)
925 71 dgisselq
                if (op_ce)
926
                begin
927 209 dgisselq
                        op_R   <= dcd_R;
928 201 dgisselq
                        op_Aid <= dcd_A;
929
                        op_Bid <= dcd_B;
930 209 dgisselq
                        op_rA  <= (dcd_rA)&&(!dcd_early_branch)&&(!dcd_illegal);
931
                        op_rB  <= (dcd_rB)&&(!dcd_early_branch)&&(!dcd_illegal);
932
                        op_Rcc <= (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie);
933 71 dgisselq
                end
934
 
935 209 dgisselq
        end else begin
936
 
937
                always @(*)
938 2 dgisselq
                begin
939 209 dgisselq
                        op_R   = dcd_R;
940
                        op_Aid = dcd_A;
941
                        op_Bid = dcd_B;
942
                        op_rA  = dcd_rA;
943
                        op_rB  = dcd_rB;
944
                        op_Rcc = (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie);
945 2 dgisselq
                end
946 56 dgisselq
 
947 209 dgisselq
        end endgenerate
948
 
949
 
950
        always @(posedge i_clk)
951
        if ((!OPT_PIPELINED)||(op_ce))
952
        begin
953
                if ((OPT_PIPELINED)&&(wr_reg_ce)&&(wr_reg_id == dcd_A))
954
                        r_op_Av <= wr_gpreg_vl;
955
                else if (dcd_Apc)
956
                        r_op_Av <= w_pcA_v;
957
                else if (dcd_Acc)
958
                        r_op_Av <= { w_cpu_info, w_op_Av[22:16], 1'b0, (dcd_A[4])?w_uflags:w_iflags };
959
                else
960
                        r_op_Av <= w_op_Av;
961
        end else if (OPT_PIPELINED)
962
        begin
963
                if ((wr_reg_ce)&&(wr_reg_id == op_Aid)&&(op_rA))
964
                        r_op_Av <= wr_gpreg_vl;
965
        end
966
 
967
        always @(*)
968
        if ((OPT_NO_USERMODE)||(dcd_B[4] == dcd_gie))
969
                w_pcB_v[(AW+1):0] = { dcd_pc[AW+1:2], 2'b00 };
970
        else
971
                w_pcB_v[(AW+1):0] = { upc[(AW+1):2], uhalt_phase, 1'b0 };
972 56 dgisselq
        generate
973 201 dgisselq
        if (AW < 30)
974 209 dgisselq
                always @(*)
975
                        w_pcB_v[31:(AW+2)] = 0;
976 56 dgisselq
        endgenerate
977
 
978 209 dgisselq
        always @(*)
979
        if (!dcd_rB)
980
                w_op_BnI = 0;
981
        else if ((OPT_PIPELINED)&&(wr_reg_ce)&&(wr_reg_id == dcd_B))
982
                w_op_BnI = wr_gpreg_vl;
983
        else if (dcd_Bcc)
984
                w_op_BnI = { w_cpu_info, w_op_Bv[22:16], 1'b0,
985
                                (dcd_B[4]) ? w_uflags : w_iflags };
986
        else
987
                w_op_BnI = w_op_Bv;
988 56 dgisselq
 
989 2 dgisselq
        always @(posedge i_clk)
990 209 dgisselq
        if ((!OPT_PIPELINED)||(op_ce))
991
        begin
992 201 dgisselq
                if ((dcd_Bpc)&&(dcd_rB))
993
                        r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 };
994
                else
995
                        r_op_Bv <= w_op_BnI + dcd_I;
996 209 dgisselq
        end else if ((OPT_PIPELINED)&&(op_rB)
997
                        &&(wr_reg_ce)&&(op_Bid == wr_reg_id))
998
                r_op_Bv <= wr_gpreg_vl;
999 2 dgisselq
 
1000
        // The logic here has become more complex than it should be, no thanks
1001
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
1002
        // be two sets of four bits: the top bits specify what bits matter, the
1003
        // bottom specify what those top bits must equal.  However, two of
1004
        // conditions check whether bits are on, and those are the only two
1005
        // conditions checking those bits.  Therefore, Vivado complains that
1006
        // these two bits are redundant.  Hence the convoluted expression
1007
        // below, arriving at what we finally want in the (now wire net)
1008 201 dgisselq
        // op_F.
1009 2 dgisselq
        always @(posedge i_clk)
1010 209 dgisselq
        if ((!OPT_PIPELINED)||(op_ce))
1011
                // Cannot do op_change_data_ce here since op_F depends
1012
                // upon being either correct for a valid op, or correct
1013
                // for the last valid op
1014
        begin // Set the flag condition codes, bit order is [3:0]=VNCZ
1015
                case(dcd_F[2:0])
1016
                3'h0:   r_op_F <= 7'h00;        // Always
1017
                3'h1:   r_op_F <= 7'h11;        // Z
1018
                3'h2:   r_op_F <= 7'h44;        // LT
1019
                3'h3:   r_op_F <= 7'h22;        // C
1020
                3'h4:   r_op_F <= 7'h08;        // V
1021
                3'h5:   r_op_F <= 7'h10;        // NE
1022
                3'h6:   r_op_F <= 7'h40;        // GE (!N)
1023
                3'h7:   r_op_F <= 7'h20;        // NC
1024
                endcase
1025
        end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
1026 201 dgisselq
        assign  op_F = { r_op_F[3], r_op_F[6:0] };
1027 2 dgisselq
 
1028 209 dgisselq
        assign  w_op_valid = (!clear_pipeline)&&(dcd_valid)
1029
                                        &&(!dcd_ljmp)&&(!dcd_early_branch);
1030
 
1031 201 dgisselq
        initial op_valid     = 1'b0;
1032
        initial op_valid_alu = 1'b0;
1033
        initial op_valid_mem = 1'b0;
1034
        initial op_valid_div = 1'b0;
1035
        initial op_valid_fpu = 1'b0;
1036 2 dgisselq
        always @(posedge i_clk)
1037 209 dgisselq
        if ((i_reset)||(clear_pipeline))
1038
        begin
1039
                op_valid     <= 1'b0;
1040
                op_valid_alu <= 1'b0;
1041
                op_valid_mem <= 1'b0;
1042
                op_valid_div <= 1'b0;
1043
                op_valid_fpu <= 1'b0;
1044
        end else if (op_ce)
1045
        begin
1046
                // Do we have a valid instruction?
1047
                //   The decoder may vote to stall one of its
1048
                //   instructions based upon something we currently
1049
                //   have in our queue.  This instruction must then
1050
                //   move forward, and get a stall cycle inserted.
1051
                //   Hence, the test on dcd_stalled here.  If we must
1052
                //   wait until our operands are valid, then we aren't
1053
                //   valid yet until then.
1054
                if (OPT_PIPELINED || !op_valid)
1055 25 dgisselq
                begin
1056 209 dgisselq
                        op_valid     <= (w_op_valid)||(dcd_early_branch);
1057
                        op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal));
1058
                        op_valid_mem <= (dcd_M)&&(!dcd_illegal)
1059
                                        &&(w_op_valid);
1060
                        op_valid_div <= (IMPLEMENT_DIVIDE)&&(dcd_DIV)&&(!dcd_illegal)&&(w_op_valid);
1061
                        op_valid_fpu <= (IMPLEMENT_FPU)&&(dcd_FP)&&(!dcd_illegal)&&(w_op_valid);
1062 193 dgisselq
                end else if ((adf_ce_unconditional)||(mem_ce))
1063 25 dgisselq
                begin
1064 201 dgisselq
                        op_valid     <= 1'b0;
1065
                        op_valid_alu <= 1'b0;
1066
                        op_valid_mem <= 1'b0;
1067
                        op_valid_div <= 1'b0;
1068
                        op_valid_fpu <= 1'b0;
1069 25 dgisselq
                end
1070 209 dgisselq
        end else if ((adf_ce_unconditional)||(mem_ce))
1071
        begin
1072
                op_valid     <= 1'b0;
1073
                op_valid_alu <= 1'b0;
1074
                op_valid_mem <= 1'b0;
1075
                op_valid_div <= 1'b0;
1076
                op_valid_fpu <= 1'b0;
1077
        end
1078 2 dgisselq
 
1079
        // Here's part of our debug interface.  When we recognize a break
1080
        // instruction, we set the op_break flag.  That'll prevent this
1081
        // instruction from entering the ALU, and cause an interrupt before
1082
        // this instruction.  Thus, returning to this code will cause the
1083
        // break to repeat and continue upon return.  To get out of this
1084
        // condition, replace the break instruction with what it is supposed
1085
        // to be, step through it, and then replace it back.  In this fashion,
1086
        // a debugger can step through code.
1087 201 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001);
1088 179 dgisselq
 
1089
        initial r_op_break = 1'b0;
1090 2 dgisselq
        always @(posedge i_clk)
1091 209 dgisselq
        if (clear_pipeline)
1092
                r_op_break <= 1'b0;
1093
        else if ((OPT_PIPELINED)&&(op_ce))
1094
                r_op_break <= (dcd_valid)&&(dcd_break)&&(!dcd_illegal);
1095
        else if ((!OPT_PIPELINED)&&(dcd_valid))
1096
                r_op_break <= (dcd_break)&&(!dcd_illegal);
1097 179 dgisselq
        assign  op_break = r_op_break;
1098 2 dgisselq
 
1099 209 dgisselq
        generate if ((!OPT_PIPELINED)||(!OPT_LOCK))
1100 69 dgisselq
        begin
1101 209 dgisselq
 
1102
                assign op_lock       = 1'b0;
1103
 
1104
                // Verilator lint_off UNUSED
1105
                wire    dcd_lock_unused;
1106
                assign  dcd_lock_unused = dcd_lock;
1107
                // Verilator lint_on  UNUSED
1108
 
1109
        end else // if (IMPLEMENT_LOCK != 0)
1110
        begin : OPLOCK
1111 201 dgisselq
                reg     r_op_lock;
1112 69 dgisselq
 
1113
                initial r_op_lock = 1'b0;
1114
                always @(posedge i_clk)
1115 209 dgisselq
                if (clear_pipeline)
1116
                        r_op_lock <= 1'b0;
1117
                else if (op_ce)
1118
                        r_op_lock <= (dcd_valid)&&(dcd_lock)
1119
                                        &&(!dcd_illegal);
1120 69 dgisselq
                assign  op_lock = r_op_lock;
1121
 
1122
        end endgenerate
1123
 
1124 71 dgisselq
        initial op_illegal = 1'b0;
1125 2 dgisselq
        always @(posedge i_clk)
1126 209 dgisselq
        if ((i_reset)||(clear_pipeline))
1127
                op_illegal <= 1'b0;
1128
        else if (OPT_PIPELINED)
1129
        begin
1130 71 dgisselq
                if (op_ce)
1131 209 dgisselq
                        op_illegal <= (dcd_valid)&&(!dcd_ljmp)
1132
                                &&(!dcd_early_branch)&&(dcd_illegal);
1133
        end else if (!OPT_PIPELINED)
1134 179 dgisselq
        begin
1135 209 dgisselq
                if (dcd_valid)
1136
                        op_illegal <= (!dcd_ljmp)&&(!dcd_early_branch)&&(dcd_illegal);
1137 179 dgisselq
        end
1138 69 dgisselq
 
1139 209 dgisselq
        always @(posedge i_clk)
1140
        if ((!OPT_PIPELINED)||(op_ce))
1141
                op_wF <= (dcd_wF)&&((!dcd_Rcc)||(!dcd_wR))
1142
                        &&(!dcd_early_branch);
1143
 
1144
        generate if ((OPT_PIPELINED)||(EARLY_BRANCHING))
1145
        begin
1146
 
1147
                always @(posedge i_clk)
1148
                if (op_ce)
1149
                        op_wR <= (dcd_wR)&&(!dcd_early_branch);
1150
 
1151
        end else begin
1152
 
1153
                always @(*)
1154
                        op_wR = (dcd_wR);
1155
 
1156
        end endgenerate
1157
 
1158 201 dgisselq
`ifdef  VERILATOR
1159 205 dgisselq
`ifdef  SINGLE_FETCH
1160
        always @(*)
1161
        begin
1162
                op_sim      = dcd_sim;
1163
                op_sim_immv = dcd_sim_immv;
1164
        end
1165
`else
1166 201 dgisselq
        always @(posedge i_clk)
1167 209 dgisselq
                if (op_ce)
1168 201 dgisselq
                begin
1169
                        op_sim      <= dcd_sim;
1170
                        op_sim_immv <= dcd_sim_immv;
1171
                end
1172
`endif
1173
`endif
1174
 
1175 205 dgisselq
 
1176 209 dgisselq
        generate if ((OPT_PIPELINED)||(EARLY_BRANCHING))
1177
        begin : SET_OP_PC
1178
 
1179
                initial op_pc[0] = 1'b0;
1180
                always @(posedge i_clk)
1181
                if (op_ce)
1182
                        op_pc <= (dcd_early_branch)?dcd_branch_pc:dcd_pc;
1183
 
1184
        end else begin : SET_OP_PC
1185
 
1186
                always @(*)
1187
                        op_pc = dcd_pc;
1188
 
1189
        end endgenerate
1190
 
1191
        generate if (!OPT_PIPELINED)
1192
        begin
1193
                always @(*)
1194
                        r_op_opn = dcd_opn;
1195
 
1196
        end else begin
1197
 
1198
                always @(posedge i_clk)
1199
                if (op_ce)
1200 2 dgisselq
                begin
1201 201 dgisselq
                        // Which ALU operation?  Early branches are
1202
                        // unimplemented moves
1203 209 dgisselq
                        r_op_opn    <= ((dcd_early_branch)||(dcd_illegal))
1204
                                        ? `CPU_MOV_OP : dcd_opn;
1205 201 dgisselq
                        // opM  <= dcd_M;       // Is this a memory operation?
1206 2 dgisselq
                        // What register will these results be written into?
1207 209 dgisselq
                end
1208 2 dgisselq
 
1209 209 dgisselq
        end endgenerate
1210
 
1211 201 dgisselq
        assign  op_opn = r_op_opn;
1212 209 dgisselq
        assign  op_gie = gie;
1213 205 dgisselq
 
1214 209 dgisselq
        assign  op_Fl = (op_gie)?(w_uflags[3:0]):(w_iflags[3:0]);
1215 2 dgisselq
 
1216 209 dgisselq
        generate if (OPT_CIS)
1217
        begin : OPT_CIS_OP_PHASE
1218 69 dgisselq
 
1219 209 dgisselq
                reg     r_op_phase;
1220
 
1221
                initial r_op_phase = 1'b0;
1222
                always @(posedge i_clk)
1223
                        if ((i_reset)||(clear_pipeline))
1224
                                r_op_phase <= 1'b0;
1225
                        else if (op_ce)
1226
                                r_op_phase <= (dcd_phase)&&((!dcd_wR)||(!dcd_Rpc));
1227
                assign  op_phase = r_op_phase;
1228
        end else begin : OPT_NOCIS_OP_PHASE
1229
                assign  op_phase = 1'b0;
1230
 
1231
                // verilator lint_off UNUSED
1232
                wire    OPT_CIS_dcdRpc;
1233
                assign  OPT_CIS_dcdRpc = dcd_Rpc;
1234
                // verilator lint_on  UNUSED
1235
        end endgenerate
1236
 
1237 2 dgisselq
        // This is tricky.  First, the PC and Flags registers aren't kept in
1238
        // register set but in special registers of their own.  So step one
1239
        // is to select the right register.  Step to is to replace that
1240
        // register with the results of an ALU or memory operation, if such
1241
        // results are now available.  Otherwise, we'd need to insert a wait
1242
        // state of some type.
1243
        //
1244
        // The alternative approach would be to define some sort of
1245
        // op_stall wire, which would stall any upstream stage.
1246
        // We'll create a flag here to start our coordination.  Once we
1247
        // define this flag to something other than just plain zero, then
1248
        // the stalls will already be in place.
1249 209 dgisselq
        generate if (OPT_PIPELINED)
1250
        begin
1251
 
1252
                assign  op_Av = ((wr_reg_ce)&&(wr_reg_id == op_Aid))
1253 201 dgisselq
                        ?  wr_gpreg_vl : r_op_Av;
1254 48 dgisselq
 
1255 209 dgisselq
        end else begin
1256
 
1257
                assign  op_Av = r_op_Av;
1258
 
1259
        end endgenerate
1260
 
1261 83 dgisselq
        // Stall if we have decoded an instruction that will read register A
1262
        //      AND ... something that may write a register is running
1263
        //      AND (series of conditions here ...)
1264
        //              The operation might set flags, and we wish to read the
1265
        //                      CC register
1266
        //              OR ... (No other conditions)
1267 209 dgisselq
        generate if (OPT_PIPELINED)
1268
        begin
1269
 
1270
                assign  dcd_A_stall = (dcd_rA) // &&(dcd_valid) is checked for elsewhere
1271 201 dgisselq
                                &&((op_valid)||(mem_rdbusy)
1272 83 dgisselq
                                        ||(div_busy)||(fpu_busy))
1273 201 dgisselq
                                &&(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Acc))
1274
                        ||((dcd_rA)&&(dcd_Acc)&&(cc_invalid_for_dcd));
1275 209 dgisselq
        end else begin
1276 36 dgisselq
 
1277 209 dgisselq
                // There are no pipeline hazards, if we aren't pipelined
1278
                assign  dcd_A_stall = 1'b0;
1279
 
1280
        end endgenerate
1281
 
1282
        assign  op_Bv = ((OPT_PIPELINED)&&(wr_reg_ce)
1283
                                        &&(wr_reg_id == op_Bid)&&(op_rB))
1284 201 dgisselq
                        ? wr_gpreg_vl: r_op_Bv;
1285 56 dgisselq
 
1286 209 dgisselq
        generate if (OPT_PIPELINED)
1287
        begin
1288 83 dgisselq
        // Stall if we have decoded an instruction that will read register B
1289
        //      AND ... something that may write a (unknown) register is running
1290
        //      AND (series of conditions here ...)
1291
        //              The operation might set flags, and we wish to read the
1292
        //                      CC register
1293
        //              OR the operation might set register B, and we still need
1294
        //                      a clock to add the offset to it
1295 201 dgisselq
        assign  dcd_B_stall = (dcd_rB) // &&(dcd_valid) is checked for elsewhere
1296 209 dgisselq
        //{{{
1297 83 dgisselq
                                // If the op stage isn't valid, yet something
1298
                                // is running, then it must have been valid.
1299
                                // We'll use the last values from that stage
1300 201 dgisselq
                                // (op_wR, op_wF, op_R) in our logic below.
1301
                                &&((op_valid)||(mem_rdbusy)
1302 132 dgisselq
                                        ||(div_busy)||(fpu_busy)||(alu_busy))
1303 83 dgisselq
                                &&(
1304 145 dgisselq
                                // Okay, what happens if the result register
1305
                                // from instruction 1 becomes the input for
1306
                                // instruction two, *and* there's an immediate
1307
                                // offset in instruction two?  In that case, we
1308 201 dgisselq
                                // need an extra clock between the two
1309
                                // instructions to calculate the base plus
1310 145 dgisselq
                                // offset.
1311
                                //
1312
                                // What if instruction 1 (or before) is in a
1313
                                // memory pipeline?  We may no longer know what
1314 201 dgisselq
                                // the register was!  We will then need  to
1315 145 dgisselq
                                // blindly wait.  We'll temper this only waiting
1316
                                // if we're not piping this new instruction.
1317
                                // If we were piping, the pipe logic in the
1318
                                // decode circuit has told us that the hazard
1319
                                // is clear, so we're okay then.
1320
                                //
1321 205 dgisselq
                                ((!dcd_zI)&&(
1322 201 dgisselq
                                        ((op_R == dcd_B)&&(op_wR))
1323 205 dgisselq
                                        ||((mem_rdbusy)&&(!dcd_pipe))
1324 209 dgisselq
                                        ||(((alu_busy)||(div_busy))&&(alu_reg == dcd_B))
1325
                                        ||((wr_reg_ce)&&(wr_reg_id[3:1] == 3'h7))
1326 145 dgisselq
                                        ))
1327 83 dgisselq
                                // Stall following any instruction that will
1328
                                // set the flags, if we're going to need the
1329 201 dgisselq
                                // flags (CC) register for op_B.
1330
                                ||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc))
1331 38 dgisselq
                                // Stall on any ongoing memory operation that
1332 201 dgisselq
                                // will write to op_B -- captured above
1333 205 dgisselq
                                // ||((mem_busy)&&(!mem_we)&&(mem_last_reg==dcd_B)&&(!dcd_zI))
1334 179 dgisselq
                                )
1335 201 dgisselq
                        ||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd));
1336 209 dgisselq
                //}}}
1337
                assign  dcd_F_stall = ((!dcd_F[3])
1338
                //{{{
1339
                                        ||((dcd_rA)&&(dcd_A[3:1]==3'h7)
1340
                                                &&(dcd_A[4:0] != { gie, 4'hf}))
1341
                                        ||((dcd_rB)&&(dcd_B[3:1]==3'h7))
1342
                                                &&(dcd_B[4:0] != { gie, 4'hf}))
1343
                                        &&(((op_valid)&&(op_wR)
1344
                                                &&(op_R[3:1]==3'h7)
1345
                                                &&(op_R[4:0]!={gie, 4'hf}))
1346
                                                ||(pending_sreg_write));
1347 201 dgisselq
                                // &&(dcd_valid) is checked for elsewhere
1348 209 dgisselq
                //}}}
1349
        end else begin
1350
                // No stalls without pipelining, 'cause how can you have a pipeline
1351
                // hazard without the pipeline?
1352
                assign  dcd_B_stall = 1'b0;
1353
                assign  dcd_F_stall = 1'b0;
1354
        end endgenerate
1355
 
1356
        //}}}
1357 2 dgisselq
        //
1358
        //
1359
        //      PIPELINE STAGE #4 :: Apply Instruction
1360
        //
1361
        //
1362 209 dgisselq
        // ALU
1363
        cpuops  #(IMPLEMENT_MPY) doalu(i_clk, ((i_reset)||(clear_pipeline)),
1364
        //{{{
1365 201 dgisselq
                        alu_ce, op_opn, op_Av, op_Bv,
1366 193 dgisselq
                        alu_result, alu_flags, alu_valid, alu_busy);
1367 209 dgisselq
        //}}}
1368 2 dgisselq
 
1369 209 dgisselq
        // Divide
1370
        //{{{
1371
        generate if (IMPLEMENT_DIVIDE != 0)
1372
        begin : DIVIDE
1373
`ifdef  FORMAL
1374
`define DIVIDE_MODULE   abs_div
1375
`else
1376
`define DIVIDE_MODULE   div
1377
`endif
1378
                `DIVIDE_MODULE thedivide(i_clk, ((i_reset)||(clear_pipeline)),
1379
                                div_ce, op_opn[0],
1380 201 dgisselq
                        op_Av, op_Bv, div_busy, div_valid, div_error, div_result,
1381 69 dgisselq
                        div_flags);
1382 209 dgisselq
 
1383 69 dgisselq
        end else begin
1384 209 dgisselq
 
1385 179 dgisselq
                assign  div_error = 1'b0; // Can't be high unless div_valid
1386 69 dgisselq
                assign  div_busy  = 1'b0;
1387
                assign  div_valid = 1'b0;
1388
                assign  div_result= 32'h00;
1389
                assign  div_flags = 4'h0;
1390 209 dgisselq
 
1391
                // Make verilator happy here
1392
                // verilator lint_off UNUSED
1393
                wire    unused_divide;
1394
                assign  unused_divide = div_ce;
1395
                // verilator lint_on  UNUSED
1396 69 dgisselq
        end endgenerate
1397 209 dgisselq
        //}}}
1398 69 dgisselq
 
1399 209 dgisselq
        // (Non-existent) FPU
1400
        //{{{
1401
        generate if (IMPLEMENT_FPU != 0)
1402
        begin : FPU
1403 69 dgisselq
                //
1404 209 dgisselq
                // sfpu thefpu(i_clk, i_reset, fpu_ce, op_opn[2:0],
1405 201 dgisselq
                //      op_Av, op_Bv, fpu_busy, fpu_valid, fpu_err, fpu_result,
1406 69 dgisselq
                //      fpu_flags);
1407
                //
1408 179 dgisselq
                assign  fpu_error = 1'b0; // Must only be true if fpu_valid
1409 69 dgisselq
                assign  fpu_busy  = 1'b0;
1410
                assign  fpu_valid = 1'b0;
1411
                assign  fpu_result= 32'h00;
1412
                assign  fpu_flags = 4'h0;
1413
        end else begin
1414 179 dgisselq
                assign  fpu_error = 1'b0;
1415 69 dgisselq
                assign  fpu_busy  = 1'b0;
1416
                assign  fpu_valid = 1'b0;
1417
                assign  fpu_result= 32'h00;
1418
                assign  fpu_flags = 4'h0;
1419
        end endgenerate
1420 209 dgisselq
        //}}}
1421 69 dgisselq
 
1422
 
1423 201 dgisselq
        assign  set_cond = ((op_F[7:4]&op_Fl[3:0])==op_F[3:0]);
1424
        initial alu_wF   = 1'b0;
1425
        initial alu_wR   = 1'b0;
1426 209 dgisselq
        generate if (OPT_PIPELINED)
1427
        begin
1428
                always @(posedge i_clk)
1429
                if (i_reset)
1430 2 dgisselq
                begin
1431 201 dgisselq
                        alu_wR   <= 1'b0;
1432
                        alu_wF   <= 1'b0;
1433 2 dgisselq
                end else if (alu_ce)
1434
                begin
1435 201 dgisselq
                        // alu_reg <= op_R;
1436 209 dgisselq
                        alu_wR  <= (op_wR)&&(set_cond)&&(!op_illegal);
1437
                        alu_wF  <= (op_wF)&&(set_cond)&&(!op_illegal);
1438 205 dgisselq
                end else if (!alu_busy) begin
1439 2 dgisselq
                        // These are strobe signals, so clear them if not
1440
                        // set for any particular clock
1441 209 dgisselq
                        alu_wR <= (r_halted)&&(i_dbg_we);
1442 201 dgisselq
                        alu_wF <= 1'b0;
1443 2 dgisselq
                end
1444 209 dgisselq
        end else begin
1445 69 dgisselq
 
1446 209 dgisselq
                always @(posedge i_clk)
1447
                        alu_wR  <= (op_wR)&&(set_cond)&&(!op_illegal);
1448
                always @(posedge i_clk)
1449
                        alu_wF  <= (op_wF)&&(set_cond)&&(!op_illegal);
1450 69 dgisselq
 
1451 209 dgisselq
        end endgenerate
1452
 
1453
        generate if (OPT_CIS)
1454
        begin : GEN_ALU_PHASE
1455
 
1456
                reg     r_alu_phase;
1457
                initial r_alu_phase = 1'b0;
1458
                always @(posedge i_clk)
1459
                        if ((i_reset)||(clear_pipeline))
1460
                                r_alu_phase <= 1'b0;
1461
                        else if (((adf_ce_unconditional)||(mem_ce))&&(op_valid))
1462
                                r_alu_phase <= op_phase;
1463
                        else if ((adf_ce_unconditional)||(mem_ce))
1464
                                r_alu_phase <= 1'b0;
1465
                assign  alu_phase = r_alu_phase;
1466
        end else begin
1467
 
1468
                assign  alu_phase = 1'b0;
1469
        end endgenerate
1470
 
1471
        generate if (OPT_PIPELINED)
1472
        begin
1473
 
1474
                always @(posedge i_clk)
1475 160 dgisselq
                if (adf_ce_unconditional)
1476 201 dgisselq
                        alu_reg <= op_R;
1477 209 dgisselq
                else if ((r_halted)&&(i_dbg_we))
1478 65 dgisselq
                        alu_reg <= i_dbg_reg;
1479 69 dgisselq
 
1480 209 dgisselq
        end else begin
1481
 
1482
                always @(posedge i_clk)
1483
                        if ((r_halted)&&(i_dbg_we))
1484
                                alu_reg <= i_dbg_reg;
1485
                        else
1486
                                alu_reg <= op_R;
1487
        end endgenerate
1488
 
1489 132 dgisselq
        //
1490
        // DEBUG Register write access starts here
1491
        //
1492 209 dgisselq
        //{{{
1493 65 dgisselq
        initial dbgv = 1'b0;
1494
        always @(posedge i_clk)
1495 209 dgisselq
        if (i_reset)
1496
                dbgv <= 0;
1497
        else
1498
                dbgv <= (i_dbg_we)&&(r_halted);
1499
 
1500 65 dgisselq
        always @(posedge i_clk)
1501 132 dgisselq
                dbg_val <= i_dbg_data;
1502
        always @(posedge i_clk)
1503 209 dgisselq
        if ((i_reset)||(clear_pipeline))
1504
                dbg_clear_pipe <= 0;
1505
        else if ((i_dbg_we)&&(r_halted))
1506
        begin
1507
                if (!OPT_PIPELINED)
1508
                        dbg_clear_pipe <= 1'b1;
1509
                else if ((i_dbg_reg == op_Bid)&&(op_rB))
1510
                        dbg_clear_pipe <= 1'b1;
1511
                else if (i_dbg_reg[3:1] == 3'h7)
1512
                        dbg_clear_pipe <= 1'b1;
1513
                else
1514
                        dbg_clear_pipe <= 1'b0;
1515
        end else if ((!OPT_PIPELINED)&&(i_clear_pf_cache))
1516
                dbg_clear_pipe <= 1'b1;
1517
        else
1518
                dbg_clear_pipe <= 1'b0;
1519 179 dgisselq
 
1520 209 dgisselq
        assign  alu_gie = gie;
1521
        //}}}
1522
 
1523
        generate if (OPT_PIPELINED)
1524
        begin : GEN_ALU_PC
1525
                reg     [(AW+1):0]       r_alu_pc;
1526
                initial r_alu_pc = 0;
1527
                always @(posedge i_clk)
1528
                if (i_reset)
1529
                        r_alu_pc <= 0;
1530
                else if ((adf_ce_unconditional)
1531
                                ||((master_ce)&&(op_valid_mem)
1532
                                        &&(!clear_pipeline)&&(!mem_stalled)))
1533 179 dgisselq
                        r_alu_pc  <= op_pc;
1534 209 dgisselq
                assign  alu_pc = r_alu_pc;
1535 65 dgisselq
 
1536 209 dgisselq
        end else begin
1537 38 dgisselq
 
1538 209 dgisselq
                assign  alu_pc = op_pc;
1539
 
1540
        end endgenerate
1541
 
1542
        generate if (OPT_PIPELINED)
1543
        begin : SET_ALU_ILLEGAL
1544
                reg             r_alu_illegal;
1545
 
1546
                initial r_alu_illegal = 0;
1547
                always @(posedge i_clk)
1548
                        if (clear_pipeline)
1549
                                r_alu_illegal <= 1'b0;
1550
                        else if (adf_ce_unconditional)
1551
                                r_alu_illegal <= op_illegal;
1552
                        else
1553
                                r_alu_illegal <= 1'b0;
1554
 
1555
                assign  alu_illegal = (r_alu_illegal);
1556
        end else begin : SET_ALU_ILLEGAL
1557
                assign  alu_illegal = op_illegal;
1558
        end endgenerate
1559
 
1560 145 dgisselq
        initial r_alu_pc_valid = 1'b0;
1561 132 dgisselq
        initial mem_pc_valid = 1'b0;
1562 2 dgisselq
        always @(posedge i_clk)
1563 201 dgisselq
                if (clear_pipeline)
1564 145 dgisselq
                        r_alu_pc_valid <= 1'b0;
1565 205 dgisselq
                else if ((adf_ce_unconditional)&&(!op_phase))
1566 145 dgisselq
                        r_alu_pc_valid <= 1'b1;
1567 205 dgisselq
                else if (((!alu_busy)&&(!div_busy)&&(!fpu_busy))||(clear_pipeline))
1568 145 dgisselq
                        r_alu_pc_valid <= 1'b0;
1569 205 dgisselq
        assign  alu_pc_valid = (r_alu_pc_valid)&&((!alu_busy)&&(!div_busy)&&(!fpu_busy));
1570 132 dgisselq
        always @(posedge i_clk)
1571 209 dgisselq
                if (i_reset)
1572 132 dgisselq
                        mem_pc_valid <= 1'b0;
1573
                else
1574
                        mem_pc_valid <= (mem_ce);
1575 2 dgisselq
 
1576 209 dgisselq
        // Bus lock logic
1577
        //{{{
1578 69 dgisselq
        generate
1579 209 dgisselq
        if ((OPT_PIPELINED)&&(!OPT_LOCK))
1580
        begin : BUSLOCK
1581 201 dgisselq
                reg     r_prelock_stall;
1582
 
1583
                initial r_prelock_stall = 1'b0;
1584
                always @(posedge i_clk)
1585
                        if (clear_pipeline)
1586
                                r_prelock_stall <= 1'b0;
1587
                        else if ((op_valid)&&(op_lock)&&(op_ce))
1588
                                r_prelock_stall <= 1'b1;
1589
                        else if ((op_valid)&&(dcd_valid)&&(pf_valid))
1590
                                r_prelock_stall <= 1'b0;
1591
 
1592
                assign  prelock_stall = r_prelock_stall;
1593
 
1594
                reg     r_prelock_primed;
1595 209 dgisselq
                initial r_prelock_primed = 1'b0;
1596 201 dgisselq
                always @(posedge i_clk)
1597
                        if (clear_pipeline)
1598
                                r_prelock_primed <= 1'b0;
1599
                        else if (r_prelock_stall)
1600
                                r_prelock_primed <= 1'b1;
1601
                        else if ((adf_ce_unconditional)||(mem_ce))
1602
                                r_prelock_primed <= 1'b0;
1603
 
1604 132 dgisselq
                reg     [1:0]    r_bus_lock;
1605
                initial r_bus_lock = 2'b00;
1606 69 dgisselq
                always @(posedge i_clk)
1607 201 dgisselq
                        if (clear_pipeline)
1608 132 dgisselq
                                r_bus_lock <= 2'b00;
1609 201 dgisselq
                        else if ((op_valid)&&((adf_ce_unconditional)||(mem_ce)))
1610
                        begin
1611
                                if (r_prelock_primed)
1612
                                        r_bus_lock <= 2'b10;
1613
                                else if (r_bus_lock != 2'h0)
1614
                                        r_bus_lock <= r_bus_lock + 2'b11;
1615
                        end
1616 132 dgisselq
                assign  bus_lock = |r_bus_lock;
1617 69 dgisselq
        end else begin
1618 201 dgisselq
                assign  prelock_stall = 1'b0;
1619 69 dgisselq
                assign  bus_lock = 1'b0;
1620
        end endgenerate
1621 209 dgisselq
        //}}}
1622
 
1623
        // Memory interface
1624
        //{{{
1625
        generate if (OPT_DCACHE)
1626
        begin : MEM_DCACHE
1627
 
1628
                dcache #(.LGCACHELEN(OPT_LGDCACHE), .ADDRESS_WIDTH(AW),
1629
                        .LGNLINES(OPT_LGDCACHE-3), .OPT_LOCAL_BUS(WITH_LOCAL_BUS),
1630
                        .OPT_PIPE(OPT_MEMPIPE),
1631
                        .OPT_LOCK(OPT_LOCK)
1632
`ifdef  FORMAL
1633
                        , .OPT_FIFO_DEPTH(2)
1634
                        , .F_LGDEPTH(F_LGDEPTH)
1635 69 dgisselq
`endif
1636 209 dgisselq
                        ) docache(i_clk, i_reset,
1637
                ///{{{
1638
                                (mem_ce)&&(set_cond), bus_lock,
1639
                                (op_opn[2:0]), op_Bv, op_Av, op_R,
1640
                                mem_busy, mem_pipe_stalled,
1641
                                mem_valid, bus_err, mem_wreg, mem_result,
1642
                        mem_cyc_gbl, mem_cyc_lcl,
1643
                                mem_stb_gbl, mem_stb_lcl,
1644
                                mem_we, mem_addr, mem_data, mem_sel,
1645
                                mem_ack, mem_stall, mem_err, i_wb_data
1646
`ifdef  FORMAL
1647
                        , f_mem_nreqs, f_mem_nacks, f_mem_outstanding, f_mem_pc
1648
`endif
1649
                                // , o_dcache_debug
1650
                        );
1651
                ///}}}
1652
        end else begin : NO_CACHE
1653
        if (OPT_PIPELINED_BUS_ACCESS)
1654
        begin : MEM
1655 69 dgisselq
 
1656 209 dgisselq
                pipemem #(.ADDRESS_WIDTH(AW),
1657
                        .IMPLEMENT_LOCK(OPT_LOCK),
1658
                        .WITH_LOCAL_BUS(WITH_LOCAL_BUS)
1659
`ifdef  FORMAL
1660
                        , .OPT_MAXDEPTH(4'h3),
1661
                        .F_LGDEPTH(F_LGDEPTH)
1662
`endif
1663
                        ) domem(i_clk,i_reset,
1664
                ///{{{
1665
                        (mem_ce)&&(set_cond), bus_lock,
1666 201 dgisselq
                                (op_opn[2:0]), op_Bv, op_Av, op_R,
1667 38 dgisselq
                                mem_busy, mem_pipe_stalled,
1668
                                mem_valid, bus_err, mem_wreg, mem_result,
1669
                        mem_cyc_gbl, mem_cyc_lcl,
1670
                                mem_stb_gbl, mem_stb_lcl,
1671 201 dgisselq
                                mem_we, mem_addr, mem_data, mem_sel,
1672 209 dgisselq
                                mem_ack, mem_stall, mem_err, i_wb_data
1673
`ifdef  FORMAL
1674
                        , f_mem_nreqs, f_mem_nacks, f_mem_outstanding, f_mem_pc
1675
`endif
1676
                        );
1677
                //}}}
1678
        end else begin : MEM
1679 201 dgisselq
 
1680 209 dgisselq
                memops  #(.ADDRESS_WIDTH(AW),
1681
                        .IMPLEMENT_LOCK(OPT_LOCK),
1682
                        .WITH_LOCAL_BUS(WITH_LOCAL_BUS)
1683
`ifdef  FORMAL
1684
                        , .F_LGDEPTH(F_LGDEPTH)
1685
`endif  // F_LGDEPTH
1686
                        ) domem(i_clk,i_reset,
1687
                //{{{
1688 205 dgisselq
                        (mem_ce)&&(set_cond), bus_lock,
1689 201 dgisselq
                                (op_opn[2:0]), op_Bv, op_Av, op_R,
1690 38 dgisselq
                                mem_busy,
1691
                                mem_valid, bus_err, mem_wreg, mem_result,
1692 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
1693
                                mem_stb_gbl, mem_stb_lcl,
1694 201 dgisselq
                                mem_we, mem_addr, mem_data, mem_sel,
1695 209 dgisselq
                                mem_ack, mem_stall, mem_err, i_wb_data
1696
`ifdef  FORMAL
1697
                        , f_mem_nreqs, f_mem_nacks, f_mem_outstanding
1698
`endif
1699
                        );
1700
`ifdef  FORMAL
1701
                assign  f_mem_pc = 1'b0;
1702
`endif
1703
                //}}}
1704
                assign  mem_pipe_stalled = 1'b0;
1705
        end end endgenerate
1706 2 dgisselq
 
1707 209 dgisselq
        assign  mem_rdbusy = (mem_busy)&&((!OPT_PIPELINED)||(!mem_we));
1708
 
1709 201 dgisselq
        // Either the prefetch or the instruction gets the memory bus, but
1710 2 dgisselq
        // never both.
1711 209 dgisselq
        wbdblpriarb     #(.DW(32),.AW(AW)
1712
`ifdef  FORMAL
1713
                ,.F_LGDEPTH(F_LGDEPTH), .F_MAX_STALL(2), .F_MAX_ACK_DELAY(2)
1714
`endif // FORMAL
1715
                ) pformem(i_clk, i_reset,
1716
        //{{{
1717 36 dgisselq
                // Memory access to the arbiter, priority position
1718
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
1719 201 dgisselq
                        mem_we, mem_addr, mem_data, mem_sel,
1720
                        mem_ack, mem_stall, mem_err,
1721 2 dgisselq
                // Prefetch access to the arbiter
1722 201 dgisselq
                //
1723
                // At a first glance, we might want something like:
1724
                //
1725
                // pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, 4'hf,
1726
                //
1727
                // However, we know that the prefetch will not generate any
1728
                // writes.  Therefore, the write specific lines (mem_data and
1729
                // mem_sel) can be shared with the memory in order to ease
1730
                // timing and LUT usage.
1731
                pf_cyc,1'b0,pf_stb, 1'b0, pf_we, pf_addr, mem_data, mem_sel,
1732 36 dgisselq
                        pf_ack, pf_stall, pf_err,
1733 2 dgisselq
                // Common wires, in and out, of the arbiter
1734 201 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
1735
                        o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
1736 209 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_err
1737
`ifdef  FORMAL
1738
                ,f_gbl_arb_nreqs, f_gbl_arb_nacks, f_gbl_arb_outstanding,
1739
                f_lcl_arb_nreqs, f_lcl_arb_nacks, f_lcl_arb_outstanding,
1740
                f_gbl_mem_nreqs, f_gbl_mem_nacks, f_gbl_mem_outstanding,
1741
                f_lcl_mem_nreqs, f_lcl_mem_nacks, f_lcl_mem_outstanding,
1742
                f_gbl_pf_nreqs, f_gbl_pf_nacks, f_gbl_pf_outstanding,
1743
                f_lcl_pf_nreqs, f_lcl_pf_nacks, f_lcl_pf_outstanding
1744
`endif
1745
                );
1746
        //}}}
1747
        //}}}
1748 2 dgisselq
 
1749 132 dgisselq
 
1750 2 dgisselq
        //
1751
        //
1752 132 dgisselq
        //
1753
        //
1754
        //
1755
        //
1756
        //
1757
        //
1758 2 dgisselq
        //      PIPELINE STAGE #5 :: Write-back results
1759
        //
1760 209 dgisselq
        //{{{
1761 2 dgisselq
        //
1762
        // This stage is not allowed to stall.  If results are ready to be
1763
        // written back, they are written back at all cost.  Sleepy CPU's
1764
        // won't prevent write back, nor debug modes, halting the CPU, nor
1765
        // anything else.  Indeed, the (master_ce) bit is only as relevant
1766
        // as knowinig something is available for writeback.
1767
 
1768
        //
1769
        // Write back to our generic register set ...
1770
        // When shall we write back?  On one of two conditions
1771
        //      Note that the flags needed to be checked before issuing the
1772
        //      bus instruction, so they don't need to be checked here.
1773 201 dgisselq
        //      Further, alu_wR includes (set_cond), so we don't need to
1774 2 dgisselq
        //      check for that here either.
1775 160 dgisselq
        assign  wr_reg_ce = (dbgv)||(mem_valid)
1776 205 dgisselq
                                ||((!clear_pipeline)&&(!alu_illegal)
1777 201 dgisselq
                                        &&(((alu_wR)&&(alu_valid))
1778 209 dgisselq
                                                ||((div_valid)&&(!div_error))
1779
                                                ||((fpu_valid)&&(!fpu_error))));
1780 2 dgisselq
        // Which register shall be written?
1781 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
1782
        //              One or PC, one for CC, and one for GIE match
1783 69 dgisselq
        //      Note that the alu_reg is the register to write on a divide or
1784
        //      FPU operation.
1785 209 dgisselq
        generate if (OPT_NO_USERMODE)
1786
        begin
1787
                assign  wr_reg_id[3:0] = (mem_valid)
1788
                                        ? mem_wreg[3:0] : alu_reg[3:0];
1789 201 dgisselq
 
1790 209 dgisselq
                assign  wr_reg_id[4] = 1'b0;
1791
        end else begin
1792
                assign  wr_reg_id = (mem_valid) ? mem_wreg : alu_reg;
1793
        end endgenerate
1794
 
1795 25 dgisselq
        // Are we writing to the CC register?
1796
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
1797 179 dgisselq
        assign  wr_write_scc = (wr_reg_id[4:0] == {1'b0, `CPU_CC_REG});
1798
        assign  wr_write_ucc = (wr_reg_id[4:0] == {1'b1, `CPU_CC_REG});
1799 2 dgisselq
        // Are we writing to the PC?
1800
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
1801 179 dgisselq
 
1802 2 dgisselq
        // What value to write?
1803 160 dgisselq
        assign  wr_gpreg_vl = ((mem_valid) ? mem_result
1804 71 dgisselq
                                :((div_valid|fpu_valid))
1805
                                        ? ((div_valid) ? div_result:fpu_result)
1806
                                :((dbgv) ? dbg_val : alu_result));
1807 160 dgisselq
        assign  wr_spreg_vl = ((mem_valid) ? mem_result
1808
                                :((dbgv) ? dbg_val : alu_result));
1809 2 dgisselq
 
1810 209 dgisselq
        generate if (OPT_NO_USERMODE)
1811
        begin : SET_REGISTERS
1812
 
1813
                always @(posedge i_clk)
1814
                        if (wr_reg_ce)
1815
                                regset[{1'b0,wr_reg_id[3:0]}] <= wr_gpreg_vl;
1816
 
1817
        end else begin : SET_REGISTERS
1818
 
1819
                always @(posedge i_clk)
1820
                        if (wr_reg_ce)
1821
                                regset[wr_reg_id] <= wr_gpreg_vl;
1822
 
1823
        end endgenerate
1824
 
1825
 
1826 2 dgisselq
        //
1827
        // Write back to the condition codes/flags register ...
1828 201 dgisselq
        // When shall we write to our flags register?  alu_wF already
1829 2 dgisselq
        // includes the set condition ...
1830 209 dgisselq
        assign  wr_flags_ce = (alu_wF)&&((alu_valid)
1831
                                ||(div_valid)||(fpu_valid))
1832
                                &&(!clear_pipeline)&&(!alu_illegal);
1833 179 dgisselq
        assign  w_uflags = { 1'b0, uhalt_phase, ufpu_err_flag,
1834 71 dgisselq
                        udiv_err_flag, ubus_err_flag, trap, ill_err_u,
1835 179 dgisselq
                        ubreak, step, 1'b1, sleep,
1836 71 dgisselq
                        ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
1837 179 dgisselq
        assign  w_iflags = { 1'b0, ihalt_phase, ifpu_err_flag,
1838 71 dgisselq
                        idiv_err_flag, ibus_err_flag, trap, ill_err_i,
1839
                        break_en, 1'b0, 1'b0, sleep,
1840 205 dgisselq
                        ((wr_flags_ce)&&(!alu_gie))?alu_flags:iflags };
1841 69 dgisselq
 
1842
 
1843 2 dgisselq
        // What value to write?
1844
        always @(posedge i_clk)
1845
                // If explicitly writing the register itself
1846 179 dgisselq
                if ((wr_reg_ce)&&(wr_write_ucc))
1847 160 dgisselq
                        flags <= wr_gpreg_vl[3:0];
1848 2 dgisselq
                // Otherwise if we're setting the flags from an ALU operation
1849
                else if ((wr_flags_ce)&&(alu_gie))
1850 69 dgisselq
                        flags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1851
                                : alu_flags);
1852 2 dgisselq
 
1853
        always @(posedge i_clk)
1854 179 dgisselq
                if ((wr_reg_ce)&&(wr_write_scc))
1855 160 dgisselq
                        iflags <= wr_gpreg_vl[3:0];
1856 205 dgisselq
                else if ((wr_flags_ce)&&(!alu_gie))
1857 69 dgisselq
                        iflags <= (div_valid)?div_flags:((fpu_valid)?fpu_flags
1858
                                : alu_flags);
1859 2 dgisselq
 
1860
        // The 'break' enable  bit.  This bit can only be set from supervisor
1861
        // mode.  It control what the CPU does upon encountering a break
1862
        // instruction.
1863
        //
1864
        // The goal, upon encountering a break is that the CPU should stop and
1865
        // not execute the break instruction, choosing instead to enter into
1866 201 dgisselq
        // either interrupt mode or halt first.
1867 2 dgisselq
        //      if ((break_en) AND (break_instruction)) // user mode or not
1868
        //              HALT CPU
1869
        //      else if (break_instruction) // only in user mode
1870 179 dgisselq
        //              set an interrupt flag, set the user break bit,
1871
        //              go to supervisor mode, allow supervisor to step the CPU.
1872 2 dgisselq
        //      Upon a CPU halt, any break condition will be reset.  The
1873
        //      external debugger will then need to deal with whatever
1874
        //      condition has taken place.
1875
        initial break_en = 1'b0;
1876
        always @(posedge i_clk)
1877 209 dgisselq
                if ((i_reset)||(i_halt))
1878 2 dgisselq
                        break_en <= 1'b0;
1879 179 dgisselq
                else if ((wr_reg_ce)&&(wr_write_scc))
1880 160 dgisselq
                        break_en <= wr_spreg_vl[`CPU_BREAK_BIT];
1881 179 dgisselq
 
1882 209 dgisselq
        generate if (OPT_PIPELINED)
1883
        begin : GEN_PENDING_BREAK
1884
                reg     r_break_pending;
1885 179 dgisselq
 
1886 209 dgisselq
                initial r_break_pending = 1'b0;
1887
                always @(posedge i_clk)
1888
                        if ((clear_pipeline)||(!op_valid))
1889
                                r_break_pending <= 1'b0;
1890
                        else if ((op_break)&&(!r_break_pending))
1891
                                r_break_pending <= (!alu_busy)&&(!div_busy)
1892
                                        &&(!fpu_busy)&&(!mem_busy)
1893
                                        &&(!wr_reg_ce);
1894
                        // else
1895
                                // r_break_pending <= 1'b0;
1896
                assign  break_pending = r_break_pending;
1897
        end else begin
1898 2 dgisselq
 
1899 209 dgisselq
                assign  break_pending = op_break;
1900
        end endgenerate
1901 2 dgisselq
 
1902 209 dgisselq
 
1903 205 dgisselq
        assign  o_break = ((break_en)||(!op_gie))&&(break_pending)
1904
                                &&(!clear_pipeline)
1905 209 dgisselq
                        ||(ill_err_i)
1906 205 dgisselq
                        ||((!alu_gie)&&(bus_err))
1907
                        ||((!alu_gie)&&(div_error))
1908
                        ||((!alu_gie)&&(fpu_error))
1909
                        ||((!alu_gie)&&(alu_illegal)&&(!clear_pipeline));
1910 179 dgisselq
 
1911 2 dgisselq
        // The sleep register.  Setting the sleep register causes the CPU to
1912
        // sleep until the next interrupt.  Setting the sleep register within
1913
        // interrupt mode causes the processor to halt until a reset.  This is
1914 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1915 201 dgisselq
        // set the sleep bit and switch to supervisor mode in the same
1916 25 dgisselq
        // instruction: users are not allowed to halt the CPU.
1917 201 dgisselq
        initial sleep = 1'b0;
1918 209 dgisselq
        generate if (OPT_NO_USERMODE)
1919
        begin : GEN_NO_USERMODE_SLEEP
1920
                reg     r_sleep_is_halt;
1921
                initial r_sleep_is_halt = 1'b0;
1922
                always @(posedge i_clk)
1923
                        if (i_reset)
1924
                                r_sleep_is_halt <= 1'b0;
1925
                        else if ((wr_reg_ce)&&(wr_write_cc)
1926
                                        &&(wr_spreg_vl[`CPU_SLEEP_BIT])
1927
                                        &&(!wr_spreg_vl[`CPU_GIE_BIT]))
1928
                                r_sleep_is_halt <= 1'b1;
1929 201 dgisselq
 
1930 209 dgisselq
                // Trying to switch to user mode, either via a WAIT or an RTU
1931
                // instruction will cause the CPU to sleep until an interrupt, in
1932
                // the NO-USERMODE build.
1933
                always @(posedge i_clk)
1934
                        if ((i_reset)||((i_interrupt)&&(!r_sleep_is_halt)))
1935
                                sleep <= 1'b0;
1936
                        else if ((wr_reg_ce)&&(wr_write_cc)
1937
                                        &&(wr_spreg_vl[`CPU_GIE_BIT]))
1938
                                sleep <= 1'b1;
1939
        end else begin : GEN_SLEEP
1940 2 dgisselq
 
1941 209 dgisselq
                always @(posedge i_clk)
1942
                        if ((i_reset)||(w_switch_to_interrupt))
1943
                                sleep <= 1'b0;
1944
                        else if ((wr_reg_ce)&&(wr_write_cc)&&(!alu_gie))
1945
                                // In supervisor mode, we have no protections.
1946
                                // The supervisor can set the sleep bit however
1947
                                // he wants.  Well ... not quite.  Switching to
1948
                                // user mode and sleep mode shouold only be
1949
                                // possible if the interrupt flag isn't set.
1950
                                //      Thus: if (i_interrupt)
1951
                                //                      &&(wr_spreg_vl[GIE])
1952
                                //              don't set the sleep bit
1953
                                //      otherwise however it would o.w. be set
1954
                                sleep <= (wr_spreg_vl[`CPU_SLEEP_BIT])
1955
                                        &&((!i_interrupt)
1956
                                                ||(!wr_spreg_vl[`CPU_GIE_BIT]));
1957
                        else if ((wr_reg_ce)&&(wr_write_cc)
1958
                                                &&(wr_spreg_vl[`CPU_GIE_BIT]))
1959
                                // In user mode, however, you can only set the
1960
                                // sleep mode while remaining in user mode.
1961
                                // You can't switch to sleep mode *and*
1962
                                // supervisor mode at the same time, lest you
1963
                                // halt the CPU.
1964
                                sleep <= wr_spreg_vl[`CPU_SLEEP_BIT];
1965
        end endgenerate
1966
 
1967 2 dgisselq
        always @(posedge i_clk)
1968 209 dgisselq
                if (i_reset)
1969 2 dgisselq
                        step <= 1'b0;
1970 205 dgisselq
                else if ((wr_reg_ce)&&(!alu_gie)&&(wr_write_ucc))
1971 160 dgisselq
                        step <= wr_spreg_vl[`CPU_STEP_BIT];
1972 2 dgisselq
 
1973
        // The GIE register.  Only interrupts can disable the interrupt register
1974 209 dgisselq
        generate if (OPT_NO_USERMODE)
1975
        begin
1976
 
1977
                assign  w_switch_to_interrupt    = 1'b0;
1978
                assign  w_release_from_interrupt = 1'b0;
1979
 
1980
        end else begin : GEN_PENDING_INTERRUPT
1981
                reg     r_pending_interrupt;
1982
 
1983
                always @(posedge i_clk)
1984
                if (i_reset)
1985
                        r_pending_interrupt <= 1'b0;
1986
                else if ((clear_pipeline)||(w_switch_to_interrupt)||(!gie))
1987
                        r_pending_interrupt <= 1'b0;
1988
                else if (i_interrupt)
1989
                        r_pending_interrupt <= 1'b1;
1990
                else if (adf_ce_unconditional)
1991
                begin
1992
                        if ((op_illegal)||(step)||(break_pending))
1993
                                r_pending_interrupt <= 1'b1;
1994
                end else if (break_pending)
1995
                        r_pending_interrupt <= 1'b1;
1996
                else if ((mem_ce)&&(step))
1997
                        r_pending_interrupt <= 1'b1;
1998
 
1999
                assign  pending_interrupt = r_pending_interrupt;
2000
 
2001
 
2002
                assign  w_switch_to_interrupt = (gie)&&(
2003 2 dgisselq
                        // On interrupt (obviously)
2004 209 dgisselq
                        ((pending_interrupt)
2005
                                &&(!alu_phase)&&(!bus_lock)&&(!mem_busy))
2006
                        //
2007 71 dgisselq
                        // On division by zero.  If the divide isn't
2008
                        // implemented, div_valid and div_error will be short
2009
                        // circuited and that logic will be bypassed
2010 179 dgisselq
                        ||(div_error)
2011 209 dgisselq
                        //
2012 179 dgisselq
                        // Same thing on a floating point error.  Note that
2013
                        // fpu_error must *never* be set unless fpu_valid is
2014
                        // also set as well, else this will fail.
2015
                        ||(fpu_error)
2016 201 dgisselq
                        //
2017 209 dgisselq
                        //
2018 69 dgisselq
                        ||(bus_err)
2019 209 dgisselq
                        //
2020 2 dgisselq
                        // If we write to the CC register
2021 205 dgisselq
                        ||((wr_reg_ce)&&(!wr_spreg_vl[`CPU_GIE_BIT])
2022 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
2023 2 dgisselq
                        );
2024 205 dgisselq
        assign  w_release_from_interrupt = (!gie)&&(!i_interrupt)
2025 179 dgisselq
                        // Then if we write the sCC register
2026 160 dgisselq
                        &&(((wr_reg_ce)&&(wr_spreg_vl[`CPU_GIE_BIT])
2027 179 dgisselq
                                &&(wr_write_scc))
2028 2 dgisselq
                        );
2029 209 dgisselq
        end endgenerate
2030 201 dgisselq
 
2031 209 dgisselq
        generate if (OPT_NO_USERMODE)
2032
        begin
2033
                assign  gie = 1'b0;
2034
        end else begin : SET_GIE
2035 201 dgisselq
 
2036 209 dgisselq
                reg     r_gie;
2037 2 dgisselq
 
2038 209 dgisselq
                initial r_gie = 1'b0;
2039
                always @(posedge i_clk)
2040
                        if (i_reset)
2041
                                r_gie <= 1'b0;
2042
                        else if (w_switch_to_interrupt)
2043
                                r_gie <= 1'b0;
2044
                        else if (w_release_from_interrupt)
2045
                                r_gie <= 1'b1;
2046
                assign  gie = r_gie;
2047
        end endgenerate
2048 201 dgisselq
 
2049 209 dgisselq
        generate if (OPT_NO_USERMODE)
2050
        begin
2051 25 dgisselq
 
2052 209 dgisselq
                assign  trap   = 1'b0;
2053
                assign  ubreak = 1'b0;
2054 201 dgisselq
 
2055 209 dgisselq
        end else begin : SET_TRAP_N_UBREAK
2056 179 dgisselq
 
2057 209 dgisselq
                reg     r_trap;
2058 179 dgisselq
 
2059 209 dgisselq
                initial r_trap = 1'b0;
2060
                always @(posedge i_clk)
2061
                        if ((i_reset)||(w_release_from_interrupt))
2062
                                r_trap <= 1'b0;
2063
                        else if ((alu_gie)&&(wr_reg_ce)&&(!wr_spreg_vl[`CPU_GIE_BIT])
2064
                                        &&(wr_write_ucc)) // &&(wr_reg_id[4]) implied
2065
                                r_trap <= 1'b1;
2066
                        else if ((wr_reg_ce)&&(wr_write_ucc)&&(!alu_gie))
2067
                                r_trap <= (r_trap)&&(wr_spreg_vl[`CPU_TRAP_BIT]);
2068 201 dgisselq
 
2069 209 dgisselq
                reg     r_ubreak;
2070
 
2071
                initial r_ubreak = 1'b0;
2072
                always @(posedge i_clk)
2073
                        if ((i_reset)||(w_release_from_interrupt))
2074
                                r_ubreak <= 1'b0;
2075
                        else if ((op_gie)&&(break_pending)&&(w_switch_to_interrupt))
2076
                                r_ubreak <= 1'b1;
2077
                        else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
2078
                                r_ubreak <= (ubreak)&&(wr_spreg_vl[`CPU_BREAK_BIT]);
2079
 
2080
                assign  trap = r_trap;
2081
                assign  ubreak = r_ubreak;
2082
 
2083
        end endgenerate
2084
 
2085
 
2086 65 dgisselq
        initial ill_err_i = 1'b0;
2087 36 dgisselq
        always @(posedge i_clk)
2088 209 dgisselq
                if (i_reset)
2089 65 dgisselq
                        ill_err_i <= 1'b0;
2090 132 dgisselq
                // Only the debug interface can clear this bit
2091 179 dgisselq
                else if ((dbgv)&&(wr_write_scc))
2092
                        ill_err_i <= (ill_err_i)&&(wr_spreg_vl[`CPU_ILL_BIT]);
2093 205 dgisselq
                else if ((alu_illegal)&&(!alu_gie)&&(!clear_pipeline))
2094 65 dgisselq
                        ill_err_i <= 1'b1;
2095 201 dgisselq
 
2096 209 dgisselq
        generate if (OPT_NO_USERMODE)
2097
        begin
2098 201 dgisselq
 
2099 209 dgisselq
                assign  ill_err_u = 1'b0;
2100 201 dgisselq
 
2101 209 dgisselq
        end else begin : SET_USER_ILLEGAL_INSN
2102
 
2103
                reg     r_ill_err_u;
2104
 
2105
                initial r_ill_err_u = 1'b0;
2106
                always @(posedge i_clk)
2107
                        // The bit is automatically cleared on release from interrupt
2108
                        // or reset
2109
                        if ((i_reset)||(w_release_from_interrupt))
2110
                                r_ill_err_u <= 1'b0;
2111
                        // If the supervisor (or debugger) writes to this
2112
                        // register, clearing the bit, then clear it
2113
                        else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
2114
                                r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[`CPU_ILL_BIT]));
2115
                        else if ((alu_illegal)&&(alu_gie)&&(!clear_pipeline))
2116
                                r_ill_err_u <= 1'b1;
2117
 
2118
                assign  ill_err_u = r_ill_err_u;
2119
 
2120
        end endgenerate
2121
 
2122 65 dgisselq
        // Supervisor/interrupt bus error flag -- this will crash the CPU if
2123
        // ever set.
2124
        initial ibus_err_flag = 1'b0;
2125 36 dgisselq
        always @(posedge i_clk)
2126 209 dgisselq
                if (i_reset)
2127 65 dgisselq
                        ibus_err_flag <= 1'b0;
2128 179 dgisselq
                else if ((dbgv)&&(wr_write_scc))
2129
                        ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
2130 205 dgisselq
                else if ((bus_err)&&(!alu_gie))
2131 65 dgisselq
                        ibus_err_flag <= 1'b1;
2132
        // User bus error flag -- if ever set, it will cause an interrupt to
2133 201 dgisselq
        // supervisor mode.
2134 209 dgisselq
        generate if (OPT_NO_USERMODE)
2135
        begin
2136 201 dgisselq
 
2137 209 dgisselq
                assign  ubus_err_flag = 1'b0;
2138 36 dgisselq
 
2139 209 dgisselq
        end else begin : SET_USER_BUSERR
2140 201 dgisselq
 
2141 209 dgisselq
                reg     r_ubus_err_flag;
2142
 
2143
                initial r_ubus_err_flag = 1'b0;
2144
                always @(posedge i_clk)
2145
                        if ((i_reset)||(w_release_from_interrupt))
2146
                                r_ubus_err_flag <= 1'b0;
2147
                        else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc))
2148
                                r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[`CPU_BUSERR_BIT]);
2149
                        else if ((bus_err)&&(alu_gie))
2150
                                r_ubus_err_flag <= 1'b1;
2151
 
2152
                assign  ubus_err_flag = r_ubus_err_flag;
2153
        end endgenerate
2154
 
2155
        generate if (IMPLEMENT_DIVIDE != 0)
2156
        begin : DIVERR
2157 69 dgisselq
                reg     r_idiv_err_flag, r_udiv_err_flag;
2158
 
2159
                // Supervisor/interrupt divide (by zero) error flag -- this will
2160
                // crash the CPU if ever set.  This bit is thus available for us
2161
                // to be able to tell if/why the CPU crashed.
2162
                initial r_idiv_err_flag = 1'b0;
2163
                always @(posedge i_clk)
2164 209 dgisselq
                        if (i_reset)
2165 69 dgisselq
                                r_idiv_err_flag <= 1'b0;
2166 179 dgisselq
                        else if ((dbgv)&&(wr_write_scc))
2167
                                r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
2168 205 dgisselq
                        else if ((div_error)&&(!alu_gie))
2169 69 dgisselq
                                r_idiv_err_flag <= 1'b1;
2170 201 dgisselq
 
2171
                assign  idiv_err_flag = r_idiv_err_flag;
2172 69 dgisselq
 
2173 209 dgisselq
                if (OPT_NO_USERMODE)
2174
                begin
2175
                        assign  udiv_err_flag = 1'b0;
2176
                end else begin
2177
 
2178
                        // User divide (by zero) error flag -- if ever set, it will
2179
                        // cause a sudden switch interrupt to supervisor mode.
2180
                        initial r_udiv_err_flag = 1'b0;
2181
                        always @(posedge i_clk)
2182
                                if ((i_reset)||(w_release_from_interrupt))
2183
                                        r_udiv_err_flag <= 1'b0;
2184
                                else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)
2185
                                                &&(wr_write_ucc))
2186
                                        r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[`CPU_DIVERR_BIT]);
2187
                                else if ((div_error)&&(alu_gie))
2188
                                        r_udiv_err_flag <= 1'b1;
2189
 
2190
                        assign  udiv_err_flag = r_udiv_err_flag;
2191
                end
2192 69 dgisselq
        end else begin
2193
                assign  idiv_err_flag = 1'b0;
2194
                assign  udiv_err_flag = 1'b0;
2195
        end endgenerate
2196
 
2197 209 dgisselq
        generate if (IMPLEMENT_FPU !=0)
2198
        begin : FPUERR
2199 69 dgisselq
                // Supervisor/interrupt floating point error flag -- this will
2200
                // crash the CPU if ever set.
2201
                reg             r_ifpu_err_flag, r_ufpu_err_flag;
2202
                initial r_ifpu_err_flag = 1'b0;
2203
                always @(posedge i_clk)
2204 209 dgisselq
                        if (i_reset)
2205 69 dgisselq
                                r_ifpu_err_flag <= 1'b0;
2206 179 dgisselq
                        else if ((dbgv)&&(wr_write_scc))
2207
                                r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
2208 205 dgisselq
                        else if ((fpu_error)&&(fpu_valid)&&(!alu_gie))
2209 69 dgisselq
                                r_ifpu_err_flag <= 1'b1;
2210
                // User floating point error flag -- if ever set, it will cause
2211 201 dgisselq
                // a sudden switch interrupt to supervisor mode.
2212 69 dgisselq
                initial r_ufpu_err_flag = 1'b0;
2213
                always @(posedge i_clk)
2214 209 dgisselq
                        if ((i_reset)&&(w_release_from_interrupt))
2215 69 dgisselq
                                r_ufpu_err_flag <= 1'b0;
2216 205 dgisselq
                        else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)
2217 179 dgisselq
                                        &&(wr_write_ucc))
2218
                                r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[`CPU_FPUERR_BIT]);
2219 69 dgisselq
                        else if ((fpu_error)&&(alu_gie)&&(fpu_valid))
2220
                                r_ufpu_err_flag <= 1'b1;
2221
 
2222
                assign  ifpu_err_flag = r_ifpu_err_flag;
2223
                assign  ufpu_err_flag = r_ufpu_err_flag;
2224
        end else begin
2225
                assign  ifpu_err_flag = 1'b0;
2226
                assign  ufpu_err_flag = 1'b0;
2227
        end endgenerate
2228
 
2229 209 dgisselq
        generate if (OPT_CIS)
2230
        begin : GEN_IHALT_PHASE
2231
                reg             r_ihalt_phase;
2232 69 dgisselq
 
2233 209 dgisselq
                initial r_ihalt_phase = 0;
2234
                always @(posedge i_clk)
2235
                        if (i_reset)
2236
                                r_ihalt_phase <= 1'b0;
2237
                        else if ((!alu_gie)&&(alu_pc_valid)&&(!clear_pipeline))
2238
                                r_ihalt_phase <= alu_phase;
2239 201 dgisselq
 
2240 209 dgisselq
                assign  ihalt_phase = r_ihalt_phase;
2241
        end else begin : GEN_IHALT_PHASE
2242 201 dgisselq
 
2243 209 dgisselq
                assign  ihalt_phase = 1'b0;
2244 201 dgisselq
 
2245 209 dgisselq
        end endgenerate
2246
 
2247
        generate if ((!OPT_CIS) || (OPT_NO_USERMODE))
2248
        begin : GEN_UHALT_PHASE
2249
 
2250
                assign  uhalt_phase = 1'b0;
2251
 
2252
        end else begin : GEN_UHALT_PHASE
2253
 
2254
                reg             r_uhalt_phase;
2255
 
2256
                initial r_uhalt_phase = 1'b0;
2257
                always @(posedge i_clk)
2258
                if ((i_reset)||(w_release_from_interrupt))
2259 179 dgisselq
                        r_uhalt_phase <= 1'b0;
2260
                else if ((alu_gie)&&(alu_pc_valid))
2261 69 dgisselq
                        r_uhalt_phase <= alu_phase;
2262 209 dgisselq
                else if ((!alu_gie)&&(wr_reg_ce)&&(wr_write_pc)
2263
                                &&(wr_reg_id[4]))
2264
                        r_uhalt_phase <= wr_spreg_vl[1];
2265 69 dgisselq
 
2266 209 dgisselq
                assign  uhalt_phase = r_uhalt_phase;
2267 69 dgisselq
 
2268 209 dgisselq
        end endgenerate
2269
 
2270 2 dgisselq
        //
2271
        // Write backs to the PC register, and general increments of it
2272
        //      We support two: upc and ipc.  If the instruction is normal,
2273
        // we increment upc, if interrupt level we increment ipc.  If
2274
        // the instruction writes the PC, we write whichever PC is appropriate.
2275
        //
2276
        // Do we need to all our partial results from the pipeline?
2277 205 dgisselq
        // What happens when the pipeline has gie and !gie instructions within
2278 2 dgisselq
        // it?  Do we clear both?  What if a gie instruction tries to clear
2279
        // a non-gie instruction?
2280 209 dgisselq
        generate if (OPT_NO_USERMODE)
2281
        begin
2282 201 dgisselq
 
2283 209 dgisselq
                assign  upc = {(AW+2){1'b0}};
2284
 
2285
        end else begin : SET_USER_PC
2286
 
2287
                reg     [(AW+1):0]       r_upc;
2288
 
2289
                always @(posedge i_clk)
2290
                        if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
2291
                                r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
2292
                        else if ((alu_gie)&&
2293
                                        (((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal))
2294
                                        ||(mem_pc_valid)))
2295
                                r_upc <= alu_pc;
2296
                assign  upc = r_upc;
2297
        end endgenerate
2298
 
2299
        initial ipc = { RESET_BUS_ADDRESS, 2'b00 };
2300 2 dgisselq
        always @(posedge i_clk)
2301 209 dgisselq
        if (i_reset)
2302
                ipc <= { RESET_BUS_ADDRESS, 2'b00 };
2303
        else if ((wr_reg_ce)&&(!wr_reg_id[4])&&(wr_write_pc))
2304
                ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
2305
        else if ((!alu_gie)&&(!alu_phase)&&
2306
                        (((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal))
2307
                        ||(mem_pc_valid)))
2308
                ipc <= alu_pc;
2309 2 dgisselq
 
2310 209 dgisselq
        initial pf_pc = { RESET_BUS_ADDRESS, 2'b00 };
2311 2 dgisselq
        always @(posedge i_clk)
2312 209 dgisselq
        if (i_reset)
2313
                pf_pc <= { RESET_BUS_ADDRESS, 2'b00 };
2314
        else if ((dbg_clear_pipe)&&(wr_reg_ce)&&(wr_write_pc))
2315
                pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
2316
        else if ((w_switch_to_interrupt)
2317
                        ||((!gie)&&((w_clear_icache)||(dbg_clear_pipe))))
2318
                pf_pc <= { ipc[(AW+1):2], 2'b00 };
2319
        else if ((w_release_from_interrupt)||((gie)&&((w_clear_icache)||(dbg_clear_pipe))))
2320
                pf_pc <= { upc[(AW+1):2], 2'b00 };
2321
        else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
2322
                pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 };
2323
        else if ((dcd_early_branch_stb)&&(!clear_pipeline))
2324
                pf_pc <= { dcd_branch_pc[AW+1:2] + 1'b1, 2'b00 };
2325
        else if ((new_pc)||((!pf_stalled)&&(pf_valid)))
2326
                pf_pc <= { pf_pc[(AW+1):2] + 1'b1, 2'b00 };
2327 2 dgisselq
 
2328 209 dgisselq
        initial last_write_to_cc = 1'b0;
2329 2 dgisselq
        always @(posedge i_clk)
2330 209 dgisselq
        if (i_reset)
2331
                last_write_to_cc <= 1'b0;
2332
        else
2333
                last_write_to_cc <= (wr_reg_ce)&&(wr_write_cc);
2334
        assign  cc_write_hold = (wr_reg_ce)&&(wr_write_cc)||(last_write_to_cc);
2335 2 dgisselq
 
2336 205 dgisselq
        // If we aren't pipelined, or equivalently if we have no cache, these
2337
        // instructions will get quietly (or not so quietly) ignored by the
2338
        // optimizer.
2339 179 dgisselq
        initial r_clear_icache = 1'b1;
2340
        always @(posedge i_clk)
2341 209 dgisselq
        if (i_reset)
2342
                r_clear_icache <= 1'b0;
2343
        else if ((r_halted)&&(i_clear_pf_cache))
2344
                r_clear_icache <= 1'b1;
2345
        else if ((wr_reg_ce)&&(wr_write_scc))
2346
                r_clear_icache <=  wr_spreg_vl[`CPU_CLRCACHE_BIT];
2347
        else
2348
                r_clear_icache <= 1'b0;
2349 179 dgisselq
        assign  w_clear_icache = r_clear_icache;
2350
 
2351 201 dgisselq
        initial new_pc = 1'b1;
2352
        always @(posedge i_clk)
2353 209 dgisselq
                if ((i_reset)||(w_clear_icache)||(dbg_clear_pipe))
2354 201 dgisselq
                        new_pc <= 1'b1;
2355
                else if (w_switch_to_interrupt)
2356
                        new_pc <= 1'b1;
2357
                else if (w_release_from_interrupt)
2358
                        new_pc <= 1'b1;
2359 209 dgisselq
                // else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
2360
                // Can't check for *this* PC here, since a user PC might be
2361
                // loaded in the pipeline and hence rewritten.  Thus, while
2362
                // I hate to do it, we'll need to clear the pipeline on any
2363
                // PC write
2364
                else if ((wr_reg_ce)&&(alu_gie == wr_reg_id[4])&&(wr_write_pc))
2365 201 dgisselq
                        new_pc <= 1'b1;
2366
                else
2367
                        new_pc <= 1'b0;
2368
 
2369 2 dgisselq
        //
2370 209 dgisselq
        // The debug write-back interface
2371
        //{{{
2372 201 dgisselq
        wire    [31:0]   w_debug_pc;
2373 209 dgisselq
        generate if (OPT_NO_USERMODE)
2374
        begin
2375
 
2376
                assign  w_debug_pc[(AW+1):0] = { ipc, 2'b00 };
2377
        end else begin
2378
 
2379
                assign  w_debug_pc[(AW+1):0] = { (i_dbg_reg[4])
2380 201 dgisselq
                                ? { upc[(AW+1):2], uhalt_phase, 1'b0 }
2381
                                : { ipc[(AW+1):2], ihalt_phase, 1'b0 } };
2382 209 dgisselq
        end endgenerate
2383
 
2384 56 dgisselq
        generate
2385 201 dgisselq
        if (AW<30)
2386
                assign  w_debug_pc[31:(AW+2)] = 0;
2387
        endgenerate
2388
 
2389 209 dgisselq
        generate if (OPT_NO_USERMODE)
2390
        begin : NO_USER_SETDBG
2391
 
2392
                always @(posedge i_clk)
2393 2 dgisselq
                begin
2394 209 dgisselq
                        o_dbg_reg <= regset[i_dbg_reg[3:0]];
2395
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
2396
                                o_dbg_reg <= w_debug_pc;
2397
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
2398
                        begin
2399
                                o_dbg_reg[14:0] <= w_iflags;
2400
                                o_dbg_reg[15] <= 1'b0;
2401
                                o_dbg_reg[31:23] <= w_cpu_info;
2402
                                o_dbg_reg[`CPU_GIE_BIT] <= gie;
2403
                        end
2404 2 dgisselq
                end
2405 209 dgisselq
        end else begin : SETDBG
2406
 
2407
`ifdef  NO_DISTRIBUTED_RAM
2408
                reg     [31:0]   pre_dbg_reg;
2409
                always @(posedge i_clk)
2410
                        pre_dbg_reg <= regset[i_dbg_reg];
2411
 
2412
                always @(posedge i_clk)
2413
                begin
2414
                        o_dbg_reg <= pre_dbg_reg;
2415
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
2416
                                o_dbg_reg <= w_debug_pc;
2417
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
2418
                        begin
2419
                                o_dbg_reg[14:0] <= (i_dbg_reg[4