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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipcpu.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This is the top level module holding the core of the Zip CPU
8
//              together.  The Zip CPU is designed to be as simple as possible.
9
//              The instruction set is about as RISC as you can get, there are
10
//              only 16 instruction types supported (of which one isn't yet
11
//              supported ...)  Please see the accompanying iset.html file
12
//              for a description of these instructions.
13
//
14
//              All instructions are 32-bits wide.  All bus accesses, both
15
//              address and data, are 32-bits over a wishbone bus.
16
//
17
//      The Zip CPU is fully pipelined with the following pipeline stages:
18
//
19
//              1. Prefetch, returns the instruction from memory.  On the
20
//              Basys board that I'm working on, one instruction may be
21
//              issued every 20 clocks or so, unless and until I implement a
22
//              cache or local memory.
23
//
24
//              2. Instruction Decode
25
//
26
//              3. Read Operands
27
//
28
//              4. Apply Instruction
29
//
30
//              4. Write-back Results
31
//
32
//      A lot of difficult work has been placed into the pipeline stall
33
//      handling.  My original proposal was not to allow pipeline stalls at all.
34
//      The idea would be that the CPU would just run every clock and whatever
35
//      stalled answer took place would just get fixed a clock or two later,
36
//      meaning that the compiler could just schedule everything out.
37
//      This idea died at the memory interface, which can take a variable
38
//      amount of time to read or write any value, thus the whole CPU needed
39
//      to stall on a stalled memory access.
40
//
41
//      My next idea was to just let things complete.  I.e., once an instrution
42
//      starts, it continues to completion no matter what and we go on.  This
43
//      failed at writing the PC.  If the PC gets written in something such as
44
//      a MOV PC,PC+5 instruction, 3 (or however long the pipeline is) clocks
45
//      later, if whether or not something happens in those clocks depends
46
//      upon the instruction fetch filling the pipeline, then the CPU has a
47
//      non-deterministic behavior.
48
//
49
//      This leads to two possibilities: either *everything* stalls upon a 
50
//      stall condition, or partial results need to be destroyed before
51
//      they are written.  This is made more difficult by the fact that
52
//      once a command is written to the memory unit, whether it be a
53
//      read or a write, there is no undoing it--since peripherals on the
54
//      bus may act upon the answer with whatever side effects they might
55
//      have.  (For example, writing a '1' to the interrupt register will
56
//      clear certain interrupts ...)  Further, since the memory ops depend
57
//      upon conditions, the we'll need to wait for the condition codes to
58
//      be available before executing a memory op.  Thus, memory ops can 
59
//      proceed without stalling whenever either the previous instruction
60
//      doesn't write the flags register, or when the memory instruction doesn't
61
//      depend upon the flags register.
62
//
63
//      The other possibility is that we leave independent instruction
64
//      execution behind, so that the pipeline is always full and stalls,
65
//      or moves forward, together on every clock.
66
//
67
//      For now, we pick the first approach: independent instruction execution.
68
//      Thus, if stage 2 stalls, stages 3-5 may still complete the instructions
69
//      in their pipeline.  This leaves another problem: what happens on a
70
//      MOV -1+PC,PC instruction?  There will be four instructions behind this
71
//      one (or is it five?) that will need to be 'cancelled'.  So here's
72
//      the plan: Anything can be cancelled before the ALU/MEM stage,
73
//      since memory ops cannot be canceled after being issued.  Thus, the
74
//      ALU/MEM stage must stall if any prior instruction is going to write
75
//      the PC register (i.e. JMP).
76
//
77
//      Further, let's define a "STALL" as a reason to not execute a stage
78
//      due to some condition at or beyond the stage, and let's define
79
//      a VALID flag to mean that this stage has completed.  Thus, the clock
80
//      enable for a stage is (STG[n-1]VALID)&&((~STG[n]VALID)||(~STG[n]STALL)).
81
//      The ALU/MEM stages will also depend upon a master clock enable
82
//      (~SLEEP) condition as well.
83
//
84
//
85
//
86
// Creator:     Dan Gisselquist, Ph.D.
87
//              Gisselquist Tecnology, LLC
88
//
89
///////////////////////////////////////////////////////////////////////////////
90
//
91
// Copyright (C) 2015, Gisselquist Technology, LLC
92
//
93
// This program is free software (firmware): you can redistribute it and/or
94
// modify it under the terms of  the GNU General Public License as published
95
// by the Free Software Foundation, either version 3 of the License, or (at
96
// your option) any later version.
97
//
98
// This program is distributed in the hope that it will be useful, but WITHOUT
99
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
100
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
101
// for more details.
102
//
103
// License:     GPL, v3, as defined and found on www.gnu.org,
104
//              http://www.gnu.org/licenses/gpl.html
105
//
106
//
107
///////////////////////////////////////////////////////////////////////////////
108
//
109 25 dgisselq
`define CPU_CC_REG      4'he
110 2 dgisselq
`define CPU_PC_REG      4'hf
111 25 dgisselq
`define CPU_TRAP_BIT    9
112 2 dgisselq
`define CPU_BREAK_BIT   7
113
`define CPU_STEP_BIT    6
114
`define CPU_GIE_BIT     5
115
`define CPU_SLEEP_BIT   4
116
module  zipcpu(i_clk, i_rst, i_interrupt,
117
                // Debug interface
118 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
119
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
120 2 dgisselq
                        o_break,
121
                // CPU interface to the wishbone bus
122
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
123
                        i_wb_ack, i_wb_stall, i_wb_data,
124
                // Accounting/CPU usage interface
125 9 dgisselq
                o_op_stall, o_pf_stall, o_i_count);
126 2 dgisselq
        parameter       RESET_ADDRESS=32'h0100000;
127
        input                   i_clk, i_rst, i_interrupt;
128
        // Debug interface -- inputs
129 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
130 2 dgisselq
        input           [4:0]    i_dbg_reg;
131
        input                   i_dbg_we;
132
        input           [31:0]   i_dbg_data;
133
        // Debug interface -- outputs
134
        output  reg             o_dbg_stall;
135
        output  reg     [31:0]   o_dbg_reg;
136 25 dgisselq
        output  reg     [1:0]    o_dbg_cc;
137 2 dgisselq
        output  wire            o_break;
138
        // Wishbone interface -- outputs
139
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
140
        output  wire    [31:0]   o_wb_addr, o_wb_data;
141
        // Wishbone interface -- inputs
142
        input                   i_wb_ack, i_wb_stall;
143
        input           [31:0]   i_wb_data;
144
        // Accounting outputs ... to help us count stalls and usage
145 9 dgisselq
        output  wire            o_op_stall;
146 2 dgisselq
        output  wire            o_pf_stall;
147 9 dgisselq
        output  wire            o_i_count;
148 2 dgisselq
 
149 25 dgisselq
 
150 2 dgisselq
        // Registers
151
        reg     [31:0]   regset [0:31];
152 9 dgisselq
 
153
        // Condition codes
154 25 dgisselq
        reg     [3:0]    flags, iflags;  // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
155
        wire    [9:0]    w_uflags, w_iflags;
156
        reg             trap, break_en, step, gie, sleep;
157 2 dgisselq
 
158 9 dgisselq
        // The master chip enable
159
        wire            master_ce;
160 2 dgisselq
 
161
        //
162
        //
163
        //      PIPELINE STAGE #1 :: Prefetch
164
        //              Variable declarations
165
        //
166 9 dgisselq
        reg     [31:0]   pf_pc;
167 25 dgisselq
        reg             new_pc, op_break;
168 18 dgisselq
        wire    clear_pipeline;
169 25 dgisselq
        assign  clear_pipeline = new_pc || i_clear_pf_cache || op_break;
170 9 dgisselq
 
171
        wire            dcd_stalled;
172 2 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall;
173
        wire    [31:0]   pf_addr, pf_data;
174
        wire    [31:0]   instruction, instruction_pc;
175
        wire    pf_valid, instruction_gie;
176
 
177
        //
178
        //
179
        //      PIPELINE STAGE #2 :: Instruction Decode
180
        //              Variable declarations
181
        //
182
        //
183 25 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
184 2 dgisselq
        wire            op_stall, dcd_ce;
185
        reg     [3:0]    dcdOp;
186
        reg     [4:0]    dcdA, dcdB;
187 25 dgisselq
        reg             dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
188 2 dgisselq
        reg     [3:0]    dcdF;
189
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
190
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
191
        reg     [31:0]   dcd_pc;
192
        reg     [23:0]   r_dcdI;
193
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
194
 
195
 
196
 
197
        //
198
        //
199
        //      PIPELINE STAGE #3 :: Read Operands
200
        //              Variable declarations
201
        //
202
        //
203
        //
204
        // Now, let's read our operands
205
        reg     [4:0]    alu_reg;
206
        reg     [3:0]    opn;
207
        reg     [4:0]    opR;
208
        reg     [31:0]   r_opA, r_opB, op_pc;
209 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
210 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
211 25 dgisselq
        reg             opR_wr, opR_cc, opF_wr, op_gie,
212 2 dgisselq
                        opA_rd, opB_rd;
213 25 dgisselq
        wire    [9:0]    opFl;
214 3 dgisselq
        reg     [6:0]    r_opF;
215 2 dgisselq
        wire    [8:0]    opF;
216
        wire            op_ce;
217
 
218
 
219
 
220
        //
221
        //
222
        //      PIPELINE STAGE #4 :: ALU / Memory
223
        //              Variable declarations
224
        //
225
        //
226
        reg     [31:0]   alu_pc;
227
        reg             alu_pc_valid;;
228
        wire            alu_ce, alu_stall;
229
        wire    [31:0]   alu_result;
230
        wire    [3:0]    alu_flags;
231
        wire            alu_valid;
232
        wire            set_cond;
233
        reg             alu_wr, alF_wr, alu_gie;
234
 
235
 
236
 
237
        wire    mem_ce, mem_stalled;
238
        wire    mem_valid, mem_ack, mem_stall,
239
                mem_cyc, mem_stb, mem_we;
240 9 dgisselq
        wire    [4:0]    mem_wreg;
241
 
242
        wire            mem_busy, mem_rdbusy;
243 2 dgisselq
        wire    [31:0]   mem_addr, mem_data, mem_result;
244
 
245
 
246
 
247
        //
248
        //
249
        //      PIPELINE STAGE #5 :: Write-back
250
        //              Variable declarations
251
        //
252 25 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
253 2 dgisselq
        wire    [4:0]    wr_reg_id;
254
        wire    [31:0]   wr_reg_vl;
255
        wire    w_switch_to_interrupt, w_release_from_interrupt;
256
        reg     [31:0]   upc, ipc;
257
 
258
 
259
 
260
        //
261
        //      MASTER: clock enable.
262
        //
263
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep)&&(~mem_rdbusy);
264
 
265
 
266
        //
267
        //      PIPELINE STAGE #1 :: Prefetch
268
        //              Calculate stall conditions
269
 
270
        //
271
        //      PIPELINE STAGE #2 :: Instruction Decode
272
        //              Calculate stall conditions
273
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled);
274
        assign          dcd_stalled = (dcdvalid)&&(
275
                                        (op_stall)
276
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
277 25 dgisselq
                                        ||((opvalid)&&((op_wr_pc)||(opR_cc))));
278 2 dgisselq
        //
279
        //      PIPELINE STAGE #3 :: Read Operands
280
        //              Calculate stall conditions
281 25 dgisselq
        assign  op_stall = ((mem_stalled)&&(opvalid_mem))
282
                                ||((alu_stall)&&(opvalid_alu));
283 2 dgisselq
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
284
 
285
        //
286
        //      PIPELINE STAGE #4 :: ALU / Memory
287
        //              Calculate stall conditions
288 25 dgisselq
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu))
289
                        ||((opvalid)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
290
                                &&(wr_write_pc)||(wr_write_cc));
291
        assign  alu_ce = (master_ce)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
292 2 dgisselq
        //
293 25 dgisselq
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
294
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
295 2 dgisselq
                                (~master_ce)
296
                                // Stall waiting for flags to be valid
297
                                ||((~opF[8])&&(
298 25 dgisselq
                                        ((wr_reg_ce)&&(wr_reg_id[4:0] == {op_gie,`CPU_CC_REG}))
299 2 dgisselq
                                        // Do I need this last condition?
300 25 dgisselq
                                        ||(wr_flags_ce)))
301 2 dgisselq
                                // Or waiting for a write to the PC register
302 25 dgisselq
                                // Or CC register, since that can change the
303
                                //  PC as well
304
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
305 2 dgisselq
 
306
 
307
        //
308
        //
309
        //      PIPELINE STAGE #1 :: Prefetch
310
        //
311
        //
312
`ifdef  SINGLE_FETCH
313 9 dgisselq
        wire            pf_ce;
314
 
315
        assign          pf_ce = (~dcd_stalled);
316 2 dgisselq
        prefetch        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
317
                                instruction, instruction_pc, instruction_gie,
318
                                        pf_valid,
319
                                pf_cyc, pf_stb, pf_we, pf_addr,
320
                                        pf_data,
321
                                pf_ack, pf_stall, i_wb_data);
322
`else // Pipe fetch
323 3 dgisselq
        pipefetch       #(RESET_ADDRESS)
324 18 dgisselq
                        pf(i_clk, i_rst, new_pc, i_clear_pf_cache, ~dcd_stalled, pf_pc,
325 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
326
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
327 3 dgisselq
                                        pf_ack, pf_stall, i_wb_data,
328
                                mem_cyc);
329 2 dgisselq
        assign  instruction_gie = gie;
330
`endif
331
 
332
        always @(posedge i_clk)
333
                if (i_rst)
334
                        dcdvalid <= 1'b0;
335
                else if (dcd_ce)
336 18 dgisselq
                        dcdvalid <= (~clear_pipeline);
337
                else if ((~dcd_stalled)||(clear_pipeline))
338 2 dgisselq
                        dcdvalid <= 1'b0;
339
 
340
        always @(posedge i_clk)
341
                if (dcd_ce)
342
                begin
343
                        dcd_pc <= instruction_pc+1;
344
 
345
                        // Record what operation we are doing
346
                        dcdOp <= instruction[31:28];
347
 
348
                        // Default values
349
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
350
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
351 25 dgisselq
                        dcdA_cc <=  (instruction[27:24] == `CPU_CC_REG);
352
                        dcdB_cc <=  (instruction[19:16] == `CPU_CC_REG);
353
                        dcdA_pc <=  (instruction[27:24] == `CPU_PC_REG);
354
                        dcdB_pc <=  (instruction[19:16] == `CPU_PC_REG);
355 2 dgisselq
                        dcdM    <= 1'b0;
356
                        dcdF_wr <= 1'b1;
357
 
358
                        // Set the condition under which we do this operation
359
                        // The top four bits are a mask, the bottom four the
360
                        // value the flags must equal once anded with the mask
361
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
362
                        casez(instruction[31:28])
363
                        4'h2: begin // Move instruction
364
                                if (~instruction_gie)
365
                                begin
366
                                        dcdA[4] <= instruction[20];
367
                                        dcdB[4] <= instruction[15];
368
                                end
369
                                dcdA_wr <= 1'b1;
370
                                dcdA_rd <= 1'b0;
371
                                dcdB_rd <= 1'b1;
372
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
373
                                dcdF_wr <= 1'b0; // Don't write flags
374
                                end
375
                        4'h3: begin // Load immediate
376
                                dcdA_wr <= 1'b1;
377
                                dcdA_rd <= 1'b0;
378
                                dcdB_rd <= 1'b0;
379
                                r_dcdI <= { instruction[23:0] };
380
                                dcdF_wr <= 1'b0; // Don't write flags
381
                                dcdF    <= 4'h8; // This is unconditional
382
                                dcdOp <= 4'h2;
383
                                end
384 25 dgisselq
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
385
                                // Don't write flags except for multiplies
386
                                dcdF_wr <= (instruction[27:25] != 3'h7);
387 2 dgisselq
                                r_dcdI <= { 8'h00, instruction[15:0] };
388
                                if (instruction[27:24] == 4'he)
389
                                begin
390
                                        // NOOP instruction
391
                                        dcdA_wr <= 1'b0;
392
                                        dcdA_rd <= 1'b0;
393
                                        dcdB_rd <= 1'b0;
394
                                        dcdOp <= 4'h2;
395
                                end else if (instruction[27:24] == 4'hf)
396
                                begin // Load partial immediate(s)
397
                                        dcdA_wr <= 1'b1;
398
                                        dcdA_rd <= 1'b1;
399
                                        dcdB_rd <= 1'b0;
400
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
401 25 dgisselq
                                        dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
402
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
403 2 dgisselq
                                        dcdOp <= { 3'h3, instruction[20] };
404
                                end else begin
405 25 dgisselq
                                        // Actual multiply instruction
406
                                        r_dcdI <= { 8'h00, instruction[15:0] };
407
                                        dcdA_rd <= 1'b1;
408
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
409
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
410 2 dgisselq
                                end end
411
                        4'b011?: begin // Load/Store
412
                                dcdF_wr <= 1'b0; // Don't write flags
413
                                dcdA_wr <= (~instruction[28]); // Write on loads
414
                                dcdA_rd <= (instruction[28]); // Read on stores
415
                                dcdB_rd <= instruction[20];
416
                                if (instruction[20])
417
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
418
                                else
419
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
420
                                dcdM <= 1'b1; // Memory operation
421
                                end
422
                        default: begin
423
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
424
                                dcdA_rd <= 1'b1;
425
                                dcdB_rd <= instruction[20];
426
                                if (instruction[20])
427
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
428
                                else
429
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
430
                                end
431
                        endcase
432
 
433
 
434
                        dcd_gie <= instruction_gie;
435
                end
436 25 dgisselq
        always @(posedge i_clk)
437
                if (dcd_ce)
438
                        dcd_break <= (instruction[31:0] == 32'h4e000001);
439
                else
440
                        dcd_break <= 1'b0;
441 2 dgisselq
 
442
 
443
        //
444
        //
445
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
446
        //
447
        //
448 25 dgisselq
        assign  w_opA = regset[dcdA];
449
        assign  w_opB = regset[dcdB];
450 2 dgisselq
        always @(posedge i_clk)
451
                if (op_ce) // &&(dcdvalid))
452
                begin
453
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
454
                                r_opA <= wr_reg_vl;
455 25 dgisselq
                        else if ((dcdA_pc)&&(dcdA[4] == dcd_gie))
456 2 dgisselq
                                r_opA <= dcd_pc;
457 25 dgisselq
                        else if (dcdA_pc)
458
                                r_opA <= upc;
459
                        else if (dcdA_cc)
460
                                r_opA <= { w_opA[31:10], (dcd_gie)?w_uflags:w_iflags };
461 2 dgisselq
                        else
462 25 dgisselq
                                r_opA <= w_opA;
463 2 dgisselq
                end
464
        wire    [31:0]   dcdI;
465
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
466
        always @(posedge i_clk)
467
                if (op_ce) // &&(dcdvalid))
468
                begin
469
                        if (~dcdB_rd)
470
                                r_opB <= dcdI;
471
                        else if ((wr_reg_ce)&&(wr_reg_id == dcdB))
472
                                r_opB <= wr_reg_vl + dcdI;
473 25 dgisselq
                        else if ((dcdB_pc)&&(dcdB[4] == dcd_gie))
474 2 dgisselq
                                r_opB <= dcd_pc + dcdI;
475 25 dgisselq
                        else if (dcdB_pc) // & dcdB[4] != dcd_gie thus is user
476
                                r_opB <= upc + dcdI;
477
                        else if (dcdB_cc)
478
                                r_opB <= { w_opB[31:10], (dcd_gie)?w_uflags:w_iflags} + dcdI;
479 2 dgisselq
                        else
480
                                r_opB <= regset[dcdB] + dcdI;
481
                end
482
 
483
        // The logic here has become more complex than it should be, no thanks
484
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
485
        // be two sets of four bits: the top bits specify what bits matter, the
486
        // bottom specify what those top bits must equal.  However, two of
487
        // conditions check whether bits are on, and those are the only two
488
        // conditions checking those bits.  Therefore, Vivado complains that
489
        // these two bits are redundant.  Hence the convoluted expression
490
        // below, arriving at what we finally want in the (now wire net)
491
        // opF.
492
        always @(posedge i_clk)
493
                if (op_ce)
494
                begin // Set the flag condition codes
495
                        case(dcdF[2:0])
496
                        3'h0:   r_opF <= 7'h80; // Always
497
                        3'h1:   r_opF <= 7'h11; // Z
498
                        3'h2:   r_opF <= 7'h10; // NE
499
                        3'h3:   r_opF <= 7'h20; // GE (!N)
500
                        3'h4:   r_opF <= 7'h30; // GT (!N&!Z)
501
                        3'h5:   r_opF <= 7'h24; // LT
502
                        3'h6:   r_opF <= 7'h02; // C
503
                        3'h7:   r_opF <= 7'h08; // V
504
                        endcase
505
                end
506
        assign  opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
507
 
508
        always @(posedge i_clk)
509
                if (i_rst)
510 25 dgisselq
                begin
511
                        opvalid     <= 1'b0;
512
                        opvalid_alu <= 1'b0;
513
                        opvalid_mem <= 1'b0;
514
                end else if (op_ce)
515
                begin
516 2 dgisselq
                        // Do we have a valid instruction?
517
                        //   The decoder may vote to stall one of its
518
                        //   instructions based upon something we currently
519
                        //   have in our queue.  This instruction must then
520
                        //   move forward, and get a stall cycle inserted.
521
                        //   Hence, the test on dcd_stalled here.  If we must
522
                        //   wait until our operands are valid, then we aren't
523
                        //   valid yet until then.
524 18 dgisselq
                        opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
525 25 dgisselq
                        opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
526
                        opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
527
                end else if ((~op_stall)||(clear_pipeline))
528
                begin
529
                        opvalid     <= 1'b0;
530
                        opvalid_alu <= 1'b0;
531
                        opvalid_mem <= 1'b0;
532
                end
533 2 dgisselq
 
534
        // Here's part of our debug interface.  When we recognize a break
535
        // instruction, we set the op_break flag.  That'll prevent this
536
        // instruction from entering the ALU, and cause an interrupt before
537
        // this instruction.  Thus, returning to this code will cause the
538
        // break to repeat and continue upon return.  To get out of this
539
        // condition, replace the break instruction with what it is supposed
540
        // to be, step through it, and then replace it back.  In this fashion,
541
        // a debugger can step through code.
542 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
543
        initial op_break = 1'b0;
544 2 dgisselq
        always @(posedge i_clk)
545 25 dgisselq
                if (i_rst)      op_break <= 1'b0;
546
                else if (op_ce) op_break <= (dcd_break);
547
                else if ((clear_pipeline)||(~opvalid))
548
                                op_break <= 1'b0;
549 2 dgisselq
 
550
        always @(posedge i_clk)
551
                if (op_ce)
552
                begin
553
                        opn    <= dcdOp;        // Which ALU operation?
554 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
555 2 dgisselq
                        // Will we write the flags/CC Register with our result?
556 25 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
557 2 dgisselq
                        // Will we be writing our results into a register?
558
                        opR_wr <= dcdA_wr;
559
                        // What register will these results be written into?
560
                        opR    <= dcdA;
561 25 dgisselq
                        opR_cc <= (dcdA_wr)&&(dcdA_cc);
562 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
563
                        op_gie <= dcd_gie;
564
 
565
                        // We're not done with these yet--we still need them
566
                        // for the unclocked assign.  We need the unclocked
567
                        // assign so that there's no wait state between an
568
                        // ALU or memory result and the next register that may
569
                        // use that value.
570
                        opA_rd <= dcdA_rd;
571
                        opB_rd <= dcdB_rd;
572
                        op_pc  <= dcd_pc;
573
                        //
574 25 dgisselq
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc));
575 2 dgisselq
                end
576
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
577
 
578
        // This is tricky.  First, the PC and Flags registers aren't kept in
579
        // register set but in special registers of their own.  So step one
580
        // is to select the right register.  Step to is to replace that
581
        // register with the results of an ALU or memory operation, if such
582
        // results are now available.  Otherwise, we'd need to insert a wait
583
        // state of some type.
584
        //
585
        // The alternative approach would be to define some sort of
586
        // op_stall wire, which would stall any upstream stage.
587
        // We'll create a flag here to start our coordination.  Once we
588
        // define this flag to something other than just plain zero, then
589
        // the stalls will already be in place.
590 25 dgisselq
`define DONT_STALL_ON_OPA
591
`ifdef  DONT_STALL_ON_OPA
592
        reg     opA_alu;
593
        always @(posedge i_clk)
594
                if (op_ce)
595
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(dcdA_rd);
596
        assign  opA = (opA_alu) ? alu_result : r_opA;
597
`else
598
        assign  opA = r_opA;
599
`endif
600
 
601
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
602
`define DONT_STALL_ON_OPB
603
`ifdef  DONT_STALL_ON_OPB
604
                // Skip the requirement on writing back opA
605
                // Stall on memory, since we'll always need to stall for a 
606
                // memory access anyway
607
                                ((opvalid_mem)&&(opR_wr)&&(opR == dcdA))||
608
`else
609
                                ((opvalid)&&(opR_wr)&&(opR == dcdA))||
610
`endif
611
                                        ((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA)));
612
`ifdef  DONT_STALL_ON_OPB
613
        reg     opB_alu;
614
        always @(posedge i_clk)
615
                if (op_ce)
616
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0);
617
        assign  opB = (opB_alu) ? alu_result : r_opB;
618
`else
619
        assign  opB = r_opB;
620
`endif
621
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
622
                                ((opvalid)&&(opR_wr)&&(opR == dcdB)
623
`ifdef  DONT_STALL_ON_OPB
624
                                        &&((opvalid_mem)||(dcdI != 0))
625
`endif
626
                                )||
627
                                ((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB)));
628
        assign  dcdF_stall = (dcdvalid)&&(
629
                                (((~dcdF[3]) ||(dcdA_cc) ||(dcdB_cc))
630
                                        &&(opvalid)&&((opR_cc)||(opF_wr)))
631 2 dgisselq
                        ||((dcdF[3])&&(dcdM)&&(opvalid)&&(opF_wr)));
632
        //
633
        //
634
        //      PIPELINE STAGE #4 :: Apply Instruction
635
        //
636
        //
637
        cpuops  doalu(i_clk, i_rst, alu_ce,
638 25 dgisselq
                        (opvalid_alu), opn, opA, opB,
639 2 dgisselq
                        alu_result, alu_flags, alu_valid);
640
 
641
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
642
        initial alF_wr   = 1'b0;
643
        initial alu_wr   = 1'b0;
644
        always @(posedge i_clk)
645
                if (i_rst)
646
                begin
647
                        alu_wr   <= 1'b0;
648
                        alF_wr   <= 1'b0;
649
                end else if (alu_ce)
650
                begin
651
                        alu_reg <= opR;
652
                        alu_wr  <= (opR_wr)&&(set_cond);
653
                        alF_wr  <= (opF_wr)&&(set_cond);
654
                end else begin
655
                        // These are strobe signals, so clear them if not
656
                        // set for any particular clock
657
                        alu_wr <= 1'b0;
658
                        alF_wr <= 1'b0;
659
                end
660
        always @(posedge i_clk)
661
                if ((alu_ce)||(mem_ce))
662
                        alu_gie  <= op_gie;
663
        always @(posedge i_clk)
664
                if ((alu_ce)||(mem_ce))
665
                        alu_pc  <= op_pc;
666
        initial alu_pc_valid = 1'b0;
667
        always @(posedge i_clk)
668 18 dgisselq
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(opvalid)&&(~clear_pipeline)
669 25 dgisselq
                                        &&((opvalid_alu)||(~mem_stalled));
670 2 dgisselq
 
671
        memops  domem(i_clk, i_rst, mem_ce,
672
                                (opn[0]), opB, opA, opR,
673
                                mem_busy, mem_valid, mem_wreg, mem_result,
674
                        mem_cyc, mem_stb, mem_we, mem_addr, mem_data,
675
                                mem_ack, mem_stall, i_wb_data);
676
        assign  mem_rdbusy = ((mem_cyc)&&(~mem_we));
677
 
678
        // Either the prefetch or the instruction gets the memory bus, but 
679
        // never both.
680
        wbarbiter       #(32,32) pformem(i_clk, i_rst,
681
                // Prefetch access to the arbiter
682
                pf_addr, pf_data, pf_we, pf_stb, pf_cyc, pf_ack, pf_stall,
683
                // Memory access to the arbiter
684
                mem_addr, mem_data, mem_we, mem_stb, mem_cyc, mem_ack, mem_stall,
685
                // Common wires, in and out, of the arbiter
686
                o_wb_addr, o_wb_data, o_wb_we, o_wb_stb, o_wb_cyc, i_wb_ack,
687
                        i_wb_stall);
688
 
689
        //
690
        //
691
        //      PIPELINE STAGE #5 :: Write-back results
692
        //
693
        //
694
        // This stage is not allowed to stall.  If results are ready to be
695
        // written back, they are written back at all cost.  Sleepy CPU's
696
        // won't prevent write back, nor debug modes, halting the CPU, nor
697
        // anything else.  Indeed, the (master_ce) bit is only as relevant
698
        // as knowinig something is available for writeback.
699
 
700
        //
701
        // Write back to our generic register set ...
702
        // When shall we write back?  On one of two conditions
703
        //      Note that the flags needed to be checked before issuing the
704
        //      bus instruction, so they don't need to be checked here.
705
        //      Further, alu_wr includes (set_cond), so we don't need to
706
        //      check for that here either.
707
        assign  wr_reg_ce = ((alu_wr)&&(alu_valid))||(mem_valid);
708
        // Which register shall be written?
709
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
710 25 dgisselq
        // Are we writing to the CC register?
711
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
712 2 dgisselq
        // Are we writing to the PC?
713
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
714
        // What value to write?
715
        assign  wr_reg_vl = (alu_wr)?alu_result:mem_result;
716
        always @(posedge i_clk)
717
                if (wr_reg_ce)
718
                        regset[wr_reg_id] <= wr_reg_vl;
719 18 dgisselq
                else if ((i_halt)&&(i_dbg_we))
720
                        regset[i_dbg_reg] <= i_dbg_data[31:0];
721 2 dgisselq
 
722
        //
723
        // Write back to the condition codes/flags register ...
724
        // When shall we write to our flags register?  alF_wr already
725
        // includes the set condition ...
726
        assign  wr_flags_ce = (alF_wr)&&(alu_valid);
727 25 dgisselq
        assign  w_uflags = { trap, 1'b0, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
728
        assign  w_iflags = { trap, 1'b0, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
729 2 dgisselq
        // What value to write?
730
        always @(posedge i_clk)
731
                // If explicitly writing the register itself
732 25 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
733 2 dgisselq
                        flags <= wr_reg_vl[3:0];
734
                // Otherwise if we're setting the flags from an ALU operation
735
                else if ((wr_flags_ce)&&(alu_gie))
736
                        flags <= alu_flags;
737
                else if ((i_halt)&&(i_dbg_we)
738
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
739
                        flags <= i_dbg_data[3:0];
740
 
741
        always @(posedge i_clk)
742 25 dgisselq
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
743 2 dgisselq
                        iflags <= wr_reg_vl[3:0];
744
                else if ((wr_flags_ce)&&(~alu_gie))
745
                        iflags <= alu_flags;
746
                else if ((i_halt)&&(i_dbg_we)
747
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
748
                        iflags <= i_dbg_data[3:0];
749
 
750
        // The 'break' enable  bit.  This bit can only be set from supervisor
751
        // mode.  It control what the CPU does upon encountering a break
752
        // instruction.
753
        //
754
        // The goal, upon encountering a break is that the CPU should stop and
755
        // not execute the break instruction, choosing instead to enter into
756
        // either interrupt mode or halt first.  
757
        //      if ((break_en) AND (break_instruction)) // user mode or not
758
        //              HALT CPU
759
        //      else if (break_instruction) // only in user mode
760
        //              set an interrupt flag, go to supervisor mode
761
        //              allow supervisor to step the CPU.
762
        //      Upon a CPU halt, any break condition will be reset.  The
763
        //      external debugger will then need to deal with whatever
764
        //      condition has taken place.
765
        initial break_en = 1'b0;
766
        always @(posedge i_clk)
767
                if ((i_rst)||(i_halt))
768
                        break_en <= 1'b0;
769 25 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
770 2 dgisselq
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
771 25 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)&&(~alu_valid)&&(~mem_valid)&&(~mem_busy);
772 2 dgisselq
 
773
 
774
        // The sleep register.  Setting the sleep register causes the CPU to
775
        // sleep until the next interrupt.  Setting the sleep register within
776
        // interrupt mode causes the processor to halt until a reset.  This is
777 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
778
        // set the sleep bit and switch to supervisor mode in the same 
779
        // instruction: users are not allowed to halt the CPU.
780 2 dgisselq
        always @(posedge i_clk)
781
                if ((i_rst)||((i_interrupt)&&(gie)))
782
                        sleep <= 1'b0;
783 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
784
                        // In supervisor mode, we have no protections.  The
785
                        // supervisor can set the sleep bit however he wants.
786 2 dgisselq
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
787 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
788
                        // In user mode, however, you can only set the sleep
789
                        // mode while remaining in user mode.  You can't switch
790
                        // to sleep mode *and* supervisor mode at the same
791
                        // time, lest you halt the CPU.
792
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
793 2 dgisselq
                else if ((i_halt)&&(i_dbg_we)
794
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
795
                        sleep <= i_dbg_data[`CPU_SLEEP_BIT];
796
 
797
        always @(posedge i_clk)
798
                if ((i_rst)||(w_switch_to_interrupt))
799
                        step <= 1'b0;
800 25 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
801 2 dgisselq
                        step <= wr_reg_vl[`CPU_STEP_BIT];
802
                else if ((i_halt)&&(i_dbg_we)
803
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
804
                        step <= i_dbg_data[`CPU_STEP_BIT];
805
                else if ((master_ce)&&(alu_pc_valid)&&(step)&&(gie))
806
                        step <= 1'b0;
807
 
808
        // The GIE register.  Only interrupts can disable the interrupt register
809
        assign  w_switch_to_interrupt = (gie)&&(
810
                        // On interrupt (obviously)
811
                        (i_interrupt)
812
                        // If we are stepping the CPU
813
                        ||((master_ce)&&(alu_pc_valid)&&(step))
814
                        // If we encounter a break instruction, if the break
815
                        //      enable isn't not set.
816 25 dgisselq
                        ||((master_ce)&&(op_break)&&(~break_en))
817 2 dgisselq
                        // If we write to the CC register
818
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
819 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
820 2 dgisselq
                        // Or if, in debug mode, we write to the CC register
821
                        ||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
822
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
823
                        );
824
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
825
                        // Then if we write the CC register
826
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
827 25 dgisselq
                                &&(~wr_reg_id[4])&&(wr_write_cc))
828 2 dgisselq
                        // Or if, in debug mode, we write the CC register
829
                          ||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
830
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
831
                        );
832
        always @(posedge i_clk)
833
                if (i_rst)
834
                        gie <= 1'b0;
835
                else if (w_switch_to_interrupt)
836
                        gie <= 1'b0;
837
                else if (w_release_from_interrupt)
838
                        gie <= 1'b1;
839
 
840 25 dgisselq
        initial trap = 1'b0;
841
        always @(posedge i_clk)
842
                if (i_rst)
843
                        trap <= 1'b0;
844
                else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
845
                                &&(wr_reg_id[4])&&(wr_write_cc))
846
                        trap <= 1'b1;
847
                else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
848
                                &&(~i_dbg_data[`CPU_GIE_BIT]))
849
                        trap <= i_dbg_data[`CPU_TRAP_BIT];
850
                else if (w_release_from_interrupt)
851
                        trap <= 1'b0;
852
 
853 2 dgisselq
        //
854
        // Write backs to the PC register, and general increments of it
855
        //      We support two: upc and ipc.  If the instruction is normal,
856
        // we increment upc, if interrupt level we increment ipc.  If
857
        // the instruction writes the PC, we write whichever PC is appropriate.
858
        //
859
        // Do we need to all our partial results from the pipeline?
860
        // What happens when the pipeline has gie and ~gie instructions within
861
        // it?  Do we clear both?  What if a gie instruction tries to clear
862
        // a non-gie instruction?
863
        always @(posedge i_clk)
864 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
865 2 dgisselq
                        upc <= wr_reg_vl;
866
                else if ((alu_gie)&&(alu_pc_valid))
867
                        upc <= alu_pc;
868
                else if ((i_halt)&&(i_dbg_we)
869
                                &&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
870
                        upc <= i_dbg_data;
871
 
872
        always @(posedge i_clk)
873
                if (i_rst)
874
                        ipc <= RESET_ADDRESS;
875
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
876
                        ipc <= wr_reg_vl;
877
                else if ((~alu_gie)&&(alu_pc_valid))
878
                        ipc <= alu_pc;
879
                else if ((i_halt)&&(i_dbg_we)
880
                                &&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
881
                        ipc <= i_dbg_data;
882
 
883
        always @(posedge i_clk)
884
                if (i_rst)
885
                        pf_pc <= RESET_ADDRESS;
886
                else if (w_switch_to_interrupt)
887
                        pf_pc <= ipc;
888
                else if (w_release_from_interrupt)
889
                        pf_pc <= upc;
890
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
891
                        pf_pc <= wr_reg_vl;
892
                else if ((i_halt)&&(i_dbg_we)
893
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
894
                        pf_pc <= i_dbg_data;
895
                else if (dcd_ce)
896
                        pf_pc <= pf_pc + 1;
897
 
898
        initial new_pc = 1'b1;
899
        always @(posedge i_clk)
900 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
901 2 dgisselq
                        new_pc <= 1'b1;
902
                else if (w_switch_to_interrupt)
903
                        new_pc <= 1'b1;
904
                else if (w_release_from_interrupt)
905
                        new_pc <= 1'b1;
906
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
907
                        new_pc <= 1'b1;
908
                else if ((i_halt)&&(i_dbg_we)
909
                                &&(wr_reg_id[4:0] == { gie, `CPU_PC_REG}))
910
                        new_pc <= 1'b1;
911
                else
912
                        new_pc <= 1'b0;
913
 
914
        //
915
        // The debug interface
916
        always @(posedge i_clk)
917
                begin
918
                        o_dbg_reg <= regset[i_dbg_reg];
919
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
920
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
921
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
922 25 dgisselq
                                o_dbg_reg[9:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
923 2 dgisselq
                end
924
        always @(posedge i_clk)
925 25 dgisselq
                o_dbg_cc <= { gie, sleep };
926 18 dgisselq
 
927
        always @(posedge i_clk)
928 25 dgisselq
                o_dbg_stall <= (i_halt)&&(
929
                        (pf_cyc)||(mem_cyc)||(mem_busy)
930 2 dgisselq
                        ||((~opvalid)&&(~i_rst))
931 25 dgisselq
                        ||((~dcdvalid)&&(~i_rst)));
932 2 dgisselq
 
933
        //
934
        //
935
        // Produce accounting outputs: Account for any CPU stalls, so we can
936
        // later evaluate how well we are doing.
937
        //
938
        //
939 9 dgisselq
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
940
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
941
        assign  o_i_count  = alu_pc_valid;
942 2 dgisselq
endmodule

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