OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [core/] [zipcpu.v] - Blame information for rev 38

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipcpu.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This is the top level module holding the core of the Zip CPU
8
//              together.  The Zip CPU is designed to be as simple as possible.
9
//              The instruction set is about as RISC as you can get, there are
10
//              only 16 instruction types supported (of which one isn't yet
11
//              supported ...)  Please see the accompanying iset.html file
12
//              for a description of these instructions.
13
//
14
//              All instructions are 32-bits wide.  All bus accesses, both
15
//              address and data, are 32-bits over a wishbone bus.
16
//
17
//      The Zip CPU is fully pipelined with the following pipeline stages:
18
//
19
//              1. Prefetch, returns the instruction from memory.  On the
20
//              Basys board that I'm working on, one instruction may be
21
//              issued every 20 clocks or so, unless and until I implement a
22
//              cache or local memory.
23
//
24
//              2. Instruction Decode
25
//
26
//              3. Read Operands
27
//
28
//              4. Apply Instruction
29
//
30
//              4. Write-back Results
31
//
32
//      A lot of difficult work has been placed into the pipeline stall
33
//      handling.  My original proposal was not to allow pipeline stalls at all.
34
//      The idea would be that the CPU would just run every clock and whatever
35
//      stalled answer took place would just get fixed a clock or two later,
36
//      meaning that the compiler could just schedule everything out.
37
//      This idea died at the memory interface, which can take a variable
38
//      amount of time to read or write any value, thus the whole CPU needed
39
//      to stall on a stalled memory access.
40
//
41
//      My next idea was to just let things complete.  I.e., once an instrution
42
//      starts, it continues to completion no matter what and we go on.  This
43
//      failed at writing the PC.  If the PC gets written in something such as
44
//      a MOV PC,PC+5 instruction, 3 (or however long the pipeline is) clocks
45
//      later, if whether or not something happens in those clocks depends
46
//      upon the instruction fetch filling the pipeline, then the CPU has a
47
//      non-deterministic behavior.
48
//
49
//      This leads to two possibilities: either *everything* stalls upon a 
50
//      stall condition, or partial results need to be destroyed before
51
//      they are written.  This is made more difficult by the fact that
52
//      once a command is written to the memory unit, whether it be a
53
//      read or a write, there is no undoing it--since peripherals on the
54
//      bus may act upon the answer with whatever side effects they might
55
//      have.  (For example, writing a '1' to the interrupt register will
56
//      clear certain interrupts ...)  Further, since the memory ops depend
57
//      upon conditions, the we'll need to wait for the condition codes to
58
//      be available before executing a memory op.  Thus, memory ops can 
59
//      proceed without stalling whenever either the previous instruction
60
//      doesn't write the flags register, or when the memory instruction doesn't
61
//      depend upon the flags register.
62
//
63
//      The other possibility is that we leave independent instruction
64
//      execution behind, so that the pipeline is always full and stalls,
65
//      or moves forward, together on every clock.
66
//
67
//      For now, we pick the first approach: independent instruction execution.
68
//      Thus, if stage 2 stalls, stages 3-5 may still complete the instructions
69
//      in their pipeline.  This leaves another problem: what happens on a
70
//      MOV -1+PC,PC instruction?  There will be four instructions behind this
71
//      one (or is it five?) that will need to be 'cancelled'.  So here's
72
//      the plan: Anything can be cancelled before the ALU/MEM stage,
73
//      since memory ops cannot be canceled after being issued.  Thus, the
74
//      ALU/MEM stage must stall if any prior instruction is going to write
75
//      the PC register (i.e. JMP).
76
//
77
//      Further, let's define a "STALL" as a reason to not execute a stage
78
//      due to some condition at or beyond the stage, and let's define
79
//      a VALID flag to mean that this stage has completed.  Thus, the clock
80
//      enable for a stage is (STG[n-1]VALID)&&((~STG[n]VALID)||(~STG[n]STALL)).
81
//      The ALU/MEM stages will also depend upon a master clock enable
82
//      (~SLEEP) condition as well.
83
//
84
//
85
//
86
// Creator:     Dan Gisselquist, Ph.D.
87
//              Gisselquist Tecnology, LLC
88
//
89
///////////////////////////////////////////////////////////////////////////////
90
//
91
// Copyright (C) 2015, Gisselquist Technology, LLC
92
//
93
// This program is free software (firmware): you can redistribute it and/or
94
// modify it under the terms of  the GNU General Public License as published
95
// by the Free Software Foundation, either version 3 of the License, or (at
96
// your option) any later version.
97
//
98
// This program is distributed in the hope that it will be useful, but WITHOUT
99
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
100
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
101
// for more details.
102
//
103
// License:     GPL, v3, as defined and found on www.gnu.org,
104
//              http://www.gnu.org/licenses/gpl.html
105
//
106
//
107
///////////////////////////////////////////////////////////////////////////////
108
//
109 36 dgisselq
// We can either pipeline our fetches, or issue one fetch at a time.  Pipelined
110
// fetches are more complicated and therefore use more FPGA resources, while
111
// single fetches will cause the CPU to stall for about 5 stalls each 
112
// instruction cycle, effectively reducing the instruction count per clock to
113
// about 0.2.  However, the area cost may be worth it.  Consider:
114
//
115
//      Slice LUTs              ZipSystem       ZipCPU
116
//      Single Fetching         2521            1734
117
//      Pipelined fetching      2796            2046
118
//
119 38 dgisselq
// `define      OPT_SINGLE_FETCH
120 36 dgisselq
//
121
//
122
//
123 25 dgisselq
`define CPU_CC_REG      4'he
124 2 dgisselq
`define CPU_PC_REG      4'hf
125 25 dgisselq
`define CPU_TRAP_BIT    9
126 2 dgisselq
`define CPU_BREAK_BIT   7
127
`define CPU_STEP_BIT    6
128
`define CPU_GIE_BIT     5
129
`define CPU_SLEEP_BIT   4
130 36 dgisselq
// Compile time defines
131 38 dgisselq
// (Currently unused)
132
// `define      OPT_SINGLE_FETCH
133
// (Best path--define these!)
134
`define OPT_CONDITIONAL_FLAGS
135
`define OPT_PRECLEAR_BUS
136
`define OPT_ILLEGAL_INSTRUCTION
137
`define OPT_EARLY_BRANCHING
138
`define OPT_PIPELINED_BUS_ACCESS
139 2 dgisselq
module  zipcpu(i_clk, i_rst, i_interrupt,
140
                // Debug interface
141 18 dgisselq
                i_halt, i_clear_pf_cache, i_dbg_reg, i_dbg_we, i_dbg_data,
142
                        o_dbg_stall, o_dbg_reg, o_dbg_cc,
143 2 dgisselq
                        o_break,
144
                // CPU interface to the wishbone bus
145 36 dgisselq
                o_wb_gbl_cyc, o_wb_gbl_stb,
146
                        o_wb_lcl_cyc, o_wb_lcl_stb,
147
                        o_wb_we, o_wb_addr, o_wb_data,
148 2 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_data,
149 36 dgisselq
                        i_wb_err,
150 2 dgisselq
                // Accounting/CPU usage interface
151 9 dgisselq
                o_op_stall, o_pf_stall, o_i_count);
152 38 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, LGICACHE=9;
153 2 dgisselq
        input                   i_clk, i_rst, i_interrupt;
154
        // Debug interface -- inputs
155 18 dgisselq
        input                   i_halt, i_clear_pf_cache;
156 2 dgisselq
        input           [4:0]    i_dbg_reg;
157
        input                   i_dbg_we;
158
        input           [31:0]   i_dbg_data;
159
        // Debug interface -- outputs
160
        output  reg             o_dbg_stall;
161
        output  reg     [31:0]   o_dbg_reg;
162 25 dgisselq
        output  reg     [1:0]    o_dbg_cc;
163 2 dgisselq
        output  wire            o_break;
164
        // Wishbone interface -- outputs
165 36 dgisselq
        output  wire            o_wb_gbl_cyc, o_wb_gbl_stb;
166
        output  wire            o_wb_lcl_cyc, o_wb_lcl_stb, o_wb_we;
167 2 dgisselq
        output  wire    [31:0]   o_wb_addr, o_wb_data;
168
        // Wishbone interface -- inputs
169
        input                   i_wb_ack, i_wb_stall;
170
        input           [31:0]   i_wb_data;
171 36 dgisselq
        input                   i_wb_err;
172 2 dgisselq
        // Accounting outputs ... to help us count stalls and usage
173 9 dgisselq
        output  wire            o_op_stall;
174 2 dgisselq
        output  wire            o_pf_stall;
175 9 dgisselq
        output  wire            o_i_count;
176 2 dgisselq
 
177 25 dgisselq
 
178 2 dgisselq
        // Registers
179
        reg     [31:0]   regset [0:31];
180 9 dgisselq
 
181
        // Condition codes
182 25 dgisselq
        reg     [3:0]    flags, iflags;  // (TRAP,FPEN,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z
183 36 dgisselq
        wire    [10:0]   w_uflags, w_iflags;
184 25 dgisselq
        reg             trap, break_en, step, gie, sleep;
185 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
186 36 dgisselq
        reg             ill_err;
187 38 dgisselq
`else
188
        wire            ill_err;
189 36 dgisselq
`endif
190
        reg             bus_err_flag;
191 2 dgisselq
 
192 9 dgisselq
        // The master chip enable
193
        wire            master_ce;
194 2 dgisselq
 
195
        //
196
        //
197
        //      PIPELINE STAGE #1 :: Prefetch
198
        //              Variable declarations
199
        //
200 9 dgisselq
        reg     [31:0]   pf_pc;
201 25 dgisselq
        reg             new_pc, op_break;
202 18 dgisselq
        wire    clear_pipeline;
203 36 dgisselq
        assign  clear_pipeline = new_pc || i_clear_pf_cache; //  || op_break;
204 9 dgisselq
 
205
        wire            dcd_stalled;
206 36 dgisselq
        wire            pf_cyc, pf_stb, pf_we, pf_busy, pf_ack, pf_stall, pf_err;
207 2 dgisselq
        wire    [31:0]   pf_addr, pf_data;
208
        wire    [31:0]   instruction, instruction_pc;
209 36 dgisselq
        wire    pf_valid, instruction_gie, pf_illegal;
210 2 dgisselq
 
211
        //
212
        //
213
        //      PIPELINE STAGE #2 :: Instruction Decode
214
        //              Variable declarations
215
        //
216
        //
217 25 dgisselq
        reg             opvalid, opvalid_mem, opvalid_alu, op_wr_pc;
218 2 dgisselq
        wire            op_stall, dcd_ce;
219
        reg     [3:0]    dcdOp;
220
        reg     [4:0]    dcdA, dcdB;
221 25 dgisselq
        reg             dcdA_cc, dcdB_cc, dcdA_pc, dcdB_pc;
222 2 dgisselq
        reg     [3:0]    dcdF;
223
        reg             dcdA_rd, dcdA_wr, dcdB_rd, dcdvalid,
224
                                dcdM, dcdF_wr, dcd_gie, dcd_break;
225
        reg     [31:0]   dcd_pc;
226
        reg     [23:0]   r_dcdI;
227
        wire    dcdA_stall, dcdB_stall, dcdF_stall;
228
 
229 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
230 36 dgisselq
        reg     dcd_clear_bus;
231
`endif
232 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
233 36 dgisselq
        reg     dcd_illegal;
234
`endif
235 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
236 36 dgisselq
        reg             dcd_early_branch_stb, dcd_early_branch;
237
        reg     [31:0]   dcd_branch_pc;
238
`else
239
        wire            dcd_early_branch_stb, dcd_early_branch;
240
        wire    [31:0]   dcd_branch_pc;
241
`endif
242 2 dgisselq
 
243
 
244
        //
245
        //
246
        //      PIPELINE STAGE #3 :: Read Operands
247
        //              Variable declarations
248
        //
249
        //
250
        //
251
        // Now, let's read our operands
252
        reg     [4:0]    alu_reg;
253
        reg     [3:0]    opn;
254
        reg     [4:0]    opR;
255
        reg     [31:0]   r_opA, r_opB, op_pc;
256 25 dgisselq
        wire    [31:0]   w_opA, w_opB;
257 2 dgisselq
        wire    [31:0]   opA_nowait, opB_nowait, opA, opB;
258 25 dgisselq
        reg             opR_wr, opR_cc, opF_wr, op_gie,
259 2 dgisselq
                        opA_rd, opB_rd;
260 36 dgisselq
        wire    [10:0]   opFl;
261 3 dgisselq
        reg     [6:0]    r_opF;
262 2 dgisselq
        wire    [8:0]    opF;
263
        wire            op_ce;
264 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
265 36 dgisselq
        reg     op_clear_bus;
266
`endif
267 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
268 36 dgisselq
        reg     op_illegal;
269
`endif
270 2 dgisselq
 
271
 
272
        //
273
        //
274
        //      PIPELINE STAGE #4 :: ALU / Memory
275
        //              Variable declarations
276
        //
277
        //
278
        reg     [31:0]   alu_pc;
279
        reg             alu_pc_valid;;
280
        wire            alu_ce, alu_stall;
281
        wire    [31:0]   alu_result;
282
        wire    [3:0]    alu_flags;
283
        wire            alu_valid;
284
        wire            set_cond;
285
        reg             alu_wr, alF_wr, alu_gie;
286 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
287 36 dgisselq
        reg             alu_illegal;
288 38 dgisselq
`else
289
        wire            alu_illegal;
290 36 dgisselq
`endif
291 2 dgisselq
 
292
 
293
 
294
        wire    mem_ce, mem_stalled;
295 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
296
        wire    mem_pipe_stalled;
297
`endif
298 36 dgisselq
        wire    mem_valid, mem_ack, mem_stall, mem_err, bus_err,
299
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl, mem_we;
300 9 dgisselq
        wire    [4:0]    mem_wreg;
301
 
302
        wire            mem_busy, mem_rdbusy;
303 2 dgisselq
        wire    [31:0]   mem_addr, mem_data, mem_result;
304
 
305
 
306
 
307
        //
308
        //
309
        //      PIPELINE STAGE #5 :: Write-back
310
        //              Variable declarations
311
        //
312 25 dgisselq
        wire            wr_reg_ce, wr_flags_ce, wr_write_pc, wr_write_cc;
313 2 dgisselq
        wire    [4:0]    wr_reg_id;
314
        wire    [31:0]   wr_reg_vl;
315
        wire    w_switch_to_interrupt, w_release_from_interrupt;
316
        reg     [31:0]   upc, ipc;
317
 
318
 
319
 
320
        //
321
        //      MASTER: clock enable.
322
        //
323 38 dgisselq
        assign  master_ce = (~i_halt)&&(~o_break)&&(~sleep);
324 2 dgisselq
 
325
 
326
        //
327
        //      PIPELINE STAGE #1 :: Prefetch
328
        //              Calculate stall conditions
329
 
330
        //
331
        //      PIPELINE STAGE #2 :: Instruction Decode
332
        //              Calculate stall conditions
333 34 dgisselq
        assign          dcd_ce = (pf_valid)&&(~dcd_stalled)&&(~clear_pipeline);
334 2 dgisselq
        assign          dcd_stalled = (dcdvalid)&&(
335
                                        (op_stall)
336
                                        ||((dcdA_stall)||(dcdB_stall)||(dcdF_stall))
337 36 dgisselq
                                        ||((opvalid_mem)&&(op_wr_pc))
338
                                        ||((opvalid_mem)&&(opR_cc)));
339 2 dgisselq
        //
340
        //      PIPELINE STAGE #3 :: Read Operands
341
        //              Calculate stall conditions
342 25 dgisselq
        assign  op_stall = ((mem_stalled)&&(opvalid_mem))
343
                                ||((alu_stall)&&(opvalid_alu));
344 2 dgisselq
        assign  op_ce = (dcdvalid)&&((~opvalid)||(~op_stall));
345
 
346
        //
347
        //      PIPELINE STAGE #4 :: ALU / Memory
348
        //              Calculate stall conditions
349 36 dgisselq
        //
350
        // 1. Basic stall is if the previous stage is valid and the next is
351
        //      busy.  
352
        // 2. Also stall if the prior stage is valid and the master clock enable
353
        //      is de-selected
354
        // 3. Next case: Stall if we want to start a memory operation and the
355
        //      prior operation will write either the PC or CC registers.
356
        // 4. Last case: Stall if we would otherwise move a break instruction
357
        //      through the ALU.  Break instructions are not allowed through
358
        //      the ALU.
359
        assign  alu_stall = (((~master_ce)||(mem_rdbusy))&&(opvalid_alu)) //Case 1&2
360
                        ||((opvalid_mem)&&(wr_reg_ce)&&(wr_reg_id[4] == op_gie)
361
                                &&((wr_write_pc)||(wr_write_cc))) // Case 3
362
                        ||((opvalid)&&(op_break)); // Case 4
363 38 dgisselq
        assign  alu_ce = (master_ce)&&(~mem_rdbusy)&&(opvalid_alu)&&(~alu_stall)&&(~clear_pipeline);
364 2 dgisselq
        //
365 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
366
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~clear_pipeline)
367
                        &&(set_cond)&&(~mem_stalled);
368
        assign  mem_stalled = (~master_ce)||((opvalid_mem)&&(
369
                                (mem_pipe_stalled)
370
                                ||((~op_pipe)&&(mem_busy))
371
                                // Stall waiting for flags to be valid
372
                                // Or waiting for a write to the PC register
373
                                // Or CC register, since that can change the
374
                                //  PC as well
375
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)
376
                                        &&((wr_write_pc)||(wr_write_cc)))));
377
`else
378 25 dgisselq
        assign  mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline)&&(set_cond);
379 38 dgisselq
 
380 25 dgisselq
        assign  mem_stalled = (mem_busy)||((opvalid_mem)&&(
381 2 dgisselq
                                (~master_ce)
382
                                // Stall waiting for flags to be valid
383
                                // Or waiting for a write to the PC register
384 25 dgisselq
                                // Or CC register, since that can change the
385
                                //  PC as well
386
                                ||((wr_reg_ce)&&(wr_reg_id[4] == op_gie)&&((wr_write_pc)||(wr_write_cc)))));
387 38 dgisselq
`endif
388 2 dgisselq
 
389
 
390
        //
391
        //
392
        //      PIPELINE STAGE #1 :: Prefetch
393
        //
394
        //
395 38 dgisselq
`ifdef  OPT_SINGLE_FETCH
396 9 dgisselq
        wire            pf_ce;
397
 
398
        assign          pf_ce = (~dcd_stalled);
399 2 dgisselq
        prefetch        pf(i_clk, i_rst, (pf_ce), pf_pc, gie,
400
                                instruction, instruction_pc, instruction_gie,
401 36 dgisselq
                                        pf_valid, pf_illegal,
402
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
403
                                pf_ack, pf_stall, pf_err, i_wb_data);
404 2 dgisselq
`else // Pipe fetch
405 38 dgisselq
        pipefetch       #(RESET_ADDRESS, LGICACHE)
406 36 dgisselq
                        pf(i_clk, i_rst, (new_pc)|(dcd_early_branch_stb),
407
                                        i_clear_pf_cache, ~dcd_stalled,
408
                                        (new_pc)?pf_pc:dcd_branch_pc,
409 2 dgisselq
                                        instruction, instruction_pc, pf_valid,
410
                                pf_cyc, pf_stb, pf_we, pf_addr, pf_data,
411 36 dgisselq
                                        pf_ack, pf_stall, pf_err, i_wb_data,
412 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
413 36 dgisselq
                                ((dcd_clear_bus)&&(dcdvalid))
414
                                ||((op_clear_bus)&&(opvalid))
415
                                ||
416
`endif
417
                                (mem_cyc_lcl)||(mem_cyc_gbl),
418
                                pf_illegal);
419 2 dgisselq
        assign  instruction_gie = gie;
420
`endif
421
 
422 36 dgisselq
        initial dcdvalid = 1'b0;
423 2 dgisselq
        always @(posedge i_clk)
424
                if (i_rst)
425
                        dcdvalid <= 1'b0;
426
                else if (dcd_ce)
427 36 dgisselq
                        dcdvalid <= (~clear_pipeline)&&(~dcd_early_branch_stb);
428
                else if ((~dcd_stalled)||(clear_pipeline)||(dcd_early_branch))
429 2 dgisselq
                        dcdvalid <= 1'b0;
430
 
431 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
432 2 dgisselq
        always @(posedge i_clk)
433 38 dgisselq
                if ((dcd_ce)&&(instruction[27:24]==`CPU_PC_REG)&&(~sleep))
434 36 dgisselq
                begin
435
                        dcd_early_branch <= 1'b0;
436
                        // First case, a move to PC instruction
437
                        if ((instruction[31:28] == 4'h2)
438
                                &&((instruction_gie)
439
                                        ||((~instruction[20])&&(~instruction[15])))
440
                                &&(instruction[23:21]==3'h0))
441
                        begin
442
                                dcd_early_branch_stb <= 1'b1;
443
                                dcd_early_branch <= 1'b1;
444
                                // r_dcdI <= { {(17){instruction[14]}}, instruction[14:0] };
445
 
446
                        end else // Next case, an Add Imm -> PC instruction
447
                        if ((instruction[31:28] == 4'ha) // Add
448
                                &&(~instruction[20]) // Immediate
449
                                &&(instruction[23:21]==3'h0)) // Always
450
                        begin
451
                                dcd_early_branch_stb <= 1'b1;
452
                                dcd_early_branch <= 1'b1;
453
                                // r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
454
                        end else // Next case: load Immediate to PC
455
                        if (instruction[31:28] == 4'h3)
456
                        begin
457
                                dcd_early_branch_stb <= 1'b1;
458
                                dcd_early_branch <= 1'b1;
459
                                // r_dcdI <= { instruction[23:0] };
460
                        end
461
                end else
462
                begin
463
                        if (dcd_ce) dcd_early_branch <= 1'b0;
464
                        dcd_early_branch_stb <= 1'b0;
465
                end
466
        always @(posedge i_clk)
467 2 dgisselq
                if (dcd_ce)
468
                begin
469 36 dgisselq
                        if (instruction[31]) // Add
470
                                dcd_branch_pc <= instruction_pc+32'h01+{ {(12){instruction[19]}}, instruction[19:0] };
471
                        else if (~instruction[28]) // 4'h2 = MOV
472
                                dcd_branch_pc <= instruction_pc+32'h01+{ {(17){instruction[14]}}, instruction[14:0] };
473
                        else // if (instruction[28]) // 4'h3 = LDI
474
                                dcd_branch_pc <= instruction_pc+32'h01+{ {(8){instruction[23]}}, instruction[23:0] };
475
                end
476 38 dgisselq
`else   //      OPT_EARLY_BRANCHING
477 36 dgisselq
        assign  dcd_early_branch_stb = 1'b0;
478
        assign  dcd_early_branch     = 1'b0;
479
        assign  dcd_branch_pc        = 32'h00;
480 38 dgisselq
`endif  //      OPT_EARLY_BRANCHING
481 36 dgisselq
 
482
        always @(posedge i_clk)
483
                if (dcd_ce)
484
                begin
485 2 dgisselq
                        dcd_pc <= instruction_pc+1;
486
 
487
                        // Record what operation we are doing
488
                        dcdOp <= instruction[31:28];
489
 
490
                        // Default values
491
                        dcdA[4:0] <= { instruction_gie, instruction[27:24] };
492
                        dcdB[4:0] <= { instruction_gie, instruction[19:16] };
493 25 dgisselq
                        dcdA_cc <=  (instruction[27:24] == `CPU_CC_REG);
494
                        dcdB_cc <=  (instruction[19:16] == `CPU_CC_REG);
495
                        dcdA_pc <=  (instruction[27:24] == `CPU_PC_REG);
496
                        dcdB_pc <=  (instruction[19:16] == `CPU_PC_REG);
497 2 dgisselq
                        dcdM    <= 1'b0;
498 38 dgisselq
`ifdef  OPT_CONDITIONAL_FLAGS
499 36 dgisselq
                        dcdF_wr <= (instruction[23:21]==3'h0);
500
`else
501 2 dgisselq
                        dcdF_wr <= 1'b1;
502 36 dgisselq
`endif
503 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
504 36 dgisselq
                        dcd_clear_bus <= 1'b0;
505
`endif
506 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
507 36 dgisselq
                        dcd_illegal <= pf_illegal;
508
`endif
509 2 dgisselq
 
510
                        // Set the condition under which we do this operation
511
                        // The top four bits are a mask, the bottom four the
512
                        // value the flags must equal once anded with the mask
513
                        dcdF <= { (instruction[23:21]==3'h0), instruction[23:21] };
514
                        casez(instruction[31:28])
515
                        4'h2: begin // Move instruction
516
                                if (~instruction_gie)
517
                                begin
518
                                        dcdA[4] <= instruction[20];
519
                                        dcdB[4] <= instruction[15];
520
                                end
521
                                dcdA_wr <= 1'b1;
522
                                dcdA_rd <= 1'b0;
523
                                dcdB_rd <= 1'b1;
524
                                r_dcdI <= { {(9){instruction[14]}}, instruction[14:0] };
525
                                dcdF_wr <= 1'b0; // Don't write flags
526
                                end
527
                        4'h3: begin // Load immediate
528
                                dcdA_wr <= 1'b1;
529
                                dcdA_rd <= 1'b0;
530
                                dcdB_rd <= 1'b0;
531
                                r_dcdI <= { instruction[23:0] };
532
                                dcdF_wr <= 1'b0; // Don't write flags
533
                                dcdF    <= 4'h8; // This is unconditional
534
                                dcdOp <= 4'h2;
535
                                end
536 25 dgisselq
                        4'h4: begin // Multiply, LDI[HI|LO], or NOOP/BREAK
537 38 dgisselq
`ifdef  OPT_CONDITIONAL_FLAGS
538 25 dgisselq
                                // Don't write flags except for multiplies
539 36 dgisselq
                                //   and then only if they are unconditional
540
                                dcdF_wr <= ((instruction[27:25] != 3'h7)
541
                                        &&(instruction[23:21]==3'h0));
542
`else
543
                                // Don't write flags except for multiplies
544 25 dgisselq
                                dcdF_wr <= (instruction[27:25] != 3'h7);
545 36 dgisselq
`endif
546 2 dgisselq
                                r_dcdI <= { 8'h00, instruction[15:0] };
547
                                if (instruction[27:24] == 4'he)
548
                                begin
549
                                        // NOOP instruction
550
                                        dcdA_wr <= 1'b0;
551
                                        dcdA_rd <= 1'b0;
552
                                        dcdB_rd <= 1'b0;
553
                                        dcdOp <= 4'h2;
554 36 dgisselq
                                        // Might also be a break.  Big
555
                                        // instruction set hole here.
556 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
557 36 dgisselq
                                        dcd_illegal <= (pf_illegal)||(instruction[23:1] != 0);
558
`endif
559 2 dgisselq
                                end else if (instruction[27:24] == 4'hf)
560
                                begin // Load partial immediate(s)
561
                                        dcdA_wr <= 1'b1;
562
                                        dcdA_rd <= 1'b1;
563
                                        dcdB_rd <= 1'b0;
564
                                        dcdA[4:0] <= { instruction_gie, instruction[19:16] };
565 25 dgisselq
                                        dcdA_cc <= (instruction[19:16] == `CPU_CC_REG);
566
                                        dcdA_pc <= (instruction[19:16] == `CPU_PC_REG);
567 2 dgisselq
                                        dcdOp <= { 3'h3, instruction[20] };
568
                                end else begin
569 25 dgisselq
                                        // Actual multiply instruction
570
                                        r_dcdI <= { 8'h00, instruction[15:0] };
571
                                        dcdA_rd <= 1'b1;
572
                                        dcdB_rd <= (instruction[19:16] != 4'hf);
573
                                        dcdOp[3:0] <= (instruction[20])? 4'h4:4'h3;
574 2 dgisselq
                                end end
575
                        4'b011?: begin // Load/Store
576
                                dcdF_wr <= 1'b0; // Don't write flags
577
                                dcdA_wr <= (~instruction[28]); // Write on loads
578
                                dcdA_rd <= (instruction[28]); // Read on stores
579
                                dcdB_rd <= instruction[20];
580
                                if (instruction[20])
581
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
582
                                else
583
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
584
                                dcdM <= 1'b1; // Memory operation
585 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
586 36 dgisselq
                                dcd_clear_bus <= (instruction[23:21]==3'h0);
587
`endif
588 2 dgisselq
                                end
589
                        default: begin
590
                                dcdA_wr <= (instruction[31])||(instruction[31:28]==4'h5);
591
                                dcdA_rd <= 1'b1;
592
                                dcdB_rd <= instruction[20];
593
                                if (instruction[20])
594
                                        r_dcdI <= { {(8){instruction[15]}}, instruction[15:0] };
595
                                else
596
                                        r_dcdI <= { {(4){instruction[19]}}, instruction[19:0] };
597
                                end
598
                        endcase
599
 
600
 
601
                        dcd_gie <= instruction_gie;
602
                end
603 25 dgisselq
        always @(posedge i_clk)
604
                if (dcd_ce)
605
                        dcd_break <= (instruction[31:0] == 32'h4e000001);
606 38 dgisselq
                else if ((clear_pipeline)||(~dcdvalid)) // SHOULDNT THIS BE ||op_ce?
607 25 dgisselq
                        dcd_break <= 1'b0;
608 2 dgisselq
 
609 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
610
        reg     [23:0]   r_opI;
611
        reg     [4:0]    op_B;
612
        reg             op_pipe;
613 2 dgisselq
 
614 38 dgisselq
        initial op_pipe = 1'b0;
615
        // To be a pipeable operation, there must be 
616
        //      two valid adjacent instructions
617
        //      Both must be memory instructions
618
        //      Both must be writes, or both must be reads
619
        //      Both operations must be to the same identical address,
620
        //              or at least a single (one) increment above that address
621
        always @(posedge i_clk)
622
                if (op_ce)
623
                        op_pipe <= (dcdvalid)&&(opvalid_mem)&&(dcdM) // Both mem
624
                                &&(dcdOp[0]==opn[0]) // Both Rd, or both Wr
625
                                &&(dcdB == op_B) // Same address register
626
                                &&((r_dcdI == r_opI)||(r_dcdI==r_opI+24'h1));
627
        always @(posedge i_clk)
628
                if (op_ce) // &&(dcdvalid))
629
                        r_opI <= r_dcdI;
630
        always @(posedge i_clk)
631
                if (op_ce) // &&(dcdvalid))
632
                        op_B <= dcdB;
633
`endif
634
 
635 2 dgisselq
        //
636
        //
637
        //      PIPELINE STAGE #3 :: Read Operands (Registers)
638
        //
639
        //
640 25 dgisselq
        assign  w_opA = regset[dcdA];
641
        assign  w_opB = regset[dcdB];
642 2 dgisselq
        always @(posedge i_clk)
643
                if (op_ce) // &&(dcdvalid))
644
                begin
645
                        if ((wr_reg_ce)&&(wr_reg_id == dcdA))
646
                                r_opA <= wr_reg_vl;
647 25 dgisselq
                        else if ((dcdA_pc)&&(dcdA[4] == dcd_gie))
648 2 dgisselq
                                r_opA <= dcd_pc;
649 25 dgisselq
                        else if (dcdA_pc)
650
                                r_opA <= upc;
651
                        else if (dcdA_cc)
652 36 dgisselq
                                r_opA <= { w_opA[31:11], (dcd_gie)?w_uflags:w_iflags };
653 2 dgisselq
                        else
654 25 dgisselq
                                r_opA <= w_opA;
655 2 dgisselq
                end
656 36 dgisselq
        wire    [31:0]   dcdI, w_opBnI;
657 2 dgisselq
        assign  dcdI = { {(8){r_dcdI[23]}}, r_dcdI };
658 36 dgisselq
        assign  w_opBnI = (~dcdB_rd) ? 32'h00
659
                        : (((wr_reg_ce)&&(wr_reg_id == dcdB)) ? wr_reg_vl
660
                        : (((dcdB_pc)&&(dcdB[4] == dcd_gie)) ? dcd_pc
661
                        : ((dcdB_pc) ? upc
662
                        : ((dcdB_cc) ? { w_opB[31:11], (dcd_gie)?w_uflags:w_iflags}
663
                        : regset[dcdB]))));
664 2 dgisselq
        always @(posedge i_clk)
665
                if (op_ce) // &&(dcdvalid))
666 36 dgisselq
                        r_opB <= w_opBnI + dcdI;
667 2 dgisselq
 
668
        // The logic here has become more complex than it should be, no thanks
669
        // to Xilinx's Vivado trying to help.  The conditions are supposed to
670
        // be two sets of four bits: the top bits specify what bits matter, the
671
        // bottom specify what those top bits must equal.  However, two of
672
        // conditions check whether bits are on, and those are the only two
673
        // conditions checking those bits.  Therefore, Vivado complains that
674
        // these two bits are redundant.  Hence the convoluted expression
675
        // below, arriving at what we finally want in the (now wire net)
676
        // opF.
677
        always @(posedge i_clk)
678
                if (op_ce)
679 36 dgisselq
                begin // Set the flag condition codes, bit order is [3:0]=VNCZ
680 2 dgisselq
                        case(dcdF[2:0])
681
                        3'h0:   r_opF <= 7'h80; // Always
682
                        3'h1:   r_opF <= 7'h11; // Z
683
                        3'h2:   r_opF <= 7'h10; // NE
684
                        3'h3:   r_opF <= 7'h20; // GE (!N)
685
                        3'h4:   r_opF <= 7'h30; // GT (!N&!Z)
686
                        3'h5:   r_opF <= 7'h24; // LT
687
                        3'h6:   r_opF <= 7'h02; // C
688
                        3'h7:   r_opF <= 7'h08; // V
689
                        endcase
690 36 dgisselq
                end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value }
691 2 dgisselq
        assign  opF = { r_opF[6], r_opF[3], r_opF[5], r_opF[1], r_opF[4:0] };
692
 
693 36 dgisselq
        initial opvalid     = 1'b0;
694
        initial opvalid_alu = 1'b0;
695
        initial opvalid_mem = 1'b0;
696 2 dgisselq
        always @(posedge i_clk)
697
                if (i_rst)
698 25 dgisselq
                begin
699
                        opvalid     <= 1'b0;
700
                        opvalid_alu <= 1'b0;
701
                        opvalid_mem <= 1'b0;
702
                end else if (op_ce)
703
                begin
704 2 dgisselq
                        // Do we have a valid instruction?
705
                        //   The decoder may vote to stall one of its
706
                        //   instructions based upon something we currently
707
                        //   have in our queue.  This instruction must then
708
                        //   move forward, and get a stall cycle inserted.
709
                        //   Hence, the test on dcd_stalled here.  If we must
710
                        //   wait until our operands are valid, then we aren't
711
                        //   valid yet until then.
712 18 dgisselq
                        opvalid<= (~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
713 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
714 36 dgisselq
                        opvalid_mem <= (dcdM)&&(~dcd_illegal)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
715
                        opvalid_alu <= ((~dcdM)||(dcd_illegal))&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
716
`else
717 25 dgisselq
                        opvalid_alu <= (~dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
718
                        opvalid_mem <= (dcdM)&&(~clear_pipeline)&&(dcdvalid)&&(~dcd_stalled);
719 36 dgisselq
`endif
720 25 dgisselq
                end else if ((~op_stall)||(clear_pipeline))
721
                begin
722
                        opvalid     <= 1'b0;
723
                        opvalid_alu <= 1'b0;
724
                        opvalid_mem <= 1'b0;
725
                end
726 2 dgisselq
 
727
        // Here's part of our debug interface.  When we recognize a break
728
        // instruction, we set the op_break flag.  That'll prevent this
729
        // instruction from entering the ALU, and cause an interrupt before
730
        // this instruction.  Thus, returning to this code will cause the
731
        // break to repeat and continue upon return.  To get out of this
732
        // condition, replace the break instruction with what it is supposed
733
        // to be, step through it, and then replace it back.  In this fashion,
734
        // a debugger can step through code.
735 25 dgisselq
        // assign w_op_break = (dcd_break)&&(r_dcdI[15:0] == 16'h0001);
736
        initial op_break = 1'b0;
737 2 dgisselq
        always @(posedge i_clk)
738 25 dgisselq
                if (i_rst)      op_break <= 1'b0;
739
                else if (op_ce) op_break <= (dcd_break);
740
                else if ((clear_pipeline)||(~opvalid))
741
                                op_break <= 1'b0;
742 2 dgisselq
 
743 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
744 2 dgisselq
        always @(posedge i_clk)
745 36 dgisselq
                if(op_ce)
746
                        op_illegal <= dcd_illegal;
747
`endif
748
 
749
        always @(posedge i_clk)
750 2 dgisselq
                if (op_ce)
751
                begin
752
                        opn    <= dcdOp;        // Which ALU operation?
753 25 dgisselq
                        // opM  <= dcdM;        // Is this a memory operation?
754 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
755 36 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr))&&(~dcd_early_branch);
756
                        opR_wr <= (dcdA_wr)&&(~dcd_early_branch);
757
`else
758 2 dgisselq
                        // Will we write the flags/CC Register with our result?
759 25 dgisselq
                        opF_wr <= (dcdF_wr)&&((~dcdA_cc)||(~dcdA_wr));
760 2 dgisselq
                        // Will we be writing our results into a register?
761
                        opR_wr <= dcdA_wr;
762 36 dgisselq
`endif
763 2 dgisselq
                        // What register will these results be written into?
764
                        opR    <= dcdA;
765 38 dgisselq
                        opR_cc <= (dcdA_wr)&&(dcdA_cc)&&(dcdA[4]==dcd_gie);
766 2 dgisselq
                        // User level (1), vs supervisor (0)/interrupts disabled
767
                        op_gie <= dcd_gie;
768
 
769
                        // We're not done with these yet--we still need them
770
                        // for the unclocked assign.  We need the unclocked
771
                        // assign so that there's no wait state between an
772
                        // ALU or memory result and the next register that may
773
                        // use that value.
774
                        opA_rd <= dcdA_rd;
775
                        opB_rd <= dcdB_rd;
776
                        op_pc  <= dcd_pc;
777
                        //
778 38 dgisselq
`ifdef  OPT_EARLY_BRANCHING
779 36 dgisselq
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie))&&(~dcd_early_branch);
780
`else
781 30 dgisselq
                        op_wr_pc <= ((dcdA_wr)&&(dcdA_pc)&&(dcdA[4] == dcd_gie));
782 36 dgisselq
`endif
783
 
784 38 dgisselq
`ifdef  OPT_PRECLEAR_BUS
785 36 dgisselq
                        op_clear_bus <= dcd_clear_bus;
786
`endif
787 2 dgisselq
                end
788
        assign  opFl = (op_gie)?(w_uflags):(w_iflags);
789
 
790
        // This is tricky.  First, the PC and Flags registers aren't kept in
791
        // register set but in special registers of their own.  So step one
792
        // is to select the right register.  Step to is to replace that
793
        // register with the results of an ALU or memory operation, if such
794
        // results are now available.  Otherwise, we'd need to insert a wait
795
        // state of some type.
796
        //
797
        // The alternative approach would be to define some sort of
798
        // op_stall wire, which would stall any upstream stage.
799
        // We'll create a flag here to start our coordination.  Once we
800
        // define this flag to something other than just plain zero, then
801
        // the stalls will already be in place.
802 25 dgisselq
        reg     opA_alu;
803
        always @(posedge i_clk)
804
                if (op_ce)
805
                        opA_alu <= (opvalid_alu)&&(opR == dcdA)&&(dcdA_rd);
806
        assign  opA = (opA_alu) ? alu_result : r_opA;
807
 
808
        assign  dcdA_stall = (dcdvalid)&&(dcdA_rd)&&(
809
                // Skip the requirement on writing back opA
810
                // Stall on memory, since we'll always need to stall for a 
811
                // memory access anyway
812
                                ((opvalid_mem)&&(opR_wr)&&(opR == dcdA))||
813 30 dgisselq
                                ((opvalid_alu)&&(opF_wr)&&(dcdA_cc))||
814 25 dgisselq
                                        ((mem_busy)&&(~mem_we)&&(mem_wreg == dcdA)));
815 36 dgisselq
 
816 25 dgisselq
        reg     opB_alu;
817
        always @(posedge i_clk)
818
                if (op_ce)
819
                        opB_alu <= (opvalid_alu)&&(opR == dcdB)&&(dcdB_rd)&&(dcdI == 0);
820
        assign  opB = (opB_alu) ? alu_result : r_opB;
821
        assign  dcdB_stall = (dcdvalid)&&(dcdB_rd)&&(
822 38 dgisselq
                                // Stall on memory ops writing to my register
823
                                //      (i.e. loads), or on any write to my
824
                                //      register if I have an immediate offset
825
                                // Note the exception for writing to the PC:
826
                                //      if I write to the PC, the whole next
827
                                //      instruction is invalid, not just the
828
                                //      operand.  That'll get wiped in the
829
                                //      next operation anyway, so don't stall
830
                                //      here.
831 25 dgisselq
                                ((opvalid)&&(opR_wr)&&(opR == dcdB)
832 38 dgisselq
                                        &&(opR != { op_gie, `CPU_PC_REG} )
833 30 dgisselq
                                        &&((opvalid_mem)||(dcdI != 0)))
834 38 dgisselq
                                // Stall on any write to the flags register,
835
                                // if we're going to need the flags value for
836
                                // opB.
837 30 dgisselq
                                ||((opvalid_alu)&&(opF_wr)&&(dcdB_cc))
838 38 dgisselq
                                // Stall on any ongoing memory operation that
839
                                // will write to opB
840 30 dgisselq
                                ||((mem_busy)&&(~mem_we)&&(mem_wreg == dcdB)));
841
        assign  dcdF_stall = (dcdvalid)&&((~dcdF[3])||(dcdA_cc)||(dcdB_cc))
842
                                        &&(opvalid)&&(opR_cc);
843 2 dgisselq
        //
844
        //
845
        //      PIPELINE STAGE #4 :: Apply Instruction
846
        //
847
        //
848
        cpuops  doalu(i_clk, i_rst, alu_ce,
849 25 dgisselq
                        (opvalid_alu), opn, opA, opB,
850 2 dgisselq
                        alu_result, alu_flags, alu_valid);
851
 
852
        assign  set_cond = ((opF[7:4]&opFl[3:0])==opF[3:0]);
853
        initial alF_wr   = 1'b0;
854
        initial alu_wr   = 1'b0;
855
        always @(posedge i_clk)
856
                if (i_rst)
857
                begin
858
                        alu_wr   <= 1'b0;
859
                        alF_wr   <= 1'b0;
860
                end else if (alu_ce)
861
                begin
862
                        alu_reg <= opR;
863
                        alu_wr  <= (opR_wr)&&(set_cond);
864
                        alF_wr  <= (opF_wr)&&(set_cond);
865
                end else begin
866
                        // These are strobe signals, so clear them if not
867
                        // set for any particular clock
868
                        alu_wr <= 1'b0;
869
                        alF_wr <= 1'b0;
870
                end
871
        always @(posedge i_clk)
872
                if ((alu_ce)||(mem_ce))
873
                        alu_gie  <= op_gie;
874
        always @(posedge i_clk)
875
                if ((alu_ce)||(mem_ce))
876
                        alu_pc  <= op_pc;
877 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
878
        always @(posedge i_clk)
879
                if ((alu_ce)||(mem_ce))
880
                        alu_illegal <= op_illegal;
881
`endif
882
 
883 2 dgisselq
        initial alu_pc_valid = 1'b0;
884
        always @(posedge i_clk)
885 38 dgisselq
                alu_pc_valid <= (~i_rst)&&(master_ce)&&(~mem_rdbusy)&&(opvalid)&&(~clear_pipeline)
886 25 dgisselq
                                        &&((opvalid_alu)||(~mem_stalled));
887 2 dgisselq
 
888 38 dgisselq
`ifdef  OPT_PIPELINED_BUS_ACCESS
889
        pipemem domem(i_clk, i_rst, mem_ce,
890
                                (opn[0]), opB, opA, opR,
891
                                mem_busy, mem_pipe_stalled,
892
                                mem_valid, bus_err, mem_wreg, mem_result,
893
                        mem_cyc_gbl, mem_cyc_lcl,
894
                                mem_stb_gbl, mem_stb_lcl,
895
                                mem_we, mem_addr, mem_data,
896
                                mem_ack, mem_stall, mem_err, i_wb_data);
897
 
898
`else // PIPELINED_BUS_ACCESS
899 2 dgisselq
        memops  domem(i_clk, i_rst, mem_ce,
900
                                (opn[0]), opB, opA, opR,
901 38 dgisselq
                                mem_busy,
902
                                mem_valid, bus_err, mem_wreg, mem_result,
903 36 dgisselq
                        mem_cyc_gbl, mem_cyc_lcl,
904
                                mem_stb_gbl, mem_stb_lcl,
905
                                mem_we, mem_addr, mem_data,
906
                                mem_ack, mem_stall, mem_err, i_wb_data);
907 38 dgisselq
`endif // PIPELINED_BUS_ACCESS
908 36 dgisselq
        assign  mem_rdbusy = (((mem_cyc_gbl)||(mem_cyc_lcl))&&(~mem_we));
909 2 dgisselq
 
910
        // Either the prefetch or the instruction gets the memory bus, but 
911
        // never both.
912 36 dgisselq
        wbdblpriarb     #(32,32) pformem(i_clk, i_rst,
913
                // Memory access to the arbiter, priority position
914
                mem_cyc_gbl, mem_cyc_lcl, mem_stb_gbl, mem_stb_lcl,
915
                        mem_we, mem_addr, mem_data, mem_ack, mem_stall, mem_err,
916 2 dgisselq
                // Prefetch access to the arbiter
917 36 dgisselq
                pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data,
918
                        pf_ack, pf_stall, pf_err,
919 2 dgisselq
                // Common wires, in and out, of the arbiter
920 36 dgisselq
                o_wb_gbl_cyc, o_wb_lcl_cyc, o_wb_gbl_stb, o_wb_lcl_stb,
921
                        o_wb_we, o_wb_addr, o_wb_data,
922
                        i_wb_ack, i_wb_stall, i_wb_err);
923 2 dgisselq
 
924
        //
925
        //
926
        //      PIPELINE STAGE #5 :: Write-back results
927
        //
928
        //
929
        // This stage is not allowed to stall.  If results are ready to be
930
        // written back, they are written back at all cost.  Sleepy CPU's
931
        // won't prevent write back, nor debug modes, halting the CPU, nor
932
        // anything else.  Indeed, the (master_ce) bit is only as relevant
933
        // as knowinig something is available for writeback.
934
 
935
        //
936
        // Write back to our generic register set ...
937
        // When shall we write back?  On one of two conditions
938
        //      Note that the flags needed to be checked before issuing the
939
        //      bus instruction, so they don't need to be checked here.
940
        //      Further, alu_wr includes (set_cond), so we don't need to
941
        //      check for that here either.
942 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
943 36 dgisselq
        assign  wr_reg_ce = (~alu_illegal)&&((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
944
`else
945
        assign  wr_reg_ce = ((alu_wr)&&(alu_valid)&&(~clear_pipeline))||(mem_valid);
946
`endif
947 2 dgisselq
        // Which register shall be written?
948 38 dgisselq
        //      COULD SIMPLIFY THIS: by adding three bits to these registers,
949
        //              One or PC, one for CC, and one for GIE match
950 2 dgisselq
        assign  wr_reg_id = (alu_wr)?alu_reg:mem_wreg;
951 25 dgisselq
        // Are we writing to the CC register?
952
        assign  wr_write_cc = (wr_reg_id[3:0] == `CPU_CC_REG);
953 2 dgisselq
        // Are we writing to the PC?
954
        assign  wr_write_pc = (wr_reg_id[3:0] == `CPU_PC_REG);
955
        // What value to write?
956
        assign  wr_reg_vl = (alu_wr)?alu_result:mem_result;
957
        always @(posedge i_clk)
958
                if (wr_reg_ce)
959
                        regset[wr_reg_id] <= wr_reg_vl;
960 18 dgisselq
                else if ((i_halt)&&(i_dbg_we))
961
                        regset[i_dbg_reg] <= i_dbg_data[31:0];
962 2 dgisselq
 
963
        //
964
        // Write back to the condition codes/flags register ...
965
        // When shall we write to our flags register?  alF_wr already
966
        // includes the set condition ...
967 36 dgisselq
        assign  wr_flags_ce = (alF_wr)&&(alu_valid)&&(~clear_pipeline)&&(~alu_illegal);
968 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
969 36 dgisselq
        assign  w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
970
        assign  w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
971
`else
972
        assign  w_uflags = { bus_err_flag, trap, ill_err, 1'b0, step, 1'b1, sleep, ((wr_flags_ce)&&(alu_gie))?alu_flags:flags };
973
        assign  w_iflags = { bus_err_flag, trap, ill_err, break_en, 1'b0, 1'b0, sleep, ((wr_flags_ce)&&(~alu_gie))?alu_flags:iflags };
974
`endif
975 2 dgisselq
        // What value to write?
976
        always @(posedge i_clk)
977
                // If explicitly writing the register itself
978 25 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_cc))
979 2 dgisselq
                        flags <= wr_reg_vl[3:0];
980
                // Otherwise if we're setting the flags from an ALU operation
981
                else if ((wr_flags_ce)&&(alu_gie))
982
                        flags <= alu_flags;
983
                else if ((i_halt)&&(i_dbg_we)
984
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
985
                        flags <= i_dbg_data[3:0];
986
 
987
        always @(posedge i_clk)
988 25 dgisselq
                if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
989 2 dgisselq
                        iflags <= wr_reg_vl[3:0];
990
                else if ((wr_flags_ce)&&(~alu_gie))
991
                        iflags <= alu_flags;
992
                else if ((i_halt)&&(i_dbg_we)
993
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
994
                        iflags <= i_dbg_data[3:0];
995
 
996
        // The 'break' enable  bit.  This bit can only be set from supervisor
997
        // mode.  It control what the CPU does upon encountering a break
998
        // instruction.
999
        //
1000
        // The goal, upon encountering a break is that the CPU should stop and
1001
        // not execute the break instruction, choosing instead to enter into
1002
        // either interrupt mode or halt first.  
1003
        //      if ((break_en) AND (break_instruction)) // user mode or not
1004
        //              HALT CPU
1005
        //      else if (break_instruction) // only in user mode
1006
        //              set an interrupt flag, go to supervisor mode
1007
        //              allow supervisor to step the CPU.
1008
        //      Upon a CPU halt, any break condition will be reset.  The
1009
        //      external debugger will then need to deal with whatever
1010
        //      condition has taken place.
1011
        initial break_en = 1'b0;
1012
        always @(posedge i_clk)
1013
                if ((i_rst)||(i_halt))
1014
                        break_en <= 1'b0;
1015 25 dgisselq
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_cc))
1016 2 dgisselq
                        break_en <= wr_reg_vl[`CPU_BREAK_BIT];
1017 34 dgisselq
                else if ((i_halt)&&(i_dbg_we)
1018
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG }))
1019
                        break_en <= i_dbg_data[`CPU_BREAK_BIT];
1020 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1021 36 dgisselq
        assign  o_break = ((break_en)||(~op_gie))&&(op_break)
1022
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1023
                                &&(~clear_pipeline)
1024
                        ||((~alu_gie)&&(bus_err))
1025
                        ||((~alu_gie)&&(alu_valid)&&(alu_illegal));
1026
`else
1027
        assign  o_break = (((break_en)||(~op_gie))&&(op_break)
1028
                                &&(~alu_valid)&&(~mem_valid)&&(~mem_busy)
1029
                                &&(~clear_pipeline))
1030 38 dgisselq
                        ||((~alu_gie)&&(bus_err));
1031 36 dgisselq
`endif
1032 2 dgisselq
 
1033
 
1034
        // The sleep register.  Setting the sleep register causes the CPU to
1035
        // sleep until the next interrupt.  Setting the sleep register within
1036
        // interrupt mode causes the processor to halt until a reset.  This is
1037 25 dgisselq
        // a panic/fault halt.  The trick is that you cannot be allowed to
1038
        // set the sleep bit and switch to supervisor mode in the same 
1039
        // instruction: users are not allowed to halt the CPU.
1040 2 dgisselq
        always @(posedge i_clk)
1041
                if ((i_rst)||((i_interrupt)&&(gie)))
1042
                        sleep <= 1'b0;
1043 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(~alu_gie))
1044
                        // In supervisor mode, we have no protections.  The
1045
                        // supervisor can set the sleep bit however he wants.
1046 2 dgisselq
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1047 25 dgisselq
                else if ((wr_reg_ce)&&(wr_write_cc)&&(wr_reg_vl[`CPU_GIE_BIT]))
1048
                        // In user mode, however, you can only set the sleep
1049
                        // mode while remaining in user mode.  You can't switch
1050
                        // to sleep mode *and* supervisor mode at the same
1051
                        // time, lest you halt the CPU.
1052
                        sleep <= wr_reg_vl[`CPU_SLEEP_BIT];
1053 2 dgisselq
                else if ((i_halt)&&(i_dbg_we)
1054
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
1055
                        sleep <= i_dbg_data[`CPU_SLEEP_BIT];
1056
 
1057
        always @(posedge i_clk)
1058
                if ((i_rst)||(w_switch_to_interrupt))
1059
                        step <= 1'b0;
1060 25 dgisselq
                else if ((wr_reg_ce)&&(~alu_gie)&&(wr_reg_id[4])&&(wr_write_cc))
1061 2 dgisselq
                        step <= wr_reg_vl[`CPU_STEP_BIT];
1062
                else if ((i_halt)&&(i_dbg_we)
1063
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG }))
1064
                        step <= i_dbg_data[`CPU_STEP_BIT];
1065 38 dgisselq
                else if ((alu_pc_valid)&&(step)&&(gie))
1066 2 dgisselq
                        step <= 1'b0;
1067
 
1068
        // The GIE register.  Only interrupts can disable the interrupt register
1069
        assign  w_switch_to_interrupt = (gie)&&(
1070
                        // On interrupt (obviously)
1071
                        (i_interrupt)
1072
                        // If we are stepping the CPU
1073 38 dgisselq
                        ||((alu_pc_valid)&&(step))
1074 2 dgisselq
                        // If we encounter a break instruction, if the break
1075 36 dgisselq
                        //      enable isn't set.
1076 38 dgisselq
                        ||((master_ce)&&(~mem_rdbusy)&&(op_break)&&(~break_en))
1077
`ifdef  OPT_ILLEGAL_INSTRUCTION
1078 36 dgisselq
                        // On an illegal instruction
1079
                        ||((alu_valid)&&(alu_illegal))
1080
`endif
1081 2 dgisselq
                        // If we write to the CC register
1082
                        ||((wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1083 25 dgisselq
                                &&(wr_reg_id[4])&&(wr_write_cc))
1084 2 dgisselq
                        // Or if, in debug mode, we write to the CC register
1085
                        ||((i_halt)&&(i_dbg_we)&&(~i_dbg_data[`CPU_GIE_BIT])
1086
                                &&(i_dbg_reg == { 1'b1, `CPU_CC_REG}))
1087
                        );
1088
        assign  w_release_from_interrupt = (~gie)&&(~i_interrupt)
1089
                        // Then if we write the CC register
1090
                        &&(((wr_reg_ce)&&(wr_reg_vl[`CPU_GIE_BIT])
1091 25 dgisselq
                                &&(~wr_reg_id[4])&&(wr_write_cc))
1092 2 dgisselq
                        // Or if, in debug mode, we write the CC register
1093
                          ||((i_halt)&&(i_dbg_we)&&(i_dbg_data[`CPU_GIE_BIT])
1094
                                &&(i_dbg_reg == { 1'b0, `CPU_CC_REG}))
1095
                        );
1096
        always @(posedge i_clk)
1097
                if (i_rst)
1098
                        gie <= 1'b0;
1099
                else if (w_switch_to_interrupt)
1100
                        gie <= 1'b0;
1101
                else if (w_release_from_interrupt)
1102
                        gie <= 1'b1;
1103
 
1104 25 dgisselq
        initial trap = 1'b0;
1105
        always @(posedge i_clk)
1106
                if (i_rst)
1107
                        trap <= 1'b0;
1108
                else if ((gie)&&(wr_reg_ce)&&(~wr_reg_vl[`CPU_GIE_BIT])
1109
                                &&(wr_reg_id[4])&&(wr_write_cc))
1110
                        trap <= 1'b1;
1111
                else if ((i_halt)&&(i_dbg_we)&&(i_dbg_reg[3:0] == `CPU_CC_REG)
1112
                                &&(~i_dbg_data[`CPU_GIE_BIT]))
1113
                        trap <= i_dbg_data[`CPU_TRAP_BIT];
1114
                else if (w_release_from_interrupt)
1115
                        trap <= 1'b0;
1116
 
1117 38 dgisselq
`ifdef  OPT_ILLEGAL_INSTRUCTION
1118 36 dgisselq
        initial ill_err = 1'b0;
1119
        always @(posedge i_clk)
1120
                if (i_rst)
1121
                        ill_err <= 1'b0;
1122
                else if (w_release_from_interrupt)
1123
                        ill_err <= 1'b0;
1124
                else if ((alu_valid)&&(alu_illegal)&&(gie))
1125
                        ill_err <= 1'b1;
1126 38 dgisselq
`else
1127
        assign ill_err = 1'b0;
1128 36 dgisselq
`endif
1129
        initial bus_err_flag = 1'b0;
1130
        always @(posedge i_clk)
1131
                if (i_rst)
1132
                        bus_err_flag <= 1'b0;
1133
                else if (w_release_from_interrupt)
1134
                        bus_err_flag <= 1'b0;
1135
                else if ((bus_err)&&(alu_gie))
1136
                        bus_err_flag <= 1'b1;
1137
 
1138 2 dgisselq
        //
1139
        // Write backs to the PC register, and general increments of it
1140
        //      We support two: upc and ipc.  If the instruction is normal,
1141
        // we increment upc, if interrupt level we increment ipc.  If
1142
        // the instruction writes the PC, we write whichever PC is appropriate.
1143
        //
1144
        // Do we need to all our partial results from the pipeline?
1145
        // What happens when the pipeline has gie and ~gie instructions within
1146
        // it?  Do we clear both?  What if a gie instruction tries to clear
1147
        // a non-gie instruction?
1148
        always @(posedge i_clk)
1149 9 dgisselq
                if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc))
1150 2 dgisselq
                        upc <= wr_reg_vl;
1151 36 dgisselq
                else if ((alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1152 2 dgisselq
                        upc <= alu_pc;
1153
                else if ((i_halt)&&(i_dbg_we)
1154
                                &&(i_dbg_reg == { 1'b1, `CPU_PC_REG }))
1155
                        upc <= i_dbg_data;
1156
 
1157
        always @(posedge i_clk)
1158
                if (i_rst)
1159
                        ipc <= RESET_ADDRESS;
1160
                else if ((wr_reg_ce)&&(~wr_reg_id[4])&&(wr_write_pc))
1161
                        ipc <= wr_reg_vl;
1162 36 dgisselq
                else if ((~alu_gie)&&(alu_pc_valid)&&(~clear_pipeline))
1163 2 dgisselq
                        ipc <= alu_pc;
1164
                else if ((i_halt)&&(i_dbg_we)
1165
                                &&(i_dbg_reg == { 1'b0, `CPU_PC_REG }))
1166
                        ipc <= i_dbg_data;
1167
 
1168
        always @(posedge i_clk)
1169
                if (i_rst)
1170
                        pf_pc <= RESET_ADDRESS;
1171
                else if (w_switch_to_interrupt)
1172
                        pf_pc <= ipc;
1173
                else if (w_release_from_interrupt)
1174
                        pf_pc <= upc;
1175
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1176
                        pf_pc <= wr_reg_vl;
1177
                else if ((i_halt)&&(i_dbg_we)
1178 34 dgisselq
                                &&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
1179 2 dgisselq
                        pf_pc <= i_dbg_data;
1180
                else if (dcd_ce)
1181
                        pf_pc <= pf_pc + 1;
1182
 
1183
        initial new_pc = 1'b1;
1184
        always @(posedge i_clk)
1185 18 dgisselq
                if ((i_rst)||(i_clear_pf_cache))
1186 2 dgisselq
                        new_pc <= 1'b1;
1187
                else if (w_switch_to_interrupt)
1188
                        new_pc <= 1'b1;
1189
                else if (w_release_from_interrupt)
1190
                        new_pc <= 1'b1;
1191
                else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc))
1192
                        new_pc <= 1'b1;
1193
                else if ((i_halt)&&(i_dbg_we)
1194 34 dgisselq
                                &&(i_dbg_reg[4:0] == { gie, `CPU_PC_REG}))
1195 2 dgisselq
                        new_pc <= 1'b1;
1196
                else
1197
                        new_pc <= 1'b0;
1198
 
1199
        //
1200
        // The debug interface
1201
        always @(posedge i_clk)
1202
                begin
1203
                        o_dbg_reg <= regset[i_dbg_reg];
1204
                        if (i_dbg_reg[3:0] == `CPU_PC_REG)
1205
                                o_dbg_reg <= (i_dbg_reg[4])?upc:ipc;
1206
                        else if (i_dbg_reg[3:0] == `CPU_CC_REG)
1207 36 dgisselq
                                o_dbg_reg[10:0] <= (i_dbg_reg[4])?w_uflags:w_iflags;
1208 2 dgisselq
                end
1209
        always @(posedge i_clk)
1210 25 dgisselq
                o_dbg_cc <= { gie, sleep };
1211 18 dgisselq
 
1212
        always @(posedge i_clk)
1213 25 dgisselq
                o_dbg_stall <= (i_halt)&&(
1214 36 dgisselq
                        (pf_cyc)||(mem_cyc_gbl)||(mem_cyc_lcl)||(mem_busy)
1215 2 dgisselq
                        ||((~opvalid)&&(~i_rst))
1216 25 dgisselq
                        ||((~dcdvalid)&&(~i_rst)));
1217 2 dgisselq
 
1218
        //
1219
        //
1220
        // Produce accounting outputs: Account for any CPU stalls, so we can
1221
        // later evaluate how well we are doing.
1222
        //
1223
        //
1224 9 dgisselq
        assign  o_op_stall = (master_ce)&&((~opvalid)||(op_stall));
1225
        assign  o_pf_stall = (master_ce)&&(~pf_valid);
1226 38 dgisselq
        assign  o_i_count  = (alu_pc_valid)&&(~clear_pipeline);
1227 2 dgisselq
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.