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[/] [zipcpu/] [trunk/] [rtl/] [ex/] [fwb_counter.v] - Blame information for rev 209

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1 209 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    fwb_counter.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2017-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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//
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module  fwb_counter(i_clk, i_reset,
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                // The Wishbone bus
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                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
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                        i_wb_ack, i_wb_stall, i_wb_idata, i_wb_err,
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                // Some convenience output parameters
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                f_nreqs, f_nacks, f_outstanding);
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        parameter               AW=32, DW=32;
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        parameter               F_MAX_STALL = 0,
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                                F_MAX_ACK_DELAY = 0;
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        parameter               F_LGDEPTH = 4;
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        parameter [(F_LGDEPTH-1):0] F_MAX_REQUESTS = 0;
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        //
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        // If true, allow the bus to be kept open when there are no outstanding
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        // requests.  This is useful for any master that might execute a
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        // read modify write cycle, such as an atomic add.
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        parameter [0:0]           F_OPT_RMW_BUS_OPTION = 1;
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        //
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        // 
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        // If true, allow the bus to issue multiple discontinuous requests.
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        // Unlike F_OPT_RMW_BUS_OPTION, these requests may be issued while other
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        // requests are outstanding
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        parameter       [0:0]     F_OPT_DISCONTINUOUS = 0;
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        //
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        //
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        // If true, insist that there be a minimum of a single clock delay
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        // between request and response.  This defaults to off since the
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        // wishbone specification specifically doesn't require this.  However,
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        // some interfaces do, so we allow it as an option here.
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        parameter       [0:0]     F_OPT_MINCLOCK_DELAY = 0;
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        //
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        //
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        localparam [(F_LGDEPTH-1):0] MAX_OUTSTANDING = {(F_LGDEPTH){1'b1}};
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        localparam      MAX_DELAY = (F_MAX_STALL > F_MAX_ACK_DELAY)
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                                ? F_MAX_STALL : F_MAX_ACK_DELAY;
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        localparam      DLYBITS= (MAX_DELAY < 4) ? 2
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                                : ((MAX_DELAY <    16) ? 4
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                                : ((MAX_DELAY <    64) ? 6
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                                : ((MAX_DELAY <   256) ? 8
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                                : ((MAX_DELAY <  1024) ? 10
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                                : ((MAX_DELAY <  4096) ? 12
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                                : ((MAX_DELAY < 16384) ? 14
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                                : ((MAX_DELAY < 65536) ? 16
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                                : 32)))))));
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        //
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        input   wire                    i_clk, i_reset;
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        // Input/master bus
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        input   wire                    i_wb_cyc, i_wb_stb, i_wb_we;
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        input   wire    [(AW-1):0]       i_wb_addr;
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        input   wire    [(DW-1):0]       i_wb_data;
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        input   wire    [(DW/8-1):0]     i_wb_sel;
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        //
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        input   wire                    i_wb_ack;
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        input   wire                    i_wb_stall;
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        input   wire    [(DW-1):0]       i_wb_idata;
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        input   wire                    i_wb_err;
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        //
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        output  reg     [(F_LGDEPTH-1):0]        f_nreqs, f_nacks;
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        output  wire    [(F_LGDEPTH-1):0]        f_outstanding;
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        //
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        // Let's just make sure our parameters are set up right
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        //
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        always @(*)
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                assert(F_MAX_REQUESTS < {(F_LGDEPTH){1'b1}});
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        //
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        //
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        // Bus requests
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        //
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        //
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        //
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        // Count the number of requests that have been received
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        //
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        initial f_nreqs = 0;
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        always @(posedge i_clk)
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        if ((i_reset)||(!i_wb_cyc))
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                f_nreqs <= 0;
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        else if ((i_wb_stb)&&(!i_wb_stall))
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                f_nreqs <= f_nreqs + 1'b1;
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        //
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        // Count the number of acknowledgements that have been returned
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        //
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        initial f_nacks = 0;
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        always @(posedge i_clk)
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        if (i_reset)
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                f_nacks <= 0;
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        else if (!i_wb_cyc)
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                f_nacks <= 0;
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        else if ((i_wb_ack)||(i_wb_err))
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                f_nacks <= f_nacks + 1'b1;
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        //
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        // The number of outstanding requests is the difference between
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        // the number of requests and the number of acknowledgements
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        //
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        assign  f_outstanding = (i_wb_cyc) ? (f_nreqs - f_nacks):0;
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endmodule

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