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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: fwb_master.v
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose: This file describes the rules of a wishbone interaction from the
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// perspective of a wishbone master. These formal rules may be used
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// with yosys-smtbmc to *prove* that the master properly handles outgoing
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// transactions and incoming responses.
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//
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// This module contains no functional logic. It is intended for formal
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// verification only. The outputs returned, the number of requests that
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// have been made, the number of acknowledgements received, and the number
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// of outstanding requests, are designed for further formal verification
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// purposes *only*.
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//
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// This file is different from a companion formal_slave.v file in that the
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// assertions are made on the outputs of the wishbone master: o_wb_cyc,
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// o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, and o_wb_sel, while only
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// assumptions are made about the inputs: i_wb_stall, i_wb_ack, i_wb_data,
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// i_wb_err. In the formal_slave.v, assumptions are made about the
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// slave inputs (the master outputs), and assertions are made about the
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// slave outputs (the master inputs).
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//
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// In order to make it easier to compare the slave against the master,
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// assumptions with respect to the slave have been marked with the
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// `SLAVE_ASSUME macro. Similarly, assertions the slave would make have
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// been marked with `SLAVE_ASSERT. This allows the master to redefine
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// these two macros to be from his perspective, and therefore the
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// diffs between the two files actually show true differences, rather
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// than just these differences in perspective.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2017-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype none
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//
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module fwb_master(i_clk, i_reset,
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// The Wishbone bus
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
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i_wb_ack, i_wb_stall, i_wb_idata, i_wb_err,
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// Some convenience output parameters
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f_nreqs, f_nacks, f_outstanding);
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parameter AW=32, DW=32;
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parameter F_MAX_STALL = 0,
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F_MAX_ACK_DELAY = 0;
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parameter F_LGDEPTH = 4;
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parameter [(F_LGDEPTH-1):0] F_MAX_REQUESTS = 0;
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//
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// If true, allow the bus to be kept open when there are no outstanding
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// requests. This is useful for any master that might execute a
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// read modify write cycle, such as an atomic add.
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parameter [0:0] F_OPT_RMW_BUS_OPTION = 1;
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//
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//
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parameter [0:0] F_OPT_SHORT_CIRCUIT_PROOF = 0;
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//
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// If this is the source of a request, then we can assume STB and CYC
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// will initially start out high. Master interfaces following the
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// source on the way to the slave may not have this property
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parameter [0:0] F_OPT_SOURCE = 0;
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//
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// If true, allow the bus to issue multiple discontinuous requests.
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// Unlike F_OPT_RMW_BUS_OPTION, these requests may be issued while other
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// requests are outstanding
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parameter [0:0] F_OPT_DISCONTINUOUS = 0;
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//
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//
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// If true, insist that there be a minimum of a single clock delay
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// between request and response. This defaults to off since the
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// wishbone specification specifically doesn't require this. However,
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// some interfaces do, so we allow it as an option here.
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parameter [0:0] F_OPT_MINCLOCK_DELAY = 0;
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//
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//
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localparam [(F_LGDEPTH-1):0] MAX_OUTSTANDING = {(F_LGDEPTH){1'b1}};
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localparam MAX_DELAY = (F_MAX_STALL > F_MAX_ACK_DELAY)
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? F_MAX_STALL : F_MAX_ACK_DELAY;
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localparam DLYBITS= (MAX_DELAY < 4) ? 2
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: ((MAX_DELAY < 16) ? 4
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: ((MAX_DELAY < 64) ? 6
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: ((MAX_DELAY < 256) ? 8
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: ((MAX_DELAY < 1024) ? 10
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: ((MAX_DELAY < 4096) ? 12
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: ((MAX_DELAY < 16384) ? 14
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: ((MAX_DELAY < 65536) ? 16
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: 32)))))));
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//
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input wire i_clk, i_reset;
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// Input/master bus
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input wire i_wb_cyc, i_wb_stb, i_wb_we;
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input wire [(AW-1):0] i_wb_addr;
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input wire [(DW-1):0] i_wb_data;
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input wire [(DW/8-1):0] i_wb_sel;
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//
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input wire i_wb_ack;
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input wire i_wb_stall;
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input wire [(DW-1):0] i_wb_idata;
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input wire i_wb_err;
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//
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output reg [(F_LGDEPTH-1):0] f_nreqs, f_nacks;
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output wire [(F_LGDEPTH-1):0] f_outstanding;
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`define SLAVE_ASSUME assert
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`define SLAVE_ASSERT assume
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//
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// Let's just make sure our parameters are set up right
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//
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initial assert(F_MAX_REQUESTS < {(F_LGDEPTH){1'b1}});
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//
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// Wrap the request line in a bundle. The top bit, named STB_BIT,
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// is the bit indicating whether the request described by this vector
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// is a valid request or not.
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//
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localparam STB_BIT = 2+AW+DW+DW/8-1;
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wire [STB_BIT:0] f_request;
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assign f_request = { i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel };
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//
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// A quick register to be used later to know if the $past() operator
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// will yield valid result
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reg f_past_valid;
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initial f_past_valid = 1'b0;
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always @(posedge i_clk)
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f_past_valid <= 1'b1;
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always @(*)
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if (!f_past_valid)
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`SLAVE_ASSUME(i_reset);
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//
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//
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// Assertions regarding the initial (and reset) state
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//
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//
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//
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// Assume we start from a reset condition
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initial assert(i_reset);
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initial `SLAVE_ASSUME(!i_wb_cyc);
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initial `SLAVE_ASSUME(!i_wb_stb);
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//
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initial `SLAVE_ASSERT(!i_wb_ack);
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initial `SLAVE_ASSERT(!i_wb_err);
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always @(posedge i_clk)
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if ((!f_past_valid)||($past(i_reset)))
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begin
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`SLAVE_ASSUME(!i_wb_cyc);
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`SLAVE_ASSUME(!i_wb_stb);
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//
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`SLAVE_ASSERT(!i_wb_ack);
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`SLAVE_ASSERT(!i_wb_err);
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end
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always @(*)
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if (!f_past_valid)
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`SLAVE_ASSUME(!i_wb_cyc);
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//
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//
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// Bus requests
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//
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//
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// Following any bus error, the CYC line should be dropped to abort
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// the transaction
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always @(posedge i_clk)
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if ((f_past_valid)&&($past(i_wb_err))&&($past(i_wb_cyc)))
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`SLAVE_ASSUME(!i_wb_cyc);
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// STB can only be true if CYC is also true
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always @(*)
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if (i_wb_stb)
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`SLAVE_ASSUME(i_wb_cyc);
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// If a request was both outstanding and stalled on the last clock,
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// then nothing should change on this clock regarding it.
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wb_stb))
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&&($past(i_wb_stall))&&(i_wb_cyc))
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begin
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`SLAVE_ASSUME(i_wb_stb);
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`SLAVE_ASSUME(i_wb_we == $past(i_wb_we));
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`SLAVE_ASSUME(i_wb_addr == $past(i_wb_addr));
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`SLAVE_ASSUME(i_wb_sel == $past(i_wb_sel));
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if (i_wb_we)
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`SLAVE_ASSUME(i_wb_data == $past(i_wb_data));
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end
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// Within any series of STB/requests, the direction of the request
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// may not change.
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always @(posedge i_clk)
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if ((f_past_valid)&&($past(i_wb_stb))&&(i_wb_stb))
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`SLAVE_ASSUME(i_wb_we == $past(i_wb_we));
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// Within any given bus cycle, the direction may *only* change when
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// there are no further outstanding requests.
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always @(posedge i_clk)
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if ((f_past_valid)&&(f_outstanding > 0))
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`SLAVE_ASSUME(i_wb_we == $past(i_wb_we));
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// Write requests must also set one (or more) of i_wb_sel
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// always @(*)
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// if ((i_wb_stb)&&(i_wb_we))
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// `SLAVE_ASSUME(|i_wb_sel);
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//
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//
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// Bus responses
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//
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//
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// If CYC was low on the last clock, then both ACK and ERR should be
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// low on this clock.
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_wb_cyc))&&(!i_wb_cyc))
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begin
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`SLAVE_ASSERT(!i_wb_ack);
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`SLAVE_ASSERT(!i_wb_err);
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// Stall may still be true--such as when we are not
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// selected at some arbiter between us and the slave
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end
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//
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// Any time the CYC line drops, it is possible that there may be a
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// remaining (registered) ACK or ERR that hasn't yet been returned.
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// Restrict such out of band returns so that they are *only* returned
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// if there is an outstanding operation.
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always @(posedge i_clk)
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if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wb_cyc))&&(!i_wb_cyc))
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begin
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if (($past(f_outstanding == 0))
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&&((!$past(i_wb_stb && !i_wb_stall))
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||($past(i_wb_ack|i_wb_err))))
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begin
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`SLAVE_ASSERT(!i_wb_ack);
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`SLAVE_ASSERT(!i_wb_err);
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end
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end
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// ACK and ERR may never both be true at the same time
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always @(*)
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`SLAVE_ASSERT((!i_wb_ack)||(!i_wb_err));
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generate if (F_MAX_STALL > 0)
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begin : MXSTALL
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//
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// Assume the slave cannnot stall for more than F_MAX_STALL
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// counts. We'll count this forward any time STB and STALL
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// are both true.
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//
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reg [(DLYBITS-1):0] f_stall_count;
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| 284 |
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initial f_stall_count = 0;
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always @(posedge i_clk)
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if ((!i_reset)&&(i_wb_stb)&&(i_wb_stall))
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f_stall_count <= f_stall_count + 1'b1;
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else
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f_stall_count <= 0;
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| 291 |
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always @(*)
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if (i_wb_cyc)
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`SLAVE_ASSERT(f_stall_count < F_MAX_STALL);
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end endgenerate
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generate if (F_MAX_ACK_DELAY > 0)
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begin : MXWAIT
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//
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| 299 |
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// Assume the slave will respond within F_MAX_ACK_DELAY cycles,
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| 300 |
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// counted either from the end of the last request, or from the
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| 301 |
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// last ACK received
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//
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| 303 |
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reg [(DLYBITS-1):0] f_ackwait_count;
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| 304 |
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| 305 |
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initial f_ackwait_count = 0;
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always @(posedge i_clk)
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if ((!i_reset)&&(i_wb_cyc)&&(!i_wb_stb)
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&&(!i_wb_ack)&&(!i_wb_err)
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&&(f_outstanding > 0))
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f_ackwait_count <= f_ackwait_count + 1'b1;
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else
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f_ackwait_count <= 0;
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| 314 |
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always @(*)
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if ((!i_reset)&&(i_wb_cyc)&&(!i_wb_stb)
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&&(!i_wb_ack)&&(!i_wb_err)
|
| 317 |
|
|
&&(f_outstanding > 0))
|
| 318 |
|
|
`SLAVE_ASSERT(f_ackwait_count < F_MAX_ACK_DELAY);
|
| 319 |
|
|
end endgenerate
|
| 320 |
|
|
|
| 321 |
|
|
//
|
| 322 |
|
|
// Count the number of requests that have been made
|
| 323 |
|
|
//
|
| 324 |
|
|
initial f_nreqs = 0;
|
| 325 |
|
|
always @(posedge i_clk)
|
| 326 |
|
|
if ((i_reset)||(!i_wb_cyc))
|
| 327 |
|
|
f_nreqs <= 0;
|
| 328 |
|
|
else if ((i_wb_stb)&&(!i_wb_stall))
|
| 329 |
|
|
f_nreqs <= f_nreqs + 1'b1;
|
| 330 |
|
|
|
| 331 |
|
|
|
| 332 |
|
|
//
|
| 333 |
|
|
// Count the number of acknowledgements that have been received
|
| 334 |
|
|
//
|
| 335 |
|
|
initial f_nacks = 0;
|
| 336 |
|
|
always @(posedge i_clk)
|
| 337 |
|
|
if (i_reset)
|
| 338 |
|
|
f_nacks <= 0;
|
| 339 |
|
|
else if (!i_wb_cyc)
|
| 340 |
|
|
f_nacks <= 0;
|
| 341 |
|
|
else if ((i_wb_ack)||(i_wb_err))
|
| 342 |
|
|
f_nacks <= f_nacks + 1'b1;
|
| 343 |
|
|
|
| 344 |
|
|
//
|
| 345 |
|
|
// The number of outstanding requests is the difference between
|
| 346 |
|
|
// the number of requests and the number of acknowledgements
|
| 347 |
|
|
//
|
| 348 |
|
|
assign f_outstanding = (i_wb_cyc) ? (f_nreqs - f_nacks):0;
|
| 349 |
|
|
|
| 350 |
|
|
always @(*)
|
| 351 |
|
|
if ((i_wb_cyc)&&(F_MAX_REQUESTS > 0))
|
| 352 |
|
|
begin
|
| 353 |
|
|
if (i_wb_stb)
|
| 354 |
|
|
`SLAVE_ASSUME(f_nreqs < F_MAX_REQUESTS);
|
| 355 |
|
|
else
|
| 356 |
|
|
`SLAVE_ASSUME(f_nreqs <= F_MAX_REQUESTS);
|
| 357 |
|
|
`SLAVE_ASSERT(f_nacks <= f_nreqs);
|
| 358 |
|
|
assert(f_outstanding < (1<<F_LGDEPTH)-1);
|
| 359 |
|
|
end else
|
| 360 |
|
|
assume(f_outstanding < (1<<F_LGDEPTH)-1);
|
| 361 |
|
|
|
| 362 |
|
|
always @(*)
|
| 363 |
|
|
if ((i_wb_cyc)&&(f_outstanding == 0))
|
| 364 |
|
|
begin
|
| 365 |
|
|
// If nothing is outstanding, then there should be
|
| 366 |
|
|
// no acknowledgements ... however, an acknowledgement
|
| 367 |
|
|
// *can* come back on the same clock as the stb is
|
| 368 |
|
|
// going out.
|
| 369 |
|
|
if (F_OPT_MINCLOCK_DELAY)
|
| 370 |
|
|
begin
|
| 371 |
|
|
`SLAVE_ASSERT(!i_wb_ack);
|
| 372 |
|
|
`SLAVE_ASSERT(!i_wb_err);
|
| 373 |
|
|
end else begin
|
| 374 |
|
|
`SLAVE_ASSERT((!i_wb_ack)||((i_wb_stb)&&(!i_wb_stall)));
|
| 375 |
|
|
// The same is true of errors. They may not be
|
| 376 |
|
|
// created before the request gets through
|
| 377 |
|
|
`SLAVE_ASSERT((!i_wb_err)||((i_wb_stb)&&(!i_wb_stall)));
|
| 378 |
|
|
end
|
| 379 |
|
|
end
|
| 380 |
|
|
|
| 381 |
|
|
generate if (F_OPT_SOURCE)
|
| 382 |
|
|
begin : SRC
|
| 383 |
|
|
// Any opening bus request starts with both CYC and STB high
|
| 384 |
|
|
// This is true for the master only, and more specifically
|
| 385 |
|
|
// only for those masters that are the initial source of any
|
| 386 |
|
|
// transaction. By the time an interaction gets to the slave,
|
| 387 |
|
|
// the CYC line may go high or low without actually affecting
|
| 388 |
|
|
// the STB line of the slave.
|
| 389 |
|
|
always @(posedge i_clk)
|
| 390 |
|
|
if ((f_past_valid)&&(!$past(i_wb_cyc))&&(i_wb_cyc))
|
| 391 |
|
|
`SLAVE_ASSUME(i_wb_stb);
|
| 392 |
|
|
end endgenerate
|
| 393 |
|
|
|
| 394 |
|
|
|
| 395 |
|
|
generate if (!F_OPT_RMW_BUS_OPTION)
|
| 396 |
|
|
begin
|
| 397 |
|
|
// If we aren't waiting for anything, and we aren't issuing
|
| 398 |
|
|
// any requests, then then our transaction is over and we
|
| 399 |
|
|
// should be dropping the CYC line.
|
| 400 |
|
|
always @(*)
|
| 401 |
|
|
if (f_outstanding == 0)
|
| 402 |
|
|
`SLAVE_ASSUME((i_wb_stb)||(!i_wb_cyc));
|
| 403 |
|
|
// Not all masters will abide by this restriction. Some
|
| 404 |
|
|
// masters may wish to implement read-modify-write bus
|
| 405 |
|
|
// interactions. These masters need to keep CYC high between
|
| 406 |
|
|
// transactions, even though nothing is outstanding. For
|
| 407 |
|
|
// these busses, turn F_OPT_RMW_BUS_OPTION on.
|
| 408 |
|
|
end endgenerate
|
| 409 |
|
|
|
| 410 |
|
|
generate if (F_OPT_SHORT_CIRCUIT_PROOF)
|
| 411 |
|
|
begin
|
| 412 |
|
|
// In many ways, we don't care what happens on the bus return
|
| 413 |
|
|
// lines if the cycle line is low, so restricting them to a
|
| 414 |
|
|
// known value makes a lot of sense.
|
| 415 |
|
|
//
|
| 416 |
|
|
// On the other hand, if something above *does* depend upon
|
| 417 |
|
|
// these values (when it shouldn't), then we might want to know
|
| 418 |
|
|
// about it.
|
| 419 |
|
|
//
|
| 420 |
|
|
//
|
| 421 |
|
|
always @(posedge i_clk)
|
| 422 |
|
|
begin
|
| 423 |
|
|
if (!i_wb_cyc)
|
| 424 |
|
|
begin
|
| 425 |
|
|
assume(!i_wb_stall);
|
| 426 |
|
|
assume($stable(i_wb_idata));
|
| 427 |
|
|
end else if ((!$past(i_wb_ack))&&(!i_wb_ack))
|
| 428 |
|
|
assume($stable(i_wb_idata));
|
| 429 |
|
|
end
|
| 430 |
|
|
end endgenerate
|
| 431 |
|
|
|
| 432 |
|
|
generate if ((!F_OPT_DISCONTINUOUS)&&(!F_OPT_RMW_BUS_OPTION))
|
| 433 |
|
|
begin : INSIST_ON_NO_DISCONTINUOUS_STBS
|
| 434 |
|
|
// Within my own code, once a request begins it goes to
|
| 435 |
|
|
// completion and the CYC line is dropped. The master
|
| 436 |
|
|
// is not allowed to raise STB again after dropping it.
|
| 437 |
|
|
// Doing so would be a *discontinuous* request.
|
| 438 |
|
|
//
|
| 439 |
|
|
// However, in any RMW scheme, discontinuous requests are
|
| 440 |
|
|
// necessary, and the spec doesn't disallow them. Hence we
|
| 441 |
|
|
// make this check optional.
|
| 442 |
|
|
always @(posedge i_clk)
|
| 443 |
|
|
if ((f_past_valid)&&($past(i_wb_cyc))&&(!$past(i_wb_stb)))
|
| 444 |
|
|
`SLAVE_ASSUME(!i_wb_stb);
|
| 445 |
|
|
end endgenerate
|
| 446 |
|
|
|
| 447 |
|
|
endmodule
|
