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[/] [zipcpu/] [trunk/] [rtl/] [ex/] [wbpriarbiter.v] - Blame information for rev 209

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1 209 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    wbpriarbiter.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     This is a priority bus arbiter.  It allows two separate wishbone
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//              masters to connect to the same bus, while also guaranteeing
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//      that one master can have the bus with no delay any time the other
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//      master is not using the bus.  The goal is to eliminate the combinatorial
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//      logic required in the other wishbone arbiter, while still guarateeing
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//      access time for the priority channel.
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//
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//      The core logic works like this:
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//
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//      1. When no one requests the bus, 'A' is granted the bus and guaranteed
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//              that any access will go right through.
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//      2. If 'B' requests the bus (asserts cyc), and the bus is idle, then
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//              'B' will be granted the bus.
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//      3. Bus grants last as long as the 'cyc' line is high.
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//      4. Once 'cyc' is dropped, the bus returns to 'A' as the owner.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015,2018-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype        none
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//
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module  wbpriarbiter(i_clk,
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        // Bus A
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        i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, o_a_ack, o_a_stall, o_a_err,
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        // Bus B
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        i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, o_b_ack, o_b_stall, o_b_err,
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        // Both buses
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        o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, i_ack, i_stall, i_err);
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        parameter                       DW=32, AW=32;
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        //
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        // ZERO_ON_IDLE uses more logic than the alternative.  It should be
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        // useful for reducing power, as these circuits tend to drive wires
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        // all the way across the design, but it may also slow down the master
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        // clock.  I've used it as an option when using VERILATOR, 'cause
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        // zeroing things on idle can make them stand out all the more when
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        // staring at wires and dumps and such.
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        parameter       [0:0]             OPT_ZERO_ON_IDLE = 1'b0;
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        //
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        input   wire                    i_clk;
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        // Bus A
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        input   wire                    i_a_cyc, i_a_stb, i_a_we;
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        input   wire    [(AW-1):0]       i_a_adr;
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        input   wire    [(DW-1):0]       i_a_dat;
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        input   wire    [(DW/8-1):0]     i_a_sel;
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        output  wire                    o_a_ack, o_a_stall, o_a_err;
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        // Bus B
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        input   wire                    i_b_cyc, i_b_stb, i_b_we;
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        input   wire    [(AW-1):0]       i_b_adr;
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        input   wire    [(DW-1):0]       i_b_dat;
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        input   wire    [(DW/8-1):0]     i_b_sel;
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        output  wire                    o_b_ack, o_b_stall, o_b_err;
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        //
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        output  wire                    o_cyc, o_stb, o_we;
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        output  wire    [(AW-1):0]       o_adr;
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        output  wire    [(DW-1):0]       o_dat;
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        output  wire    [(DW/8-1):0]     o_sel;
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        input   wire                    i_ack, i_stall, i_err;
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        // Go high immediately (new cycle) if ...
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        //      Previous cycle was low and *someone* is requesting a bus cycle
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        // Go low immadiately if ...
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        //      We were just high and the owner no longer wants the bus
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        // WISHBONE Spec recommends no logic between a FF and the o_cyc
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        //      This violates that spec.  (Rec 3.15, p35)
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        reg     r_a_owner;
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        initial r_a_owner = 1'b1;
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        always @(posedge i_clk)
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                if (!i_b_cyc)
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                        r_a_owner <= 1'b1;
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                // Allow B to set its CYC line w/o activating this interface
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                else if ((i_b_cyc)&&(i_b_stb)&&(!i_a_cyc))
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                        r_a_owner <= 1'b0;
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        // Realistically, if neither master owns the bus, the output is a
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        // don't care.  Thus we trigger off whether or not 'A' owns the bus.
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        // If 'B' owns it all we care is that 'A' does not.  Likewise, if
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        // neither owns the bus than the values on these various lines are
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        // irrelevant.
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        assign o_cyc = (r_a_owner) ? i_a_cyc : i_b_cyc;
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        assign o_we  = (r_a_owner) ? i_a_we  : i_b_we;
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        assign o_stb   = (r_a_owner) ? i_a_stb   : i_b_stb;
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        generate if (OPT_ZERO_ON_IDLE)
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        begin
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                assign  o_adr     = (o_stb)?((r_a_owner) ? i_a_adr  : i_b_adr):0;
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                assign  o_dat     = (o_stb)?((r_a_owner) ? i_a_dat  : i_b_dat):0;
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                assign  o_sel     = (o_stb)?((r_a_owner) ? i_a_sel  : i_b_sel):0;
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                assign  o_a_ack   = (o_cyc)&&( r_a_owner) ? i_ack   : 1'b0;
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                assign  o_b_ack   = (o_cyc)&&(!r_a_owner) ? i_ack   : 1'b0;
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                assign  o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1;
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                assign  o_b_stall = (o_cyc)&&(!r_a_owner) ? i_stall : 1'b1;
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                assign  o_a_err   = (o_cyc)&&( r_a_owner) ? i_err : 1'b0;
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                assign  o_b_err   = (o_cyc)&&(!r_a_owner) ? i_err : 1'b0;
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        end else begin
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                assign o_adr   = (r_a_owner) ? i_a_adr   : i_b_adr;
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                assign o_dat   = (r_a_owner) ? i_a_dat   : i_b_dat;
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                assign o_sel   = (r_a_owner) ? i_a_sel   : i_b_sel;
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                // We cannot allow the return acknowledgement to ever go high if
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                // the master in question does not own the bus.  Hence we force it
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                // low if the particular master doesn't own the bus.
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                assign  o_a_ack   = ( r_a_owner) ? i_ack   : 1'b0;
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                assign  o_b_ack   = (!r_a_owner) ? i_ack   : 1'b0;
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                // Stall must be asserted on the same cycle the input master asserts
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                // the bus, if the bus isn't granted to him.
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                assign  o_a_stall = ( r_a_owner) ? i_stall : 1'b1;
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                assign  o_b_stall = (!r_a_owner) ? i_stall : 1'b1;
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                //
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                //
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                assign  o_a_err = ( r_a_owner) ? i_err : 1'b0;
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                assign  o_b_err = (!r_a_owner) ? i_err : 1'b0;
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        end endgenerate
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`ifdef  FORMAL
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`ifdef  WBPRIARBITER
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`define ASSUME  assume
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`else
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`define ASSUME  assert
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`endif
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        reg     f_past_valid;
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        initial f_past_valid = 1'b0;
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        always @(posedge i_clk)
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                f_past_valid <= 1'b1;
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        initial assume(!i_a_cyc);
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        initial assume(!i_a_stb);
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        initial assume(!i_b_cyc);
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        initial assume(!i_b_stb);
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        initial assume(!i_ack);
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        initial assume(!i_err);
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        always @(posedge i_clk)
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        begin
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                if (o_cyc)
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                        assert((i_a_cyc)||(i_b_cyc));
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                if ((f_past_valid)&&($past(o_cyc))&&(o_cyc))
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                        assert($past(r_a_owner) == r_a_owner);
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                if ((f_past_valid)&&($past(!o_cyc))&&($past(i_a_stb)))
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                        assert(r_a_owner);
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                if ((f_past_valid)&&($past(!o_cyc))&&($past(i_b_stb)))
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                        assert(!r_a_owner);
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        end
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        reg     f_reset;
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        initial f_reset = 1'b1;
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        always @(posedge i_clk)
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                f_reset <= 1'b0;
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        always @(*)
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                if (!f_past_valid)
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                        assert(f_reset);
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        parameter       F_LGDEPTH=3;
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        wire    [(F_LGDEPTH-1):0]        f_nreqs, f_nacks, f_outstanding,
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                        f_a_nreqs, f_a_nacks, f_a_outstanding,
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                        f_b_nreqs, f_b_nacks, f_b_outstanding;
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        fwb_master #(.F_MAX_STALL(0),
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                        .F_LGDEPTH(F_LGDEPTH),
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                        .F_MAX_ACK_DELAY(0),
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                        .F_OPT_RMW_BUS_OPTION(1),
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                        .F_OPT_DISCONTINUOUS(1))
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                f_wbm(i_clk, f_reset,
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                        o_cyc, o_stb, o_we, o_adr, o_dat, o_sel,
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                        i_ack, i_stall, 32'h0, i_err,
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                        f_nreqs, f_nacks, f_outstanding);
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        fwb_slave  #(.F_MAX_STALL(0),
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                        .F_LGDEPTH(F_LGDEPTH),
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                        .F_MAX_ACK_DELAY(0),
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                        .F_OPT_RMW_BUS_OPTION(1),
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                        .F_OPT_DISCONTINUOUS(1))
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                f_wba(i_clk, f_reset,
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                        i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel,
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                        o_a_ack, o_a_stall, 32'h0, o_a_err,
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                        f_a_nreqs, f_a_nacks, f_a_outstanding);
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        fwb_slave  #(.F_MAX_STALL(0),
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                        .F_LGDEPTH(F_LGDEPTH),
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                        .F_MAX_ACK_DELAY(0),
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                        .F_OPT_RMW_BUS_OPTION(1),
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                        .F_OPT_DISCONTINUOUS(1))
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                f_wbb(i_clk, f_reset,
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                        i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel,
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                        o_b_ack, o_b_stall, 32'h0, o_b_err,
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                        f_b_nreqs, f_b_nacks, f_b_outstanding);
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        always @(posedge i_clk)
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                if (r_a_owner)
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                begin
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                        assert(f_b_nreqs == 0);
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                        assert(f_b_nacks == 0);
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                        assert(f_a_outstanding == f_outstanding);
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                end else begin
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                        assert(f_a_nreqs == 0);
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                        assert(f_a_nacks == 0);
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                        assert(f_b_outstanding == f_outstanding);
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                end
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        always @(posedge i_clk)
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                if ((r_a_owner)&&(i_b_cyc))
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                        assume(i_b_stb);
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        always @(posedge i_clk)
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                if ((r_a_owner)&&(i_a_cyc))
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                        assume(i_a_stb);
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`endif
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endmodule

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