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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [wbdmac.v] - Blame information for rev 209

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1 36 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    wbdmac.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     Wishbone DMA controller
8
//
9
//      This module is controllable via the wishbone, and moves values from
10
//      one location in the wishbone address space to another.  The amount of
11
//      memory moved at any given time can be up to 4kB, or equivalently 1kW.
12
//      Four registers control this DMA controller: a control/status register,
13
//      a length register, a source WB address and a destination WB address.
14
//      These register may be read at any time, but they may only be written
15
//      to when the controller is idle.
16
//
17
//      The meanings of three of the setup registers should be self explanatory:
18
//              - The length register controls the total number of words to
19
//                      transfer.
20
//              - The source address register controls where the DMA controller
21
//                      reads from.  This address may or may not be incremented
22
//                      after each read, depending upon the setting in the
23
//                      control/status register.
24
//              - The destination address register, which controls where the DMA
25
//                      controller writes to.  This address may or may not be
26
//                      incremented after each write, also depending upon the
27
//                      setting in the control/status register.
28
//
29
//      It is the control/status register, at local address zero, that needs
30
//      more definition:
31
//
32
//      Bits:
33
//      31      R       Write protect   If this is set to one, it means the
34
//                              write protect bit is set and the controller
35
//                              is therefore idle.  This bit will be set upon
36
//                              completing any transfer.
37
//      30      R       Error.          The controller stopped mid-transfer
38
//                                      after receiving a bus error.
39
//      29      R/W     inc_s_n         If set to one, the source address
40
//                              will not increment from one read to the next.
41
//      28      R/W     inc_d_n         If set to one, the destination address
42
//                              will not increment from one write to the next.
43
//      27      R       Always 0
44
//      26..16  R       nread           Indicates how many words have been read,
45
//                              and not necessarily written (yet).  This
46
//                              combined with the cfg_len parameter should tell
47
//                              exactly where the controller is at mid-transfer.
48
//      27..16  W       WriteProtect    When a 12'h3db is written to these
49
//                              bits, the write protect bit will be cleared.
50
//                              
51
//      15      R/W     on_dev_trigger  When set to '1', the controller will
52
//                              wait for an external interrupt before starting.
53
//      14..10  R/W     device_id       This determines which external interrupt
54
//                              will trigger a transfer.
55
//      9..0    R/W     transfer_len    How many bytes to transfer at one time.
56
//                              The minimum transfer length is one, while zero
57
//                              is mapped to a transfer length of 1kW.
58
//
59 209 dgisselq
//      Write 32'hffed00 to halt an ongoing transaction, completing anything
60
//      remaining, or 32'hafed00 to abort the current transaction leaving
61
//      any unfinished read/write in an undetermined state.
62 36 dgisselq
//
63 209 dgisselq
//
64 36 dgisselq
//      To use this, follow this checklist:
65
//      1. Wait for any prior DMA operation to complete
66
//              (Read address 0, wait 'till either top bit is set or cfg_len==0)
67
//      2. Write values into length, source and destination address. 
68
//              (writei(3, &vals) should be sufficient for this.)
69
//      3. Enable the DMAC interrupt in whatever interrupt controller is present
70
//              on the system.
71
//      4. Write the final start command to the setup/control/status register:
72
//              Set inc_s_n, inc_d_n, on_dev_trigger, dev_trigger,
73
//                      appropriately for your task
74
//              Write 12'h3db to the upper word.
75
//              Set the lower word to either all zeros, or a smaller transfer
76
//              length if desired.
77
//      5. wait() for the interrupt and the operation to complete.
78
//              Prior to completion, number of items successfully transferred
79
//              be read from the length register.  If the internal buffer is
80
//              being used, then you can read how much has been read into that
81
//              buffer by reading from bits 25..16 of this control/status
82
//              register.
83
//
84 201 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
85 69 dgisselq
//              Gisselquist Technology, LLC
86 36 dgisselq
//
87
////////////////////////////////////////////////////////////////////////////////
88
//
89 209 dgisselq
// Copyright (C) 2015-2019, Gisselquist Technology, LLC
90 36 dgisselq
//
91
// This program is free software (firmware): you can redistribute it and/or
92
// modify it under the terms of  the GNU General Public License as published
93
// by the Free Software Foundation, either version 3 of the License, or (at
94
// your option) any later version.
95
//
96
// This program is distributed in the hope that it will be useful, but WITHOUT
97
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
98
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
99
// for more details.
100
//
101 201 dgisselq
// You should have received a copy of the GNU General Public License along
102
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
103
// target there if the PDF file isn't present.)  If not, see
104
// <http://www.gnu.org/licenses/> for a copy.
105
//
106 36 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
107
//              http://www.gnu.org/licenses/gpl.html
108
//
109
//
110 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
111 36 dgisselq
//
112
//
113 160 dgisselq
`define DMA_IDLE        3'b000
114
`define DMA_WAIT        3'b001
115
`define DMA_READ_REQ    3'b010
116
`define DMA_READ_ACK    3'b011
117
`define DMA_PRE_WRITE   3'b100
118
`define DMA_WRITE_REQ   3'b101
119
`define DMA_WRITE_ACK   3'b110
120
 
121 209 dgisselq
module wbdmac(i_clk, i_reset,
122 36 dgisselq
                i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
123
                        o_swb_ack, o_swb_stall, o_swb_data,
124
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
125
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
126
                i_dev_ints,
127 69 dgisselq
                o_interrupt);
128 209 dgisselq
        parameter       ADDRESS_WIDTH=30, LGMEMLEN = 10, DW=32;
129
        localparam      LGDV=5;
130
        localparam      AW=ADDRESS_WIDTH;
131
        input   wire            i_clk, i_reset;
132 36 dgisselq
        // Slave/control wishbone inputs
133 209 dgisselq
        input   wire            i_swb_cyc, i_swb_stb, i_swb_we;
134
        input   wire    [1:0]    i_swb_addr;
135
        input   wire [(DW-1):0]  i_swb_data;
136 36 dgisselq
        // Slave/control wishbone outputs
137
        output  reg             o_swb_ack;
138
        output  wire            o_swb_stall;
139
        output  reg [(DW-1):0]   o_swb_data;
140
        // Master/DMA wishbone control
141 160 dgisselq
        output  wire            o_mwb_cyc, o_mwb_stb, o_mwb_we;
142 48 dgisselq
        output  reg [(AW-1):0]   o_mwb_addr;
143
        output  reg [(DW-1):0]   o_mwb_data;
144 36 dgisselq
        // Master/DMA wishbone responses from the bus
145 209 dgisselq
        input   wire            i_mwb_ack, i_mwb_stall;
146
        input   wire [(DW-1):0]  i_mwb_data;
147
        input   wire            i_mwb_err;
148 36 dgisselq
        // The interrupt device interrupt lines
149 209 dgisselq
        input   wire [(DW-1):0]  i_dev_ints;
150 36 dgisselq
        // An interrupt to be set upon completion
151
        output  reg             o_interrupt;
152
        // Need to release the bus for a higher priority user
153 69 dgisselq
        //      This logic had lots of problems, so it is being
154
        //      removed.  If you want to make sure the bus is available
155
        //      for a higher priority user, adjust the transfer length
156
        //      accordingly.
157
        //
158
        // input                        i_other_busmaster_requests_bus;
159
        //
160 36 dgisselq
 
161 209 dgisselq
        wire    s_cyc, s_stb, s_we;
162
        wire    [1:0]    s_addr;
163
        wire    [31:0]   s_data;
164
`define DELAY_ACCESS
165
`ifdef  DELAY_ACCESS
166
        reg     r_s_cyc, r_s_stb, r_s_we;
167
        reg     [1:0]    r_s_addr;
168
        reg     [31:0]   r_s_data;
169 36 dgisselq
 
170 209 dgisselq
        always @(posedge i_clk)
171
                r_s_cyc <= i_swb_cyc;
172
        always @(posedge i_clk)
173
        if (i_reset)
174
                r_s_stb <= 1'b0;
175
        else
176
                r_s_stb <= i_swb_stb;
177
        always @(posedge i_clk)
178
                r_s_we  <= i_swb_we;
179
        always @(posedge i_clk)
180
                r_s_addr<= i_swb_addr;
181
        always @(posedge i_clk)
182
                r_s_data<= i_swb_data;
183
 
184
        assign  s_cyc = r_s_cyc;
185
        assign  s_stb = r_s_stb;
186
        assign  s_we  = r_s_we;
187
        assign  s_addr= r_s_addr;
188
        assign  s_data= r_s_data;
189
`else
190
        assign  s_cyc = i_swb_cyc;
191
        assign  s_stb = i_swb_stb;
192
        assign  s_we  = i_swb_we;
193
        assign  s_addr= i_swb_addr;
194
        assign  s_data= i_swb_data;
195
`endif
196
 
197 160 dgisselq
        reg     [2:0]            dma_state;
198
        reg                     cfg_err, cfg_len_nonzero;
199 48 dgisselq
        reg     [(AW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
200 36 dgisselq
        reg [(LGMEMLEN-1):0]     cfg_blocklen_sub_one;
201
        reg                     cfg_incs, cfg_incd;
202
        reg     [(LGDV-1):0]     cfg_dev_trigger;
203
        reg                     cfg_on_dev_trigger;
204
 
205
        // Single block operations: We'll read, then write, up to a single
206
        // memory block here.
207
 
208
        reg     [(DW-1):0]       dma_mem [0:(((1<<LGMEMLEN))-1)];
209 160 dgisselq
        reg     [(LGMEMLEN):0]   nread, nwritten, nwacks, nracks;
210
        wire    [(AW-1):0]       bus_nracks;
211
        assign  bus_nracks = { {(AW-LGMEMLEN-1){1'b0}}, nracks };
212 36 dgisselq
 
213 160 dgisselq
        reg     last_read_request, last_read_ack,
214
                last_write_request, last_write_ack;
215 201 dgisselq
        reg     trigger, abort, user_halt;
216 160 dgisselq
 
217
        initial dma_state = `DMA_IDLE;
218 36 dgisselq
        initial o_interrupt = 1'b0;
219
        initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
220
        initial cfg_on_dev_trigger = 1'b0;
221
        always @(posedge i_clk)
222 209 dgisselq
        if (i_reset)
223
        begin
224
                dma_state <= `DMA_IDLE;
225
                cfg_on_dev_trigger <= 1'b0;
226
                cfg_incs  <= 1'b0;
227
                cfg_incd  <= 1'b0;
228
        end else case(dma_state)
229 160 dgisselq
        `DMA_IDLE: begin
230
                o_mwb_addr <= cfg_raddr;
231
 
232
                // When the slave wishbone writes, and we are in this 
233
                // (ready) configuration, then allow the DMA to be controlled
234
                // and thus to start.
235 209 dgisselq
                if ((s_stb)&&(s_we))
236 36 dgisselq
                begin
237 209 dgisselq
                        case(s_addr)
238 160 dgisselq
                        2'b00: begin
239 209 dgisselq
                                if ((s_data[27:16] == 12'hfed)
240
                                        &&(s_data[31:30] == 2'b00)
241 160 dgisselq
                                                &&(cfg_len_nonzero))
242
                                        dma_state <= `DMA_WAIT;
243
                                cfg_blocklen_sub_one
244 209 dgisselq
                                        <= s_data[(LGMEMLEN-1):0]
245 160 dgisselq
                                        + {(LGMEMLEN){1'b1}};
246
                                        // i.e. -1;
247 209 dgisselq
                                cfg_dev_trigger    <= s_data[14:10];
248
                                cfg_on_dev_trigger <= s_data[15];
249
                                cfg_incs  <= !s_data[29];
250
                                cfg_incd  <= !s_data[28];
251 36 dgisselq
                                end
252 209 dgisselq
                        2'b01: begin end // This is done elsewhere
253
                        2'b10: cfg_raddr <=  s_data[(AW+2-1):2];
254
                        2'b11: cfg_waddr <=  s_data[(AW+2-1):2];
255 160 dgisselq
                        endcase
256
                end end
257
        `DMA_WAIT: begin
258
                o_mwb_addr <= cfg_raddr;
259
                if (abort)
260
                        dma_state <= `DMA_IDLE;
261 201 dgisselq
                else if (user_halt)
262
                        dma_state <= `DMA_IDLE;
263 160 dgisselq
                else if (trigger)
264
                        dma_state <= `DMA_READ_REQ;
265
                end
266
        `DMA_READ_REQ: begin
267 209 dgisselq
                if (!i_mwb_stall)
268 36 dgisselq
                begin
269 160 dgisselq
                        // Number of read acknowledgements needed
270 209 dgisselq
                        if ((last_read_request)||(user_halt))
271 160 dgisselq
        //((nracks == {1'b0, cfg_blocklen_sub_one})||(bus_nracks == cfg_len-1))
272
                                // Wishbone interruptus
273
                                dma_state <= `DMA_READ_ACK;
274
                        if (cfg_incs)
275
                                o_mwb_addr <= o_mwb_addr
276
                                                + {{(AW-1){1'b0}},1'b1};
277
                end
278
 
279 209 dgisselq
                if ((i_mwb_err)||(abort))
280 160 dgisselq
                        dma_state <= `DMA_IDLE;
281 209 dgisselq
                else if (i_mwb_ack)
282 160 dgisselq
                begin
283
                        if (cfg_incs)
284
                                cfg_raddr  <= cfg_raddr
285
                                                + {{(AW-1){1'b0}},1'b1};
286 209 dgisselq
                        if (last_read_ack)
287
                                dma_state <= `DMA_PRE_WRITE;
288 160 dgisselq
                end end
289
        `DMA_READ_ACK: begin
290 209 dgisselq
                if ((i_mwb_err)||(abort))
291 160 dgisselq
                        dma_state <= `DMA_IDLE;
292 209 dgisselq
                else if (i_mwb_ack)
293 160 dgisselq
                begin
294
                        if (last_read_ack) // (nread+1 == nracks)
295
                                dma_state  <= `DMA_PRE_WRITE;
296 201 dgisselq
                        if (user_halt)
297
                                dma_state <= `DMA_IDLE;
298 160 dgisselq
                        if (cfg_incs)
299
                                cfg_raddr  <= cfg_raddr
300
                                                + {{(AW-1){1'b0}},1'b1};
301
                end
302
                end
303
        `DMA_PRE_WRITE: begin
304
                o_mwb_addr <= cfg_waddr;
305
                dma_state <= (abort)?`DMA_IDLE:`DMA_WRITE_REQ;
306
                end
307
        `DMA_WRITE_REQ: begin
308 209 dgisselq
                if (!i_mwb_stall)
309 160 dgisselq
                begin
310
                        if (last_write_request) // (nwritten == nread-1)
311
                                // Wishbone interruptus
312
                                dma_state <= `DMA_WRITE_ACK;
313
                        if (cfg_incd)
314 36 dgisselq
                        begin
315 160 dgisselq
                                o_mwb_addr <= o_mwb_addr
316
                                                + {{(AW-1){1'b0}},1'b1};
317
                                cfg_waddr  <= cfg_waddr
318
                                                + {{(AW-1){1'b0}},1'b1};
319 36 dgisselq
                        end
320 160 dgisselq
                end
321 36 dgisselq
 
322 209 dgisselq
                if ((i_mwb_err)||(abort))
323 160 dgisselq
                        dma_state <= `DMA_IDLE;
324 209 dgisselq
                else if ((i_mwb_ack)&&(last_write_ack))
325
                        dma_state <= (cfg_len <= 1)?`DMA_IDLE:`DMA_WAIT;
326
                else if (!cfg_len_nonzero)
327 160 dgisselq
                        dma_state <= `DMA_IDLE;
328
                end
329
        `DMA_WRITE_ACK: begin
330 209 dgisselq
                if ((i_mwb_err)||(abort))
331 160 dgisselq
                        dma_state <= `DMA_IDLE;
332 209 dgisselq
                else if ((i_mwb_ack)&&(last_write_ack))
333
                        // (nwacks+1 == nwritten)
334
                        dma_state <= (cfg_len <= 1)?`DMA_IDLE:`DMA_WAIT;
335
                else if (!cfg_len_nonzero)
336 160 dgisselq
                        dma_state <= `DMA_IDLE;
337
                end
338
        default:
339
                dma_state <= `DMA_IDLE;
340
        endcase
341
 
342
        initial o_interrupt = 1'b0;
343
        always @(posedge i_clk)
344 209 dgisselq
        if (i_reset)
345
                o_interrupt <= 1'b0;
346
        else
347 201 dgisselq
                o_interrupt <= ((dma_state == `DMA_WRITE_ACK)&&(i_mwb_ack)
348
                                        &&(last_write_ack)
349
                                        &&(cfg_len == {{(AW-1){1'b0}},1'b1}))
350
                                ||((dma_state != `DMA_IDLE)&&(i_mwb_err));
351 160 dgisselq
 
352 209 dgisselq
 
353
        initial cfg_len     = 0;
354
        initial cfg_len_nonzero = 1'b0;
355
        always @(posedge i_clk)
356
        if (i_reset)
357
        begin
358
                cfg_len <= 0;
359
                cfg_len_nonzero <= 1'b0;
360
        end else if ((dma_state == `DMA_IDLE)
361
                        &&(s_stb)&&(s_we)&&(s_addr == 2'b01))
362
        begin
363
                cfg_len   <=  s_data[(AW-1):0];
364
                cfg_len_nonzero <= (|s_data[(AW-1):0]);
365
        end else if ((o_mwb_cyc)&&(o_mwb_we)&&(i_mwb_ack))
366
        begin
367
                cfg_len <= cfg_len - 1'b1;
368
                cfg_len_nonzero <= (cfg_len > 1);
369
        end
370
 
371
        initial nracks   = 0;
372
        always @(posedge i_clk)
373
        if (i_reset)
374
                nracks <= 0;
375
        else if ((dma_state == `DMA_IDLE)||(dma_state == `DMA_WAIT))
376
                nracks <= 0;
377
        else if ((o_mwb_stb)&&(!o_mwb_we)&&(!i_mwb_stall))
378
                nracks <= nracks + 1'b1;
379
 
380
        initial nread   = 0;
381
        always @(posedge i_clk)
382
        if (i_reset)
383
                nread <= 0;
384
        else if ((dma_state == `DMA_IDLE)||(dma_state == `DMA_WAIT))
385
                nread <= 0;
386
        else if ((!o_mwb_we)&&(i_mwb_ack))
387
                nread <= nread + 1'b1;
388
 
389
        initial nwritten = 0;
390
        always @(posedge i_clk)
391
        if (i_reset)
392
                nwritten <= 0;
393
        else if ((!o_mwb_cyc)||(!o_mwb_we))
394
                nwritten <= 0;
395
        else if ((o_mwb_stb)&&(!i_mwb_stall))
396
                nwritten <= nwritten + 1'b1;
397
 
398
        initial nwacks   = 0;
399
        always @(posedge i_clk)
400
        if (i_reset)
401
                nwacks <= 0;
402
        else if ((!o_mwb_cyc)||(!o_mwb_we))
403
                nwacks <= 0;
404
        else if (i_mwb_ack)
405
                nwacks <= nwacks + 1'b1;
406
 
407 160 dgisselq
        initial cfg_err = 1'b0;
408
        always @(posedge i_clk)
409 209 dgisselq
        if (i_reset)
410
                cfg_err <= 1'b0;
411
        else if (dma_state == `DMA_IDLE)
412
        begin
413
                if ((s_stb)&&(s_we)&&(s_addr==2'b00))
414
                        cfg_err <= 1'b0;
415
        end else if (((i_mwb_err)&&(o_mwb_cyc))||(abort))
416
                cfg_err <= 1'b1;
417 160 dgisselq
 
418
        initial last_read_request = 1'b0;
419
        always @(posedge i_clk)
420 209 dgisselq
        if (i_reset)
421
                last_read_request <= 1'b0;
422
        else if ((dma_state == `DMA_WAIT)||(dma_state == `DMA_READ_REQ))
423
        begin
424
                if ((!i_mwb_stall)&&(dma_state == `DMA_READ_REQ))
425 160 dgisselq
                begin
426 209 dgisselq
                        last_read_request <=
427
                        (nracks + 1 == { 1'b0, cfg_blocklen_sub_one})
428
                                ||(bus_nracks == cfg_len-2);
429 160 dgisselq
                end else
430 209 dgisselq
                        last_read_request <=
431
                                (nracks== { 1'b0, cfg_blocklen_sub_one})
432
                                ||(bus_nracks == cfg_len-1);
433
        end else
434
                last_read_request <= 1'b0;
435 160 dgisselq
 
436 209 dgisselq
 
437
        wire    [(LGMEMLEN):0]   next_nread;
438
        assign  next_nread = nread + 1'b1;
439
 
440 160 dgisselq
        initial last_read_ack = 1'b0;
441
        always @(posedge i_clk)
442 209 dgisselq
        if (i_reset)
443
                last_read_ack <= 0;
444
        else if (dma_state == `DMA_READ_REQ)
445
        begin
446
                if ((i_mwb_ack)&&((!o_mwb_stb)||(i_mwb_stall)))
447
                        last_read_ack <= (next_nread == { 1'b0, cfg_blocklen_sub_one });
448
                else
449
                        last_read_ack <= (nread == { 1'b0, cfg_blocklen_sub_one });
450
        end else if (dma_state == `DMA_READ_ACK)
451
        begin
452
                if ((i_mwb_ack)&&((!o_mwb_stb)||(i_mwb_stall)))
453
                        last_read_ack <= (nread+2 == nracks);
454
                else
455
                        last_read_ack <= (next_nread == nracks);
456
        end else
457
                last_read_ack <= 1'b0;
458 160 dgisselq
 
459
        initial last_write_request = 1'b0;
460
        always @(posedge i_clk)
461 209 dgisselq
        if (i_reset)
462
                last_write_request <= 1'b0;
463
        else if (dma_state == `DMA_PRE_WRITE)
464
                last_write_request <= (nread <= 1);
465
        else if (dma_state == `DMA_WRITE_REQ)
466
        begin
467
                if (i_mwb_stall)
468
                        last_write_request <= (nwritten >= nread-1);
469
                else
470
                        last_write_request <= (nwritten >= nread-2);
471
        end else
472
                last_write_request <= 1'b0;
473 160 dgisselq
 
474
        initial last_write_ack = 1'b0;
475
        always @(posedge i_clk)
476 209 dgisselq
        if (i_reset)
477
                last_write_ack <= 1'b0;
478
        else if((dma_state == `DMA_WRITE_REQ)||(dma_state == `DMA_WRITE_ACK))
479
        begin
480
                if ((i_mwb_ack)&&((!o_mwb_stb)||(i_mwb_stall)))
481
                        last_write_ack <= (nwacks+2 == nwritten);
482
                else
483
                        last_write_ack <= (nwacks+1 == nwritten);
484
        end else
485
                last_write_ack <= 1'b0;
486 160 dgisselq
 
487 209 dgisselq
 
488 160 dgisselq
        assign  o_mwb_cyc = (dma_state == `DMA_READ_REQ)
489
                        ||(dma_state == `DMA_READ_ACK)
490
                        ||(dma_state == `DMA_WRITE_REQ)
491
                        ||(dma_state == `DMA_WRITE_ACK);
492
 
493
        assign  o_mwb_stb = (dma_state == `DMA_READ_REQ)
494
                        ||(dma_state == `DMA_WRITE_REQ);
495
 
496
        assign  o_mwb_we = (dma_state == `DMA_PRE_WRITE)
497
                        ||(dma_state == `DMA_WRITE_REQ)
498
                        ||(dma_state == `DMA_WRITE_ACK);
499
 
500 36 dgisselq
        //
501
        // This is tricky.  In order for Vivado to consider dma_mem to be a 
502
        // proper memory, it must have a simple address fed into it.  Hence
503
        // the read_address (rdaddr) register.  The problem is that this
504
        // register must always be one greater than the address we actually
505
        // want to read from, unless we are idling.  So ... the math is touchy.
506
        //
507
        reg     [(LGMEMLEN-1):0] rdaddr;
508 209 dgisselq
 
509
        initial rdaddr = 0;
510 36 dgisselq
        always @(posedge i_clk)
511 209 dgisselq
        if (i_reset)
512
                rdaddr <= 0;
513
        else if((dma_state == `DMA_IDLE)||(dma_state == `DMA_WAIT)
514
                        ||(dma_state == `DMA_WRITE_ACK))
515
                rdaddr <= 0;
516
        else if ((dma_state == `DMA_PRE_WRITE)
517
                        ||((dma_state==`DMA_WRITE_REQ)&&(!i_mwb_stall)))
518
                rdaddr <= rdaddr + {{(LGMEMLEN-1){1'b0}},1'b1};
519
 
520 36 dgisselq
        always @(posedge i_clk)
521 209 dgisselq
        if (i_reset)
522
                o_mwb_data <= 0;
523
        else if ((dma_state != `DMA_WRITE_REQ)||(!i_mwb_stall))
524
                o_mwb_data <= dma_mem[rdaddr];
525 36 dgisselq
        always @(posedge i_clk)
526 160 dgisselq
                if((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK))
527 36 dgisselq
                        dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
528
 
529
        always @(posedge i_clk)
530 209 dgisselq
        if (i_reset)
531
                o_swb_data <= 0;
532
        else casez(s_addr)
533 160 dgisselq
                2'b00: o_swb_data <= {  (dma_state != `DMA_IDLE), cfg_err,
534 209 dgisselq
                                        !cfg_incs, !cfg_incd,
535 36 dgisselq
                                        1'b0, nread,
536
                                        cfg_on_dev_trigger, cfg_dev_trigger,
537
                                        cfg_blocklen_sub_one
538
                                        };
539 48 dgisselq
                2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len  };
540 209 dgisselq
                2'b10: o_swb_data <= { {(DW-2-AW){1'b0}}, cfg_raddr, 2'b00 };
541
                2'b11: o_swb_data <= { {(DW-2-AW){1'b0}}, cfg_waddr, 2'b00 };
542
        endcase
543 36 dgisselq
 
544 160 dgisselq
        // This causes us to wait a minimum of two clocks before starting: One
545
        // to go into the wait state, and then one while in the wait state to
546
        // develop the trigger.
547
        initial trigger = 1'b0;
548 36 dgisselq
        always @(posedge i_clk)
549 209 dgisselq
        if (i_reset)
550
                trigger <= 1'b0;
551
        else
552 160 dgisselq
                trigger <=  (dma_state == `DMA_WAIT)
553 209 dgisselq
                                &&((!cfg_on_dev_trigger)
554 160 dgisselq
                                        ||(i_dev_ints[cfg_dev_trigger]));
555 36 dgisselq
 
556 160 dgisselq
        // Ack any access.  We'll quietly ignore any access where we are busy,
557
        // but ack it anyway.  In other words, before writing to the device,
558
        // double check that it isn't busy, and then write.
559 209 dgisselq
        initial o_swb_ack = 1'b0;
560 160 dgisselq
        always @(posedge i_clk)
561 209 dgisselq
        if (i_reset)
562
                o_swb_ack <= 1'b0;
563
        else if (!i_swb_cyc)
564
                o_swb_ack <= 1'b0;
565
        else
566
                o_swb_ack <= (s_stb);
567 160 dgisselq
 
568 36 dgisselq
        assign  o_swb_stall = 1'b0;
569
 
570 160 dgisselq
        initial abort = 1'b0;
571
        always @(posedge i_clk)
572 209 dgisselq
        if (i_reset)
573
                abort <= 1'b0;
574
        else if (dma_state == `DMA_IDLE)
575
                abort <= 1'b0;
576
        else
577
                abort <= ((s_stb)&&(s_we)
578
                        &&(s_addr == 2'b00)
579
                        &&(s_data == 32'hffed0000));
580 160 dgisselq
 
581 201 dgisselq
        initial user_halt = 1'b0;
582
        always @(posedge i_clk)
583
                user_halt <= ((user_halt)&&(dma_state != `DMA_IDLE))
584 209 dgisselq
                        ||((s_stb)&&(s_we)&&(dma_state != `DMA_IDLE)
585
                                &&(s_addr == 2'b00)
586
                                &&(s_data == 32'hafed0000));
587 201 dgisselq
 
588 209 dgisselq
 
589
        // Make verilator happy
590
        // verilator lint_off UNUSED
591
        wire    unused;
592
        assign  unused = s_cyc;
593
        // verilator lint_on  UNUSED
594
`ifdef  FORMAL
595
        reg     f_past_valid;
596
        initial f_past_valid = 1'b0;
597
        always @(posedge i_clk)
598
                f_past_valid <= 1'b1;
599
 
600
        always @(*)
601
        if (!f_past_valid)
602
                assume(i_reset);
603
 
604
        always @(posedge i_clk)
605
        if ((!f_past_valid)||($past(i_reset)))
606
                assert(dma_state == `DMA_IDLE);
607
 
608
        parameter       F_SLV_LGDEPTH = 3;
609
        parameter       F_MSTR_LGDEPTH = LGMEMLEN+1;
610
 
611
        wire [F_SLV_LGDEPTH-1:0] f_swb_nreqs, f_swb_nacks, f_swb_outstanding;
612
        wire [F_MSTR_LGDEPTH-1:0] f_mwb_nreqs, f_mwb_nacks, f_mwb_outstanding;
613
 
614
        fwb_slave #(
615
                .AW(2), .DW(32), .F_MAX_STALL(0), .F_MAX_ACK_DELAY(2),
616
                        .F_LGDEPTH(F_SLV_LGDEPTH)
617
                ) control_port(i_clk, i_reset,
618
                i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,4'b1111,
619
                        o_swb_ack, o_swb_stall, o_swb_data, 1'b0,
620
                        f_swb_nreqs, f_swb_nacks, f_swb_outstanding);
621
        always @(*)
622
                assert(o_swb_stall == 0);
623
`ifdef  DELAY_ACCESS
624
        always @(*)
625
        if ((!i_reset)&&(i_swb_cyc))
626
        begin
627
                if ((!s_stb)&&(!o_swb_ack))
628
                        assert(f_swb_outstanding == 0);
629
                else if ((s_stb)&&(!o_swb_ack))
630
                        assert(f_swb_outstanding == 1);
631
                else if ((!s_stb)&&(o_swb_ack))
632
                        assert(f_swb_outstanding == 1);
633
                else if ((s_stb)&&(o_swb_ack))
634
                        assert(f_swb_outstanding == 2);
635
        end
636
`else
637
        always @(*)
638
        if ((!i_reset)&&(!o_swb_ack))
639
                assert(f_swb_outstanding == 0);
640
`endif
641
 
642
        fwb_master #(.AW(AW), .DW(32), .F_MAX_STALL(4), .F_MAX_ACK_DELAY(8),
643
                        .F_LGDEPTH(F_MSTR_LGDEPTH),
644
                        .F_OPT_RMW_BUS_OPTION(1'b1),
645
                        .F_OPT_DISCONTINUOUS(1'b0),
646
                        .F_OPT_SOURCE(1'b1)
647
                ) external_bus(i_clk, i_reset,
648
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,4'b1111,
649
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
650
                        f_mwb_nreqs, f_mwb_nacks, f_mwb_outstanding);
651
 
652
        always @(posedge i_clk)
653
        if ((f_past_valid)&&($past(dma_state == `DMA_IDLE)))
654
                assert(o_mwb_cyc == 1'b0);
655
 
656
        always @(*)
657
        if ((o_mwb_cyc)&&(!o_mwb_we))
658
        begin
659
                assert(nracks == f_mwb_nreqs);
660
                assert(nread == f_mwb_nacks);
661
        end
662
 
663
        always @(*)
664
        if ((o_mwb_cyc)&&(o_mwb_we))
665
        begin
666
                assert(nwacks   == f_mwb_nacks);
667
                assert(nwritten == f_mwb_nreqs);
668
        end
669
 
670
        always @(posedge i_clk)
671
        if ((f_past_valid)&&($past(abort))&&($past(dma_state != `DMA_IDLE)))
672
                assert(dma_state == `DMA_IDLE);
673
 
674
        always @(posedge i_clk)
675
        if ((f_past_valid)&&($past(o_mwb_cyc))&&(o_mwb_cyc)&&(
676
                        ((  !cfg_incs)&&(!o_mwb_we))
677
                        ||((!cfg_incd)&&( o_mwb_we))))
678
        begin
679
                assert(o_mwb_addr == $past(o_mwb_addr));
680
        end
681
 
682
        always @(posedge i_clk)
683
        if ((f_past_valid)&&($past(o_mwb_cyc))&&(
684
                        ((!cfg_incs)||($past(o_mwb_we))||(!$past(i_mwb_ack)))))
685
                assert(cfg_raddr == $past(cfg_raddr));
686
 
687
        always @(posedge i_clk)
688
        if ((f_past_valid)&&(dma_state == `DMA_WRITE_REQ))
689
                assert(cfg_waddr == o_mwb_addr);
690
 
691
        always @(posedge i_clk)
692
        if ((f_past_valid)&&(!$past(i_reset))
693
                        &&($past(o_mwb_stb))&&(!$past(i_mwb_stall)))
694
        begin
695
                assert(   ((!cfg_incs)&&(!$past(o_mwb_we)))
696
                        ||((!cfg_incd)&&( $past(o_mwb_we)))
697
                        ||(o_mwb_addr==$past(o_mwb_addr)+1'b1));
698
        end
699
 
700
        always @(posedge i_clk)
701
        if ((f_past_valid)&&(!$past(o_mwb_cyc))&&(o_mwb_cyc))
702
        begin
703
                if (o_mwb_we)
704
                        assert(o_mwb_addr == cfg_waddr);
705
                else
706
                        assert(o_mwb_addr == cfg_raddr);
707
        end
708
 
709
        always @(*)
710
        assert(cfg_len_nonzero == (cfg_len != 0));
711
 
712
        always @(posedge i_clk)
713
        if ((f_past_valid)&&($past(i_reset)))
714
        begin
715
                assert(cfg_len == 0);
716
                assert(!cfg_len_nonzero);
717
        end else if ((f_past_valid)&&($past(o_mwb_cyc)))
718
        begin
719
                if (($past(i_mwb_ack))&&($past(o_mwb_we)))
720
                        assert(cfg_len == $past(cfg_len)-1'b1);
721
                else
722
                        assert(cfg_len == $past(cfg_len));
723
        end else if ((f_past_valid)&&(($past(dma_state) != `DMA_IDLE)
724
                        ||(!$past(s_stb))||(!$past(s_we))
725
                        ||($past(s_addr)!=2'b01)))
726
                assert(cfg_len == $past(cfg_len));
727
 
728
        always @(posedge i_clk)
729
        if ((f_past_valid)&&($past(o_mwb_cyc))&&($past(cfg_len == 0))
730
                        &&(!$past(user_halt)))
731
        begin
732
                assert(cfg_len == 0);
733
                assert((dma_state != $past(dma_state))||(!o_mwb_cyc));
734
        end
735
 
736
        always @(posedge i_clk)
737
        if (cfg_len == 0)
738
                assert(!o_mwb_stb);
739
 
740
        always @(posedge i_clk)
741
        if ((f_past_valid)&&(!$past(i_reset))&&($past(dma_state) != `DMA_IDLE))
742
        begin
743
                assert(cfg_incs == $past(cfg_incs));
744
                assert(cfg_incd == $past(cfg_incd));
745
                assert(cfg_blocklen_sub_one == $past(cfg_blocklen_sub_one));
746
        end
747
 
748
        always @(posedge i_clk)
749
        if ((f_past_valid)&&($past(dma_state) == `DMA_IDLE))
750
                assert(cfg_len_nonzero == (cfg_len != 0));
751
 
752
        always @(posedge i_clk)
753
        if ((f_past_valid)&&(!$past(o_mwb_cyc))||(!$past(o_mwb_we)))
754
                assert((nwritten == 0)&&(nwacks == 0));
755
        always @(posedge i_clk)
756
        if ((o_mwb_cyc)&&(!o_mwb_we))
757
                assert(bus_nracks <= cfg_len);
758
        always @(posedge i_clk)
759
        if ((o_mwb_cyc)&&(!o_mwb_we))
760
                assert(nread <= nracks);
761
        always @(posedge i_clk)
762
        if ((o_mwb_cyc)&&(o_mwb_we))
763
                assert(nwritten-nwacks
764
                        +((o_mwb_stb)? 1'b1:1'b0)
765
                        - f_mwb_outstanding
766
                        // -((i_mwb_ack)? 1'b1:1'b0)
767
                        <= cfg_len);
768
        always @(*)
769
                assert(f_mwb_outstanding
770
                        + ((o_mwb_stb)? 1'b1:1'b0) <= cfg_len);
771
 
772
        wire    [LGMEMLEN:0]     f_cfg_blocklen;
773
        assign  f_cfg_blocklen = { 1'b0, cfg_blocklen_sub_one}  + 1'b1;
774
 
775
        always @(*)
776
        if (dma_state == `DMA_WAIT)
777
                assert(cfg_len > 0);
778
 
779
        always @(*)
780
        if ((o_mwb_stb)&&(o_mwb_we))
781
                assert(nread == nracks);
782
 
783
        always @(*)
784
        if (o_mwb_stb)
785
                assert(nwritten <= cfg_blocklen_sub_one);
786
        always @(posedge i_clk)
787
                assert(nwritten <= f_cfg_blocklen);
788
 
789
        always @(*)
790
        if ((o_mwb_stb)&&(!o_mwb_we))
791
                assert(nracks < f_cfg_blocklen);
792
        else
793
                assert(nracks <= f_cfg_blocklen);
794
        always @(*)
795
        if ((o_mwb_cyc)&&(i_mwb_ack)&&(!o_mwb_we))
796
                assert(nread < f_cfg_blocklen);
797
        always @(*)
798
                assert(nread <= nracks);
799
 
800
        always @(*)
801
        if ((o_mwb_cyc)&&(o_mwb_we)&&(!user_halt))
802
                assert(nread == nracks);
803
 
804
        always @(*)
805
        if ((o_mwb_cyc)&&(o_mwb_we))
806
                assert(nwritten >= nwacks);
807
 
808
        always @(*)
809
        if (dma_state == `DMA_WRITE_REQ)
810
                assert(last_write_request == (nwritten == nread-1));
811
 
812
        always @(*)
813
                assert(nwritten >= nwacks);
814
 
815
        always @(*)
816
                assert(nread >= nwritten);
817
 
818
        always @(*)
819
                assert(nracks >= nread);
820
 
821
        wire    [LGMEMLEN:0]     f_npending;
822
        assign  f_npending = nread-nwacks;
823
        always @(*)
824
        if (dma_state != `DMA_IDLE)
825
                assert({ {(AW-LGMEMLEN-1){1'b0}}, f_npending} <= cfg_len);
826
 
827
        always @(posedge i_clk)
828
        begin
829
                assert(cfg_len_nonzero == (cfg_len != 0));
830
                if ((f_past_valid)&&($past(dma_state != `DMA_IDLE))&&($past(cfg_len == 0)))
831
                        assert(cfg_len == 0);
832
        end
833
 
834
 
835
`endif
836 36 dgisselq
endmodule

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