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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [wbdmac.v] - Blame information for rev 201

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1 36 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    wbdmac.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     Wishbone DMA controller
8
//
9
//      This module is controllable via the wishbone, and moves values from
10
//      one location in the wishbone address space to another.  The amount of
11
//      memory moved at any given time can be up to 4kB, or equivalently 1kW.
12
//      Four registers control this DMA controller: a control/status register,
13
//      a length register, a source WB address and a destination WB address.
14
//      These register may be read at any time, but they may only be written
15
//      to when the controller is idle.
16
//
17
//      The meanings of three of the setup registers should be self explanatory:
18
//              - The length register controls the total number of words to
19
//                      transfer.
20
//              - The source address register controls where the DMA controller
21
//                      reads from.  This address may or may not be incremented
22
//                      after each read, depending upon the setting in the
23
//                      control/status register.
24
//              - The destination address register, which controls where the DMA
25
//                      controller writes to.  This address may or may not be
26
//                      incremented after each write, also depending upon the
27
//                      setting in the control/status register.
28
//
29
//      It is the control/status register, at local address zero, that needs
30
//      more definition:
31
//
32
//      Bits:
33
//      31      R       Write protect   If this is set to one, it means the
34
//                              write protect bit is set and the controller
35
//                              is therefore idle.  This bit will be set upon
36
//                              completing any transfer.
37
//      30      R       Error.          The controller stopped mid-transfer
38
//                                      after receiving a bus error.
39
//      29      R/W     inc_s_n         If set to one, the source address
40
//                              will not increment from one read to the next.
41
//      28      R/W     inc_d_n         If set to one, the destination address
42
//                              will not increment from one write to the next.
43
//      27      R       Always 0
44
//      26..16  R       nread           Indicates how many words have been read,
45
//                              and not necessarily written (yet).  This
46
//                              combined with the cfg_len parameter should tell
47
//                              exactly where the controller is at mid-transfer.
48
//      27..16  W       WriteProtect    When a 12'h3db is written to these
49
//                              bits, the write protect bit will be cleared.
50
//                              
51
//      15      R/W     on_dev_trigger  When set to '1', the controller will
52
//                              wait for an external interrupt before starting.
53
//      14..10  R/W     device_id       This determines which external interrupt
54
//                              will trigger a transfer.
55
//      9..0    R/W     transfer_len    How many bytes to transfer at one time.
56
//                              The minimum transfer length is one, while zero
57
//                              is mapped to a transfer length of 1kW.
58
//
59
//
60
//      To use this, follow this checklist:
61
//      1. Wait for any prior DMA operation to complete
62
//              (Read address 0, wait 'till either top bit is set or cfg_len==0)
63
//      2. Write values into length, source and destination address. 
64
//              (writei(3, &vals) should be sufficient for this.)
65
//      3. Enable the DMAC interrupt in whatever interrupt controller is present
66
//              on the system.
67
//      4. Write the final start command to the setup/control/status register:
68
//              Set inc_s_n, inc_d_n, on_dev_trigger, dev_trigger,
69
//                      appropriately for your task
70
//              Write 12'h3db to the upper word.
71
//              Set the lower word to either all zeros, or a smaller transfer
72
//              length if desired.
73
//      5. wait() for the interrupt and the operation to complete.
74
//              Prior to completion, number of items successfully transferred
75
//              be read from the length register.  If the internal buffer is
76
//              being used, then you can read how much has been read into that
77
//              buffer by reading from bits 25..16 of this control/status
78
//              register.
79
//
80 201 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
81 69 dgisselq
//              Gisselquist Technology, LLC
82 36 dgisselq
//
83
////////////////////////////////////////////////////////////////////////////////
84
//
85 201 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
86 36 dgisselq
//
87
// This program is free software (firmware): you can redistribute it and/or
88
// modify it under the terms of  the GNU General Public License as published
89
// by the Free Software Foundation, either version 3 of the License, or (at
90
// your option) any later version.
91
//
92
// This program is distributed in the hope that it will be useful, but WITHOUT
93
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
94
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
95
// for more details.
96
//
97 201 dgisselq
// You should have received a copy of the GNU General Public License along
98
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
99
// target there if the PDF file isn't present.)  If not, see
100
// <http://www.gnu.org/licenses/> for a copy.
101
//
102 36 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
103
//              http://www.gnu.org/licenses/gpl.html
104
//
105
//
106 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
107 36 dgisselq
//
108
//
109 160 dgisselq
`define DMA_IDLE        3'b000
110
`define DMA_WAIT        3'b001
111
`define DMA_READ_REQ    3'b010
112
`define DMA_READ_ACK    3'b011
113
`define DMA_PRE_WRITE   3'b100
114
`define DMA_WRITE_REQ   3'b101
115
`define DMA_WRITE_ACK   3'b110
116
 
117
module wbdmac(i_clk, i_rst,
118 36 dgisselq
                i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
119
                        o_swb_ack, o_swb_stall, o_swb_data,
120
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
121
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
122
                i_dev_ints,
123 69 dgisselq
                o_interrupt);
124 48 dgisselq
        parameter       ADDRESS_WIDTH=32, LGMEMLEN = 10,
125
                        DW=32, LGDV=5,AW=ADDRESS_WIDTH;
126 160 dgisselq
        input                   i_clk, i_rst;
127 36 dgisselq
        // Slave/control wishbone inputs
128
        input                   i_swb_cyc, i_swb_stb, i_swb_we;
129
        input   [1:0]            i_swb_addr;
130
        input   [(DW-1):0]       i_swb_data;
131
        // Slave/control wishbone outputs
132
        output  reg             o_swb_ack;
133
        output  wire            o_swb_stall;
134
        output  reg [(DW-1):0]   o_swb_data;
135
        // Master/DMA wishbone control
136 160 dgisselq
        output  wire            o_mwb_cyc, o_mwb_stb, o_mwb_we;
137 48 dgisselq
        output  reg [(AW-1):0]   o_mwb_addr;
138
        output  reg [(DW-1):0]   o_mwb_data;
139 36 dgisselq
        // Master/DMA wishbone responses from the bus
140
        input                   i_mwb_ack, i_mwb_stall;
141
        input   [(DW-1):0]       i_mwb_data;
142
        input                   i_mwb_err;
143
        // The interrupt device interrupt lines
144
        input   [(DW-1):0]       i_dev_ints;
145
        // An interrupt to be set upon completion
146
        output  reg             o_interrupt;
147
        // Need to release the bus for a higher priority user
148 69 dgisselq
        //      This logic had lots of problems, so it is being
149
        //      removed.  If you want to make sure the bus is available
150
        //      for a higher priority user, adjust the transfer length
151
        //      accordingly.
152
        //
153
        // input                        i_other_busmaster_requests_bus;
154
        //
155 36 dgisselq
 
156
 
157 160 dgisselq
        reg     [2:0]            dma_state;
158
        reg                     cfg_err, cfg_len_nonzero;
159 48 dgisselq
        reg     [(AW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
160 36 dgisselq
        reg [(LGMEMLEN-1):0]     cfg_blocklen_sub_one;
161
        reg                     cfg_incs, cfg_incd;
162
        reg     [(LGDV-1):0]     cfg_dev_trigger;
163
        reg                     cfg_on_dev_trigger;
164
 
165
        // Single block operations: We'll read, then write, up to a single
166
        // memory block here.
167
 
168
        reg     [(DW-1):0]       dma_mem [0:(((1<<LGMEMLEN))-1)];
169 160 dgisselq
        reg     [(LGMEMLEN):0]   nread, nwritten, nwacks, nracks;
170
        wire    [(AW-1):0]       bus_nracks;
171
        assign  bus_nracks = { {(AW-LGMEMLEN-1){1'b0}}, nracks };
172 36 dgisselq
 
173 160 dgisselq
        reg     last_read_request, last_read_ack,
174
                last_write_request, last_write_ack;
175 201 dgisselq
        reg     trigger, abort, user_halt;
176 160 dgisselq
 
177
        initial dma_state = `DMA_IDLE;
178 36 dgisselq
        initial o_interrupt = 1'b0;
179 48 dgisselq
        initial cfg_len     = {(AW){1'b0}};
180 36 dgisselq
        initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
181
        initial cfg_on_dev_trigger = 1'b0;
182 160 dgisselq
        initial cfg_len_nonzero = 1'b0;
183 36 dgisselq
        always @(posedge i_clk)
184 160 dgisselq
        case(dma_state)
185
        `DMA_IDLE: begin
186
                o_mwb_addr <= cfg_raddr;
187
                nwritten   <= 0;
188
                nread      <= 0;
189
                nracks     <= 0;
190
                nwacks     <= 0;
191
                cfg_len_nonzero <= (|cfg_len);
192
 
193
                // When the slave wishbone writes, and we are in this 
194
                // (ready) configuration, then allow the DMA to be controlled
195
                // and thus to start.
196 182 dgisselq
                if ((i_swb_stb)&&(i_swb_we))
197 36 dgisselq
                begin
198 160 dgisselq
                        case(i_swb_addr)
199
                        2'b00: begin
200 201 dgisselq
                                if ((i_swb_data[31:16] == 16'h0fed)
201 160 dgisselq
                                                &&(cfg_len_nonzero))
202
                                        dma_state <= `DMA_WAIT;
203
                                cfg_blocklen_sub_one
204
                                        <= i_swb_data[(LGMEMLEN-1):0]
205
                                        + {(LGMEMLEN){1'b1}};
206
                                        // i.e. -1;
207
                                cfg_dev_trigger    <= i_swb_data[14:10];
208
                                cfg_on_dev_trigger <= i_swb_data[15];
209
                                cfg_incs  <= ~i_swb_data[29];
210
                                cfg_incd  <= ~i_swb_data[28];
211 36 dgisselq
                                end
212 160 dgisselq
                        2'b01: begin
213
                                cfg_len   <=  i_swb_data[(AW-1):0];
214
                                cfg_len_nonzero <= (|i_swb_data[(AW-1):0]);
215
                                end
216
                        2'b10: cfg_raddr <=  i_swb_data[(AW-1):0];
217
                        2'b11: cfg_waddr <=  i_swb_data[(AW-1):0];
218
                        endcase
219
                end end
220
        `DMA_WAIT: begin
221
                o_mwb_addr <= cfg_raddr;
222
                nracks     <= 0;
223
                nwacks     <= 0;
224
                nwritten   <= 0;
225
                nread      <= 0;
226
                if (abort)
227
                        dma_state <= `DMA_IDLE;
228 201 dgisselq
                else if (user_halt)
229
                        dma_state <= `DMA_IDLE;
230 160 dgisselq
                else if (trigger)
231
                        dma_state <= `DMA_READ_REQ;
232
                end
233
        `DMA_READ_REQ: begin
234
                nwritten  <= 0;
235 36 dgisselq
 
236 160 dgisselq
                if (~i_mwb_stall)
237 36 dgisselq
                begin
238 160 dgisselq
                        // Number of read acknowledgements needed
239
                        nracks <= nracks+1;
240
                        if (last_read_request)
241
        //((nracks == {1'b0, cfg_blocklen_sub_one})||(bus_nracks == cfg_len-1))
242
                                // Wishbone interruptus
243
                                dma_state <= `DMA_READ_ACK;
244
                        if (cfg_incs)
245
                                o_mwb_addr <= o_mwb_addr
246
                                                + {{(AW-1){1'b0}},1'b1};
247
                end
248
 
249 201 dgisselq
                if (user_halt)
250
                        dma_state <= `DMA_READ_ACK;
251 160 dgisselq
                if (i_mwb_err)
252
                begin
253
                        cfg_len <= 0;
254
                        dma_state <= `DMA_IDLE;
255
                end
256 201 dgisselq
 
257 160 dgisselq
                if (abort)
258
                        dma_state <= `DMA_IDLE;
259
                if (i_mwb_ack)
260
                begin
261
                        nread <= nread+1;
262
                        if (cfg_incs)
263
                                cfg_raddr  <= cfg_raddr
264
                                                + {{(AW-1){1'b0}},1'b1};
265
                end end
266
        `DMA_READ_ACK: begin
267
                nwritten  <= 0;
268
 
269
                if (i_mwb_err)
270
                begin
271
                        cfg_len <= 0;
272
                        dma_state <= `DMA_IDLE;
273
                end else if (i_mwb_ack)
274
                begin
275
                        nread <= nread+1;
276
                        if (last_read_ack) // (nread+1 == nracks)
277
                                dma_state  <= `DMA_PRE_WRITE;
278 201 dgisselq
                        if (user_halt)
279
                                dma_state <= `DMA_IDLE;
280 160 dgisselq
                        if (cfg_incs)
281
                                cfg_raddr  <= cfg_raddr
282
                                                + {{(AW-1){1'b0}},1'b1};
283
                end
284
                if (abort)
285
                        dma_state <= `DMA_IDLE;
286
                end
287
        `DMA_PRE_WRITE: begin
288
                o_mwb_addr <= cfg_waddr;
289
                dma_state <= (abort)?`DMA_IDLE:`DMA_WRITE_REQ;
290
                end
291
        `DMA_WRITE_REQ: begin
292
                if (~i_mwb_stall)
293
                begin
294
                        nwritten <= nwritten+1;
295
                        if (last_write_request) // (nwritten == nread-1)
296
                                // Wishbone interruptus
297
                                dma_state <= `DMA_WRITE_ACK;
298
                        if (cfg_incd)
299 36 dgisselq
                        begin
300 160 dgisselq
                                o_mwb_addr <= o_mwb_addr
301
                                                + {{(AW-1){1'b0}},1'b1};
302
                                cfg_waddr  <= cfg_waddr
303
                                                + {{(AW-1){1'b0}},1'b1};
304 36 dgisselq
                        end
305 160 dgisselq
                end
306 36 dgisselq
 
307 160 dgisselq
                if (i_mwb_err)
308
                begin
309
                        cfg_len  <= 0;
310
                        dma_state <= `DMA_IDLE;
311
                end
312
                if (i_mwb_ack)
313
                begin
314
                        nwacks <= nwacks+1;
315
                        cfg_len <= cfg_len +{(AW){1'b1}}; // -1
316
                end
317 201 dgisselq
                if (user_halt)
318
                        dma_state <= `DMA_WRITE_ACK;
319 160 dgisselq
                if (abort)
320
                        dma_state <= `DMA_IDLE;
321
                end
322
        `DMA_WRITE_ACK: begin
323
                if (i_mwb_err)
324
                begin
325
                        cfg_len  <= 0;
326
                        nread    <= 0;
327
                        dma_state <= `DMA_IDLE;
328
                end else if (i_mwb_ack)
329
                begin
330
                        nwacks <= nwacks+1;
331
                        cfg_len <= cfg_len +{(AW){1'b1}};//cfg_len -= 1;
332
                        if (last_write_ack) // (nwacks+1 == nwritten)
333 36 dgisselq
                        begin
334
                                nread <= 0;
335 160 dgisselq
                                dma_state <= (cfg_len == 1)?`DMA_IDLE:`DMA_WAIT;
336 36 dgisselq
                        end
337
                end
338
 
339 160 dgisselq
                if (abort)
340
                        dma_state <= `DMA_IDLE;
341
                end
342
        default:
343
                dma_state <= `DMA_IDLE;
344
        endcase
345
 
346
        initial o_interrupt = 1'b0;
347
        always @(posedge i_clk)
348 201 dgisselq
                o_interrupt <= ((dma_state == `DMA_WRITE_ACK)&&(i_mwb_ack)
349
                                        &&(last_write_ack)
350
                                        &&(cfg_len == {{(AW-1){1'b0}},1'b1}))
351
                                ||((dma_state != `DMA_IDLE)&&(i_mwb_err));
352 160 dgisselq
 
353
        initial cfg_err = 1'b0;
354
        always @(posedge i_clk)
355
                if (dma_state == `DMA_IDLE)
356
                begin
357 182 dgisselq
                        if ((i_swb_stb)&&(i_swb_we)&&(i_swb_addr==2'b00))
358 160 dgisselq
                                cfg_err <= 1'b0;
359
                end else if (((i_mwb_err)&&(o_mwb_cyc))||(abort))
360
                        cfg_err <= 1'b1;
361
 
362
        initial last_read_request = 1'b0;
363
        always @(posedge i_clk)
364
                if ((dma_state == `DMA_WAIT)||(dma_state == `DMA_READ_REQ))
365
                begin
366
                        if ((~i_mwb_stall)&&(dma_state == `DMA_READ_REQ))
367
                        begin
368
                                last_read_request <=
369
                                (nracks + 1 == { 1'b0, cfg_blocklen_sub_one})
370
                                        ||(bus_nracks == cfg_len-2);
371
                        end else
372
                                last_read_request <=
373
                                        (nracks== { 1'b0, cfg_blocklen_sub_one})
374
                                        ||(bus_nracks == cfg_len-1);
375
                end else
376
                        last_read_request <= 1'b0;
377
 
378
        initial last_read_ack = 1'b0;
379
        always @(posedge i_clk)
380
                if ((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK))
381
                begin
382 182 dgisselq
                        if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall)))
383 160 dgisselq
                                last_read_ack <= (nread+2 == nracks);
384
                        else
385
                                last_read_ack <= (nread+1 == nracks);
386
                end else
387
                        last_read_ack <= 1'b0;
388
 
389
        initial last_write_request = 1'b0;
390
        always @(posedge i_clk)
391
                if (dma_state == `DMA_PRE_WRITE)
392
                        last_write_request <= (nread <= 1);
393
                else if (dma_state == `DMA_WRITE_REQ)
394
                begin
395
                        if (i_mwb_stall)
396
                                last_write_request <= (nwritten >= nread-1);
397
                        else
398
                                last_write_request <= (nwritten >= nread-2);
399
                end else
400
                        last_write_request <= 1'b0;
401
 
402
        initial last_write_ack = 1'b0;
403
        always @(posedge i_clk)
404
                if((dma_state == `DMA_WRITE_REQ)||(dma_state == `DMA_WRITE_ACK))
405
                begin
406 182 dgisselq
                        if ((i_mwb_ack)&&((~o_mwb_stb)||(i_mwb_stall)))
407 160 dgisselq
                                last_write_ack <= (nwacks+2 == nwritten);
408
                        else
409
                                last_write_ack <= (nwacks+1 == nwritten);
410
                end else
411
                        last_write_ack <= 1'b0;
412
 
413
        assign  o_mwb_cyc = (dma_state == `DMA_READ_REQ)
414
                        ||(dma_state == `DMA_READ_ACK)
415
                        ||(dma_state == `DMA_WRITE_REQ)
416
                        ||(dma_state == `DMA_WRITE_ACK);
417
 
418
        assign  o_mwb_stb = (dma_state == `DMA_READ_REQ)
419
                        ||(dma_state == `DMA_WRITE_REQ);
420
 
421
        assign  o_mwb_we = (dma_state == `DMA_PRE_WRITE)
422
                        ||(dma_state == `DMA_WRITE_REQ)
423
                        ||(dma_state == `DMA_WRITE_ACK);
424
 
425 36 dgisselq
        //
426
        // This is tricky.  In order for Vivado to consider dma_mem to be a 
427
        // proper memory, it must have a simple address fed into it.  Hence
428
        // the read_address (rdaddr) register.  The problem is that this
429
        // register must always be one greater than the address we actually
430
        // want to read from, unless we are idling.  So ... the math is touchy.
431
        //
432
        reg     [(LGMEMLEN-1):0] rdaddr;
433
        always @(posedge i_clk)
434 160 dgisselq
                if((dma_state == `DMA_IDLE)||(dma_state == `DMA_WAIT)
435
                                ||(dma_state == `DMA_WRITE_ACK))
436
                        rdaddr <= 0;
437
                else if ((dma_state == `DMA_PRE_WRITE)
438
                                ||((dma_state==`DMA_WRITE_REQ)&&(~i_mwb_stall)))
439
                        rdaddr <= rdaddr + {{(LGMEMLEN-1){1'b0}},1'b1};
440 36 dgisselq
        always @(posedge i_clk)
441 160 dgisselq
                if ((dma_state != `DMA_WRITE_REQ)||(~i_mwb_stall))
442 36 dgisselq
                        o_mwb_data <= dma_mem[rdaddr];
443
        always @(posedge i_clk)
444 160 dgisselq
                if((dma_state == `DMA_READ_REQ)||(dma_state == `DMA_READ_ACK))
445 36 dgisselq
                        dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
446
 
447
        always @(posedge i_clk)
448
                casez(i_swb_addr)
449 160 dgisselq
                2'b00: o_swb_data <= {  (dma_state != `DMA_IDLE), cfg_err,
450 36 dgisselq
                                        ~cfg_incs, ~cfg_incd,
451
                                        1'b0, nread,
452
                                        cfg_on_dev_trigger, cfg_dev_trigger,
453
                                        cfg_blocklen_sub_one
454
                                        };
455 48 dgisselq
                2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len  };
456
                2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr};
457
                2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr};
458 36 dgisselq
                endcase
459
 
460 160 dgisselq
        // This causes us to wait a minimum of two clocks before starting: One
461
        // to go into the wait state, and then one while in the wait state to
462
        // develop the trigger.
463
        initial trigger = 1'b0;
464 36 dgisselq
        always @(posedge i_clk)
465 160 dgisselq
                trigger <=  (dma_state == `DMA_WAIT)
466
                                &&((~cfg_on_dev_trigger)
467
                                        ||(i_dev_ints[cfg_dev_trigger]));
468 36 dgisselq
 
469 160 dgisselq
        // Ack any access.  We'll quietly ignore any access where we are busy,
470
        // but ack it anyway.  In other words, before writing to the device,
471
        // double check that it isn't busy, and then write.
472
        always @(posedge i_clk)
473 182 dgisselq
                o_swb_ack <= (i_swb_stb);
474 160 dgisselq
 
475 36 dgisselq
        assign  o_swb_stall = 1'b0;
476
 
477 160 dgisselq
        initial abort = 1'b0;
478
        always @(posedge i_clk)
479 182 dgisselq
                abort <= (i_rst)||((i_swb_stb)&&(i_swb_we)
480 160 dgisselq
                        &&(i_swb_addr == 2'b00)
481
                        &&(i_swb_data == 32'hffed0000));
482
 
483 201 dgisselq
        initial user_halt = 1'b0;
484
        always @(posedge i_clk)
485
                user_halt <= ((user_halt)&&(dma_state != `DMA_IDLE))
486
                        ||((i_swb_stb)&&(i_swb_we)&&(dma_state != `DMA_IDLE)
487
                                &&(i_swb_addr == 2'b00)
488
                                &&(i_swb_data == 32'hafed0000));
489
 
490 36 dgisselq
endmodule
491
 

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