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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [wbdmac.v] - Blame information for rev 48

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1 36 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename:    wbdmac.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     Wishbone DMA controller
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//
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//      This module is controllable via the wishbone, and moves values from
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//      one location in the wishbone address space to another.  The amount of
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//      memory moved at any given time can be up to 4kB, or equivalently 1kW.
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//      Four registers control this DMA controller: a control/status register,
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//      a length register, a source WB address and a destination WB address.
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//      These register may be read at any time, but they may only be written
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//      to when the controller is idle.
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//
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//      The meanings of three of the setup registers should be self explanatory:
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//              - The length register controls the total number of words to
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//                      transfer.
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//              - The source address register controls where the DMA controller
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//                      reads from.  This address may or may not be incremented
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//                      after each read, depending upon the setting in the
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//                      control/status register.
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//              - The destination address register, which controls where the DMA
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//                      controller writes to.  This address may or may not be
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//                      incremented after each write, also depending upon the
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//                      setting in the control/status register.
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//
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//      It is the control/status register, at local address zero, that needs
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//      more definition:
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//
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//      Bits:
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//      31      R       Write protect   If this is set to one, it means the
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//                              write protect bit is set and the controller
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//                              is therefore idle.  This bit will be set upon
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//                              completing any transfer.
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//      30      R       Error.          The controller stopped mid-transfer
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//                                      after receiving a bus error.
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//      29      R/W     inc_s_n         If set to one, the source address
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//                              will not increment from one read to the next.
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//      28      R/W     inc_d_n         If set to one, the destination address
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//                              will not increment from one write to the next.
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//      27      R       Always 0
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//      26..16  R       nread           Indicates how many words have been read,
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//                              and not necessarily written (yet).  This
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//                              combined with the cfg_len parameter should tell
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//                              exactly where the controller is at mid-transfer.
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//      27..16  W       WriteProtect    When a 12'h3db is written to these
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//                              bits, the write protect bit will be cleared.
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//                              
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//      15      R/W     on_dev_trigger  When set to '1', the controller will
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//                              wait for an external interrupt before starting.
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//      14..10  R/W     device_id       This determines which external interrupt
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//                              will trigger a transfer.
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//      9..0    R/W     transfer_len    How many bytes to transfer at one time.
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//                              The minimum transfer length is one, while zero
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//                              is mapped to a transfer length of 1kW.
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//
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//
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//      To use this, follow this checklist:
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//      1. Wait for any prior DMA operation to complete
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//              (Read address 0, wait 'till either top bit is set or cfg_len==0)
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//      2. Write values into length, source and destination address. 
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//              (writei(3, &vals) should be sufficient for this.)
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//      3. Enable the DMAC interrupt in whatever interrupt controller is present
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//              on the system.
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//      4. Write the final start command to the setup/control/status register:
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//              Set inc_s_n, inc_d_n, on_dev_trigger, dev_trigger,
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//                      appropriately for your task
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//              Write 12'h3db to the upper word.
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//              Set the lower word to either all zeros, or a smaller transfer
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//              length if desired.
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//      5. wait() for the interrupt and the operation to complete.
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//              Prior to completion, number of items successfully transferred
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//              be read from the length register.  If the internal buffer is
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//              being used, then you can read how much has been read into that
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//              buffer by reading from bits 25..16 of this control/status
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//              register.
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//
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// Creator:     Dan Gisselquist
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//              Gisselquist Tecnology, LLC
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//
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// Copyright:   2015
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module wbdmac(i_clk,
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                i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
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                        o_swb_ack, o_swb_stall, o_swb_data,
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                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
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                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
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                i_dev_ints,
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                o_interrupt,
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                i_other_busmaster_requests_bus);
116 48 dgisselq
        parameter       ADDRESS_WIDTH=32, LGMEMLEN = 10,
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                        DW=32, LGDV=5,AW=ADDRESS_WIDTH;
118 36 dgisselq
        input                   i_clk;
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        // Slave/control wishbone inputs
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        input                   i_swb_cyc, i_swb_stb, i_swb_we;
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        input   [1:0]            i_swb_addr;
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        input   [(DW-1):0]       i_swb_data;
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        // Slave/control wishbone outputs
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        output  reg             o_swb_ack;
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        output  wire            o_swb_stall;
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        output  reg [(DW-1):0]   o_swb_data;
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        // Master/DMA wishbone control
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        output  reg             o_mwb_cyc, o_mwb_stb, o_mwb_we;
129 48 dgisselq
        output  reg [(AW-1):0]   o_mwb_addr;
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        output  reg [(DW-1):0]   o_mwb_data;
131 36 dgisselq
        // Master/DMA wishbone responses from the bus
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        input                   i_mwb_ack, i_mwb_stall;
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        input   [(DW-1):0]       i_mwb_data;
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        input                   i_mwb_err;
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        // The interrupt device interrupt lines
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        input   [(DW-1):0]       i_dev_ints;
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        // An interrupt to be set upon completion
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        output  reg             o_interrupt;
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        // Need to release the bus for a higher priority user
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        input                   i_other_busmaster_requests_bus;
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        reg                     cfg_wp; // Write protect
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        reg                     cfg_err;
145 48 dgisselq
        reg     [(AW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
146 36 dgisselq
        reg [(LGMEMLEN-1):0]     cfg_blocklen_sub_one;
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        reg                     cfg_incs, cfg_incd;
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        reg     [(LGDV-1):0]     cfg_dev_trigger;
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        reg                     cfg_on_dev_trigger;
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        // Single block operations: We'll read, then write, up to a single
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        // memory block here.
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        reg     [(DW-1):0]       dma_mem [0:(((1<<LGMEMLEN))-1)];
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        reg     [(LGMEMLEN):0]   nread, nwritten, nacks;
156 48 dgisselq
        wire    [(AW-1):0]       bus_nacks;
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        assign  bus_nacks = { {(AW-LGMEMLEN-1){1'b0}}, nacks };
158 36 dgisselq
 
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        initial o_interrupt = 1'b0;
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        initial o_mwb_cyc   = 1'b0;
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        initial cfg_err     = 1'b0;
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        initial cfg_wp      = 1'b0;
163 48 dgisselq
        initial cfg_len     = {(AW){1'b0}};
164 36 dgisselq
        initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
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        initial cfg_on_dev_trigger = 1'b0;
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        always @(posedge i_clk)
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                if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
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                begin
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                        if ((o_mwb_stb)&&(~i_mwb_stall))
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                        begin
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                                nwritten <= nwritten+1;
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                                if ((nwritten == nread-1)
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                                        ||(i_other_busmaster_requests_bus))
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                                        // Wishbone interruptus
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                                        o_mwb_stb <= 1'b0;
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                                else if (cfg_incd) begin
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                                        o_mwb_addr <= o_mwb_addr + 1;
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                                        cfg_waddr  <= cfg_waddr  + 1;
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                                end
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                                // o_mwb_data <= dma_mem[nwritten + 1];
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                        end
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                        if (i_mwb_err)
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                        begin
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                                o_mwb_cyc <= 1'b0;
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                                cfg_err <= 1'b1;
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                                cfg_len <= 0;
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                                nread   <= 0;
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                        end else if (i_mwb_ack)
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                        begin
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                                nacks <= nacks+1;
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                                cfg_len <= cfg_len - 1;
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                                if ((nacks+1 == nwritten)&&(~o_mwb_stb))
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                                begin
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                                        o_mwb_cyc <= 1'b0;
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                                        nread <= 0;
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                                        o_interrupt <= (cfg_len == 1);
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                                        // Turn write protect back on
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                                        cfg_wp    <= 1'b1;
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                                end
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                        end
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                end else if ((o_mwb_cyc)&&(~o_mwb_we)) // Read cycle
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                begin
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                        if ((o_mwb_stb)&&(~i_mwb_stall))
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                        begin
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                                nacks <= nacks+1;
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                                if ((nacks == {1'b0, cfg_blocklen_sub_one})
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                                        ||(bus_nacks <= cfg_len-1)
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                                        ||(i_other_busmaster_requests_bus))
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                                        // Wishbone interruptus
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                                        o_mwb_stb <= 1'b0;
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                                else if (cfg_incs) begin
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                                        o_mwb_addr <= o_mwb_addr + 1;
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                                end
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                        end
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                        if (i_mwb_err)
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                        begin
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                                o_mwb_cyc <= 1'b0;
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                                cfg_err <= 1'b1;
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                                cfg_len <= 0;
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                                nread <= 0;
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                        end else if (i_mwb_ack)
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                        begin
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                                nread <= nread+1;
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                                if ((~o_mwb_stb)&&(nread+1 == nacks))
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                                begin
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                                        o_mwb_cyc <= 1'b0;
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                                        nacks <= 0;
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                                end
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                                if (cfg_incs)
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                                        cfg_raddr  <= cfg_raddr  + 1;
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                                // dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
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                        end
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                end else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err))
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                begin // Initiate/continue a write cycle
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                        o_mwb_cyc  <= 1'b1;
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                        o_mwb_stb  <= 1'b1;
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                        o_mwb_we   <= 1'b1;
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                        // o_mwb_data <= dma_mem[0];
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                        o_mwb_addr <= cfg_waddr;
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                        // nwritten  <= 0; // Can't set to zero, in case we're
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                        // nacks     <= 0; //   continuing a cycle
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                end else if ((~o_mwb_cyc)&&(nread == 0)&&(cfg_len>0)&&(~cfg_wp)
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                                &&((~cfg_on_dev_trigger)
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                                        ||(i_dev_ints[cfg_dev_trigger])))
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                begin // Initiate a read cycle
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                        o_mwb_cyc <= 1'b1;
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                        o_mwb_stb <= 1'b1;
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                        o_mwb_we  <= 1'b0;
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                        o_mwb_addr<= cfg_raddr;
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                        nwritten  <= 0;
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                        nread     <= 0;
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                        nacks     <= 0;
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                end else begin
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                        o_mwb_cyc  <= 1'b0;
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                        o_mwb_stb  <= 1'b0;
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                        o_mwb_we   <= 1'b0;
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                        o_mwb_addr <= cfg_raddr;
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                        o_interrupt<= 1'b0;
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                        nwritten   <= 0;
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                        if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we))
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                        begin
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                                cfg_wp <= 1'b1;
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                                case(i_swb_addr)
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                                2'b00: begin
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                                        cfg_wp    <= (i_swb_data[27:16]!=12'hfed);
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                                        cfg_blocklen_sub_one
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                                                <= i_swb_data[(LGMEMLEN-1):0]-1;
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                                        cfg_dev_trigger    <= i_swb_data[14:10];
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                                        cfg_on_dev_trigger <= i_swb_data[15];
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                                        cfg_incs  <= ~i_swb_data[29];
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                                        cfg_incd  <= ~i_swb_data[28];
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                                        cfg_err   <= 1'b0;
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                                        end
276 48 dgisselq
                                2'b01: cfg_len   <=  i_swb_data[(AW-1):0];
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                                2'b10: cfg_raddr <=  i_swb_data[(AW-1):0];
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                                2'b11: cfg_waddr <=  i_swb_data[(AW-1):0];
279 36 dgisselq
                                endcase
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                        end
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                end
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        //
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        // This is tricky.  In order for Vivado to consider dma_mem to be a 
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        // proper memory, it must have a simple address fed into it.  Hence
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        // the read_address (rdaddr) register.  The problem is that this
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        // register must always be one greater than the address we actually
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        // want to read from, unless we are idling.  So ... the math is touchy.
289
        //
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        reg     [(LGMEMLEN-1):0] rdaddr;
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        always @(posedge i_clk)
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                if ((o_mwb_cyc)&&(o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall))
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                        // This would be the normal advance, save that we are
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                        // already one ahead of nwritten
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                        rdaddr <= rdaddr + 1; // {{(LGMEMLEN-1){1'b0}},1};
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                else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err))
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                        // Here's where we do our extra advance
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                        rdaddr <= nwritten[(LGMEMLEN-1):0]+1;
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                else if ((~o_mwb_cyc)||(~o_mwb_we))
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                        rdaddr <= nwritten[(LGMEMLEN-1):0];
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        always @(posedge i_clk)
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                if ((~o_mwb_cyc)||((o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall)))
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                        o_mwb_data <= dma_mem[rdaddr];
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        always @(posedge i_clk)
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                if ((o_mwb_cyc)&&(~o_mwb_we)&&(i_mwb_ack))
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                        dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
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308
        always @(posedge i_clk)
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                casez(i_swb_addr)
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                2'b00: o_swb_data <= {  ~cfg_wp, cfg_err,
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                                        ~cfg_incs, ~cfg_incd,
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                                        1'b0, nread,
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                                        cfg_on_dev_trigger, cfg_dev_trigger,
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                                        cfg_blocklen_sub_one
315
                                        };
316 48 dgisselq
                2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len  };
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                2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr};
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                2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr};
319 36 dgisselq
                endcase
320
 
321
        always @(posedge i_clk)
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                if ((i_swb_cyc)&&(i_swb_stb)) // &&(~i_swb_we))
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                        o_swb_ack <= 1'b1;
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                // else if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)&&(~o_mwb_cyc)&&(nread == 0))
325
                else
326
                        o_swb_ack <= 1'b0;
327
 
328
        assign  o_swb_stall = 1'b0;
329
 
330
endmodule
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