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////////////////////////////////////////////////////////////////////////////////
//
//
// Filename:    wbdmac.v
//
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose:     Wishbone DMA controller
//
//      This module is controllable via the wishbone, and moves values from
//      one location in the wishbone address space to another.  The amount of
//      memory moved at any given time can be up to 4kB, or equivalently 1kW.
//      Four registers control this DMA controller: a control/status register,
//      a length register, a source WB address and a destination WB address.
//      These register may be read at any time, but they may only be written
//      to when the controller is idle.
//
//      The meanings of three of the setup registers should be self explanatory:
//              - The length register controls the total number of words to
//                      transfer.
//              - The source address register controls where the DMA controller
//                      reads from.  This address may or may not be incremented
//                      after each read, depending upon the setting in the
//                      control/status register.
//              - The destination address register, which controls where the DMA
//                      controller writes to.  This address may or may not be
//                      incremented after each write, also depending upon the
//                      setting in the control/status register.
//
//      It is the control/status register, at local address zero, that needs
//      more definition:
//
//      Bits:
//      31      R       Write protect   If this is set to one, it means the
//                              write protect bit is set and the controller
//                              is therefore idle.  This bit will be set upon
//                              completing any transfer.
//      30      R       Error.          The controller stopped mid-transfer
//                                      after receiving a bus error.
//      29      R/W     inc_s_n         If set to one, the source address
//                              will not increment from one read to the next.
//      28      R/W     inc_d_n         If set to one, the destination address
//                              will not increment from one write to the next.
//      27      R       Always 0
//      26..16  R       nread           Indicates how many words have been read,
//                              and not necessarily written (yet).  This
//                              combined with the cfg_len parameter should tell
//                              exactly where the controller is at mid-transfer.
//      27..16  W       WriteProtect    When a 12'h3db is written to these
//                              bits, the write protect bit will be cleared.
//                              
//      15      R/W     on_dev_trigger  When set to '1', the controller will
//                              wait for an external interrupt before starting.
//      14..10  R/W     device_id       This determines which external interrupt
//                              will trigger a transfer.
//      9..0    R/W     transfer_len    How many bytes to transfer at one time.
//                              The minimum transfer length is one, while zero
//                              is mapped to a transfer length of 1kW.
//
//
//      To use this, follow this checklist:
//      1. Wait for any prior DMA operation to complete
//              (Read address 0, wait 'till either top bit is set or cfg_len==0)
//      2. Write values into length, source and destination address. 
//              (writei(3, &vals) should be sufficient for this.)
//      3. Enable the DMAC interrupt in whatever interrupt controller is present
//              on the system.
//      4. Write the final start command to the setup/control/status register:
//              Set inc_s_n, inc_d_n, on_dev_trigger, dev_trigger,
//                      appropriately for your task
//              Write 12'h3db to the upper word.
//              Set the lower word to either all zeros, or a smaller transfer
//              length if desired.
//      5. wait() for the interrupt and the operation to complete.
//              Prior to completion, number of items successfully transferred
//              be read from the length register.  If the internal buffer is
//              being used, then you can read how much has been read into that
//              buffer by reading from bits 25..16 of this control/status
//              register.
//
// Creator:     Dan Gisselquist
//              Gisselquist Technology, LLC
//
// Copyright:   2015
//
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// License:     GPL, v3, as defined and found on www.gnu.org,
//              http://www.gnu.org/licenses/gpl.html
//
//
///////////////////////////////////////////////////////////////////////////
//
//
module wbdmac(i_clk,
                i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,
                        o_swb_ack, o_swb_stall, o_swb_data,
                o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,
                        i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,
                i_dev_ints,
                o_interrupt);
        parameter       ADDRESS_WIDTH=32, LGMEMLEN = 10,
                        DW=32, LGDV=5,AW=ADDRESS_WIDTH;
        input                   i_clk;
        // Slave/control wishbone inputs
        input                   i_swb_cyc, i_swb_stb, i_swb_we;
        input   [1:0]            i_swb_addr;
        input   [(DW-1):0]       i_swb_data;
        // Slave/control wishbone outputs
        output  reg             o_swb_ack;
        output  wire            o_swb_stall;
        output  reg [(DW-1):0]   o_swb_data;
        // Master/DMA wishbone control
        output  reg             o_mwb_cyc, o_mwb_stb, o_mwb_we;
        output  reg [(AW-1):0]   o_mwb_addr;
        output  reg [(DW-1):0]   o_mwb_data;
        // Master/DMA wishbone responses from the bus
        input                   i_mwb_ack, i_mwb_stall;
        input   [(DW-1):0]       i_mwb_data;
        input                   i_mwb_err;
        // The interrupt device interrupt lines
        input   [(DW-1):0]       i_dev_ints;
        // An interrupt to be set upon completion
        output  reg             o_interrupt;
        // Need to release the bus for a higher priority user
        //      This logic had lots of problems, so it is being
        //      removed.  If you want to make sure the bus is available
        //      for a higher priority user, adjust the transfer length
        //      accordingly.
        //
        // input                        i_other_busmaster_requests_bus;
        //
 
 
        reg                     cfg_wp; // Write protect
        reg                     cfg_err;
        reg     [(AW-1):0]       cfg_waddr, cfg_raddr, cfg_len;
        reg [(LGMEMLEN-1):0]     cfg_blocklen_sub_one;
        reg                     cfg_incs, cfg_incd;
        reg     [(LGDV-1):0]     cfg_dev_trigger;
        reg                     cfg_on_dev_trigger;
 
        // Single block operations: We'll read, then write, up to a single
        // memory block here.
 
        reg     [(DW-1):0]       dma_mem [0:(((1<<LGMEMLEN))-1)];
        reg     [(LGMEMLEN):0]   nread, nwritten, nacks;
        wire    [(AW-1):0]       bus_nacks;
        assign  bus_nacks = { {(AW-LGMEMLEN-1){1'b0}}, nacks };
 
        initial o_interrupt = 1'b0;
        initial o_mwb_cyc   = 1'b0;
        initial cfg_err     = 1'b0;
        initial cfg_wp      = 1'b0;
        initial cfg_len     = {(AW){1'b0}};
        initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};
        initial cfg_on_dev_trigger = 1'b0;
        always @(posedge i_clk)
                if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle
                begin
                        if ((o_mwb_stb)&&(~i_mwb_stall))
                        begin
                                nwritten <= nwritten+1;
                                if (nwritten == nread-1)
                                        // Wishbone interruptus
                                        o_mwb_stb <= 1'b0;
                                else if (cfg_incd) begin
                                        o_mwb_addr <= o_mwb_addr + 1;
                                        cfg_waddr  <= cfg_waddr  + 1;
                                end
                                // o_mwb_data <= dma_mem[nwritten + 1];
                        end
 
                        if (i_mwb_err)
                        begin
                                o_mwb_cyc <= 1'b0;
                                cfg_err <= 1'b1;
                                cfg_len <= 0;
                                nread   <= 0;
                        end else if (i_mwb_ack)
                        begin
                                nacks <= nacks+1;
                                cfg_len <= cfg_len - 1;
                                if ((nacks+1 == nwritten)&&(~o_mwb_stb))
                                begin
                                        o_mwb_cyc <= 1'b0;
                                        nread <= 0;
                                        o_interrupt <= (cfg_len == 1);
                                        // Turn write protect back on
                                        cfg_wp    <= 1'b1;
                                end
                        end
                end else if ((o_mwb_cyc)&&(~o_mwb_we)) // Read cycle
                begin
                        if ((o_mwb_stb)&&(~i_mwb_stall))
                        begin
                                nacks <= nacks+1;
                                if ((nacks == {1'b0, cfg_blocklen_sub_one})
                                        ||(bus_nacks <= cfg_len-1))
                                        // Wishbone interruptus
                                        o_mwb_stb <= 1'b0;
                                else if (cfg_incs) begin
                                        o_mwb_addr <= o_mwb_addr + 1;
                                end
                        end
 
                        if (i_mwb_err)
                        begin
                                o_mwb_cyc <= 1'b0;
                                cfg_err <= 1'b1;
                                cfg_len <= 0;
                                nread <= 0;
                        end else if (i_mwb_ack)
                        begin
                                nread <= nread+1;
                                if ((~o_mwb_stb)&&(nread+1 == nacks))
                                begin
                                        o_mwb_cyc <= 1'b0;
                                        nacks <= 0;
                                end
                                if (cfg_incs)
                                        cfg_raddr  <= cfg_raddr  + 1;
                                // dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
                        end
                end else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err))
                begin // Initiate/continue a write cycle
                        o_mwb_cyc  <= 1'b1;
                        o_mwb_stb  <= 1'b1;
                        o_mwb_we   <= 1'b1;
                        // o_mwb_data <= dma_mem[0];
                        o_mwb_addr <= cfg_waddr;
                        // nwritten  <= 0; // Can't set to zero, in case we're
                        // nacks     <= 0; //   continuing a cycle
                end else if ((~o_mwb_cyc)&&(nread == 0)&&(cfg_len>0)&&(~cfg_wp)
                                &&((~cfg_on_dev_trigger)
                                        ||(i_dev_ints[cfg_dev_trigger])))
                begin // Initiate a read cycle
                        o_mwb_cyc <= 1'b1;
                        o_mwb_stb <= 1'b1;
                        o_mwb_we  <= 1'b0;
                        o_mwb_addr<= cfg_raddr;
                        nwritten  <= 0;
                        nread     <= 0;
                        nacks     <= 0;
                end else begin
                        o_mwb_cyc  <= 1'b0;
                        o_mwb_stb  <= 1'b0;
                        o_mwb_we   <= 1'b0;
                        o_mwb_addr <= cfg_raddr;
                        o_interrupt<= 1'b0;
                        nwritten   <= 0;
                        if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we))
                        begin
                                cfg_wp <= 1'b1;
                                case(i_swb_addr)
                                2'b00: begin
                                        cfg_wp    <= (i_swb_data[27:16]!=12'hfed);
                                        cfg_blocklen_sub_one
                                                <= i_swb_data[(LGMEMLEN-1):0]
                                                + {(LGMEMLEN){1'b1}};
                                                // i.e. -1;
                                        cfg_dev_trigger    <= i_swb_data[14:10];
                                        cfg_on_dev_trigger <= i_swb_data[15];
                                        cfg_incs  <= ~i_swb_data[29];
                                        cfg_incd  <= ~i_swb_data[28];
                                        cfg_err   <= 1'b0;
                                        end
                                2'b01: cfg_len   <=  i_swb_data[(AW-1):0];
                                2'b10: cfg_raddr <=  i_swb_data[(AW-1):0];
                                2'b11: cfg_waddr <=  i_swb_data[(AW-1):0];
                                endcase
                        end
                end
 
        //
        // This is tricky.  In order for Vivado to consider dma_mem to be a 
        // proper memory, it must have a simple address fed into it.  Hence
        // the read_address (rdaddr) register.  The problem is that this
        // register must always be one greater than the address we actually
        // want to read from, unless we are idling.  So ... the math is touchy.
        //
        reg     [(LGMEMLEN-1):0] rdaddr;
        always @(posedge i_clk)
                if ((o_mwb_cyc)&&(o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall))
                        // This would be the normal advance, save that we are
                        // already one ahead of nwritten
                        rdaddr <= rdaddr + 1; // {{(LGMEMLEN-1){1'b0}},1};
                else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err))
                        // Here's where we do our extra advance
                        rdaddr <= nwritten[(LGMEMLEN-1):0]+1;
                else if ((~o_mwb_cyc)||(~o_mwb_we))
                        rdaddr <= nwritten[(LGMEMLEN-1):0];
        always @(posedge i_clk)
                if ((~o_mwb_cyc)||((o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall)))
                        o_mwb_data <= dma_mem[rdaddr];
        always @(posedge i_clk)
                if ((o_mwb_cyc)&&(~o_mwb_we)&&(i_mwb_ack))
                        dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;
 
        always @(posedge i_clk)
                casez(i_swb_addr)
                2'b00: o_swb_data <= {  ~cfg_wp, cfg_err,
                                        ~cfg_incs, ~cfg_incd,
                                        1'b0, nread,
                                        cfg_on_dev_trigger, cfg_dev_trigger,
                                        cfg_blocklen_sub_one
                                        };
                2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len  };
                2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr};
                2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr};
                endcase
 
        always @(posedge i_clk)
                if ((i_swb_cyc)&&(i_swb_stb)) // &&(~i_swb_we))
                        o_swb_ack <= 1'b1;
                // else if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)&&(~o_mwb_cyc)&&(nread == 0))
                else
                        o_swb_ack <= 1'b0;
 
        assign  o_swb_stall = 1'b0;
 
endmodule
 

Line No.	Rev	Author	Line
1	36	dgisselq	`////////////////////////////////////////////////////////////////////////////////`
2			`//`
3			`//`
4			`// Filename: wbdmac.v`
5			`//`
6			`// Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
7			`//`
8			`// Purpose: Wishbone DMA controller`
9			`//`
10			`// This module is controllable via the wishbone, and moves values from`
11			`// one location in the wishbone address space to another. The amount of`
12			`// memory moved at any given time can be up to 4kB, or equivalently 1kW.`
13			`// Four registers control this DMA controller: a control/status register,`
14			`// a length register, a source WB address and a destination WB address.`
15			`// These register may be read at any time, but they may only be written`
16			`// to when the controller is idle.`
17			`//`
18			`// The meanings of three of the setup registers should be self explanatory:`
19			`// - The length register controls the total number of words to`
20			`// transfer.`
21			`// - The source address register controls where the DMA controller`
22			`// reads from. This address may or may not be incremented`
23			`// after each read, depending upon the setting in the`
24			`// control/status register.`
25			`// - The destination address register, which controls where the DMA`
26			`// controller writes to. This address may or may not be`
27			`// incremented after each write, also depending upon the`
28			`// setting in the control/status register.`
29			`//`
30			`// It is the control/status register, at local address zero, that needs`
31			`// more definition:`
32			`//`
33			`// Bits:`
34			`// 31 R Write protect If this is set to one, it means the`
35			`// write protect bit is set and the controller`
36			`// is therefore idle. This bit will be set upon`
37			`// completing any transfer.`
38			`// 30 R Error. The controller stopped mid-transfer`
39			`// after receiving a bus error.`
40			`// 29 R/W inc_s_n If set to one, the source address`
41			`// will not increment from one read to the next.`
42			`// 28 R/W inc_d_n If set to one, the destination address`
43			`// will not increment from one write to the next.`
44			`// 27 R Always 0`
45			`// 26..16 R nread Indicates how many words have been read,`
46			`// and not necessarily written (yet). This`
47			`// combined with the cfg_len parameter should tell`
48			`// exactly where the controller is at mid-transfer.`
49			`// 27..16 W WriteProtect When a 12'h3db is written to these`
50			`// bits, the write protect bit will be cleared.`
51			`//`
52			`// 15 R/W on_dev_trigger When set to '1', the controller will`
53			`// wait for an external interrupt before starting.`
54			`// 14..10 R/W device_id This determines which external interrupt`
55			`// will trigger a transfer.`
56			`// 9..0 R/W transfer_len How many bytes to transfer at one time.`
57			`// The minimum transfer length is one, while zero`
58			`// is mapped to a transfer length of 1kW.`
59			`//`
60			`//`
61			`// To use this, follow this checklist:`
62			`// 1. Wait for any prior DMA operation to complete`
63			`// (Read address 0, wait 'till either top bit is set or cfg_len==0)`
64			`// 2. Write values into length, source and destination address.`
65			`// (writei(3, &vals) should be sufficient for this.)`
66			`// 3. Enable the DMAC interrupt in whatever interrupt controller is present`
67			`// on the system.`
68			`// 4. Write the final start command to the setup/control/status register:`
69			`// Set inc_s_n, inc_d_n, on_dev_trigger, dev_trigger,`
70			`// appropriately for your task`
71			`// Write 12'h3db to the upper word.`
72			`// Set the lower word to either all zeros, or a smaller transfer`
73			`// length if desired.`
74			`// 5. wait() for the interrupt and the operation to complete.`
75			`// Prior to completion, number of items successfully transferred`
76			`// be read from the length register. If the internal buffer is`
77			`// being used, then you can read how much has been read into that`
78			`// buffer by reading from bits 25..16 of this control/status`
79			`// register.`
80			`//`
81			`// Creator: Dan Gisselquist`
82	69	dgisselq	`// Gisselquist Technology, LLC`
83	36	dgisselq	`//`
84			`// Copyright: 2015`
85			`//`
86			`//`
87			`////////////////////////////////////////////////////////////////////////////////`
88			`//`
89			`// Copyright (C) 2015, Gisselquist Technology, LLC`
90			`//`
91			`// This program is free software (firmware): you can redistribute it and/or`
92			`// modify it under the terms of the GNU General Public License as published`
93			`// by the Free Software Foundation, either version 3 of the License, or (at`
94			`// your option) any later version.`
95			`//`
96			`// This program is distributed in the hope that it will be useful, but WITHOUT`
97			`// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or`
98			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
99			`// for more details.`
100			`//`
101			`// License: GPL, v3, as defined and found on www.gnu.org,`
102			`// http://www.gnu.org/licenses/gpl.html`
103			`//`
104			`//`
105			`///////////////////////////////////////////////////////////////////////////`
106			`//`
107			`//`
108			`module wbdmac(i_clk,`
109			`i_swb_cyc, i_swb_stb, i_swb_we, i_swb_addr, i_swb_data,`
110			`o_swb_ack, o_swb_stall, o_swb_data,`
111			`o_mwb_cyc, o_mwb_stb, o_mwb_we, o_mwb_addr, o_mwb_data,`
112			`i_mwb_ack, i_mwb_stall, i_mwb_data, i_mwb_err,`
113			`i_dev_ints,`
114	69	dgisselq	`o_interrupt);`
115	48	dgisselq	`parameter ADDRESS_WIDTH=32, LGMEMLEN = 10,`
116			`DW=32, LGDV=5,AW=ADDRESS_WIDTH;`
117	36	dgisselq	`input i_clk;`
118			`// Slave/control wishbone inputs`
119			`input i_swb_cyc, i_swb_stb, i_swb_we;`
120			`input [1:0] i_swb_addr;`
121			`input [(DW-1):0] i_swb_data;`
122			`// Slave/control wishbone outputs`
123			`output reg o_swb_ack;`
124			`output wire o_swb_stall;`
125			`output reg [(DW-1):0] o_swb_data;`
126			`// Master/DMA wishbone control`
127			`output reg o_mwb_cyc, o_mwb_stb, o_mwb_we;`
128	48	dgisselq	`output reg [(AW-1):0] o_mwb_addr;`
129			`output reg [(DW-1):0] o_mwb_data;`
130	36	dgisselq	`// Master/DMA wishbone responses from the bus`
131			`input i_mwb_ack, i_mwb_stall;`
132			`input [(DW-1):0] i_mwb_data;`
133			`input i_mwb_err;`
134			`// The interrupt device interrupt lines`
135			`input [(DW-1):0] i_dev_ints;`
136			`// An interrupt to be set upon completion`
137			`output reg o_interrupt;`
138			`// Need to release the bus for a higher priority user`
139	69	dgisselq	`// This logic had lots of problems, so it is being`
140			`// removed. If you want to make sure the bus is available`
141			`// for a higher priority user, adjust the transfer length`
142			`// accordingly.`
143			`//`
144			`// input i_other_busmaster_requests_bus;`
145			`//`
146	36	dgisselq
147
148			`reg cfg_wp; // Write protect`
149			`reg cfg_err;`
150	48	dgisselq	`reg [(AW-1):0] cfg_waddr, cfg_raddr, cfg_len;`
151	36	dgisselq	`reg [(LGMEMLEN-1):0] cfg_blocklen_sub_one;`
152			`reg cfg_incs, cfg_incd;`
153			`reg [(LGDV-1):0] cfg_dev_trigger;`
154			`reg cfg_on_dev_trigger;`
155
156			`// Single block operations: We'll read, then write, up to a single`
157			`// memory block here.`
158
159			`reg [(DW-1):0] dma_mem [0:(((1<<LGMEMLEN))-1)];`
160			`reg [(LGMEMLEN):0] nread, nwritten, nacks;`
161	48	dgisselq	`wire [(AW-1):0] bus_nacks;`
162			`assign bus_nacks = { {(AW-LGMEMLEN-1){1'b0}}, nacks };`
163	36	dgisselq
164			`initial o_interrupt = 1'b0;`
165			`initial o_mwb_cyc = 1'b0;`
166			`initial cfg_err = 1'b0;`
167			`initial cfg_wp = 1'b0;`
168	48	dgisselq	`initial cfg_len = {(AW){1'b0}};`
169	36	dgisselq	`initial cfg_blocklen_sub_one = {(LGMEMLEN){1'b1}};`
170			`initial cfg_on_dev_trigger = 1'b0;`
171			`always @(posedge i_clk)`
172			`if ((o_mwb_cyc)&&(o_mwb_we)) // Write cycle`
173			`begin`
174			`if ((o_mwb_stb)&&(~i_mwb_stall))`
175			`begin`
176			`nwritten <= nwritten+1;`
177	69	dgisselq	`if (nwritten == nread-1)`
178	36	dgisselq	`// Wishbone interruptus`
179			`o_mwb_stb <= 1'b0;`
180			`else if (cfg_incd) begin`
181			`o_mwb_addr <= o_mwb_addr + 1;`
182			`cfg_waddr <= cfg_waddr + 1;`
183			`end`
184			`// o_mwb_data <= dma_mem[nwritten + 1];`
185			`end`
186
187			`if (i_mwb_err)`
188			`begin`
189			`o_mwb_cyc <= 1'b0;`
190			`cfg_err <= 1'b1;`
191			`cfg_len <= 0;`
192			`nread <= 0;`
193			`end else if (i_mwb_ack)`
194			`begin`
195			`nacks <= nacks+1;`
196			`cfg_len <= cfg_len - 1;`
197			`if ((nacks+1 == nwritten)&&(~o_mwb_stb))`
198			`begin`
199			`o_mwb_cyc <= 1'b0;`
200			`nread <= 0;`
201			`o_interrupt <= (cfg_len == 1);`
202			`// Turn write protect back on`
203			`cfg_wp <= 1'b1;`
204			`end`
205			`end`
206			`end else if ((o_mwb_cyc)&&(~o_mwb_we)) // Read cycle`
207			`begin`
208			`if ((o_mwb_stb)&&(~i_mwb_stall))`
209			`begin`
210			`nacks <= nacks+1;`
211			`if ((nacks == {1'b0, cfg_blocklen_sub_one})`
212	69	dgisselq	`\|\|(bus_nacks <= cfg_len-1))`
213	36	dgisselq	`// Wishbone interruptus`
214			`o_mwb_stb <= 1'b0;`
215			`else if (cfg_incs) begin`
216			`o_mwb_addr <= o_mwb_addr + 1;`
217			`end`
218			`end`
219
220			`if (i_mwb_err)`
221			`begin`
222			`o_mwb_cyc <= 1'b0;`
223			`cfg_err <= 1'b1;`
224			`cfg_len <= 0;`
225			`nread <= 0;`
226			`end else if (i_mwb_ack)`
227			`begin`
228			`nread <= nread+1;`
229			`if ((~o_mwb_stb)&&(nread+1 == nacks))`
230			`begin`
231			`o_mwb_cyc <= 1'b0;`
232			`nacks <= 0;`
233			`end`
234			`if (cfg_incs)`
235			`cfg_raddr <= cfg_raddr + 1;`
236			`// dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;`
237			`end`
238			`end else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err))`
239			`begin // Initiate/continue a write cycle`
240			`o_mwb_cyc <= 1'b1;`
241			`o_mwb_stb <= 1'b1;`
242			`o_mwb_we <= 1'b1;`
243			`// o_mwb_data <= dma_mem[0];`
244			`o_mwb_addr <= cfg_waddr;`
245			`// nwritten <= 0; // Can't set to zero, in case we're`
246			`// nacks <= 0; // continuing a cycle`
247			`end else if ((~o_mwb_cyc)&&(nread == 0)&&(cfg_len>0)&&(~cfg_wp)`
248			`&&((~cfg_on_dev_trigger)`
249			`\|\|(i_dev_ints[cfg_dev_trigger])))`
250			`begin // Initiate a read cycle`
251			`o_mwb_cyc <= 1'b1;`
252			`o_mwb_stb <= 1'b1;`
253			`o_mwb_we <= 1'b0;`
254			`o_mwb_addr<= cfg_raddr;`
255			`nwritten <= 0;`
256			`nread <= 0;`
257			`nacks <= 0;`
258			`end else begin`
259			`o_mwb_cyc <= 1'b0;`
260			`o_mwb_stb <= 1'b0;`
261			`o_mwb_we <= 1'b0;`
262			`o_mwb_addr <= cfg_raddr;`
263			`o_interrupt<= 1'b0;`
264			`nwritten <= 0;`
265			`if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we))`
266			`begin`
267			`cfg_wp <= 1'b1;`
268			`case(i_swb_addr)`
269			`2'b00: begin`
270			`cfg_wp <= (i_swb_data[27:16]!=12'hfed);`
271			`cfg_blocklen_sub_one`
272	88	dgisselq	`<= i_swb_data[(LGMEMLEN-1):0]`
273			`+ {(LGMEMLEN){1'b1}};`
274			`// i.e. -1;`
275	36	dgisselq	`cfg_dev_trigger <= i_swb_data[14:10];`
276			`cfg_on_dev_trigger <= i_swb_data[15];`
277			`cfg_incs <= ~i_swb_data[29];`
278			`cfg_incd <= ~i_swb_data[28];`
279			`cfg_err <= 1'b0;`
280			`end`
281	48	dgisselq	`2'b01: cfg_len <= i_swb_data[(AW-1):0];`
282			`2'b10: cfg_raddr <= i_swb_data[(AW-1):0];`
283			`2'b11: cfg_waddr <= i_swb_data[(AW-1):0];`
284	36	dgisselq	`endcase`
285			`end`
286			`end`
287
288			`//`
289			`// This is tricky. In order for Vivado to consider dma_mem to be a`
290			`// proper memory, it must have a simple address fed into it. Hence`
291			`// the read_address (rdaddr) register. The problem is that this`
292			`// register must always be one greater than the address we actually`
293			`// want to read from, unless we are idling. So ... the math is touchy.`
294			`//`
295			`reg [(LGMEMLEN-1):0] rdaddr;`
296			`always @(posedge i_clk)`
297			`if ((o_mwb_cyc)&&(o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall))`
298			`// This would be the normal advance, save that we are`
299			`// already one ahead of nwritten`
300			`rdaddr <= rdaddr + 1; // {{(LGMEMLEN-1){1'b0}},1};`
301			`else if ((~o_mwb_cyc)&&(nread > 0)&&(~cfg_err))`
302			`// Here's where we do our extra advance`
303			`rdaddr <= nwritten[(LGMEMLEN-1):0]+1;`
304			`else if ((~o_mwb_cyc)\|\|(~o_mwb_we))`
305			`rdaddr <= nwritten[(LGMEMLEN-1):0];`
306			`always @(posedge i_clk)`
307			`if ((~o_mwb_cyc)\|\|((o_mwb_we)&&(o_mwb_stb)&&(~i_mwb_stall)))`
308			`o_mwb_data <= dma_mem[rdaddr];`
309			`always @(posedge i_clk)`
310			`if ((o_mwb_cyc)&&(~o_mwb_we)&&(i_mwb_ack))`
311			`dma_mem[nread[(LGMEMLEN-1):0]] <= i_mwb_data;`
312
313			`always @(posedge i_clk)`
314			`casez(i_swb_addr)`
315			`2'b00: o_swb_data <= { ~cfg_wp, cfg_err,`
316			`~cfg_incs, ~cfg_incd,`
317			`1'b0, nread,`
318			`cfg_on_dev_trigger, cfg_dev_trigger,`
319			`cfg_blocklen_sub_one`
320			`};`
321	48	dgisselq	`2'b01: o_swb_data <= { {(DW-AW){1'b0}}, cfg_len };`
322			`2'b10: o_swb_data <= { {(DW-AW){1'b0}}, cfg_raddr};`
323			`2'b11: o_swb_data <= { {(DW-AW){1'b0}}, cfg_waddr};`
324	36	dgisselq	`endcase`
325
326			`always @(posedge i_clk)`
327			`if ((i_swb_cyc)&&(i_swb_stb)) // &&(~i_swb_we))`
328			`o_swb_ack <= 1'b1;`
329			`// else if ((i_swb_cyc)&&(i_swb_stb)&&(i_swb_we)&&(~o_mwb_cyc)&&(nread == 0))`
330			`else`
331			`o_swb_ack <= 1'b0;`
332
333			`assign o_swb_stall = 1'b0;`
334
335			`endmodule`
336

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