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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [wbwatchdog.v] - Blame information for rev 209

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1 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    wbwatchdog.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     A Zip timer, redesigned to be a bus watchdog
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//
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//      This is basically a timer, but there are some unique features to it.
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//
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//      1. There is no way to "write" the timeout to this watchdog.  It is
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//              fixed with an input (that is assumed to be constant)
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//      2. The counter returns to i_timer and the interrupt is cleared on any
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//              reset.
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//      3. Between resets, the counter counts down to zero.  Once (and if) it
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//              hits zero, it will remain at zero until reset.
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//      4. Any time the counter is at zero, and until the reset that resets
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//              the counter, the output interrupt will be set.
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015,2017-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype        none
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//
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module  wbwatchdog(i_clk, i_reset, i_timeout, o_int);
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        parameter       BW = 32;
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        input   wire            i_clk, i_reset;
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        // Inputs (these were at one time wishbone controlled ...)
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        input   wire [(BW-1):0]  i_timeout;
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        // Interrupt line
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        output  reg             o_int;
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        reg     [(BW-1):0]       r_value;
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        initial r_value = {(BW){1'b1}};
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        always @(posedge i_clk)
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                if (i_reset)
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                        r_value <= i_timeout[(BW-1):0];
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                else if (!o_int)
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                        r_value <= r_value + {(BW){1'b1}}; // r_value - 1;
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        // Set the interrupt on our last tick.
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        initial o_int   = 1'b0;
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        always @(posedge i_clk)
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                if (i_reset)
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                        o_int <= 1'b0;
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                else if (!o_int)
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                        o_int <= (r_value == { {(BW-1){1'b0}}, 1'b1 });
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`ifdef  FORMAL
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        reg     f_past_valid;
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        initial f_past_valid = 1'b0;
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        always @(posedge f_past_valid)
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                f_past_valid <= 1'b1;
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        ///////////////////////////////////////////////
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        //
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        //
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        // Assumptions about our inputs
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        //
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        //
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        ///////////////////////////////////////////////
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        always @(*)
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                assume(i_timeout > 1);
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        always @(posedge i_clk)
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        if (f_past_valid)
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                assume(i_timeout == $past(i_timeout));
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        //
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        //
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        ///////////////////////////////////////////////
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        //
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        //
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        // Assertions about our internal state and our outputs
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        //
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        //
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        ///////////////////////////////////////////////
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        //
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        //
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        always @(posedge i_clk)
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        if ((f_past_valid)&&($past(o_int))&&(!$past(i_reset)))
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                assert(o_int);
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        always @(*)
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                assert(o_int == (r_value == 0));
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        always @(posedge i_clk)
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        if ((f_past_valid)&&(!$past(i_reset))&&(!$past(o_int)))
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        begin
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                assert(r_value == $past(r_value)-1'b1);
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        end
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        always @(posedge i_clk)
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        if ((!f_past_valid)||($past(i_reset)))
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        begin
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                if (!f_past_valid)
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                        assert(r_value == {(BW){1'b1}});
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                else // if ($past(i_reset))
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                        assert(r_value == $past(i_timeout));
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                assert(!o_int);
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        end
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`endif
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endmodule

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