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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [zipcounter.v] - Blame information for rev 209

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1 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipcounter.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:
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//              A very, _very_ simple counter.  It's purpose doesn't really
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//      include rollover, but it will interrupt on rollover.  It can be set,
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//      although my design concept is that it can be reset.  It cannot be
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//      halted.  It will always produce interrupts--whether or not they are 
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//      handled interrupts is another question--that's up to the interrupt
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//      controller.
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//
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//      My intention is to use this counter for process accounting: I should
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//      be able to use this to count clock ticks of processor time assigned to
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//      each task by resetting the counter at the beginning of every task
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//      interval, and reading the result at the end of the interval.  As long
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//      as the interval is less than 2^32 clocks, there should be no problem.
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//      Similarly, this can be used to measure CPU wishbone bus stalls, 
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//      prefetch stalls, or other CPU stalls (i.e. stalling as part of a JMP
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//      instruction, or a read from the condition codes following a write).
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2019, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
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// target there if the PDF file isn't present.)  If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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`default_nettype        none
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//
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module  zipcounter(i_clk, i_reset, i_event,
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                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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                        o_wb_ack, o_wb_stall, o_wb_data,
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                o_int);
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        parameter       BW = 32;
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        //
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        localparam      F_LGDEPTH = 2;
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        //
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        input   wire                    i_clk, i_reset, i_event;
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        // Wishbone inputs
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        input   wire                    i_wb_cyc, i_wb_stb, i_wb_we;
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        input   wire    [(BW-1):0]       i_wb_data;
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        // Wishbone outputs
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        output  reg                     o_wb_ack;
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        output  wire                    o_wb_stall;
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        output  reg     [(BW-1):0]       o_wb_data;
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        // Interrupt line
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        output  reg                     o_int;
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        initial o_int = 0;
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        initial o_wb_data = 32'h00;
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        always @(posedge i_clk)
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                if (i_reset)
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                        { o_int, o_wb_data } <= 0;
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                else if ((i_wb_stb)&&(i_wb_we))
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                        { o_int, o_wb_data } <= { 1'b0, i_wb_data };
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                else if (i_event)
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                        { o_int, o_wb_data } <= o_wb_data+{{(BW-1){1'b0}},1'b1};
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                else
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                        o_int <= 1'b0;
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        initial o_wb_ack = 1'b0;
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        always @(posedge i_clk)
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        if (i_reset)
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                o_wb_ack <= 1'b0;
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        else
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                o_wb_ack <= i_wb_stb;
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        assign  o_wb_stall = 1'b0;
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        // Make verilator happy
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        // verilator lint_off UNUSED
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        wire    unused;
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        assign  unused = i_wb_cyc;
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        // verilator lint_on  UNUSED
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`ifdef  FORMAL
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        reg     f_past_valid;
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        initial f_past_valid = 1'b0;
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        always @(posedge i_clk)
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                f_past_valid <= 1'b1;
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        always @(*)
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        if (!f_past_valid)
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                assume(i_reset);
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        ////////////////////////////////////////////////
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        //
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        //
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        // Assumptions about our inputs
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        //
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        //
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        ////////////////////////////////////////////////
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        //
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        ////////////////////////////////////////////////
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        //
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        //
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        // Bus interface properties
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        //
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        //
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        ////////////////////////////////////////////////
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        //
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        // We never stall the bus
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        always @(*)
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                assert(!o_wb_stall);
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        // We always ack every transaction on the following clock
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        always @(posedge i_clk)
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                assert(o_wb_ack == ((f_past_valid)&&(!$past(i_reset))
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                                                &&($past(i_wb_stb))));
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        wire    [(F_LGDEPTH-1):0]        f_nreqs, f_nacks, f_outstanding;
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        fwb_slave #( .AW(1), .F_MAX_STALL(0),
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                        .F_MAX_ACK_DELAY(1), .F_LGDEPTH(F_LGDEPTH)
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                ) fwbi(i_clk, i_reset,
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                i_wb_cyc, i_wb_stb, i_wb_we, 1'b0, i_wb_data, 4'hf,
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                        o_wb_ack, o_wb_stall, o_wb_data, 1'b0,
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                f_nreqs, f_nacks, f_outstanding);
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        always @(*)
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        if ((o_wb_ack)&&(i_wb_cyc))
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                assert(f_outstanding==1);
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        else
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                assert(f_outstanding == 0);
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        ////////////////////////////////////////////////
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        //
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        //
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        // Assumptions about our outputs
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        //
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        //
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        ////////////////////////////////////////////////
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        //
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        // Drop the interrupt line and reset the counter on any reset
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        always @(posedge i_clk)
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        if ((f_past_valid)&&($past(i_reset)))
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                assert((!o_int)&&(o_wb_data == 0));
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        // Clear the interrupt and set the counter on any write (other than
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        // during a reset)
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        always @(posedge i_clk)
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        if ((f_past_valid)&&(!$past(i_reset))
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                &&($past(i_wb_stb))&&($past(i_wb_we)))
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                assert((!o_int)&&(o_wb_data == $past(i_wb_data)));
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        // Normal logic of the routine itself
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        always @(posedge i_clk)
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        if ((f_past_valid)&&(!$past(i_reset))&&(!$past(i_wb_stb)))
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        begin
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                if (!$past(i_event))
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                begin
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                        // If the CE line wasn't set on the last clock, then the
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                        // counter must not change, and the interrupt line must
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                        // be low.
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                        assert(o_wb_data == $past(o_wb_data));
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                        assert(!o_int);
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                end else // if ($past(i_event))
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                begin
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                        // Otherwise, if the CE line was high on the last clock,
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                        // then our counter should have incremented.
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                        assert(o_wb_data == $past(o_wb_data) + 1'b1);
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                        // Likewise, if the counter rolled over, then the
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                        // output interrupt, o_int, should be true.
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                        if ($past(o_wb_data)=={(BW){1'b1}})
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                                assert(o_int);
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                        else
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                                // In all other circumstances it should be clear
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                                assert(!o_int);
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                end
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        end
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        //
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        // The output interrupt should never be true two clocks in a row
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        always @(posedge i_clk)
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        if ((f_past_valid)&&($past(o_int)))
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                assert(!o_int);
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`endif
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endmodule

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