OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [zipjiffies.v] - Blame information for rev 201

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipjiffies.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This peripheral is motivated by the Linux use of 'jiffies'.
8
//      A process, in Linux, can request to be put to sleep until a certain
9
//      number of 'jiffies' have elapsed.  Using this interface, the CPU can
10
//      read the number of 'jiffies' from this peripheral (it only has the
11
//      one location in address space), add the sleep length to it, and
12
//      write the result back to the peripheral.  The zipjiffies peripheral
13
//      will record the value written to it only if it is nearer the current
14
//      counter value than the last current waiting interrupt time.  If no
15
//      other interrupts are waiting, and this time is in the future, it will
16
//      be enabled.  (There is currrently no way to disable a jiffie interrupt
17
//      once set.)  The processor may then place this sleep request into a
18
//      list among other sleep requests.  Once the timer expires, it would
19
//      write the next jiffy request to the peripheral and wake up the process
20
//      whose timer had expired.
21
//
22
//      Quite elementary, really.
23
//
24
// Interface:
25
//      This peripheral contains one register: a counter.  Reads from the
26
//      register return the current value of the counter.  Writes within
27
//      the (N-1) bit space following the current time set an interrupt.
28
//      Writes of values that occurred in the last 2^(N-1) ticks will be
29
//      ignored.  The timer then interrupts when it's value equals that time. 
30
//      Multiple writes cause the jiffies timer to select the nearest possible
31
//      interrupt.  Upon an interrupt, the next interrupt time/value is cleared
32
//      and will need to be reset if the CPU wants to get notified again.  With
33
//      only the single interface, there is no way of knowing when the next
34
//      interrupt is scheduled for, neither is there any way to slow down the
35
//      interrupt timer in case you don't want it overflowing as often and you
36
//      wish to wait more jiffies than it supports.  Thus, currently, if you
37
//      have a timer you wish to wait upon that is more than 2^31 into the
38
//      future, you would need to set timers along the way, wake up on those
39
//      timers, and set further timer's until you finally get to your
40
//      destination.
41
//
42
//
43
// Creator:     Dan Gisselquist, Ph.D.
44 69 dgisselq
//              Gisselquist Technology, LLC
45 2 dgisselq
//
46
////////////////////////////////////////////////////////////////////////////////
47
//
48 201 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
49 2 dgisselq
//
50
// This program is free software (firmware): you can redistribute it and/or
51
// modify it under the terms of  the GNU General Public License as published
52
// by the Free Software Foundation, either version 3 of the License, or (at
53
// your option) any later version.
54
//
55
// This program is distributed in the hope that it will be useful, but WITHOUT
56
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
57
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
58
// for more details.
59
//
60 201 dgisselq
// You should have received a copy of the GNU General Public License along
61
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
62
// target there if the PDF file isn't present.)  If not, see
63
// <http://www.gnu.org/licenses/> for a copy.
64
//
65 2 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
66
//              http://www.gnu.org/licenses/gpl.html
67
//
68
//
69
////////////////////////////////////////////////////////////////////////////////
70
//
71 201 dgisselq
//
72 2 dgisselq
module  zipjiffies(i_clk, i_ce,
73
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
74
                        o_wb_ack, o_wb_stall, o_wb_data,
75
                o_int);
76 160 dgisselq
        parameter       BW = 32;
77 2 dgisselq
        input                           i_clk, i_ce;
78
        // Wishbone inputs
79
        input                           i_wb_cyc, i_wb_stb, i_wb_we;
80
        input           [(BW-1):0]       i_wb_data;
81
        // Wishbone outputs
82
        output  reg                     o_wb_ack;
83
        output  wire                    o_wb_stall;
84
        output  wire    [(BW-1):0]       o_wb_data;
85
        // Interrupt line
86
        output  reg                     o_int;
87
 
88
        //
89
        // Our counter logic: The counter is always counting up--it cannot
90
        // be stopped or altered.  It's really quite simple.  Okay, not quite.
91
        // We still support the clock enable line.  We do this in order to
92
        // support debugging, so that if we get everything running inside a
93
        // debugger, the timer's all slow down so that everything can be stepped
94
        // together, one clock at a time.
95
        //
96
        reg     [(BW-1):0]       r_counter;
97
        always @(posedge i_clk)
98
                if (i_ce)
99
                        r_counter <= r_counter+1;
100
 
101
        //
102
        // Writes to the counter set an interrupt--but only if they are in the
103
        // future as determined by the signed result of an unsigned subtract.
104
        //
105
        reg                             int_set,  new_set;
106
        reg             [(BW-1):0]       int_when, new_when;
107
        wire    signed  [(BW-1):0]       till_when, till_wb;
108
        assign  till_when = int_when-r_counter;
109
        assign  till_wb   = new_when-r_counter;
110 9 dgisselq
 
111
        initial new_set = 1'b0;
112
        always @(posedge i_clk)
113 160 dgisselq
        begin
114 9 dgisselq
                // Delay things by a clock to simplify our logic
115 160 dgisselq
                new_set <= ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we));
116
                // new_when is a don't care when new_set = 0, so don't worry
117
                // about setting it at all times.
118
                new_when<= i_wb_data;
119
        end
120 9 dgisselq
 
121 2 dgisselq
        initial o_int   = 1'b0;
122
        initial int_set = 1'b0;
123
        always @(posedge i_clk)
124
        begin
125
                o_int <= 1'b0;
126
                if ((i_ce)&&(int_set)&&(r_counter == int_when))
127 160 dgisselq
                        // Interrupts are self-clearing
128
                        o_int <= 1'b1;  // Set the interrupt flag for one clock
129
                else if ((new_set)&&(till_wb <= 0))
130
                        o_int <= 1'b1;
131 2 dgisselq
 
132 160 dgisselq
                if ((new_set)&&(till_wb > 0))
133
                        int_set <= 1'b1;
134
                else if ((i_ce)&&(r_counter == int_when))
135
                        int_set <= 1'b0;
136
 
137 2 dgisselq
                if ((new_set)&&(till_wb > 0)&&((till_wb<till_when)||(~int_set)))
138
                        int_when <= new_when;
139
        end
140
 
141
        //
142
        // Acknowledge any wishbone accesses -- everything we did took only
143
        // one clock anyway.
144
        //
145
        always @(posedge i_clk)
146
                o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
147 9 dgisselq
 
148 2 dgisselq
        assign  o_wb_data = r_counter;
149
        assign  o_wb_stall = 1'b0;
150
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.