OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [ziptrap.v] - Blame information for rev 69

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    ziptrap.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     On any write, generate an interrupt.  On any read, return
8
//              the value from the last write.
9
//
10
//      This peripheral was added to the Zip System to compensate for the lack
11
//      of any trap instruction within the Zip instruction set.  Such an 
12
//      instruction is used heavily by modern operating systems to switch
13
//      from a user process to a system process.  Since there was no way
14
//      to build such an interface without a trap instruction, this was added
15
//      to accomplish that purpose.
16
//
17
//      However, in early simulation testing it was discovered that this
18
//      approach would not be very suitable: the interrupt was not generated
19
//      the next clock as one would expect.  Hence, executing a trap became:
20
//
21
//              TRAP    $5              MOV $TrapAddr, R0
22
//                                      LDI $5,R1
23
//                                      STO R1,(R0)
24
//                                      NOOP
25
//                                      NOOP -- here the trap would take effect
26
//              ADD $5,R6               ADD $5,R6
27
//
28
//      This was too cumbersome, necessitating NOOPS and such.  Therefore,
29
//      the CC register was extended to hold a trap value.  This leads to
30
//
31
//              TRAP $5                 LDI     $500h,CC
32
//                              ; Trap executes immediately, user sees no
33
//                              ; delay's, no extra wait instructions.
34
//              ADD $5,R6               ADD $5,R6
35
//
36
//      (BTW: The add is just the "next instruction", whatever that may be.)
37
//      Note the difference: there's no longer any need to load the trap
38
//      address into a register (something that usually could not be done with
39
//      a move, but rather a LDIHI/LDILO pair).  There's no longer any wait
40
//      for the Wishbone bus, which could've introduced a variable delay.
41
//      Neither are there any wait states while waiting for the system process
42
//      to take over and respond.  Oh, and another difference, the new approach
43
//      no longer requires the system to activate an interrupt line--the user
44
//      process can always initiate such an interrupt.  Hence, the new
45
//      solution is better rendering this peripheral obsolete.
46
//
47
//      It is maintained here to document this part of the learning process.
48
//
49
//
50
//
51
// Creator:     Dan Gisselquist, Ph.D.
52 69 dgisselq
//              Gisselquist Technology, LLC
53 2 dgisselq
//
54
///////////////////////////////////////////////////////////////////////////
55
//
56
// Copyright (C) 2015, Gisselquist Technology, LLC
57
//
58
// This program is free software (firmware): you can redistribute it and/or
59
// modify it under the terms of  the GNU General Public License as published
60
// by the Free Software Foundation, either version 3 of the License, or (at
61
// your option) any later version.
62
//
63
// This program is distributed in the hope that it will be useful, but WITHOUT
64
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
65
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
66
// for more details.
67
//
68
// License:     GPL, v3, as defined and found on www.gnu.org,
69
//              http://www.gnu.org/licenses/gpl.html
70
//
71
//
72
///////////////////////////////////////////////////////////////////////////
73
//
74
module  ziptrap(i_clk,
75
                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
76
                        o_wb_ack, o_wb_stall, o_wb_data,
77
                o_int);
78
        parameter               BW = 32; // Bus width
79
        input                           i_clk;
80
        // Wishbone inputs
81
        input                           i_wb_cyc, i_wb_stb, i_wb_we;
82
        input           [(BW-1):0]       i_wb_data;
83
        // Wishbone outputs
84
        output  reg                     o_wb_ack;
85
        output  wire                    o_wb_stall;
86
        output  reg     [(BW-1):0]       o_wb_data;
87
        // Interrupt output
88
        output  reg                     o_int;
89
 
90
        initial o_wb_ack = 1'b0;
91
        always @(posedge i_clk)
92
                o_wb_ack <= ((i_wb_cyc)&&(i_wb_stb));
93
        assign  o_wb_stall = 1'b0;
94
 
95
        // Initially set to some of bounds value, such as all ones.
96
        initial o_wb_data = {(BW){1'b1}};
97
        always @(posedge i_clk)
98
                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
99
                        o_wb_data <= i_wb_data;
100
 
101
        // Set the interrupt bit on any write.
102
        initial o_int = 1'b0;
103
        always @(posedge i_clk)
104
                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
105
                        o_int <= 1'b1;
106
                else
107
                        o_int <= 1'b0;
108
 
109
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.