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[/] [zipcpu/] [trunk/] [rtl/] [peripherals/] [ziptrap.v] - Blame information for rev 9

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
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//
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// Filename:    ziptrap.v
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     On any write, generate an interrupt.  On any read, return
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//              the value from the last write.
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//
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//      This peripheral was added to the Zip System to compensate for the lack
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//      of any trap instruction within the Zip instruction set.  Such an 
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//      instruction is used heavily by modern operating systems to switch
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//      from a user process to a system process.  Since there was no way
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//      to build such an interface without a trap instruction, this was added
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//      to accomplish that purpose.
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//
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//      However, in early simulation testing it was discovered that this
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//      approach would not be very suitable: the interrupt was not generated
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//      the next clock as one would expect.  Hence, executing a trap became:
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//
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//              TRAP    $5              MOV $TrapAddr, R0
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//                                      LDI $5,R1
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//                                      STO R1,(R0)
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//                                      NOOP
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//                                      NOOP -- here the trap would take effect
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//              ADD $5,R6               ADD $5,R6
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//
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//      This was too cumbersome, necessitating NOOPS and such.  Therefore,
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//      the CC register was extended to hold a trap value.  This leads to
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//
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//              TRAP $5                 LDI     $500h,CC
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//                              ; Trap executes immediately, user sees no
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//                              ; delay's, no extra wait instructions.
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//              ADD $5,R6               ADD $5,R6
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//
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//      (BTW: The add is just the "next instruction", whatever that may be.)
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//      Note the difference: there's no longer any need to load the trap
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//      address into a register (something that usually could not be done with
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//      a move, but rather a LDIHI/LDILO pair).  There's no longer any wait
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//      for the Wishbone bus, which could've introduced a variable delay.
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//      Neither are there any wait states while waiting for the system process
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//      to take over and respond.  Oh, and another difference, the new approach
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//      no longer requires the system to activate an interrupt line--the user
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//      process can always initiate such an interrupt.  Hence, the new
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//      solution is better rendering this peripheral obsolete.
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//
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//      It is maintained here to document this part of the learning process.
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//
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
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//              Gisselquist Tecnology, LLC
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//
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///////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////
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//
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module  ziptrap(i_clk,
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                i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data,
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                        o_wb_ack, o_wb_stall, o_wb_data,
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                o_int);
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        parameter               BW = 32; // Bus width
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        input                           i_clk;
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        // Wishbone inputs
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        input                           i_wb_cyc, i_wb_stb, i_wb_we;
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        input           [(BW-1):0]       i_wb_data;
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        // Wishbone outputs
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        output  reg                     o_wb_ack;
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        output  wire                    o_wb_stall;
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        output  reg     [(BW-1):0]       o_wb_data;
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        // Interrupt output
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        output  reg                     o_int;
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        initial o_wb_ack = 1'b0;
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        always @(posedge i_clk)
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                o_wb_ack <= ((i_wb_cyc)&&(i_wb_stb));
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        assign  o_wb_stall = 1'b0;
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        // Initially set to some of bounds value, such as all ones.
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        initial o_wb_data = {(BW){1'b1}};
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        always @(posedge i_clk)
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                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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                        o_wb_data <= i_wb_data;
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        // Set the interrupt bit on any write.
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        initial o_int = 1'b0;
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        always @(posedge i_clk)
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                if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
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                        o_int <= 1'b1;
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                else
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                        o_int <= 1'b0;
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endmodule

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