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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Blame information for rev 209

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1 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
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//
3
// Filename:    zipsystem.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This portion of the ZIP CPU implements a number of soft
8
//              peripherals to the CPU nearby its CORE.  The functionality
9 209 dgisselq
//      sits on the data bus, and does not include any true external hardware
10
//      peripherals.  The peripherals included here include:
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//
12
//      Local interrupt controller--for any/all of the interrupts generated
13
//              here.  This would include a pin for interrupts generated
14
//              elsewhere, so this interrupt controller could be a master
15
//              handling all interrupts.  My interrupt controller would work
16
//              for this purpose.
17
//
18
//              The ZIP-CPU supports only one interrupt because, as I understand
19
//              modern systems (Linux), they tend to send all interrupts to the
20
//              same interrupt vector anyway.  Hence, that's what we do here.
21
//
22
//      Interval timer(s) (Count down from fixed value, and either stop on
23
//              zero, or issue an interrupt and restart automatically on zero)
24
//              These can be implemented as watchdog timers if desired--the
25
//              only difference is that a watchdog timer's interrupt feeds the
26
//              reset line instead of the processor interrupt line.
27
//
28
//      Watch-dog timer: this is the same as an interval timer, only it's
29
//              interrupt/time-out line is wired to the reset line instead of
30
//              the interrupt line of the CPU.
31
//
32 209 dgisselq
//      Direct Memory Access Controller: This controller allows you to command
33
//              automatic memory moves.  Such memory moves will take place
34
//              without the CPU's involvement until they are done.  See the
35
//              DMA specification for more information. (Currently contained
36
//              w/in the ZipCPU spec.)
37 2 dgisselq
//
38 209 dgisselq
//      (Potentially an eventual floating point co-processor ...?)
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//
40 209 dgisselq
// Busses:      The ZipSystem implements a series of busses to make this take
41
//              place.  These busses are identified by their prefix:
42 2 dgisselq
//
43 209 dgisselq
//      cpu     This is the bus as the CPU sees it.  Since the CPU controls
44
//              two busses (a local and a global one), it uses _gbl_ to indicate
45
//              the external bus (going through the MMU if necessary) and
46
//              _lcl_ to indicate a peripheral bus seen here.
47
//
48
//      mmu     Sits between the CPU's wishbone interface and the external
49
//              bus.  Has no access to peripherals.
50
//
51
//      sys     A local bus implemented here within this space.  This is how the
52
//              CPU talks to the ZipSystem peripherals.  However, this bus
53
//              can also be accessed from the external debug bus.
54
//
55
//      io_dbg
56
//      io_wb
57
//
58
//      dbg     This is identical to the io_dbg bus, but separated by a clock
59
//      dc      The output of the DMA controller
60
//
61 2 dgisselq
// Creator:     Dan Gisselquist, Ph.D.
62 69 dgisselq
//              Gisselquist Technology, LLC
63 2 dgisselq
//
64 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
65 2 dgisselq
//
66 209 dgisselq
// Copyright (C) 2015-2019, Gisselquist Technology, LLC
67 2 dgisselq
//
68
// This program is free software (firmware): you can redistribute it and/or
69
// modify it under the terms of  the GNU General Public License as published
70
// by the Free Software Foundation, either version 3 of the License, or (at
71
// your option) any later version.
72
//
73
// This program is distributed in the hope that it will be useful, but WITHOUT
74
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
75
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
76
// for more details.
77
//
78 201 dgisselq
// You should have received a copy of the GNU General Public License along
79
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
80
// target there if the PDF file isn't present.)  If not, see
81
// <http://www.gnu.org/licenses/> for a copy.
82
//
83 2 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
84
//              http://www.gnu.org/licenses/gpl.html
85
//
86
//
87 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
88 2 dgisselq
//
89 201 dgisselq
//
90 209 dgisselq
`default_nettype        none
91
//
92 66 dgisselq
`include "cpudefs.v"
93
//
94 209 dgisselq
`define RESET_BIT       6
95
`define STEP_BIT        8
96
`define HALT_BIT        10
97
`define CLEAR_CACHE_BIT 11
98
//
99 36 dgisselq
// While I hate adding delays to any bus access, this next delay is required
100 3 dgisselq
// to make timing close in my Basys-3 design.
101
`define DELAY_DBG_BUS
102
//
103 209 dgisselq
// `define      DELAY_EXT_BUS
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//
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//
106
// If space is tight, you might not wish to have your performance and
107
// accounting counters, so let's make those optional here
108
//      Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU)
109
//      When including counters, 
110
//              Slice LUTs      ZipSystem       ZipCPU
111
//      With Counters           3315            2432
112
//      Without Counters        2796            2046
113
 
114
//
115 3 dgisselq
// Now, where am I placing all of my peripherals?
116 2 dgisselq
`define PERIPHBASE      32'hc0000000
117 209 dgisselq
`define INTCTRL         8'h0    // 
118
`define WATCHDOG        8'h1    // Interrupt generates reset signal
119
`define BUSWATCHDOG     8'h2    // Sets IVEC[0]
120
`define CTRINT          8'h3    // Sets IVEC[5]
121
`define TIMER_A         8'h4    // Sets IVEC[4]
122
`define TIMER_B         8'h5    // Sets IVEC[3]
123
`define TIMER_C         8'h6    // Sets IVEC[2]
124
`define JIFFIES         8'h7    // Sets IVEC[1]
125 2 dgisselq
 
126
 
127 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
128 209 dgisselq
`define MSTR_TASK_CTR   8'h08
129
`define MSTR_MSTL_CTR   8'h09
130
`define MSTR_PSTL_CTR   8'h0a
131
`define MSTR_INST_CTR   8'h0b
132
`define USER_TASK_CTR   8'h0c
133
`define USER_MSTL_CTR   8'h0d
134
`define USER_PSTL_CTR   8'h0e
135
`define USER_INST_CTR   8'h0f
136 36 dgisselq
`endif
137
 
138 209 dgisselq
`ifdef  OPT_MMU
139
`define MMU_ADDR        8'h80
140
`endif
141
 
142 36 dgisselq
// Although I have a hole at 5'h2, the DMA controller requires four wishbone
143
// addresses, therefore we place it by itself and expand our address bus
144
// width here by another bit.
145
`define DMAC            5'h10
146
 
147 2 dgisselq
// `define      RTC_CLOCK       32'hc0000008    // A global something
148
// `define      BITREV          32'hc0000003
149
//
150
//      DBGCTRL
151
//              10 HALT
152
//               9 HALT(ED)
153
//               8 STEP (W=1 steps, and returns to halted)
154
//               7 INTERRUPT-FLAG
155
//               6 RESET_FLAG
156
//              ADDRESS:
157
//               5      PERIPHERAL-BIT
158
//              [4:0]   REGISTER-ADDR
159
//      DBGDATA
160
//              read/writes internal registers
161 66 dgisselq
//
162
//
163
//
164 209 dgisselq
module  zipsystem(i_clk, i_reset,
165 2 dgisselq
                // Wishbone master interface from the CPU
166 201 dgisselq
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
167 36 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
168 2 dgisselq
                // Incoming interrupts
169
                i_ext_int,
170 18 dgisselq
                // Our one outgoing interrupt
171
                o_ext_int,
172 2 dgisselq
                // Wishbone slave interface for debugging purposes
173
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
174 66 dgisselq
                        o_dbg_ack, o_dbg_stall, o_dbg_data
175
`ifdef  DEBUG_SCOPE
176
                , o_cpu_debug
177
`endif
178
                );
179 209 dgisselq
        parameter       RESET_ADDRESS=32'h1000_0000, ADDRESS_WIDTH=30,
180
                        LGICACHE=10,
181
                        LGDCACHE=12;    // Set to zero for no data cache
182
        parameter [0:0]   START_HALTED=1;
183
        parameter       EXTERNAL_INTERRUPTS=1,
184 69 dgisselq
`ifdef  OPT_MULTIPLY
185 209 dgisselq
                        IMPLEMENT_MPY = `OPT_MULTIPLY;
186 69 dgisselq
`else
187 209 dgisselq
                        IMPLEMENT_MPY = 0;
188 69 dgisselq
`endif
189 209 dgisselq
        parameter [0:0]
190 69 dgisselq
`ifdef  OPT_DIVIDE
191
                        IMPLEMENT_DIVIDE=1,
192
`else
193
                        IMPLEMENT_DIVIDE=0,
194
`endif
195
`ifdef  OPT_IMPLEMENT_FPU
196 71 dgisselq
                        IMPLEMENT_FPU=1,
197
`else
198 69 dgisselq
                        IMPLEMENT_FPU=0,
199
`endif
200 201 dgisselq
                        IMPLEMENT_LOCK=1;
201
        localparam      // Derived parameters
202 209 dgisselq
                        PHYSICAL_ADDRESS_WIDTH=ADDRESS_WIDTH,
203
                        PAW=ADDRESS_WIDTH,
204
`ifdef  OPT_MMU
205
                        VIRTUAL_ADDRESS_WIDTH=30,
206
`else
207
                        VIRTUAL_ADDRESS_WIDTH=PAW,
208
`endif
209
                        LGTLBSZ = 6,
210
                        VAW=VIRTUAL_ADDRESS_WIDTH;
211
 
212
        localparam      AW=ADDRESS_WIDTH;
213
        input   wire    i_clk, i_reset;
214 2 dgisselq
        // Wishbone master
215
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
216 209 dgisselq
        output  wire    [(PAW-1):0]      o_wb_addr;
217 2 dgisselq
        output  wire    [31:0]   o_wb_data;
218 201 dgisselq
        output  wire    [3:0]    o_wb_sel;
219 209 dgisselq
        input   wire            i_wb_ack, i_wb_stall;
220
        input   wire    [31:0]   i_wb_data;
221
        input   wire            i_wb_err;
222 2 dgisselq
        // Incoming interrupts
223 209 dgisselq
        input   wire    [(EXTERNAL_INTERRUPTS-1):0]      i_ext_int;
224 18 dgisselq
        // Outgoing interrupt
225
        output  wire            o_ext_int;
226 2 dgisselq
        // Wishbone slave
227 209 dgisselq
        input   wire            i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
228
        input   wire    [31:0]   i_dbg_data;
229 2 dgisselq
        output  wire            o_dbg_ack;
230
        output  wire            o_dbg_stall;
231
        output  wire    [31:0]   o_dbg_data;
232 56 dgisselq
        //
233 66 dgisselq
`ifdef  DEBUG_SCOPE
234 56 dgisselq
        output  wire    [31:0]   o_cpu_debug;
235 66 dgisselq
`endif
236 2 dgisselq
 
237
        wire    [31:0]   ext_idata;
238
 
239 69 dgisselq
        // Handle our interrupt vector generation/coordination
240
        wire    [14:0]   main_int_vector, alt_int_vector;
241
        wire            ctri_int, tma_int, tmb_int, tmc_int, jif_int, dmac_int;
242
        wire            mtc_int, moc_int, mpc_int, mic_int,
243
                        utc_int, uoc_int, upc_int, uic_int;
244 201 dgisselq
 
245
        assign  main_int_vector[5:0] = { ctri_int, tma_int, tmb_int, tmc_int,
246
                                        jif_int, dmac_int };
247
 
248 69 dgisselq
        generate
249
        if (EXTERNAL_INTERRUPTS < 9)
250 201 dgisselq
                assign  main_int_vector[14:6] = { {(9-EXTERNAL_INTERRUPTS){1'b0}},
251
                                        i_ext_int };
252 69 dgisselq
        else
253 201 dgisselq
                assign  main_int_vector[14:6] = i_ext_int[8:0];
254 69 dgisselq
        endgenerate
255
        generate
256
        if (EXTERNAL_INTERRUPTS <= 9)
257
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
258
                assign  alt_int_vector = { 7'h00,
259
                                        mtc_int, moc_int, mpc_int, mic_int,
260
                                        utc_int, uoc_int, upc_int, uic_int };
261
`else
262
                assign  alt_int_vector = { 15'h00 };
263
`endif
264
        else
265
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
266 209 dgisselq
        if (EXTERNAL_INTERRUPTS >= 15)
267
                assign  alt_int_vector = { i_ext_int[14:8],
268
                                        mtc_int, moc_int, mpc_int, mic_int,
269
                                        utc_int, uoc_int, upc_int, uic_int };
270
        else
271 69 dgisselq
                assign  alt_int_vector = { {(7-(EXTERNAL_INTERRUPTS-9)){1'b0}},
272
                                        i_ext_int[(EXTERNAL_INTERRUPTS-1):9],
273
                                        mtc_int, moc_int, mpc_int, mic_int,
274
                                        utc_int, uoc_int, upc_int, uic_int };
275
`else
276 209 dgisselq
        if (EXTERNAL_INTERRUPTS >= 24)
277
                assign  alt_int_vector = { i_ext_int[(EXTERNAL_INTERRUPTS-1):9] };
278
        else
279 69 dgisselq
                assign  alt_int_vector = { {(15-(EXTERNAL_INTERRUPTS-9)){1'b0}},
280
                                        i_ext_int[(EXTERNAL_INTERRUPTS-1):9] };
281
`endif
282
        endgenerate
283
 
284 201 dgisselq
 
285 2 dgisselq
        // Delay the debug port by one clock, to meet timing requirements
286
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
287
        wire    [31:0]   dbg_idata, dbg_odata;
288
        reg             dbg_ack;
289 209 dgisselq
        wire    [3:0]    dbg_sel;
290
        wire            no_dbg_err;
291 3 dgisselq
`ifdef  DELAY_DBG_BUS
292 209 dgisselq
        // Make verilator happy
293
        // verilator lint_off UNUSED
294
        // verilator lint_on  UNUSED
295
        wire            dbg_err;
296 36 dgisselq
        assign          dbg_err = 1'b0;
297 209 dgisselq
        busdelay #(1,32) wbdelay(i_clk, i_reset,
298 201 dgisselq
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, 4'hf,
299 36 dgisselq
                        o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
300 201 dgisselq
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata, dbg_sel,
301 36 dgisselq
                        dbg_ack, dbg_stall, dbg_odata, dbg_err);
302 3 dgisselq
`else
303
        assign  dbg_cyc     = i_dbg_cyc;
304
        assign  dbg_stb     = i_dbg_stb;
305
        assign  dbg_we      = i_dbg_we;
306
        assign  dbg_addr    = i_dbg_addr;
307
        assign  dbg_idata   = i_dbg_data;
308
        assign  o_dbg_ack   = dbg_ack;
309
        assign  o_dbg_stall = dbg_stall;
310
        assign  o_dbg_data  = dbg_odata;
311 209 dgisselq
        assign  dbg_sel     = 4'b1111;
312
        assign  no_dbg_err  = 1'b0;
313 3 dgisselq
`endif
314 2 dgisselq
 
315
        // 
316
        //
317
        //
318
        wire    sys_cyc, sys_stb, sys_we;
319 209 dgisselq
        wire    [7:0]    sys_addr;
320
        wire    [(PAW-1):0]      cpu_addr;
321 2 dgisselq
        wire    [31:0]   sys_data;
322 209 dgisselq
        reg     [31:0]   sys_idata;
323
        reg             sys_ack;
324
        wire            sys_stall;
325 2 dgisselq
 
326 209 dgisselq
        wire    sel_counter, sel_timer, sel_pic, sel_apic,
327
                sel_watchdog, sel_bus_watchdog, sel_dmac, sel_mmus;
328 2 dgisselq
        //
329 209 dgisselq
        assign  sel_pic         = (sys_stb)&&(sys_addr == `INTCTRL);
330
        assign  sel_watchdog    = (sys_stb)&&(sys_addr == `WATCHDOG);
331
        assign  sel_bus_watchdog= (sys_stb)&&(sys_addr == `BUSWATCHDOG);
332
        assign  sel_apic        = (sys_stb)&&(sys_addr == `CTRINT);
333
        assign  sel_timer       = (sys_stb)&&(sys_addr[7:2] == 6'h1);
334
        assign  sel_counter     = (sys_stb)&&(sys_addr[7:3] == 5'h1);
335
        assign  sel_dmac        = (sys_stb)&&(sys_addr[7:4] == 4'h1);
336
        assign  sel_mmus        = (sys_stb)&&(sys_addr[7]);
337
 
338
        //
339 2 dgisselq
        // The external debug interface
340
        //
341
        // We offer only a limited interface here, requiring a pre-register
342
        // write to set the local address.  This interface allows access to
343
        // the Zip System on a debug basis only, and not to the rest of the
344
        // wishbone bus.  Further, to access these registers, the control
345
        // register must first be accessed to both stop the CPU and to 
346
        // set the following address in question.  Hence all accesses require
347
        // two accesses: write the address to the control register (and halt
348
        // the CPU if not halted), then read/write the data from the data
349
        // register.
350
        //
351 9 dgisselq
        wire            cpu_break, dbg_cmd_write;
352 18 dgisselq
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
353 2 dgisselq
        reg     [5:0]    cmd_addr;
354 56 dgisselq
        wire    [3:0]    cpu_dbg_cc;
355 209 dgisselq
        assign  dbg_cmd_write = (dbg_stb)&&(dbg_we)&&(!dbg_addr);
356 9 dgisselq
        //
357 209 dgisselq
        // Always start us off with an initial reset
358
        //
359 2 dgisselq
        initial cmd_reset = 1'b1;
360 9 dgisselq
        always @(posedge i_clk)
361 209 dgisselq
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[`RESET_BIT]))
362
                        ||(wdt_reset);
363 9 dgisselq
        //
364 183 dgisselq
        initial cmd_halt  = START_HALTED;
365 2 dgisselq
        always @(posedge i_clk)
366 209 dgisselq
        if (i_reset)
367
                cmd_halt <= START_HALTED;
368
        else if (cmd_reset)
369
                cmd_halt <= START_HALTED;
370
        else if (dbg_cmd_write)
371
                cmd_halt <= ((dbg_idata[`HALT_BIT])&&(!dbg_idata[`STEP_BIT]));
372
        else if ((cmd_step)||(cpu_break))
373
                cmd_halt  <= 1'b1;
374 18 dgisselq
 
375 183 dgisselq
        initial cmd_clear_pf_cache = 1'b1;
376 18 dgisselq
        always @(posedge i_clk)
377 209 dgisselq
                cmd_clear_pf_cache <= (dbg_cmd_write)&&(dbg_idata[`CLEAR_CACHE_BIT]);
378 9 dgisselq
        //
379
        initial cmd_step  = 1'b0;
380
        always @(posedge i_clk)
381 209 dgisselq
                cmd_step <= (dbg_cmd_write)&&(dbg_idata[`STEP_BIT]);
382 9 dgisselq
        //
383 209 dgisselq
        initial cmd_addr = 6'h0;
384 9 dgisselq
        always @(posedge i_clk)
385
                if (dbg_cmd_write)
386 2 dgisselq
                        cmd_addr <= dbg_idata[5:0];
387 9 dgisselq
 
388 2 dgisselq
        wire    cpu_reset;
389 209 dgisselq
        assign  cpu_reset = (cmd_reset);
390 2 dgisselq
 
391
        wire    cpu_halt, cpu_dbg_stall;
392 209 dgisselq
        assign  cpu_halt = (cmd_halt);
393 2 dgisselq
        wire    [31:0]   pic_data;
394
        wire    [31:0]   cmd_data;
395 18 dgisselq
        // Values:
396
        //      0x0003f -> cmd_addr mask
397
        //      0x00040 -> reset
398 69 dgisselq
        //      0x00080 -> PIC interrrupt pending
399 18 dgisselq
        //      0x00100 -> cmd_step
400
        //      0x00200 -> cmd_stall
401
        //      0x00400 -> cmd_halt
402
        //      0x00800 -> cmd_clear_pf_cache
403
        //      0x01000 -> cc.sleep
404
        //      0x02000 -> cc.gie
405 69 dgisselq
        //      0x04000 -> External (PIC) interrupt line is high
406
        //      Other external interrupts follow
407
        generate
408
        if (EXTERNAL_INTERRUPTS < 16)
409
                assign  cmd_data = { {(16-EXTERNAL_INTERRUPTS){1'b0}},
410
                                        i_ext_int,
411
                                cpu_dbg_cc,     // 4 bits
412 209 dgisselq
                                1'b0, cmd_halt, (!cpu_dbg_stall), 1'b0,
413 69 dgisselq
                                pic_data[15], cpu_reset, cmd_addr };
414
        else
415
                assign  cmd_data = { i_ext_int[15:0], cpu_dbg_cc,
416 209 dgisselq
                                1'b0, cmd_halt, (!cpu_dbg_stall), 1'b0,
417 69 dgisselq
                                pic_data[15], cpu_reset, cmd_addr };
418
        endgenerate
419
 
420 38 dgisselq
        wire    cpu_gie;
421
        assign  cpu_gie = cpu_dbg_cc[1];
422 2 dgisselq
 
423
        //
424
        // The WATCHDOG Timer
425
        //
426
        wire            wdt_ack, wdt_stall, wdt_reset;
427
        wire    [31:0]   wdt_data;
428 160 dgisselq
        ziptimer #(32,31,0)
429 209 dgisselq
                watchdog(i_clk, cpu_reset, !cmd_halt,
430
                        sys_cyc, (sys_stb)&&(sel_watchdog), sys_we,
431 2 dgisselq
                                sys_data,
432
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
433
 
434
        //
435 56 dgisselq
        // Position two, a second watchdog timer--this time for the wishbone
436
        // bus, in order to tell/find wishbone bus lockups.  In its current
437
        // configuration, it cannot be configured and all bus accesses must
438
        // take less than the number written to this register.
439 2 dgisselq
        //
440 56 dgisselq
        reg     wdbus_ack;
441 209 dgisselq
        reg     [(PAW-1):0]      r_wdbus_data;
442 56 dgisselq
        wire    [31:0]           wdbus_data;
443 69 dgisselq
        wire    reset_wdbus_timer, wdbus_int;
444 209 dgisselq
        assign  reset_wdbus_timer = (!o_wb_cyc)||(o_wb_stb)||(i_wb_ack);
445 69 dgisselq
        wbwatchdog #(14) watchbus(i_clk,(cpu_reset)||(reset_wdbus_timer),
446 209 dgisselq
                        14'h2000, wdbus_int);
447 56 dgisselq
        initial r_wdbus_data = 0;
448 36 dgisselq
        always @(posedge i_clk)
449 209 dgisselq
                if ((wdbus_int)||(cpu_err))
450
                        r_wdbus_data <= o_wb_addr;
451
        assign  wdbus_data = { {(32-PAW){1'b0}}, r_wdbus_data };
452 56 dgisselq
        initial wdbus_ack = 1'b0;
453
        always @(posedge i_clk)
454 209 dgisselq
                wdbus_ack <= ((sys_cyc)&&(sys_stb)&&(sel_bus_watchdog));
455 56 dgisselq
 
456 2 dgisselq
        // Counters -- for performance measurement and accounting
457
        //
458
        // Here's the stuff we'll be counting ....
459
        //
460 9 dgisselq
        wire            cpu_op_stall, cpu_pf_stall, cpu_i_count;
461 2 dgisselq
 
462 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
463 2 dgisselq
        //
464
        // The master counters will, in general, not be reset.  They'll be used
465
        // for an overall counter.
466
        //
467
        // Master task counter
468 69 dgisselq
        wire            mtc_ack, mtc_stall;
469 2 dgisselq
        wire    [31:0]   mtc_data;
470 209 dgisselq
        zipcounter      mtask_ctr(i_clk, 1'b0, (!cpu_halt), sys_cyc,
471
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b000),
472 2 dgisselq
                                        sys_we, sys_data,
473
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
474
 
475 9 dgisselq
        // Master Operand Stall counter
476 69 dgisselq
        wire            moc_ack, moc_stall;
477 9 dgisselq
        wire    [31:0]   moc_data;
478 209 dgisselq
        zipcounter      mmstall_ctr(i_clk,1'b0, (cpu_op_stall), sys_cyc,
479
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b001),
480 2 dgisselq
                                        sys_we, sys_data,
481 9 dgisselq
                                moc_ack, moc_stall, moc_data, moc_int);
482 2 dgisselq
 
483
        // Master PreFetch-Stall counter
484 69 dgisselq
        wire            mpc_ack, mpc_stall;
485 2 dgisselq
        wire    [31:0]   mpc_data;
486 209 dgisselq
        zipcounter      mpstall_ctr(i_clk,1'b0, (cpu_pf_stall), sys_cyc,
487
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b010),
488 2 dgisselq
                                        sys_we, sys_data,
489
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
490
 
491 9 dgisselq
        // Master Instruction counter
492 69 dgisselq
        wire            mic_ack, mic_stall;
493 9 dgisselq
        wire    [31:0]   mic_data;
494 209 dgisselq
        zipcounter      mins_ctr(i_clk,1'b0, (cpu_i_count), sys_cyc,
495
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b011),
496 2 dgisselq
                                        sys_we, sys_data,
497 9 dgisselq
                                mic_ack, mic_stall, mic_data, mic_int);
498 2 dgisselq
 
499
        //
500
        // The user counters are different from those of the master.  They will
501
        // be reset any time a task is given control of the CPU.
502
        //
503
        // User task counter
504 69 dgisselq
        wire            utc_ack, utc_stall;
505 2 dgisselq
        wire    [31:0]   utc_data;
506 209 dgisselq
        zipcounter      utask_ctr(i_clk,1'b0, (!cpu_halt)&&(cpu_gie), sys_cyc,
507
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b100),
508 2 dgisselq
                                        sys_we, sys_data,
509
                                utc_ack, utc_stall, utc_data, utc_int);
510
 
511 9 dgisselq
        // User Op-Stall counter
512 69 dgisselq
        wire            uoc_ack, uoc_stall;
513 9 dgisselq
        wire    [31:0]   uoc_data;
514 209 dgisselq
        zipcounter      umstall_ctr(i_clk,1'b0, (cpu_op_stall)&&(cpu_gie), sys_cyc,
515
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b101),
516 2 dgisselq
                                        sys_we, sys_data,
517 9 dgisselq
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
518 2 dgisselq
 
519
        // User PreFetch-Stall counter
520 69 dgisselq
        wire            upc_ack, upc_stall;
521 2 dgisselq
        wire    [31:0]   upc_data;
522 209 dgisselq
        zipcounter      upstall_ctr(i_clk,1'b0, (cpu_pf_stall)&&(cpu_gie), sys_cyc,
523
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b110),
524 2 dgisselq
                                        sys_we, sys_data,
525
                                upc_ack, upc_stall, upc_data, upc_int);
526
 
527 9 dgisselq
        // User instruction counter
528 69 dgisselq
        wire            uic_ack, uic_stall;
529 9 dgisselq
        wire    [31:0]   uic_data;
530 209 dgisselq
        zipcounter      uins_ctr(i_clk,1'b0, (cpu_i_count)&&(cpu_gie), sys_cyc,
531
                                (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b111),
532 2 dgisselq
                                        sys_we, sys_data,
533 9 dgisselq
                                uic_ack, uic_stall, uic_data, uic_int);
534 2 dgisselq
 
535
        // A little bit of pre-cleanup (actr = accounting counters)
536
        wire            actr_ack, actr_stall;
537
        wire    [31:0]   actr_data;
538 9 dgisselq
        assign  actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack)
539
                                |(utc_ack | uoc_ack | upc_ack | uic_ack));
540
        assign  actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall)
541
                                |(utc_stall | uoc_stall | upc_stall|uic_stall));
542 2 dgisselq
        assign  actr_data = ((mtc_ack) ? mtc_data
543 9 dgisselq
                                : ((moc_ack) ? moc_data
544 2 dgisselq
                                : ((mpc_ack) ? mpc_data
545 9 dgisselq
                                : ((mic_ack) ? mic_data
546 2 dgisselq
                                : ((utc_ack) ? utc_data
547 9 dgisselq
                                : ((uoc_ack) ? uoc_data
548 2 dgisselq
                                : ((upc_ack) ? upc_data
549 9 dgisselq
                                : uic_data)))))));
550 36 dgisselq
`else //        INCLUDE_ACCOUNTING_COUNTERS
551
        reg             actr_ack;
552
        wire            actr_stall;
553
        wire    [31:0]   actr_data;
554
        assign  actr_stall = 1'b0;
555
        assign  actr_data = 32'h0000;
556 2 dgisselq
 
557 36 dgisselq
        assign  mtc_int = 1'b0;
558
        assign  moc_int = 1'b0;
559
        assign  mpc_int = 1'b0;
560
        assign  mic_int = 1'b0;
561
        assign  utc_int = 1'b0;
562
        assign  uoc_int = 1'b0;
563
        assign  upc_int = 1'b0;
564
        assign  uic_int = 1'b0;
565
 
566
        always @(posedge i_clk)
567 209 dgisselq
                actr_ack <= sel_counter;
568 36 dgisselq
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
569
 
570
        //
571
        // The DMA Controller
572
        //
573 69 dgisselq
        wire            dmac_stb, dc_err;
574 36 dgisselq
        wire    [31:0]   dmac_data;
575
        wire            dmac_ack, dmac_stall;
576
        wire            dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
577 48 dgisselq
        wire    [31:0]   dc_data;
578 209 dgisselq
        wire    [(PAW-1):0]      dc_addr;
579 36 dgisselq
        wire            cpu_gbl_cyc;
580 194 dgisselq
        wire    [31:0]   dmac_int_vec;
581
        assign  dmac_int_vec = { 1'b0, alt_int_vector, 1'b0,
582
                                        main_int_vector[14:1], 1'b0 };
583 209 dgisselq
        assign  dmac_stb = (sys_stb)&&(sel_dmac);
584 56 dgisselq
`ifdef  INCLUDE_DMA_CONTROLLER
585 209 dgisselq
        wbdmac  #(PAW) dma_controller(i_clk, cpu_reset,
586 36 dgisselq
                                sys_cyc, dmac_stb, sys_we,
587
                                        sys_addr[1:0], sys_data,
588
                                        dmac_ack, dmac_stall, dmac_data,
589
                                // Need the outgoing DMAC wishbone bus
590
                                dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
591
                                        dc_ack, dc_stall, ext_idata, dc_err,
592
                                // External device interrupts
593 194 dgisselq
                                dmac_int_vec,
594 36 dgisselq
                                // DMAC interrupt, for upon completion
595 69 dgisselq
                                dmac_int);
596 56 dgisselq
`else
597
        reg     r_dmac_ack;
598 209 dgisselq
        initial r_dmac_ack = 1'b0;
599 56 dgisselq
        always @(posedge i_clk)
600
                r_dmac_ack <= (sys_cyc)&&(dmac_stb);
601
        assign  dmac_ack = r_dmac_ack;
602
        assign  dmac_data = 32'h000;
603
        assign  dmac_stall = 1'b0;
604 2 dgisselq
 
605 56 dgisselq
        assign  dc_cyc  = 1'b0;
606
        assign  dc_stb  = 1'b0;
607
        assign  dc_we   = 1'b0;
608 209 dgisselq
        assign  dc_addr = { (PAW) {1'b0} };
609 56 dgisselq
        assign  dc_data = 32'h00;
610
 
611
        assign  dmac_int = 1'b0;
612
`endif
613
 
614 71 dgisselq
        wire            ctri_sel, ctri_stall;
615
        reg             ctri_ack;
616
        wire    [31:0]   ctri_data;
617 209 dgisselq
        assign  ctri_sel = (sys_stb)&&(sel_apic);
618
        initial ctri_ack = 1'b0;
619 69 dgisselq
        always @(posedge i_clk)
620 209 dgisselq
                ctri_ack <= (ctri_sel)&&(!cpu_reset);
621 71 dgisselq
        assign  ctri_stall = 1'b0;
622 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
623 2 dgisselq
        //
624
        // Counter Interrupt controller
625
        //
626 209 dgisselq
        generate if (EXTERNAL_INTERRUPTS <= 9)
627
        begin : ALT_PIC
628 69 dgisselq
                icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel),
629
                                        sys_data, ctri_data, alt_int_vector[7:0],
630
                                        ctri_int);
631 209 dgisselq
        end else begin : ALT_PIC
632 69 dgisselq
                icontrol #(8+(EXTERNAL_INTERRUPTS-9))
633
                                ctri(i_clk, cpu_reset, (ctri_sel),
634
                                        sys_data, ctri_data,
635 115 dgisselq
                                        alt_int_vector[(EXTERNAL_INTERRUPTS-2):0],
636 69 dgisselq
                                        ctri_int);
637
        end endgenerate
638
 
639 36 dgisselq
`else   //      INCLUDE_ACCOUNTING_COUNTERS
640 2 dgisselq
 
641 209 dgisselq
        generate if (EXTERNAL_INTERRUPTS <= 9)
642
        begin : ALT_PIC
643 69 dgisselq
                assign  ctri_stall = 1'b0;
644
                assign  ctri_data  = 32'h0000;
645
                assign  ctri_int   = 1'b0;
646 209 dgisselq
        end else begin : ALT_PIC
647 69 dgisselq
                icontrol #(EXTERNAL_INTERRUPTS-9)
648
                                ctri(i_clk, cpu_reset, (ctri_sel),
649
                                        sys_data, ctri_data,
650
                                alt_int_vector[(EXTERNAL_INTERRUPTS-10):0],
651
                                        ctri_int);
652
        end endgenerate
653 36 dgisselq
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
654 2 dgisselq
 
655 36 dgisselq
 
656 2 dgisselq
        //
657
        // Timer A
658
        //
659 69 dgisselq
        wire            tma_ack, tma_stall;
660 2 dgisselq
        wire    [31:0]   tma_data;
661 209 dgisselq
        ziptimer timer_a(i_clk, cpu_reset, !cmd_halt,
662
                sys_cyc, (sys_stb)&&(sel_timer)&&(sys_addr[1:0] == 2'b00),
663
                        sys_we, sys_data,
664
                tma_ack, tma_stall, tma_data, tma_int);
665 2 dgisselq
 
666
        //
667
        // Timer B
668
        //
669 69 dgisselq
        wire            tmb_ack, tmb_stall;
670 2 dgisselq
        wire    [31:0]   tmb_data;
671 209 dgisselq
        ziptimer timer_b(i_clk, cpu_reset, !cmd_halt,
672
                sys_cyc, (sys_stb)&&(sel_timer)&&(sys_addr[1:0] == 2'b01),
673
                        sys_we, sys_data,
674
                tmb_ack, tmb_stall, tmb_data, tmb_int);
675 2 dgisselq
 
676
        //
677
        // Timer C
678
        //
679 69 dgisselq
        wire            tmc_ack, tmc_stall;
680 2 dgisselq
        wire    [31:0]   tmc_data;
681 209 dgisselq
        ziptimer timer_c(i_clk, cpu_reset, !cmd_halt,
682
                sys_cyc, (sys_stb)&&(sel_timer)&&(sys_addr[1:0]==2'b10),
683
                        sys_we, sys_data,
684
                tmc_ack, tmc_stall, tmc_data, tmc_int);
685 2 dgisselq
 
686
        //
687
        // JIFFIES
688
        //
689 69 dgisselq
        wire            jif_ack, jif_stall;
690 2 dgisselq
        wire    [31:0]   jif_data;
691 209 dgisselq
        zipjiffies jiffies(i_clk, cpu_reset, !cmd_halt,
692
                        sys_cyc, (sys_stb)&&(sel_timer)&&(sys_addr[1:0] == 2'b11), sys_we,
693 2 dgisselq
                                sys_data,
694
                        jif_ack, jif_stall, jif_data, jif_int);
695
 
696
        //
697
        // The programmable interrupt controller peripheral
698
        //
699
        wire            pic_interrupt;
700 209 dgisselq
        generate if (EXTERNAL_INTERRUPTS < 9)
701
        begin : MAIN_PIC
702 69 dgisselq
                icontrol #(6+EXTERNAL_INTERRUPTS)       pic(i_clk, cpu_reset,
703
                                        (sys_cyc)&&(sys_stb)&&(sys_we)
704 209 dgisselq
                                                &&(sel_pic),
705 69 dgisselq
                                        sys_data, pic_data,
706
                                        main_int_vector[(6+EXTERNAL_INTERRUPTS-1):0], pic_interrupt);
707 209 dgisselq
        end else begin : MAIN_PIC
708 69 dgisselq
                icontrol #(15)  pic(i_clk, cpu_reset,
709
                                        (sys_cyc)&&(sys_stb)&&(sys_we)
710 209 dgisselq
                                                &&(sel_pic),
711 69 dgisselq
                                        sys_data, pic_data,
712
                                        main_int_vector[14:0], pic_interrupt);
713
        end endgenerate
714
 
715 36 dgisselq
        wire    pic_stall;
716
        assign  pic_stall = 1'b0;
717 2 dgisselq
        reg     pic_ack;
718
        always @(posedge i_clk)
719 209 dgisselq
                pic_ack <= (sys_stb)&&(sel_pic);
720 2 dgisselq
 
721
        //
722
        // The CPU itself
723
        //
724 36 dgisselq
        wire            cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
725
                        cpu_we, cpu_dbg_we;
726 209 dgisselq
        wire    [31:0]   cpu_data, cpu_idata;
727
        wire    [3:0]    cpu_sel, mmu_sel;
728 36 dgisselq
        wire            cpu_ack, cpu_stall, cpu_err;
729 2 dgisselq
        wire    [31:0]   cpu_dbg_data;
730 209 dgisselq
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(!cmd_addr[5])
731 2 dgisselq
                                        &&(dbg_we)&&(dbg_addr));
732 209 dgisselq
        zipcpu  #(      .RESET_ADDRESS(RESET_ADDRESS),
733
                        .ADDRESS_WIDTH(VIRTUAL_ADDRESS_WIDTH),
734 160 dgisselq
                        .LGICACHE(LGICACHE),
735 209 dgisselq
                        .OPT_LGDCACHE(LGDCACHE),
736 160 dgisselq
                        .IMPLEMENT_MPY(IMPLEMENT_MPY),
737
                        .IMPLEMENT_DIVIDE(IMPLEMENT_DIVIDE),
738
                        .IMPLEMENT_FPU(IMPLEMENT_FPU),
739 209 dgisselq
                        .IMPLEMENT_LOCK(IMPLEMENT_LOCK),
740
                        .WITH_LOCAL_BUS(1'b1)
741 160 dgisselq
                )
742 48 dgisselq
                thecpu(i_clk, cpu_reset, pic_interrupt,
743 18 dgisselq
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
744 2 dgisselq
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
745 18 dgisselq
                                cpu_dbg_cc, cpu_break,
746 36 dgisselq
                        cpu_gbl_cyc, cpu_gbl_stb,
747
                                cpu_lcl_cyc, cpu_lcl_stb,
748 201 dgisselq
                                cpu_we, cpu_addr, cpu_data, cpu_sel,
749 209 dgisselq
                                // Return values from the Wishbone bus
750
                                cpu_ack, cpu_stall, cpu_idata, cpu_err,
751 66 dgisselq
                        cpu_op_stall, cpu_pf_stall, cpu_i_count
752
`ifdef  DEBUG_SCOPE
753
                        , o_cpu_debug
754
`endif
755
                        );
756 2 dgisselq
 
757 209 dgisselq
        wire    ext_ack, ext_stall;
758
        wire    mmu_cyc, mmu_stb, mmu_we, mmu_stall, mmu_ack, mmu_err;
759
        wire    mmus_ack, mmus_stall;
760
        wire [PAW-1:0]   mmu_addr;
761
        wire [31:0]      mmu_data, mmu_idata, mmus_data;
762
 
763
        // Specific responses from the MMU
764
        wire            cpu_miss;
765
 
766
        // The mmu_cpu_ lines are the return bus lines from the MMU.  They
767
        // are separate from the cpu_'s lines simply because either the sys_
768
        // (local) bus or the mmu_cpu_ (global) bus might return a response to
769
        // the CPU, and the responses haven't been merged back together again
770
        // yet.
771
        wire            mmu_cpu_ack, mmu_cpu_stall;
772
        wire    [31:0]   mmu_cpu_idata;
773
 
774
        // The wires associated with cache snooping
775
        wire            pf_return_stb, pf_return_we, pf_return_cachable;
776
        wire    [19:0]   pf_return_v, pf_return_p;
777
 
778
`ifdef  OPT_MMU
779
        // Ok ... here's the MMU
780
        zipmmu  #(      .LGTBL(LGTLBSZ),
781
                        .ADDRESS_WIDTH(PHYSICAL_ADDRESS_WIDTH)
782
                        )
783
                themmu(i_clk, cpu_reset,
784
                        // Slave interface
785
                        (sys_stb)&&(sel_mmus),
786
                                sys_we, sys_addr[7:0], sys_data,
787
                                mmus_ack, mmus_stall, mmus_data,
788
                        // CPU global bus master lines
789
                        cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr,
790
                                cpu_data, cpu_sel,
791
                        // MMU bus master outgoing lines
792
                        mmu_cyc, mmu_stb, mmu_we, mmu_addr, mmu_data, mmu_sel,
793
                                // .... and the return from the slave(s)
794
                                mmu_stall, mmu_ack, mmu_err, mmu_idata,
795
                        // CPU gobal bus master return lines
796
                                mmu_cpu_stall, mmu_cpu_ack, cpu_err, cpu_miss, mmu_cpu_idata,
797
                                pf_return_stb, pf_return_we, pf_return_p, pf_return_v,
798
                                        pf_return_cachable);
799
 
800
`else
801
        assign  mmu_cyc   = cpu_gbl_cyc;
802
        assign  mmu_stb   = cpu_gbl_stb;
803
        assign  mmu_we    = cpu_we;
804
        assign  mmu_addr  = cpu_addr;
805
        assign  mmu_data  = cpu_data;
806
        assign  mmu_sel   = cpu_sel;
807
        assign  cpu_miss  = 1'b0;
808
        assign  cpu_err   = (mmu_err)&&(cpu_gbl_cyc);
809
        assign  mmu_cpu_idata = mmu_idata;
810
        assign  mmu_cpu_stall = mmu_stall;
811
        assign  mmu_cpu_ack   = mmu_ack;
812
        reg     r_mmus_ack;
813
        initial r_mmus_ack = 1'b0;
814
        always @(posedge i_clk)
815
                r_mmus_ack <= (sys_stb)&&(sys_addr[7]);
816
        assign  mmus_ack   = r_mmus_ack;
817
        assign  mmus_stall = 1'b0;
818
        assign  mmus_data  = 32'h0;
819
 
820
        assign  pf_return_stb = 0;
821
        assign  pf_return_v   = 0;
822
        assign  pf_return_p   = 0;
823
        assign  pf_return_we  = 0;
824
        assign  pf_return_cachable = 0;
825
`endif
826
        // Responses from the MMU still need to be merged/muxed back together
827
        // with the responses from the local bus
828
        assign  cpu_ack   = ((cpu_lcl_cyc)&&(sys_ack))
829
                                ||((cpu_gbl_cyc)&&(mmu_cpu_ack));
830
        assign  cpu_stall = ((cpu_lcl_cyc)&&(sys_stall))
831
                                ||((cpu_gbl_cyc)&&(mmu_cpu_stall));
832
        assign  cpu_idata     = (cpu_gbl_cyc)?mmu_cpu_idata : sys_idata;
833
 
834
        // The following lines (will be/) are used to allow the prefetch to
835
        // snoop on any external interaction.  Until this capability is
836
        // integrated into the CPU, they are unused.  Here we tell Verilator
837
        // not to be surprised that these lines are unused:
838
 
839
        // verilator lint_off UNUSED
840
        wire    [(3+1+20+20-1):0]        mmu_unused;
841
        assign  mmu_unused = { pf_return_stb, pf_return_we,
842
                                pf_return_p, pf_return_v, pf_return_cachable,
843
                                cpu_miss };
844
        // verilator lint_on UNUSED
845
 
846 2 dgisselq
        // Now, arbitrate the bus ... first for the local peripherals
847 36 dgisselq
        // For the debugger to have access to the local system bus, the
848
        // following must be true:
849
        //      (dbg_cyc)       The debugger must request the bus
850 209 dgisselq
        //      (!cpu_lcl_cyc)  The CPU cannot be using it (CPU gets priority)
851 36 dgisselq
        //      (dbg_addr)      The debugger must be requesting its data
852
        //                              register, not just the control register
853
        // and one of two other things.  Either
854 209 dgisselq
        //      ((cpu_halt)&&(!cpu_dbg_stall))  the CPU is completely halted,
855 36 dgisselq
        // or
856 209 dgisselq
        //      (!cmd_addr[5])          we are trying to read a CPU register
857 36 dgisselq
        //                      while in motion.  Let the user beware that,
858
        //                      by not waiting for the CPU to fully halt,
859
        //                      his results may not be what he expects.
860
        //
861 209 dgisselq
        wire    sys_dbg_cyc = ((dbg_cyc)&&(!cpu_lcl_cyc)&&(dbg_addr))
862
                                &&(cmd_addr[5]);
863 36 dgisselq
        assign  sys_cyc = (cpu_lcl_cyc)||(sys_dbg_cyc);
864
        assign  sys_stb = (cpu_lcl_cyc)
865
                                ? (cpu_lcl_stb)
866 2 dgisselq
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
867
 
868 36 dgisselq
        assign  sys_we  = (cpu_lcl_cyc) ? cpu_we : dbg_we;
869 209 dgisselq
        assign  sys_addr= (cpu_lcl_cyc) ? cpu_addr[7:0] : { 3'h0, cmd_addr[4:0]};
870 36 dgisselq
        assign  sys_data= (cpu_lcl_cyc) ? cpu_data : dbg_idata;
871 2 dgisselq
 
872
        // Return debug response values
873 209 dgisselq
        // A return from one of three busses:
874
        //      CMD     giving command instructions to the CPU (step, halt, etc)
875
        //      CPU-DBG-DATA    internal register responses from within the CPU
876
        //      sys     Responses from the front-side bus here in the ZipSystem
877
        assign  dbg_odata = (!dbg_addr) ? cmd_data
878
                                :((!cmd_addr[5])?cpu_dbg_data : sys_idata);
879 2 dgisselq
        initial dbg_ack = 1'b0;
880
        always @(posedge i_clk)
881 209 dgisselq
                dbg_ack <= (dbg_stb)&&(!dbg_stall);
882
        assign  dbg_stall=(dbg_cyc)&&(
883
                ((!sys_dbg_cyc)&&(cpu_dbg_stall))
884
                        ||(sys_stall)
885
                )&&(dbg_addr);
886 2 dgisselq
 
887
        // Now for the external wishbone bus
888
        //      Need to arbitrate between the flash cache and the CPU
889
        // The way this works, though, the CPU will stall once the flash 
890
        // cache gets access to the bus--the CPU will be stuck until the 
891
        // flash cache is finished with the bus.
892 36 dgisselq
        wire            ext_cyc, ext_stb, ext_we, ext_err;
893 209 dgisselq
        wire    [(PAW-1):0]      ext_addr;
894 48 dgisselq
        wire    [31:0]           ext_odata;
895 201 dgisselq
        wire    [3:0]            ext_sel;
896 209 dgisselq
        wbpriarbiter #(32,PAW) dmacvcpu(i_clk,
897
                        mmu_cyc, mmu_stb, mmu_we, mmu_addr, mmu_data, mmu_sel,
898
                                mmu_ack, mmu_stall, mmu_err,
899 201 dgisselq
                        dc_cyc, dc_stb, dc_we, dc_addr, dc_data, 4'hf,
900 36 dgisselq
                                        dc_ack, dc_stall, dc_err,
901 201 dgisselq
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, ext_sel,
902 36 dgisselq
                                ext_ack, ext_stall, ext_err);
903 209 dgisselq
        assign  mmu_idata = ext_idata;
904
/*
905
        assign  ext_cyc  = mmu_cyc;
906
        assign  ext_stb  = mmu_stb;
907
        assign  ext_we   = mmu_we;
908
        assign  ext_odata= mmu_data;
909
        assign  ext_addr = mmu_addr;
910
        assign  ext_sel  = mmu_sel;
911
        assign  mmu_ack  = ext_ack;
912
        assign  mmu_stall= ext_stall;
913
        assign  mmu_err  = ext_err;
914
*/
915 2 dgisselq
 
916 3 dgisselq
`ifdef  DELAY_EXT_BUS
917 209 dgisselq
        busdelay #(.AW(PAW),.DW(32),.DELAY_STALL(0)) extbus(i_clk, i_reset,
918
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, ext_sel,
919 36 dgisselq
                                ext_ack, ext_stall, ext_idata, ext_err,
920 201 dgisselq
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
921 56 dgisselq
                                i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int));
922 3 dgisselq
`else
923 201 dgisselq
        assign  o_wb_cyc  = ext_cyc;
924
        assign  o_wb_stb  = ext_stb;
925
        assign  o_wb_we   = ext_we;
926
        assign  o_wb_addr = ext_addr;
927
        assign  o_wb_data = ext_odata;
928
        assign  o_wb_sel  = ext_sel;
929
        assign  ext_ack   = i_wb_ack;
930
        assign  ext_stall = i_wb_stall;
931
        assign  ext_idata = i_wb_data;
932
        assign  ext_err   = (i_wb_err)||(wdbus_int);
933 3 dgisselq
`endif
934 2 dgisselq
 
935
        wire            tmr_ack;
936
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
937
        wire    [31:0]   tmr_data;
938
        assign  tmr_data = (tma_ack)?tma_data
939
                                :(tmb_ack ? tmb_data
940
                                :(tmc_ack ? tmc_data
941
                                :jif_data));
942 209 dgisselq
        always @(posedge i_clk)
943
                casez({ mmus_ack,  tmr_ack, wdt_ack,  actr_ack,
944
                        dmac_ack, pic_ack, ctri_ack, wdbus_ack })
945
                8'b1???????: sys_idata <=  mmus_data;
946
                8'b01??????: sys_idata <=  tmr_data;
947
                8'b001?????: sys_idata <=  wdt_data;
948
                8'b0001????: sys_idata <=  actr_data;
949
                8'b00001???: sys_idata <=  dmac_data;
950
                8'b000001??: sys_idata <=  pic_data;
951
                8'b0000001?: sys_idata <=  ctri_data;
952
                8'b00000001: sys_idata <=  wdbus_data;
953
                default:     sys_idata <=  mmus_data;
954
                endcase
955 2 dgisselq
 
956 209 dgisselq
        always @(posedge i_clk)
957
        if ((i_reset)||(!sys_cyc))
958
                sys_ack <= 1'b0;
959
        else
960
                sys_ack <= (|{  mmu_ack, tmr_ack, wdt_ack, actr_ack,
961
                                dmac_ack, pic_ack, ctri_ack, wdbus_ack,
962
                                mmus_ack });
963
 
964 36 dgisselq
        assign  sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
965
                                | wdt_stall | ctri_stall | actr_stall
966 209 dgisselq
                                | pic_stall | dmac_stall | mmus_stall); // Always 1'b0!
967 18 dgisselq
 
968 209 dgisselq
        assign  o_ext_int = (cmd_halt) && (!cpu_stall);
969 18 dgisselq
 
970 209 dgisselq
        // Make verilator happy
971
        // verilator lint_off UNUSED
972
        wire    [5:0]    unused;
973
        assign unused = { no_dbg_err, dbg_sel, sel_mmus };
974
`ifndef INCLUDE_ACCOUNTING_COUNTERS
975
        wire    [11:0]   unused_ctrs;
976
        assign  unused_ctrs = {
977
                moc_int, mpc_int, mic_int, mtc_int,
978
                uoc_int, upc_int, uic_int, utc_int,
979
                cpu_gie, cpu_op_stall, cpu_pf_stall, cpu_i_count };
980
`endif
981
`ifndef INCLUDE_DMA_CONTROLLER
982
        wire    [34:0]   unused_dmac;
983
        assign  unused_dmac = { dc_err, dc_ack, dc_stall, dmac_int_vec };
984
`endif
985
        // verilator lint_on UNUSED
986 2 dgisselq
endmodule

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