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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Blame information for rev 2

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipsystem.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
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// Purpose:     This portion of the ZIP CPU implements a number of soft
8
//              peripherals to the CPU nearby its CORE.  The functionality
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//              sits on the data bus, and does not include any true
10
//              external hardware peripherals.  The peripherals included here
11
//              include:
12
//
13
//
14
//      Local interrupt controller--for any/all of the interrupts generated
15
//              here.  This would include a pin for interrupts generated
16
//              elsewhere, so this interrupt controller could be a master
17
//              handling all interrupts.  My interrupt controller would work
18
//              for this purpose.
19
//
20
//              The ZIP-CPU supports only one interrupt because, as I understand
21
//              modern systems (Linux), they tend to send all interrupts to the
22
//              same interrupt vector anyway.  Hence, that's what we do here.
23
//
24
//      Bus Error interrupts -- generates an interrupt any time the wishbone
25
//              bus produces an error on a given access, for whatever purpose
26
//              also records the address on the bus at the time of the error.
27
//
28
//      Trap instructions
29
//              Writing to this "register" will always create an interrupt.
30
//              After the interrupt, this register may be read to see what
31
//              value had been written to it.
32
//
33
//      Bit reverse register ... ?
34
//
35
//      (Potentially an eventual floating point co-processor ...)
36
//
37
//      Real-time clock
38
//
39
//      Interval timer(s) (Count down from fixed value, and either stop on
40
//              zero, or issue an interrupt and restart automatically on zero)
41
//              These can be implemented as watchdog timers if desired--the
42
//              only difference is that a watchdog timer's interrupt feeds the
43
//              reset line instead of the processor interrupt line.
44
//
45
//      Watch-dog timer: this is the same as an interval timer, only it's
46
//              interrupt/time-out line is wired to the reset line instead of
47
//              the interrupt line of the CPU.
48
//
49
//      ROM Memory map
50
//              Set a register to control this map, and a DMA will begin to
51
//              fill this memory from a slower FLASH.  Once filled, accesses
52
//              will be from this memory instead of 
53
//
54
//
55
//      Doing some market comparison, let's look at what peripherals a TI
56
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
57
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
58
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
59
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
60
//      watchdog-timers,
61
//
62
// Creator:     Dan Gisselquist, Ph.D.
63
//              Gisselquist Tecnology, LLC
64
//
65
///////////////////////////////////////////////////////////////////////////
66
//
67
// Copyright (C) 2015, Gisselquist Technology, LLC
68
//
69
// This program is free software (firmware): you can redistribute it and/or
70
// modify it under the terms of  the GNU General Public License as published
71
// by the Free Software Foundation, either version 3 of the License, or (at
72
// your option) any later version.
73
//
74
// This program is distributed in the hope that it will be useful, but WITHOUT
75
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
76
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
77
// for more details.
78
//
79
// License:     GPL, v3, as defined and found on www.gnu.org,
80
//              http://www.gnu.org/licenses/gpl.html
81
//
82
//
83
///////////////////////////////////////////////////////////////////////////
84
//
85
`define PERIPHBASE      32'hc0000000
86
`define INTCTRL         4'h0    // 
87
`define WATCHDOG        4'h1    // Interrupt generates reset signal
88
`define CACHECTRL       4'h2    // Sets IVEC[0]
89
`define CTRINT          4'h3    // Sets IVEC[5]
90
`define TIMER_A         4'h4    // Sets IVEC[4]
91
`define TIMER_B         4'h5    // Sets IVEC[3]
92
`define TIMER_C         4'h6    // Sets IVEC[2]
93
`define JIFFIES         4'h7    // Sets IVEC[1]
94
 
95
`define MSTR_TASK_CTR   4'h8
96
`define MSTR_MSTL_CTR   4'h9
97
`define MSTR_PSTL_CTR   4'ha
98
`define MSTR_ASTL_CTR   4'hb
99
`define USER_TASK_CTR   4'hc
100
`define USER_MSTL_CTR   4'hd
101
`define USER_PSTL_CTR   4'he
102
`define USER_ASTL_CTR   4'hf
103
 
104
`define CACHEBASE       16'hc010        //
105
// `define      RTC_CLOCK       32'hc0000008    // A global something
106
// `define      BITREV          32'hc0000003
107
//
108
//      DBGCTRL
109
//              10 HALT
110
//               9 HALT(ED)
111
//               8 STEP (W=1 steps, and returns to halted)
112
//               7 INTERRUPT-FLAG
113
//               6 RESET_FLAG
114
//              ADDRESS:
115
//               5      PERIPHERAL-BIT
116
//              [4:0]   REGISTER-ADDR
117
//      DBGDATA
118
//              read/writes internal registers
119
module  zipsystem(i_clk, i_rst,
120
                // Wishbone master interface from the CPU
121
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
122
                        i_wb_ack, i_wb_stall, i_wb_data,
123
                // Incoming interrupts
124
                i_ext_int,
125
                // Wishbone slave interface for debugging purposes
126
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
127
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
128
        parameter       RESET_ADDRESS=32'h0100000;
129
        input   i_clk, i_rst;
130
        // Wishbone master
131
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
132
        output  wire    [31:0]   o_wb_addr;
133
        output  wire    [31:0]   o_wb_data;
134
        input                   i_wb_ack, i_wb_stall;
135
        input           [31:0]   i_wb_data;
136
        // Incoming interrupts
137
        input                   i_ext_int;
138
        // Wishbone slave
139
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
140
        input           [31:0]   i_dbg_data;
141
        output  wire            o_dbg_ack;
142
        output  wire            o_dbg_stall;
143
        output  wire    [31:0]   o_dbg_data;
144
 
145
        wire    [31:0]   ext_idata;
146
 
147
        // Delay the debug port by one clock, to meet timing requirements
148
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
149
        wire    [31:0]   dbg_idata, dbg_odata;
150
        reg             dbg_ack;
151
        busdelay #(1,32) wbdelay(i_clk,
152
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
153
                        o_dbg_ack, o_dbg_stall, o_dbg_data,
154
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
155
                        dbg_ack, dbg_stall, dbg_odata);
156
 
157
        // 
158
        //
159
        //
160
        wire    sys_cyc, sys_stb, sys_we;
161
        wire    [3:0]    sys_addr;
162
        wire    [31:0]   cpu_addr;
163
        wire    [31:0]   sys_data;
164
        // wire         sys_ack, sys_stall;
165
 
166
        //
167
        // The external debug interface
168
        //
169
        // We offer only a limited interface here, requiring a pre-register
170
        // write to set the local address.  This interface allows access to
171
        // the Zip System on a debug basis only, and not to the rest of the
172
        // wishbone bus.  Further, to access these registers, the control
173
        // register must first be accessed to both stop the CPU and to 
174
        // set the following address in question.  Hence all accesses require
175
        // two accesses: write the address to the control register (and halt
176
        // the CPU if not halted), then read/write the data from the data
177
        // register.
178
        //
179
        wire            cpu_break;
180
        reg             cmd_reset, cmd_halt, cmd_step;
181
        reg     [5:0]    cmd_addr;
182
        initial cmd_reset = 1'b1;
183
        initial cmd_halt  = 1'b1;
184
        initial cmd_step  = 1'b0;
185
        always @(posedge i_clk)
186
                if (i_rst)
187
                begin
188
                        cmd_halt <= 1'b0;
189
                        cmd_step <= 1'b0;
190
                        cmd_reset<= 1'b0;
191
                        cmd_addr <= 6'h00;
192
                end else if ((dbg_cyc)&&(dbg_stb)
193
                                        &&(dbg_we)&&(~dbg_addr))
194
                begin
195
                        cmd_halt <= dbg_idata[10];
196
                        cmd_step <= dbg_idata[ 8];
197
                        cmd_reset<= dbg_idata[ 6];
198
                        cmd_addr <= dbg_idata[5:0];
199
                end else if (cmd_step)
200
                begin
201
                        cmd_halt <= 1'b1;
202
                        cmd_step <= 1'b0;
203
                end else if (cpu_break)
204
                        cmd_halt <= 1'b1;
205
        wire    cpu_reset;
206
        assign  cpu_reset = (i_rst)||(cmd_reset)||(wdt_reset);
207
 
208
        wire    cpu_halt, cpu_dbg_stall;
209
        assign  cpu_halt = (cmd_halt)&&(~cmd_step);
210
        wire    [31:0]   pic_data;
211
        wire    [31:0]   cmd_data;
212
        assign  cmd_data = { 21'h00, cmd_halt, (~cpu_dbg_stall), 1'b0, pic_data[15],
213
                        cpu_reset, cmd_addr };
214
 
215
`ifdef  USE_TRAP
216
        //
217
        // The TRAP peripheral
218
        //
219
        wire            trap_ack, trap_stall, trap_int;
220
        wire    [31:0]   trap_data;
221
        ziptrap trapp(i_clk,
222
                        sys_cyc, (sys_stb)&&(sys_addr == `TRAP_ADDR), sys_we,
223
                                sys_data,
224
                                trap_ack, trap_stall, trap_data, trap_int);
225
`endif
226
 
227
        //
228
        // The WATCHDOG Timer
229
        //
230
        wire            wdt_ack, wdt_stall, wdt_reset;
231
        wire    [31:0]   wdt_data;
232
        ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,
233
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
234
                                sys_data,
235
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
236
 
237
        //
238
        // The Flash Cache, a pre-read cache to memory that can be used to
239
        // create a fast memory access area
240
        //
241
        wire            cache_int;
242
        wire    [31:0]   cache_data;
243
        wire            cache_stb, cache_ack, cache_stall;
244
        wire            fc_cyc, fc_stb, fc_we, fc_ack, fc_stall;
245
        wire    [31:0]   fc_data, fc_addr;
246
        flashcache      #(10) manualcache(i_clk,
247
                                sys_cyc, cache_stb,
248
                                ((sys_stb)&&(sys_addr == `CACHECTRL)),
249
                                sys_we, cpu_addr[9:0], sys_data,
250
                                        cache_ack, cache_stall, cache_data,
251
                                // Need the outgoing CACHE wishbone bus
252
                                fc_cyc, fc_stb, fc_we, fc_addr, fc_data,
253
                                        fc_ack, fc_stall, ext_idata,
254
                                // Cache interrupt, for upon completion
255
                                cache_int);
256
 
257
 
258
        // Counters -- for performance measurement and accounting
259
        //
260
        // Here's the stuff we'll be counting ....
261
        //
262
        wire            cpu_mem_stall, cpu_pf_stall, cpu_alu_stall;
263
 
264
        //
265
        // The master counters will, in general, not be reset.  They'll be used
266
        // for an overall counter.
267
        //
268
        // Master task counter
269
        wire            mtc_ack, mtc_stall, mtc_int;
270
        wire    [31:0]   mtc_data;
271
        zipcounter      mtask_ctr(i_clk, (~cmd_halt), sys_cyc,
272
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
273
                                        sys_we, sys_data,
274
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
275
 
276
        // Master Memory-Stall counter
277
        wire            mmc_ack, mmc_stall, mmc_int;
278
        wire    [31:0]   mmc_data;
279
        zipcounter      mmstall_ctr(i_clk,(~cmd_halt)&&(cpu_mem_stall), sys_cyc,
280
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
281
                                        sys_we, sys_data,
282
                                mmc_ack, mmc_stall, mmc_data, mmc_int);
283
 
284
        // Master PreFetch-Stall counter
285
        wire            mpc_ack, mpc_stall, mpc_int;
286
        wire    [31:0]   mpc_data;
287
        zipcounter      mpstall_ctr(i_clk,(~cmd_halt)&&(cpu_pf_stall), sys_cyc,
288
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
289
                                        sys_we, sys_data,
290
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
291
 
292
        // Master ALU-Stall counter
293
        wire            mac_ack, mac_stall, mac_int;
294
        wire    [31:0]   mac_data;
295
        zipcounter      mastall_ctr(i_clk,(~cmd_halt)&&(cpu_alu_stall), sys_cyc,
296
                                (sys_stb)&&(sys_addr == `MSTR_ASTL_CTR),
297
                                        sys_we, sys_data,
298
                                mac_ack, mac_stall, mac_data, mac_int);
299
 
300
        //
301
        // The user counters are different from those of the master.  They will
302
        // be reset any time a task is given control of the CPU.
303
        //
304
        // User task counter
305
        wire            utc_ack, utc_stall, utc_int;
306
        wire    [31:0]   utc_data;
307
        zipcounter      utask_ctr(i_clk,(~cmd_halt), sys_cyc,
308
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
309
                                        sys_we, sys_data,
310
                                utc_ack, utc_stall, utc_data, utc_int);
311
 
312
        // User Memory-Stall counter
313
        wire            umc_ack, umc_stall, umc_int;
314
        wire    [31:0]   umc_data;
315
        zipcounter      umstall_ctr(i_clk,(~cmd_halt)&&(cpu_mem_stall), sys_cyc,
316
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
317
                                        sys_we, sys_data,
318
                                umc_ack, umc_stall, umc_data, umc_int);
319
 
320
        // User PreFetch-Stall counter
321
        wire            upc_ack, upc_stall, upc_int;
322
        wire    [31:0]   upc_data;
323
        zipcounter      upstall_ctr(i_clk,(~cmd_halt)&&(cpu_pf_stall), sys_cyc,
324
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
325
                                        sys_we, sys_data,
326
                                upc_ack, upc_stall, upc_data, upc_int);
327
 
328
        // User ALU-Stall counter
329
        wire            uac_ack, uac_stall, uac_int;
330
        wire    [31:0]   uac_data;
331
        zipcounter      uastall_ctr(i_clk,(~cmd_halt)&&(cpu_alu_stall), sys_cyc,
332
                                (sys_stb)&&(sys_addr == `USER_ASTL_CTR),
333
                                        sys_we, sys_data,
334
                                uac_ack, uac_stall, uac_data, uac_int);
335
 
336
        // A little bit of pre-cleanup (actr = accounting counters)
337
        wire            actr_ack, actr_stall;
338
        wire    [31:0]   actr_data;
339
        assign  actr_ack = ((mtc_ack | mmc_ack | mpc_ack | mac_ack)
340
                                |(utc_ack | umc_ack | upc_ack | uac_ack));
341
        assign  actr_stall = ((mtc_stall | mmc_stall | mpc_stall | mac_stall)
342
                                |(utc_stall | umc_stall | upc_stall|uac_stall));
343
        assign  actr_data = ((mtc_ack) ? mtc_data
344
                                : ((mmc_ack) ? mmc_data
345
                                : ((mpc_ack) ? mpc_data
346
                                : ((mac_ack) ? mac_data
347
                                : ((utc_ack) ? utc_data
348
                                : ((umc_ack) ? umc_data
349
                                : ((upc_ack) ? upc_data
350
                                : uac_data)))))));
351
 
352
 
353
 
354
        //
355
        // Counter Interrupt controller
356
        //
357
        reg             ctri_ack;
358
        wire            ctri_stall, ctri_int, ctri_sel;
359
        wire    [7:0]    ctri_vector;
360
        wire    [31:0]   ctri_data;
361
        assign  ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
362
        assign  ctri_vector = { mtc_int, mmc_int, mpc_int, mac_int,
363
                                        utc_int, umc_int, upc_int, uac_int };
364
        icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
365
                                sys_data, ctri_data, ctri_vector, ctri_int);
366
        always @(posedge i_clk)
367
                ctri_ack <= ctri_sel;
368
 
369
 
370
        //
371
        // Timer A
372
        //
373
        wire            tma_ack, tma_stall, tma_int;
374
        wire    [31:0]   tma_data;
375
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
376
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
377
                                sys_data,
378
                        tma_ack, tma_stall, tma_data, tma_int);
379
 
380
        //
381
        // Timer B
382
        //
383
        wire            tmb_ack, tmb_stall, tmb_int;
384
        wire    [31:0]   tmb_data;
385
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
386
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
387
                                sys_data,
388
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
389
 
390
        //
391
        // Timer C
392
        //
393
        wire            tmc_ack, tmc_stall, tmc_int;
394
        wire    [31:0]   tmc_data;
395
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
396
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
397
                                sys_data,
398
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
399
 
400
        //
401
        // JIFFIES
402
        //
403
        wire            jif_ack, jif_stall, jif_int;
404
        wire    [31:0]   jif_data;
405
        zipjiffies jiffies(i_clk, ~cmd_halt,
406
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
407
                                sys_data,
408
                        jif_ack, jif_stall, jif_data, jif_int);
409
 
410
        //
411
        // The programmable interrupt controller peripheral
412
        //
413
        wire            pic_interrupt;
414
        wire    [6:0]    int_vector;
415
        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
416
                                        jif_int, cache_int };
417
        icontrol #(7)   pic(i_clk, cpu_reset,
418
                                (sys_cyc)&&(sys_stb)&&(sys_we)
419
                                        &&(sys_addr==`INTCTRL),
420
                                sys_data, pic_data,
421
                                int_vector, pic_interrupt);
422
        reg     pic_ack;
423
        always @(posedge i_clk)
424
                pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
425
 
426
        //
427
        // The CPU itself
428
        //
429
        wire            cpu_cyc, cpu_stb, cpu_we, cpu_dbg_we;
430
        wire    [31:0]   cpu_data, wb_data;
431
        wire            cpu_ack, cpu_stall;
432
        wire    [31:0]   cpu_dbg_data;
433
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
434
                                        &&(dbg_we)&&(dbg_addr));
435
        zipcpu  #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
436
                        cpu_halt, cmd_addr[4:0], cpu_dbg_we,
437
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
438
                                cpu_break,
439
                        cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data,
440
                                cpu_ack, cpu_stall, wb_data,
441
                        cpu_mem_stall, cpu_pf_stall, cpu_alu_stall);
442
 
443
        // Now, arbitrate the bus ... first for the local peripherals
444
        assign  sys_cyc = (cpu_cyc)||((cpu_halt)&&(~cpu_dbg_stall)&&(dbg_cyc));
445
        assign  sys_stb = (cpu_cyc)
446
                                ? ((cpu_stb)&&(cpu_addr[31:4] == 28'hc000000))
447
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
448
 
449
        assign  sys_we  = (cpu_cyc) ? cpu_we : dbg_we;
450
        assign  sys_addr= (cpu_cyc) ? cpu_addr[3:0] : cmd_addr[3:0];
451
        assign  sys_data= (cpu_cyc) ? cpu_data : dbg_idata;
452
        assign  cache_stb=((cpu_cyc)&&(cpu_stb)&&(cpu_addr[31:16]==`CACHEBASE));
453
 
454
        // Return debug response values
455
        assign  dbg_odata = (~dbg_addr)?cmd_data
456
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
457
        initial dbg_ack = 1'b0;
458
        always @(posedge i_clk)
459
                dbg_ack <= (dbg_cyc)&&(dbg_stb)&&
460
                                ((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));
461
        assign  dbg_stall=(dbg_addr)&&(dbg_cyc)
462
                                &&((cpu_cyc)||(~cpu_halt)||(cpu_dbg_stall));
463
 
464
        // Now for the external wishbone bus
465
        //      Need to arbitrate between the flash cache and the CPU
466
        // The way this works, though, the CPU will stall once the flash 
467
        // cache gets access to the bus--the CPU will be stuck until the 
468
        // flash cache is finished with the bus.
469
        wire            ext_cyc, ext_stb, ext_we;
470
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall;
471
        wire    [31:0]   ext_addr, ext_odata;
472
        wbarbiter #(32,32) flashvcpu(i_clk, i_rst,
473
                        fc_addr, fc_data, fc_we, fc_stb, fc_cyc,
474
                                        fc_ack, fc_stall,
475
                        cpu_addr, cpu_data, cpu_we,
476
                                ((cpu_stb)&&(~sys_stb)&&(~cache_stb)),
477
                                cpu_cyc, cpu_ext_ack, cpu_ext_stall,
478
                        ext_addr, ext_odata, ext_we, ext_stb,
479
                                ext_cyc, ext_ack, ext_stall);
480
 
481
        busdelay #(32,32) extbus(i_clk,
482
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
483
                                ext_ack, ext_stall, ext_idata,
484
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
485
                                i_wb_ack, i_wb_stall, i_wb_data);
486
 
487
        wire            tmr_ack;
488
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
489
        wire    [31:0]   tmr_data;
490
        assign  tmr_data = (tma_ack)?tma_data
491
                                :(tmb_ack ? tmb_data
492
                                :(tmc_ack ? tmc_data
493
                                :jif_data));
494
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
495
                        :((actr_ack|cache_ack)?((actr_ack)?actr_data:cache_data)
496
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
497
                        :(ext_idata)));
498
 
499
        assign  cpu_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
500
                                | wdt_stall | cache_stall
501
                                | cpu_ext_stall);
502
        assign  cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack);
503
endmodule

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