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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Blame information for rev 201

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1 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
2 2 dgisselq
//
3
// Filename:    zipsystem.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This portion of the ZIP CPU implements a number of soft
8
//              peripherals to the CPU nearby its CORE.  The functionality
9
//              sits on the data bus, and does not include any true
10
//              external hardware peripherals.  The peripherals included here
11
//              include:
12
//
13
//
14
//      Local interrupt controller--for any/all of the interrupts generated
15
//              here.  This would include a pin for interrupts generated
16
//              elsewhere, so this interrupt controller could be a master
17
//              handling all interrupts.  My interrupt controller would work
18
//              for this purpose.
19
//
20
//              The ZIP-CPU supports only one interrupt because, as I understand
21
//              modern systems (Linux), they tend to send all interrupts to the
22
//              same interrupt vector anyway.  Hence, that's what we do here.
23
//
24
//      Bus Error interrupts -- generates an interrupt any time the wishbone
25
//              bus produces an error on a given access, for whatever purpose
26
//              also records the address on the bus at the time of the error.
27
//
28
//      Trap instructions
29
//              Writing to this "register" will always create an interrupt.
30
//              After the interrupt, this register may be read to see what
31
//              value had been written to it.
32
//
33
//      Bit reverse register ... ?
34
//
35
//      (Potentially an eventual floating point co-processor ...)
36
//
37
//      Real-time clock
38
//
39
//      Interval timer(s) (Count down from fixed value, and either stop on
40
//              zero, or issue an interrupt and restart automatically on zero)
41
//              These can be implemented as watchdog timers if desired--the
42
//              only difference is that a watchdog timer's interrupt feeds the
43
//              reset line instead of the processor interrupt line.
44
//
45
//      Watch-dog timer: this is the same as an interval timer, only it's
46
//              interrupt/time-out line is wired to the reset line instead of
47
//              the interrupt line of the CPU.
48
//
49
//      ROM Memory map
50
//              Set a register to control this map, and a DMA will begin to
51
//              fill this memory from a slower FLASH.  Once filled, accesses
52
//              will be from this memory instead of 
53
//
54
//
55
//      Doing some market comparison, let's look at what peripherals a TI
56
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
57
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
58
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
59
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
60
//      watchdog-timers,
61
//
62
// Creator:     Dan Gisselquist, Ph.D.
63 69 dgisselq
//              Gisselquist Technology, LLC
64 2 dgisselq
//
65 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
66 2 dgisselq
//
67 201 dgisselq
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
68 2 dgisselq
//
69
// This program is free software (firmware): you can redistribute it and/or
70
// modify it under the terms of  the GNU General Public License as published
71
// by the Free Software Foundation, either version 3 of the License, or (at
72
// your option) any later version.
73
//
74
// This program is distributed in the hope that it will be useful, but WITHOUT
75
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
76
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
77
// for more details.
78
//
79 201 dgisselq
// You should have received a copy of the GNU General Public License along
80
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
81
// target there if the PDF file isn't present.)  If not, see
82
// <http://www.gnu.org/licenses/> for a copy.
83
//
84 2 dgisselq
// License:     GPL, v3, as defined and found on www.gnu.org,
85
//              http://www.gnu.org/licenses/gpl.html
86
//
87
//
88 201 dgisselq
////////////////////////////////////////////////////////////////////////////////
89 2 dgisselq
//
90 201 dgisselq
//
91 66 dgisselq
`include "cpudefs.v"
92
//
93 36 dgisselq
// While I hate adding delays to any bus access, this next delay is required
94 3 dgisselq
// to make timing close in my Basys-3 design.
95
`define DELAY_DBG_BUS
96 36 dgisselq
// On my previous version, I needed to add a delay to access the external
97
// bus.  Activate the define below and that delay will be put back into place.
98
// This particular version no longer needs the delay in order to run at 
99
// 100 MHz.  Timing indicates I may even run this at 250 MHz without the
100
// delay too, so we're doing better.  To get rid of this, I placed the logic
101
// determining whether or not I was accessing the local system bus one clock
102
// earlier, or into the memops.v file.  This also required my wishbone bus
103
// arbiter to maintain the bus selection as well, so that got updated ...
104
// you get the picture.  But, the bottom line is that I no longer need this
105
// delay.
106 3 dgisselq
//
107 56 dgisselq
// `define      DELAY_EXT_BUS   // Required no longer!
108 3 dgisselq
//
109 36 dgisselq
//
110
// If space is tight, you might not wish to have your performance and
111
// accounting counters, so let's make those optional here
112
//      Without this flag, Slice LUT count is 3315 (ZipSystem),2432 (ZipCPU)
113
//      When including counters, 
114
//              Slice LUTs      ZipSystem       ZipCPU
115
//      With Counters           3315            2432
116
//      Without Counters        2796            2046
117
 
118
//
119 3 dgisselq
// Now, where am I placing all of my peripherals?
120 2 dgisselq
`define PERIPHBASE      32'hc0000000
121 36 dgisselq
`define INTCTRL         5'h0    // 
122
`define WATCHDOG        5'h1    // Interrupt generates reset signal
123 56 dgisselq
`define BUSWATCHDOG     5'h2    // Sets IVEC[0]
124 36 dgisselq
`define CTRINT          5'h3    // Sets IVEC[5]
125
`define TIMER_A         5'h4    // Sets IVEC[4]
126
`define TIMER_B         5'h5    // Sets IVEC[3]
127
`define TIMER_C         5'h6    // Sets IVEC[2]
128
`define JIFFIES         5'h7    // Sets IVEC[1]
129 2 dgisselq
 
130
 
131 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
132
`define MSTR_TASK_CTR   5'h08
133
`define MSTR_MSTL_CTR   5'h09
134
`define MSTR_PSTL_CTR   5'h0a
135
`define MSTR_INST_CTR   5'h0b
136
`define USER_TASK_CTR   5'h0c
137
`define USER_MSTL_CTR   5'h0d
138
`define USER_PSTL_CTR   5'h0e
139
`define USER_INST_CTR   5'h0f
140
`endif
141
 
142
// Although I have a hole at 5'h2, the DMA controller requires four wishbone
143
// addresses, therefore we place it by itself and expand our address bus
144
// width here by another bit.
145
`define DMAC            5'h10
146
 
147 2 dgisselq
// `define      RTC_CLOCK       32'hc0000008    // A global something
148
// `define      BITREV          32'hc0000003
149
//
150
//      DBGCTRL
151
//              10 HALT
152
//               9 HALT(ED)
153
//               8 STEP (W=1 steps, and returns to halted)
154
//               7 INTERRUPT-FLAG
155
//               6 RESET_FLAG
156
//              ADDRESS:
157
//               5      PERIPHERAL-BIT
158
//              [4:0]   REGISTER-ADDR
159
//      DBGDATA
160
//              read/writes internal registers
161 66 dgisselq
//
162
//
163
//
164 2 dgisselq
module  zipsystem(i_clk, i_rst,
165
                // Wishbone master interface from the CPU
166 201 dgisselq
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
167 36 dgisselq
                        i_wb_ack, i_wb_stall, i_wb_data, i_wb_err,
168 2 dgisselq
                // Incoming interrupts
169
                i_ext_int,
170 18 dgisselq
                // Our one outgoing interrupt
171
                o_ext_int,
172 2 dgisselq
                // Wishbone slave interface for debugging purposes
173
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
174 66 dgisselq
                        o_dbg_ack, o_dbg_stall, o_dbg_data
175
`ifdef  DEBUG_SCOPE
176
                , o_cpu_debug
177
`endif
178
                );
179 201 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, ADDRESS_WIDTH=30,
180 84 dgisselq
                        LGICACHE=10, START_HALTED=1, EXTERNAL_INTERRUPTS=1,
181 69 dgisselq
`ifdef  OPT_MULTIPLY
182 160 dgisselq
                        IMPLEMENT_MPY = `OPT_MULTIPLY,
183 69 dgisselq
`else
184
                        IMPLEMENT_MPY = 0,
185
`endif
186
`ifdef  OPT_DIVIDE
187
                        IMPLEMENT_DIVIDE=1,
188
`else
189
                        IMPLEMENT_DIVIDE=0,
190
`endif
191
`ifdef  OPT_IMPLEMENT_FPU
192 71 dgisselq
                        IMPLEMENT_FPU=1,
193
`else
194 69 dgisselq
                        IMPLEMENT_FPU=0,
195
`endif
196 201 dgisselq
                        IMPLEMENT_LOCK=1;
197
        localparam      // Derived parameters
198 48 dgisselq
                        AW=ADDRESS_WIDTH;
199 2 dgisselq
        input   i_clk, i_rst;
200
        // Wishbone master
201
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
202 48 dgisselq
        output  wire    [(AW-1):0]       o_wb_addr;
203 2 dgisselq
        output  wire    [31:0]   o_wb_data;
204 201 dgisselq
        output  wire    [3:0]    o_wb_sel;
205 2 dgisselq
        input                   i_wb_ack, i_wb_stall;
206
        input           [31:0]   i_wb_data;
207 36 dgisselq
        input                   i_wb_err;
208 2 dgisselq
        // Incoming interrupts
209 34 dgisselq
        input           [(EXTERNAL_INTERRUPTS-1):0]      i_ext_int;
210 18 dgisselq
        // Outgoing interrupt
211
        output  wire            o_ext_int;
212 2 dgisselq
        // Wishbone slave
213
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
214
        input           [31:0]   i_dbg_data;
215
        output  wire            o_dbg_ack;
216
        output  wire            o_dbg_stall;
217
        output  wire    [31:0]   o_dbg_data;
218 56 dgisselq
        //
219 66 dgisselq
`ifdef  DEBUG_SCOPE
220 56 dgisselq
        output  wire    [31:0]   o_cpu_debug;
221 66 dgisselq
`endif
222 2 dgisselq
 
223
        wire    [31:0]   ext_idata;
224
 
225 69 dgisselq
        // Handle our interrupt vector generation/coordination
226
        wire    [14:0]   main_int_vector, alt_int_vector;
227
        wire            ctri_int, tma_int, tmb_int, tmc_int, jif_int, dmac_int;
228
        wire            mtc_int, moc_int, mpc_int, mic_int,
229
                        utc_int, uoc_int, upc_int, uic_int;
230 201 dgisselq
 
231
        assign  main_int_vector[5:0] = { ctri_int, tma_int, tmb_int, tmc_int,
232
                                        jif_int, dmac_int };
233
 
234 69 dgisselq
        generate
235
        if (EXTERNAL_INTERRUPTS < 9)
236 201 dgisselq
                assign  main_int_vector[14:6] = { {(9-EXTERNAL_INTERRUPTS){1'b0}},
237
                                        i_ext_int };
238 69 dgisselq
        else
239 201 dgisselq
                assign  main_int_vector[14:6] = i_ext_int[8:0];
240 69 dgisselq
        endgenerate
241
        generate
242
        if (EXTERNAL_INTERRUPTS <= 9)
243
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
244
                assign  alt_int_vector = { 7'h00,
245
                                        mtc_int, moc_int, mpc_int, mic_int,
246
                                        utc_int, uoc_int, upc_int, uic_int };
247
`else
248
                assign  alt_int_vector = { 15'h00 };
249
`endif
250
        else
251
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
252
                assign  alt_int_vector = { {(7-(EXTERNAL_INTERRUPTS-9)){1'b0}},
253
                                        i_ext_int[(EXTERNAL_INTERRUPTS-1):9],
254
                                        mtc_int, moc_int, mpc_int, mic_int,
255
                                        utc_int, uoc_int, upc_int, uic_int };
256
`else
257
                assign  alt_int_vector = { {(15-(EXTERNAL_INTERRUPTS-9)){1'b0}},
258
                                        i_ext_int[(EXTERNAL_INTERRUPTS-1):9] };
259
`endif
260
        endgenerate
261
 
262 201 dgisselq
 
263 2 dgisselq
        // Delay the debug port by one clock, to meet timing requirements
264
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
265
        wire    [31:0]   dbg_idata, dbg_odata;
266
        reg             dbg_ack;
267 3 dgisselq
`ifdef  DELAY_DBG_BUS
268 36 dgisselq
        wire            dbg_err, no_dbg_err;
269 201 dgisselq
        wire    [3:0]    dbg_sel;
270 36 dgisselq
        assign          dbg_err = 1'b0;
271 2 dgisselq
        busdelay #(1,32) wbdelay(i_clk,
272 201 dgisselq
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, 4'hf,
273 36 dgisselq
                        o_dbg_ack, o_dbg_stall, o_dbg_data, no_dbg_err,
274 201 dgisselq
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata, dbg_sel,
275 36 dgisselq
                        dbg_ack, dbg_stall, dbg_odata, dbg_err);
276 3 dgisselq
`else
277
        assign  dbg_cyc     = i_dbg_cyc;
278
        assign  dbg_stb     = i_dbg_stb;
279
        assign  dbg_we      = i_dbg_we;
280
        assign  dbg_addr    = i_dbg_addr;
281
        assign  dbg_idata   = i_dbg_data;
282
        assign  o_dbg_ack   = dbg_ack;
283
        assign  o_dbg_stall = dbg_stall;
284
        assign  o_dbg_data  = dbg_odata;
285
`endif
286 2 dgisselq
 
287
        // 
288
        //
289
        //
290
        wire    sys_cyc, sys_stb, sys_we;
291 36 dgisselq
        wire    [4:0]    sys_addr;
292 48 dgisselq
        wire    [(AW-1):0]       cpu_addr;
293 2 dgisselq
        wire    [31:0]   sys_data;
294 36 dgisselq
        wire            sys_ack, sys_stall;
295 2 dgisselq
 
296
        //
297
        // The external debug interface
298
        //
299
        // We offer only a limited interface here, requiring a pre-register
300
        // write to set the local address.  This interface allows access to
301
        // the Zip System on a debug basis only, and not to the rest of the
302
        // wishbone bus.  Further, to access these registers, the control
303
        // register must first be accessed to both stop the CPU and to 
304
        // set the following address in question.  Hence all accesses require
305
        // two accesses: write the address to the control register (and halt
306
        // the CPU if not halted), then read/write the data from the data
307
        // register.
308
        //
309 9 dgisselq
        wire            cpu_break, dbg_cmd_write;
310 18 dgisselq
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
311 2 dgisselq
        reg     [5:0]    cmd_addr;
312 56 dgisselq
        wire    [3:0]    cpu_dbg_cc;
313 9 dgisselq
        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
314
        //
315 2 dgisselq
        initial cmd_reset = 1'b1;
316 9 dgisselq
        always @(posedge i_clk)
317
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
318
        //
319 183 dgisselq
        initial cmd_halt  = START_HALTED;
320 2 dgisselq
        always @(posedge i_clk)
321
                if (i_rst)
322 34 dgisselq
                        cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
323 9 dgisselq
                else if (dbg_cmd_write)
324 36 dgisselq
                        cmd_halt <= ((dbg_idata[10])||(dbg_idata[8]));
325 9 dgisselq
                else if ((cmd_step)||(cpu_break))
326
                        cmd_halt  <= 1'b1;
327 18 dgisselq
 
328 183 dgisselq
        initial cmd_clear_pf_cache = 1'b1;
329 18 dgisselq
        always @(posedge i_clk)
330 56 dgisselq
                cmd_clear_pf_cache = (~i_rst)&&(dbg_cmd_write)
331
                                        &&((dbg_idata[11])||(dbg_idata[6]));
332 9 dgisselq
        //
333
        initial cmd_step  = 1'b0;
334
        always @(posedge i_clk)
335
                cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
336
        //
337
        always @(posedge i_clk)
338
                if (dbg_cmd_write)
339 2 dgisselq
                        cmd_addr <= dbg_idata[5:0];
340 9 dgisselq
 
341 2 dgisselq
        wire    cpu_reset;
342 36 dgisselq
        assign  cpu_reset = (cmd_reset)||(wdt_reset)||(i_rst);
343 2 dgisselq
 
344
        wire    cpu_halt, cpu_dbg_stall;
345 34 dgisselq
        assign  cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
346 2 dgisselq
        wire    [31:0]   pic_data;
347
        wire    [31:0]   cmd_data;
348 18 dgisselq
        // Values:
349
        //      0x0003f -> cmd_addr mask
350
        //      0x00040 -> reset
351 69 dgisselq
        //      0x00080 -> PIC interrrupt pending
352 18 dgisselq
        //      0x00100 -> cmd_step
353
        //      0x00200 -> cmd_stall
354
        //      0x00400 -> cmd_halt
355
        //      0x00800 -> cmd_clear_pf_cache
356
        //      0x01000 -> cc.sleep
357
        //      0x02000 -> cc.gie
358 69 dgisselq
        //      0x04000 -> External (PIC) interrupt line is high
359
        //      Other external interrupts follow
360
        generate
361
        if (EXTERNAL_INTERRUPTS < 16)
362
                assign  cmd_data = { {(16-EXTERNAL_INTERRUPTS){1'b0}},
363
                                        i_ext_int,
364
                                cpu_dbg_cc,     // 4 bits
365
                                1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
366
                                pic_data[15], cpu_reset, cmd_addr };
367
        else
368
                assign  cmd_data = { i_ext_int[15:0], cpu_dbg_cc,
369
                                1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
370
                                pic_data[15], cpu_reset, cmd_addr };
371
        endgenerate
372
 
373 38 dgisselq
        wire    cpu_gie;
374
        assign  cpu_gie = cpu_dbg_cc[1];
375 2 dgisselq
 
376
        //
377
        // The WATCHDOG Timer
378
        //
379
        wire            wdt_ack, wdt_stall, wdt_reset;
380
        wire    [31:0]   wdt_data;
381 160 dgisselq
        ziptimer #(32,31,0)
382
                watchdog(i_clk, cpu_reset, ~cmd_halt,
383 2 dgisselq
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
384
                                sys_data,
385
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
386
 
387
        //
388 56 dgisselq
        // Position two, a second watchdog timer--this time for the wishbone
389
        // bus, in order to tell/find wishbone bus lockups.  In its current
390
        // configuration, it cannot be configured and all bus accesses must
391
        // take less than the number written to this register.
392 2 dgisselq
        //
393 56 dgisselq
        reg     wdbus_ack;
394
        reg     [(AW-1):0]       r_wdbus_data;
395
        wire    [31:0]           wdbus_data;
396
        wire    [14:0]   wdbus_ignored_data;
397 69 dgisselq
        wire    reset_wdbus_timer, wdbus_int;
398 56 dgisselq
        assign  reset_wdbus_timer = ((o_wb_cyc)&&((o_wb_stb)||(i_wb_ack)));
399 69 dgisselq
        wbwatchdog #(14) watchbus(i_clk,(cpu_reset)||(reset_wdbus_timer),
400
                        o_wb_cyc, 14'h2000, wdbus_int);
401 56 dgisselq
        initial r_wdbus_data = 0;
402 36 dgisselq
        always @(posedge i_clk)
403 69 dgisselq
                if ((wdbus_int)||(cpu_ext_err))
404 56 dgisselq
                        r_wdbus_data = o_wb_addr;
405
        assign  wdbus_data = { {(32-AW){1'b0}}, r_wdbus_data };
406
        initial wdbus_ack = 1'b0;
407
        always @(posedge i_clk)
408
                wdbus_ack <= ((sys_cyc)&&(sys_stb)&&(sys_addr == 5'h02));
409
 
410 2 dgisselq
        // Counters -- for performance measurement and accounting
411
        //
412
        // Here's the stuff we'll be counting ....
413
        //
414 9 dgisselq
        wire            cpu_op_stall, cpu_pf_stall, cpu_i_count;
415 2 dgisselq
 
416 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
417 2 dgisselq
        //
418
        // The master counters will, in general, not be reset.  They'll be used
419
        // for an overall counter.
420
        //
421
        // Master task counter
422 69 dgisselq
        wire            mtc_ack, mtc_stall;
423 2 dgisselq
        wire    [31:0]   mtc_data;
424 36 dgisselq
        zipcounter      mtask_ctr(i_clk, (~cpu_halt), sys_cyc,
425 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
426
                                        sys_we, sys_data,
427
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
428
 
429 9 dgisselq
        // Master Operand Stall counter
430 69 dgisselq
        wire            moc_ack, moc_stall;
431 9 dgisselq
        wire    [31:0]   moc_data;
432
        zipcounter      mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
433 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
434
                                        sys_we, sys_data,
435 9 dgisselq
                                moc_ack, moc_stall, moc_data, moc_int);
436 2 dgisselq
 
437
        // Master PreFetch-Stall counter
438 69 dgisselq
        wire            mpc_ack, mpc_stall;
439 2 dgisselq
        wire    [31:0]   mpc_data;
440 9 dgisselq
        zipcounter      mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
441 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
442
                                        sys_we, sys_data,
443
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
444
 
445 9 dgisselq
        // Master Instruction counter
446 69 dgisselq
        wire            mic_ack, mic_stall;
447 9 dgisselq
        wire    [31:0]   mic_data;
448
        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,
449 25 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_INST_CTR),
450 2 dgisselq
                                        sys_we, sys_data,
451 9 dgisselq
                                mic_ack, mic_stall, mic_data, mic_int);
452 2 dgisselq
 
453
        //
454
        // The user counters are different from those of the master.  They will
455
        // be reset any time a task is given control of the CPU.
456
        //
457
        // User task counter
458 69 dgisselq
        wire            utc_ack, utc_stall;
459 2 dgisselq
        wire    [31:0]   utc_data;
460 38 dgisselq
        zipcounter      utask_ctr(i_clk,(~cpu_halt)&&(cpu_gie), sys_cyc,
461 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
462
                                        sys_we, sys_data,
463
                                utc_ack, utc_stall, utc_data, utc_int);
464
 
465 9 dgisselq
        // User Op-Stall counter
466 69 dgisselq
        wire            uoc_ack, uoc_stall;
467 9 dgisselq
        wire    [31:0]   uoc_data;
468 38 dgisselq
        zipcounter      umstall_ctr(i_clk,(cpu_op_stall)&&(cpu_gie), sys_cyc,
469 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
470
                                        sys_we, sys_data,
471 9 dgisselq
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
472 2 dgisselq
 
473
        // User PreFetch-Stall counter
474 69 dgisselq
        wire            upc_ack, upc_stall;
475 2 dgisselq
        wire    [31:0]   upc_data;
476 38 dgisselq
        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall)&&(cpu_gie), sys_cyc,
477 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
478
                                        sys_we, sys_data,
479
                                upc_ack, upc_stall, upc_data, upc_int);
480
 
481 9 dgisselq
        // User instruction counter
482 69 dgisselq
        wire            uic_ack, uic_stall;
483 9 dgisselq
        wire    [31:0]   uic_data;
484 38 dgisselq
        zipcounter      uins_ctr(i_clk,(cpu_i_count)&&(cpu_gie), sys_cyc,
485 25 dgisselq
                                (sys_stb)&&(sys_addr == `USER_INST_CTR),
486 2 dgisselq
                                        sys_we, sys_data,
487 9 dgisselq
                                uic_ack, uic_stall, uic_data, uic_int);
488 2 dgisselq
 
489
        // A little bit of pre-cleanup (actr = accounting counters)
490
        wire            actr_ack, actr_stall;
491
        wire    [31:0]   actr_data;
492 9 dgisselq
        assign  actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack)
493
                                |(utc_ack | uoc_ack | upc_ack | uic_ack));
494
        assign  actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall)
495
                                |(utc_stall | uoc_stall | upc_stall|uic_stall));
496 2 dgisselq
        assign  actr_data = ((mtc_ack) ? mtc_data
497 9 dgisselq
                                : ((moc_ack) ? moc_data
498 2 dgisselq
                                : ((mpc_ack) ? mpc_data
499 9 dgisselq
                                : ((mic_ack) ? mic_data
500 2 dgisselq
                                : ((utc_ack) ? utc_data
501 9 dgisselq
                                : ((uoc_ack) ? uoc_data
502 2 dgisselq
                                : ((upc_ack) ? upc_data
503 9 dgisselq
                                : uic_data)))))));
504 36 dgisselq
`else //        INCLUDE_ACCOUNTING_COUNTERS
505
        reg             actr_ack;
506
        wire            actr_stall;
507
        wire    [31:0]   actr_data;
508
        assign  actr_stall = 1'b0;
509
        assign  actr_data = 32'h0000;
510 2 dgisselq
 
511 36 dgisselq
        assign  mtc_int = 1'b0;
512
        assign  moc_int = 1'b0;
513
        assign  mpc_int = 1'b0;
514
        assign  mic_int = 1'b0;
515
        assign  utc_int = 1'b0;
516
        assign  uoc_int = 1'b0;
517
        assign  upc_int = 1'b0;
518
        assign  uic_int = 1'b0;
519
 
520
        always @(posedge i_clk)
521
                actr_ack <= (sys_stb)&&(sys_addr[4:3] == 2'b01);
522
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
523
 
524
        //
525
        // The DMA Controller
526
        //
527 69 dgisselq
        wire            dmac_stb, dc_err;
528 36 dgisselq
        wire    [31:0]   dmac_data;
529
        wire            dmac_ack, dmac_stall;
530
        wire            dc_cyc, dc_stb, dc_we, dc_ack, dc_stall;
531 48 dgisselq
        wire    [31:0]   dc_data;
532
        wire    [(AW-1):0]       dc_addr;
533 36 dgisselq
        wire            cpu_gbl_cyc;
534 194 dgisselq
        wire    [31:0]   dmac_int_vec;
535
        assign  dmac_int_vec = { 1'b0, alt_int_vector, 1'b0,
536
                                        main_int_vector[14:1], 1'b0 };
537 36 dgisselq
        assign  dmac_stb = (sys_stb)&&(sys_addr[4]);
538 56 dgisselq
`ifdef  INCLUDE_DMA_CONTROLLER
539 160 dgisselq
        wbdmac  #(AW) dma_controller(i_clk, cpu_reset,
540 36 dgisselq
                                sys_cyc, dmac_stb, sys_we,
541
                                        sys_addr[1:0], sys_data,
542
                                        dmac_ack, dmac_stall, dmac_data,
543
                                // Need the outgoing DMAC wishbone bus
544
                                dc_cyc, dc_stb, dc_we, dc_addr, dc_data,
545
                                        dc_ack, dc_stall, ext_idata, dc_err,
546
                                // External device interrupts
547 194 dgisselq
                                dmac_int_vec,
548 36 dgisselq
                                // DMAC interrupt, for upon completion
549 69 dgisselq
                                dmac_int);
550 56 dgisselq
`else
551
        reg     r_dmac_ack;
552
        always @(posedge i_clk)
553
                r_dmac_ack <= (sys_cyc)&&(dmac_stb);
554
        assign  dmac_ack = r_dmac_ack;
555
        assign  dmac_data = 32'h000;
556
        assign  dmac_stall = 1'b0;
557 2 dgisselq
 
558 56 dgisselq
        assign  dc_cyc  = 1'b0;
559
        assign  dc_stb  = 1'b0;
560
        assign  dc_we   = 1'b0;
561
        assign  dc_addr = { (AW) {1'b0} };
562
        assign  dc_data = 32'h00;
563
 
564
        assign  dmac_int = 1'b0;
565
`endif
566
 
567 71 dgisselq
        wire            ctri_sel, ctri_stall;
568
        reg             ctri_ack;
569
        wire    [31:0]   ctri_data;
570 183 dgisselq
        assign  ctri_sel = (sys_stb)&&(sys_addr == `CTRINT);
571 69 dgisselq
        always @(posedge i_clk)
572
                ctri_ack <= ctri_sel;
573 71 dgisselq
        assign  ctri_stall = 1'b0;
574 36 dgisselq
`ifdef  INCLUDE_ACCOUNTING_COUNTERS
575 2 dgisselq
        //
576
        // Counter Interrupt controller
577
        //
578 69 dgisselq
        generate
579
        if (EXTERNAL_INTERRUPTS <= 9)
580
        begin
581
                icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel),
582
                                        sys_data, ctri_data, alt_int_vector[7:0],
583
                                        ctri_int);
584
        end else begin
585
                icontrol #(8+(EXTERNAL_INTERRUPTS-9))
586
                                ctri(i_clk, cpu_reset, (ctri_sel),
587
                                        sys_data, ctri_data,
588 115 dgisselq
                                        alt_int_vector[(EXTERNAL_INTERRUPTS-2):0],
589 69 dgisselq
                                        ctri_int);
590
        end endgenerate
591
 
592 36 dgisselq
`else   //      INCLUDE_ACCOUNTING_COUNTERS
593 2 dgisselq
 
594 69 dgisselq
        generate
595
        if (EXTERNAL_INTERRUPTS <= 9)
596
        begin
597
                assign  ctri_stall = 1'b0;
598
                assign  ctri_data  = 32'h0000;
599
                assign  ctri_int   = 1'b0;
600
        end else begin
601
                icontrol #(EXTERNAL_INTERRUPTS-9)
602
                                ctri(i_clk, cpu_reset, (ctri_sel),
603
                                        sys_data, ctri_data,
604
                                alt_int_vector[(EXTERNAL_INTERRUPTS-10):0],
605
                                        ctri_int);
606
        end endgenerate
607 36 dgisselq
`endif  //      INCLUDE_ACCOUNTING_COUNTERS
608 2 dgisselq
 
609 36 dgisselq
 
610 2 dgisselq
        //
611
        // Timer A
612
        //
613 69 dgisselq
        wire            tma_ack, tma_stall;
614 2 dgisselq
        wire    [31:0]   tma_data;
615
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
616
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
617
                                sys_data,
618
                        tma_ack, tma_stall, tma_data, tma_int);
619
 
620
        //
621
        // Timer B
622
        //
623 69 dgisselq
        wire            tmb_ack, tmb_stall;
624 2 dgisselq
        wire    [31:0]   tmb_data;
625
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
626
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
627
                                sys_data,
628
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
629
 
630
        //
631
        // Timer C
632
        //
633 69 dgisselq
        wire            tmc_ack, tmc_stall;
634 2 dgisselq
        wire    [31:0]   tmc_data;
635
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
636
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
637
                                sys_data,
638
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
639
 
640
        //
641
        // JIFFIES
642
        //
643 69 dgisselq
        wire            jif_ack, jif_stall;
644 2 dgisselq
        wire    [31:0]   jif_data;
645
        zipjiffies jiffies(i_clk, ~cmd_halt,
646
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
647
                                sys_data,
648
                        jif_ack, jif_stall, jif_data, jif_int);
649
 
650
        //
651
        // The programmable interrupt controller peripheral
652
        //
653
        wire            pic_interrupt;
654 69 dgisselq
        generate
655
        if (EXTERNAL_INTERRUPTS < 9)
656
        begin
657
                icontrol #(6+EXTERNAL_INTERRUPTS)       pic(i_clk, cpu_reset,
658
                                        (sys_cyc)&&(sys_stb)&&(sys_we)
659
                                                &&(sys_addr==`INTCTRL),
660
                                        sys_data, pic_data,
661
                                        main_int_vector[(6+EXTERNAL_INTERRUPTS-1):0], pic_interrupt);
662
        end else begin
663
                icontrol #(15)  pic(i_clk, cpu_reset,
664
                                        (sys_cyc)&&(sys_stb)&&(sys_we)
665
                                                &&(sys_addr==`INTCTRL),
666
                                        sys_data, pic_data,
667
                                        main_int_vector[14:0], pic_interrupt);
668
        end endgenerate
669
 
670 36 dgisselq
        wire    pic_stall;
671
        assign  pic_stall = 1'b0;
672 2 dgisselq
        reg     pic_ack;
673
        always @(posedge i_clk)
674 183 dgisselq
                pic_ack <= (sys_stb)&&(sys_addr == `INTCTRL);
675 2 dgisselq
 
676
        //
677
        // The CPU itself
678
        //
679 36 dgisselq
        wire            cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb,
680
                        cpu_we, cpu_dbg_we;
681 2 dgisselq
        wire    [31:0]   cpu_data, wb_data;
682 201 dgisselq
        wire    [3:0]    cpu_sel;
683 36 dgisselq
        wire            cpu_ack, cpu_stall, cpu_err;
684 2 dgisselq
        wire    [31:0]   cpu_dbg_data;
685
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
686
                                        &&(dbg_we)&&(dbg_addr));
687 160 dgisselq
        zipcpu  #(
688
                        .RESET_ADDRESS(RESET_ADDRESS),
689
                        .ADDRESS_WIDTH(ADDRESS_WIDTH),
690
                        .LGICACHE(LGICACHE),
691
                        .IMPLEMENT_MPY(IMPLEMENT_MPY),
692
                        .IMPLEMENT_DIVIDE(IMPLEMENT_DIVIDE),
693
                        .IMPLEMENT_FPU(IMPLEMENT_FPU),
694
                        .IMPLEMENT_LOCK(IMPLEMENT_LOCK)
695
                )
696 48 dgisselq
                thecpu(i_clk, cpu_reset, pic_interrupt,
697 18 dgisselq
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
698 2 dgisselq
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
699 18 dgisselq
                                cpu_dbg_cc, cpu_break,
700 36 dgisselq
                        cpu_gbl_cyc, cpu_gbl_stb,
701
                                cpu_lcl_cyc, cpu_lcl_stb,
702 201 dgisselq
                                cpu_we, cpu_addr, cpu_data, cpu_sel,
703 2 dgisselq
                                cpu_ack, cpu_stall, wb_data,
704 36 dgisselq
                                cpu_err,
705 66 dgisselq
                        cpu_op_stall, cpu_pf_stall, cpu_i_count
706
`ifdef  DEBUG_SCOPE
707
                        , o_cpu_debug
708
`endif
709
                        );
710 2 dgisselq
 
711
        // Now, arbitrate the bus ... first for the local peripherals
712 36 dgisselq
        // For the debugger to have access to the local system bus, the
713
        // following must be true:
714
        //      (dbg_cyc)       The debugger must request the bus
715
        //      (~cpu_lcl_cyc)  The CPU cannot be using it (CPU gets priority)
716
        //      (dbg_addr)      The debugger must be requesting its data
717
        //                              register, not just the control register
718
        // and one of two other things.  Either
719
        //      ((cpu_halt)&&(~cpu_dbg_stall))  the CPU is completely halted,
720
        // or
721
        //      (~cmd_addr[5])          we are trying to read a CPU register
722
        //                      while in motion.  Let the user beware that,
723
        //                      by not waiting for the CPU to fully halt,
724
        //                      his results may not be what he expects.
725
        //
726
        wire    sys_dbg_cyc = ((dbg_cyc)&&(~cpu_lcl_cyc)&&(dbg_addr))
727
                                &&(((cpu_halt)&&(~cpu_dbg_stall))
728
                                        ||(~cmd_addr[5]));
729
        assign  sys_cyc = (cpu_lcl_cyc)||(sys_dbg_cyc);
730
        assign  sys_stb = (cpu_lcl_cyc)
731
                                ? (cpu_lcl_stb)
732 2 dgisselq
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
733
 
734 36 dgisselq
        assign  sys_we  = (cpu_lcl_cyc) ? cpu_we : dbg_we;
735
        assign  sys_addr= (cpu_lcl_cyc) ? cpu_addr[4:0] : cmd_addr[4:0];
736
        assign  sys_data= (cpu_lcl_cyc) ? cpu_data : dbg_idata;
737 2 dgisselq
 
738
        // Return debug response values
739
        assign  dbg_odata = (~dbg_addr)?cmd_data
740
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
741
        initial dbg_ack = 1'b0;
742
        always @(posedge i_clk)
743 160 dgisselq
                dbg_ack <= (dbg_cyc)&&(dbg_stb)&&(~dbg_stall);
744 36 dgisselq
        assign  dbg_stall=(dbg_cyc)&&((~sys_dbg_cyc)||(sys_stall))&&(dbg_addr);
745 2 dgisselq
 
746
        // Now for the external wishbone bus
747
        //      Need to arbitrate between the flash cache and the CPU
748
        // The way this works, though, the CPU will stall once the flash 
749
        // cache gets access to the bus--the CPU will be stuck until the 
750
        // flash cache is finished with the bus.
751 36 dgisselq
        wire            ext_cyc, ext_stb, ext_we, ext_err;
752
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall,
753
                                cpu_ext_err;
754 48 dgisselq
        wire    [(AW-1):0]       ext_addr;
755
        wire    [31:0]           ext_odata;
756 201 dgisselq
        wire    [3:0]            ext_sel;
757 56 dgisselq
        wbpriarbiter #(32,AW) dmacvcpu(i_clk,
758 201 dgisselq
                        cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, cpu_data, cpu_sel,
759 36 dgisselq
                                cpu_ext_ack, cpu_ext_stall, cpu_ext_err,
760 201 dgisselq
                        dc_cyc, dc_stb, dc_we, dc_addr, dc_data, 4'hf,
761 36 dgisselq
                                        dc_ack, dc_stall, dc_err,
762 201 dgisselq
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, ext_sel,
763 36 dgisselq
                                ext_ack, ext_stall, ext_err);
764 2 dgisselq
 
765 3 dgisselq
`ifdef  DELAY_EXT_BUS
766 48 dgisselq
        busdelay #(AW,32) extbus(i_clk,
767 2 dgisselq
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
768 36 dgisselq
                                ext_ack, ext_stall, ext_idata, ext_err,
769 201 dgisselq
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
770 56 dgisselq
                                i_wb_ack, i_wb_stall, i_wb_data, (i_wb_err)||(wdbus_int));
771 3 dgisselq
`else
772 201 dgisselq
        assign  o_wb_cyc  = ext_cyc;
773
        assign  o_wb_stb  = ext_stb;
774
        assign  o_wb_we   = ext_we;
775
        assign  o_wb_addr = ext_addr;
776
        assign  o_wb_data = ext_odata;
777
        assign  o_wb_sel  = ext_sel;
778
        assign  ext_ack   = i_wb_ack;
779
        assign  ext_stall = i_wb_stall;
780
        assign  ext_idata = i_wb_data;
781
        assign  ext_err   = (i_wb_err)||(wdbus_int);
782 3 dgisselq
`endif
783 2 dgisselq
 
784
        wire            tmr_ack;
785
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
786
        wire    [31:0]   tmr_data;
787
        assign  tmr_data = (tma_ack)?tma_data
788
                                :(tmb_ack ? tmb_data
789
                                :(tmc_ack ? tmc_data
790
                                :jif_data));
791
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
792 36 dgisselq
                        :((actr_ack|dmac_ack)?((actr_ack)?actr_data:dmac_data)
793 2 dgisselq
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
794 56 dgisselq
                        :((wdbus_ack)?wdbus_data:(ext_idata))));
795 2 dgisselq
 
796 36 dgisselq
        assign  sys_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
797
                                | wdt_stall | ctri_stall | actr_stall
798 194 dgisselq
                                | pic_stall | dmac_stall); // Always 1'b0!
799 36 dgisselq
        assign  cpu_stall = (sys_stall)|(cpu_ext_stall);
800 56 dgisselq
        assign  sys_ack = (tmr_ack|wdt_ack|ctri_ack|actr_ack|pic_ack|dmac_ack|wdbus_ack);
801 36 dgisselq
        assign  cpu_ack = (sys_ack)||(cpu_ext_ack);
802
        assign  cpu_err = (cpu_ext_err)&&(cpu_gbl_cyc);
803 18 dgisselq
 
804
        assign  o_ext_int = (cmd_halt) && (~cpu_stall);
805
 
806 2 dgisselq
endmodule

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