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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Blame information for rev 25

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipsystem.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This portion of the ZIP CPU implements a number of soft
8
//              peripherals to the CPU nearby its CORE.  The functionality
9
//              sits on the data bus, and does not include any true
10
//              external hardware peripherals.  The peripherals included here
11
//              include:
12
//
13
//
14
//      Local interrupt controller--for any/all of the interrupts generated
15
//              here.  This would include a pin for interrupts generated
16
//              elsewhere, so this interrupt controller could be a master
17
//              handling all interrupts.  My interrupt controller would work
18
//              for this purpose.
19
//
20
//              The ZIP-CPU supports only one interrupt because, as I understand
21
//              modern systems (Linux), they tend to send all interrupts to the
22
//              same interrupt vector anyway.  Hence, that's what we do here.
23
//
24
//      Bus Error interrupts -- generates an interrupt any time the wishbone
25
//              bus produces an error on a given access, for whatever purpose
26
//              also records the address on the bus at the time of the error.
27
//
28
//      Trap instructions
29
//              Writing to this "register" will always create an interrupt.
30
//              After the interrupt, this register may be read to see what
31
//              value had been written to it.
32
//
33
//      Bit reverse register ... ?
34
//
35
//      (Potentially an eventual floating point co-processor ...)
36
//
37
//      Real-time clock
38
//
39
//      Interval timer(s) (Count down from fixed value, and either stop on
40
//              zero, or issue an interrupt and restart automatically on zero)
41
//              These can be implemented as watchdog timers if desired--the
42
//              only difference is that a watchdog timer's interrupt feeds the
43
//              reset line instead of the processor interrupt line.
44
//
45
//      Watch-dog timer: this is the same as an interval timer, only it's
46
//              interrupt/time-out line is wired to the reset line instead of
47
//              the interrupt line of the CPU.
48
//
49
//      ROM Memory map
50
//              Set a register to control this map, and a DMA will begin to
51
//              fill this memory from a slower FLASH.  Once filled, accesses
52
//              will be from this memory instead of 
53
//
54
//
55
//      Doing some market comparison, let's look at what peripherals a TI
56
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
57
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
58
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
59
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
60
//      watchdog-timers,
61
//
62
// Creator:     Dan Gisselquist, Ph.D.
63
//              Gisselquist Tecnology, LLC
64
//
65
///////////////////////////////////////////////////////////////////////////
66
//
67
// Copyright (C) 2015, Gisselquist Technology, LLC
68
//
69
// This program is free software (firmware): you can redistribute it and/or
70
// modify it under the terms of  the GNU General Public License as published
71
// by the Free Software Foundation, either version 3 of the License, or (at
72
// your option) any later version.
73
//
74
// This program is distributed in the hope that it will be useful, but WITHOUT
75
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
76
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
77
// for more details.
78
//
79
// License:     GPL, v3, as defined and found on www.gnu.org,
80
//              http://www.gnu.org/licenses/gpl.html
81
//
82
//
83
///////////////////////////////////////////////////////////////////////////
84
//
85 3 dgisselq
// While I hate adding delays to any bus access, these two are required
86
// to make timing close in my Basys-3 design.
87
`define DELAY_EXT_BUS
88
`define DELAY_DBG_BUS
89
//
90
//
91
// Now, where am I placing all of my peripherals?
92 2 dgisselq
`define PERIPHBASE      32'hc0000000
93
`define INTCTRL         4'h0    // 
94
`define WATCHDOG        4'h1    // Interrupt generates reset signal
95
`define CACHECTRL       4'h2    // Sets IVEC[0]
96
`define CTRINT          4'h3    // Sets IVEC[5]
97
`define TIMER_A         4'h4    // Sets IVEC[4]
98
`define TIMER_B         4'h5    // Sets IVEC[3]
99
`define TIMER_C         4'h6    // Sets IVEC[2]
100
`define JIFFIES         4'h7    // Sets IVEC[1]
101
 
102
`define MSTR_TASK_CTR   4'h8
103
`define MSTR_MSTL_CTR   4'h9
104
`define MSTR_PSTL_CTR   4'ha
105 25 dgisselq
`define MSTR_INST_CTR   4'hb
106 2 dgisselq
`define USER_TASK_CTR   4'hc
107
`define USER_MSTL_CTR   4'hd
108
`define USER_PSTL_CTR   4'he
109 25 dgisselq
`define USER_INST_CTR   4'hf
110 2 dgisselq
 
111
`define CACHEBASE       16'hc010        //
112
// `define      RTC_CLOCK       32'hc0000008    // A global something
113
// `define      BITREV          32'hc0000003
114
//
115
//      DBGCTRL
116
//              10 HALT
117
//               9 HALT(ED)
118
//               8 STEP (W=1 steps, and returns to halted)
119
//               7 INTERRUPT-FLAG
120
//               6 RESET_FLAG
121
//              ADDRESS:
122
//               5      PERIPHERAL-BIT
123
//              [4:0]   REGISTER-ADDR
124
//      DBGDATA
125
//              read/writes internal registers
126
module  zipsystem(i_clk, i_rst,
127
                // Wishbone master interface from the CPU
128
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
129
                        i_wb_ack, i_wb_stall, i_wb_data,
130
                // Incoming interrupts
131
                i_ext_int,
132 18 dgisselq
                // Our one outgoing interrupt
133
                o_ext_int,
134 2 dgisselq
                // Wishbone slave interface for debugging purposes
135
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
136
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
137
        parameter       RESET_ADDRESS=32'h0100000;
138
        input   i_clk, i_rst;
139
        // Wishbone master
140
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
141
        output  wire    [31:0]   o_wb_addr;
142
        output  wire    [31:0]   o_wb_data;
143
        input                   i_wb_ack, i_wb_stall;
144
        input           [31:0]   i_wb_data;
145
        // Incoming interrupts
146
        input                   i_ext_int;
147 18 dgisselq
        // Outgoing interrupt
148
        output  wire            o_ext_int;
149 2 dgisselq
        // Wishbone slave
150
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
151
        input           [31:0]   i_dbg_data;
152
        output  wire            o_dbg_ack;
153
        output  wire            o_dbg_stall;
154
        output  wire    [31:0]   o_dbg_data;
155
 
156
        wire    [31:0]   ext_idata;
157
 
158
        // Delay the debug port by one clock, to meet timing requirements
159
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
160
        wire    [31:0]   dbg_idata, dbg_odata;
161
        reg             dbg_ack;
162 3 dgisselq
`ifdef  DELAY_DBG_BUS
163 2 dgisselq
        busdelay #(1,32) wbdelay(i_clk,
164
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
165
                        o_dbg_ack, o_dbg_stall, o_dbg_data,
166
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
167
                        dbg_ack, dbg_stall, dbg_odata);
168 3 dgisselq
`else
169
        assign  dbg_cyc     = i_dbg_cyc;
170
        assign  dbg_stb     = i_dbg_stb;
171
        assign  dbg_we      = i_dbg_we;
172
        assign  dbg_addr    = i_dbg_addr;
173
        assign  dbg_idata   = i_dbg_data;
174
        assign  o_dbg_ack   = dbg_ack;
175
        assign  o_dbg_stall = dbg_stall;
176
        assign  o_dbg_data  = dbg_odata;
177
`endif
178 2 dgisselq
 
179
        // 
180
        //
181
        //
182
        wire    sys_cyc, sys_stb, sys_we;
183
        wire    [3:0]    sys_addr;
184
        wire    [31:0]   cpu_addr;
185
        wire    [31:0]   sys_data;
186
        // wire         sys_ack, sys_stall;
187
 
188
        //
189
        // The external debug interface
190
        //
191
        // We offer only a limited interface here, requiring a pre-register
192
        // write to set the local address.  This interface allows access to
193
        // the Zip System on a debug basis only, and not to the rest of the
194
        // wishbone bus.  Further, to access these registers, the control
195
        // register must first be accessed to both stop the CPU and to 
196
        // set the following address in question.  Hence all accesses require
197
        // two accesses: write the address to the control register (and halt
198
        // the CPU if not halted), then read/write the data from the data
199
        // register.
200
        //
201 9 dgisselq
        wire            cpu_break, dbg_cmd_write;
202 18 dgisselq
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
203 2 dgisselq
        reg     [5:0]    cmd_addr;
204 25 dgisselq
        wire    [1:0]    cpu_dbg_cc;
205 9 dgisselq
        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
206
        //
207 2 dgisselq
        initial cmd_reset = 1'b1;
208 9 dgisselq
        always @(posedge i_clk)
209
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
210
        //
211 2 dgisselq
        initial cmd_halt  = 1'b1;
212
        always @(posedge i_clk)
213
                if (i_rst)
214 11 dgisselq
                        cmd_halt <= 1'b1;
215 9 dgisselq
                else if (dbg_cmd_write)
216 2 dgisselq
                        cmd_halt <= dbg_idata[10];
217 9 dgisselq
                else if ((cmd_step)||(cpu_break))
218
                        cmd_halt  <= 1'b1;
219 18 dgisselq
 
220
        always @(posedge i_clk)
221
                if (i_rst)
222
                        cmd_clear_pf_cache <= 1'b0;
223
                else if (dbg_cmd_write)
224
                        cmd_clear_pf_cache <= dbg_idata[11];
225
                else
226
                        cmd_clear_pf_cache <= 1'b0;
227 9 dgisselq
        //
228
        initial cmd_step  = 1'b0;
229
        always @(posedge i_clk)
230
                cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
231
        //
232
        always @(posedge i_clk)
233
                if (dbg_cmd_write)
234 2 dgisselq
                        cmd_addr <= dbg_idata[5:0];
235 9 dgisselq
 
236 2 dgisselq
        wire    cpu_reset;
237
        assign  cpu_reset = (i_rst)||(cmd_reset)||(wdt_reset);
238
 
239
        wire    cpu_halt, cpu_dbg_stall;
240
        assign  cpu_halt = (cmd_halt)&&(~cmd_step);
241
        wire    [31:0]   pic_data;
242
        wire    [31:0]   cmd_data;
243 18 dgisselq
        // Values:
244
        //      0x0003f -> cmd_addr mask
245
        //      0x00040 -> reset
246
        //      0x00080 -> interrrupts enabled
247
        //      0x00100 -> cmd_step
248
        //      0x00200 -> cmd_stall
249
        //      0x00400 -> cmd_halt
250
        //      0x00800 -> cmd_clear_pf_cache
251
        //      0x01000 -> cc.sleep
252
        //      0x02000 -> cc.gie
253
        //      0x10000 -> External interrupt line is high
254 25 dgisselq
        assign  cmd_data = { 15'h00, i_ext_int, 2'b00, cpu_dbg_cc,
255 18 dgisselq
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
256
                        pic_data[15], cpu_reset, cmd_addr };
257 2 dgisselq
 
258
`ifdef  USE_TRAP
259
        //
260
        // The TRAP peripheral
261
        //
262
        wire            trap_ack, trap_stall, trap_int;
263
        wire    [31:0]   trap_data;
264
        ziptrap trapp(i_clk,
265
                        sys_cyc, (sys_stb)&&(sys_addr == `TRAP_ADDR), sys_we,
266
                                sys_data,
267
                                trap_ack, trap_stall, trap_data, trap_int);
268
`endif
269
 
270
        //
271
        // The WATCHDOG Timer
272
        //
273
        wire            wdt_ack, wdt_stall, wdt_reset;
274
        wire    [31:0]   wdt_data;
275
        ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,
276
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
277
                                sys_data,
278
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
279
 
280
        //
281
        // The Flash Cache, a pre-read cache to memory that can be used to
282
        // create a fast memory access area
283
        //
284
        wire            cache_int;
285
        wire    [31:0]   cache_data;
286
        wire            cache_stb, cache_ack, cache_stall;
287
        wire            fc_cyc, fc_stb, fc_we, fc_ack, fc_stall;
288
        wire    [31:0]   fc_data, fc_addr;
289
        flashcache      #(10) manualcache(i_clk,
290
                                sys_cyc, cache_stb,
291
                                ((sys_stb)&&(sys_addr == `CACHECTRL)),
292
                                sys_we, cpu_addr[9:0], sys_data,
293
                                        cache_ack, cache_stall, cache_data,
294
                                // Need the outgoing CACHE wishbone bus
295
                                fc_cyc, fc_stb, fc_we, fc_addr, fc_data,
296
                                        fc_ack, fc_stall, ext_idata,
297
                                // Cache interrupt, for upon completion
298
                                cache_int);
299
 
300
 
301
        // Counters -- for performance measurement and accounting
302
        //
303
        // Here's the stuff we'll be counting ....
304
        //
305 9 dgisselq
        wire            cpu_op_stall, cpu_pf_stall, cpu_i_count;
306 2 dgisselq
 
307
        //
308
        // The master counters will, in general, not be reset.  They'll be used
309
        // for an overall counter.
310
        //
311
        // Master task counter
312
        wire            mtc_ack, mtc_stall, mtc_int;
313
        wire    [31:0]   mtc_data;
314
        zipcounter      mtask_ctr(i_clk, (~cmd_halt), sys_cyc,
315
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
316
                                        sys_we, sys_data,
317
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
318
 
319 9 dgisselq
        // Master Operand Stall counter
320
        wire            moc_ack, moc_stall, moc_int;
321
        wire    [31:0]   moc_data;
322
        zipcounter      mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
323 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
324
                                        sys_we, sys_data,
325 9 dgisselq
                                moc_ack, moc_stall, moc_data, moc_int);
326 2 dgisselq
 
327
        // Master PreFetch-Stall counter
328
        wire            mpc_ack, mpc_stall, mpc_int;
329
        wire    [31:0]   mpc_data;
330 9 dgisselq
        zipcounter      mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
331 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
332
                                        sys_we, sys_data,
333
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
334
 
335 9 dgisselq
        // Master Instruction counter
336
        wire            mic_ack, mic_stall, mic_int;
337
        wire    [31:0]   mic_data;
338
        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,
339 25 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_INST_CTR),
340 2 dgisselq
                                        sys_we, sys_data,
341 9 dgisselq
                                mic_ack, mic_stall, mic_data, mic_int);
342 2 dgisselq
 
343
        //
344
        // The user counters are different from those of the master.  They will
345
        // be reset any time a task is given control of the CPU.
346
        //
347
        // User task counter
348
        wire            utc_ack, utc_stall, utc_int;
349
        wire    [31:0]   utc_data;
350
        zipcounter      utask_ctr(i_clk,(~cmd_halt), sys_cyc,
351
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
352
                                        sys_we, sys_data,
353
                                utc_ack, utc_stall, utc_data, utc_int);
354
 
355 9 dgisselq
        // User Op-Stall counter
356
        wire            uoc_ack, uoc_stall, uoc_int;
357
        wire    [31:0]   uoc_data;
358
        zipcounter      umstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
359 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
360
                                        sys_we, sys_data,
361 9 dgisselq
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
362 2 dgisselq
 
363
        // User PreFetch-Stall counter
364
        wire            upc_ack, upc_stall, upc_int;
365
        wire    [31:0]   upc_data;
366 9 dgisselq
        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
367 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
368
                                        sys_we, sys_data,
369
                                upc_ack, upc_stall, upc_data, upc_int);
370
 
371 9 dgisselq
        // User instruction counter
372
        wire            uic_ack, uic_stall, uic_int;
373
        wire    [31:0]   uic_data;
374
        zipcounter      uins_ctr(i_clk,(cpu_i_count), sys_cyc,
375 25 dgisselq
                                (sys_stb)&&(sys_addr == `USER_INST_CTR),
376 2 dgisselq
                                        sys_we, sys_data,
377 9 dgisselq
                                uic_ack, uic_stall, uic_data, uic_int);
378 2 dgisselq
 
379
        // A little bit of pre-cleanup (actr = accounting counters)
380
        wire            actr_ack, actr_stall;
381
        wire    [31:0]   actr_data;
382 9 dgisselq
        assign  actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack)
383
                                |(utc_ack | uoc_ack | upc_ack | uic_ack));
384
        assign  actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall)
385
                                |(utc_stall | uoc_stall | upc_stall|uic_stall));
386 2 dgisselq
        assign  actr_data = ((mtc_ack) ? mtc_data
387 9 dgisselq
                                : ((moc_ack) ? moc_data
388 2 dgisselq
                                : ((mpc_ack) ? mpc_data
389 9 dgisselq
                                : ((mic_ack) ? mic_data
390 2 dgisselq
                                : ((utc_ack) ? utc_data
391 9 dgisselq
                                : ((uoc_ack) ? uoc_data
392 2 dgisselq
                                : ((upc_ack) ? upc_data
393 9 dgisselq
                                : uic_data)))))));
394 2 dgisselq
 
395
 
396
 
397
        //
398
        // Counter Interrupt controller
399
        //
400
        reg             ctri_ack;
401
        wire            ctri_stall, ctri_int, ctri_sel;
402
        wire    [7:0]    ctri_vector;
403
        wire    [31:0]   ctri_data;
404
        assign  ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
405 9 dgisselq
        assign  ctri_vector = { mtc_int, moc_int, mpc_int, mic_int,
406
                                        utc_int, uoc_int, upc_int, uic_int };
407 2 dgisselq
        icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
408
                                sys_data, ctri_data, ctri_vector, ctri_int);
409
        always @(posedge i_clk)
410
                ctri_ack <= ctri_sel;
411
 
412
 
413
        //
414
        // Timer A
415
        //
416
        wire            tma_ack, tma_stall, tma_int;
417
        wire    [31:0]   tma_data;
418
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
419
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
420
                                sys_data,
421
                        tma_ack, tma_stall, tma_data, tma_int);
422
 
423
        //
424
        // Timer B
425
        //
426
        wire            tmb_ack, tmb_stall, tmb_int;
427
        wire    [31:0]   tmb_data;
428
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
429
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
430
                                sys_data,
431
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
432
 
433
        //
434
        // Timer C
435
        //
436
        wire            tmc_ack, tmc_stall, tmc_int;
437
        wire    [31:0]   tmc_data;
438
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
439
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
440
                                sys_data,
441
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
442
 
443
        //
444
        // JIFFIES
445
        //
446
        wire            jif_ack, jif_stall, jif_int;
447
        wire    [31:0]   jif_data;
448
        zipjiffies jiffies(i_clk, ~cmd_halt,
449
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
450
                                sys_data,
451
                        jif_ack, jif_stall, jif_data, jif_int);
452
 
453
        //
454
        // The programmable interrupt controller peripheral
455
        //
456
        wire            pic_interrupt;
457
        wire    [6:0]    int_vector;
458
        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
459
                                        jif_int, cache_int };
460
        icontrol #(7)   pic(i_clk, cpu_reset,
461
                                (sys_cyc)&&(sys_stb)&&(sys_we)
462
                                        &&(sys_addr==`INTCTRL),
463
                                sys_data, pic_data,
464
                                int_vector, pic_interrupt);
465
        reg     pic_ack;
466
        always @(posedge i_clk)
467
                pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
468
 
469
        //
470
        // The CPU itself
471
        //
472
        wire            cpu_cyc, cpu_stb, cpu_we, cpu_dbg_we;
473
        wire    [31:0]   cpu_data, wb_data;
474
        wire            cpu_ack, cpu_stall;
475
        wire    [31:0]   cpu_dbg_data;
476
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
477
                                        &&(dbg_we)&&(dbg_addr));
478
        zipcpu  #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
479 18 dgisselq
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
480 2 dgisselq
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
481 18 dgisselq
                                cpu_dbg_cc, cpu_break,
482 2 dgisselq
                        cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data,
483
                                cpu_ack, cpu_stall, wb_data,
484 9 dgisselq
                        cpu_op_stall, cpu_pf_stall, cpu_i_count);
485 2 dgisselq
 
486
        // Now, arbitrate the bus ... first for the local peripherals
487
        assign  sys_cyc = (cpu_cyc)||((cpu_halt)&&(~cpu_dbg_stall)&&(dbg_cyc));
488
        assign  sys_stb = (cpu_cyc)
489
                                ? ((cpu_stb)&&(cpu_addr[31:4] == 28'hc000000))
490
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
491
 
492
        assign  sys_we  = (cpu_cyc) ? cpu_we : dbg_we;
493
        assign  sys_addr= (cpu_cyc) ? cpu_addr[3:0] : cmd_addr[3:0];
494
        assign  sys_data= (cpu_cyc) ? cpu_data : dbg_idata;
495
        assign  cache_stb=((cpu_cyc)&&(cpu_stb)&&(cpu_addr[31:16]==`CACHEBASE));
496
 
497
        // Return debug response values
498
        assign  dbg_odata = (~dbg_addr)?cmd_data
499
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
500
        initial dbg_ack = 1'b0;
501
        always @(posedge i_clk)
502
                dbg_ack <= (dbg_cyc)&&(dbg_stb)&&
503
                                ((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));
504
        assign  dbg_stall=(dbg_addr)&&(dbg_cyc)
505 25 dgisselq
                                &&((cpu_cyc)||((cmd_halt)&&(~cpu_halt))
506
                                        ||(cpu_dbg_stall));
507 2 dgisselq
 
508
        // Now for the external wishbone bus
509
        //      Need to arbitrate between the flash cache and the CPU
510
        // The way this works, though, the CPU will stall once the flash 
511
        // cache gets access to the bus--the CPU will be stuck until the 
512
        // flash cache is finished with the bus.
513
        wire            ext_cyc, ext_stb, ext_we;
514
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall;
515
        wire    [31:0]   ext_addr, ext_odata;
516
        wbarbiter #(32,32) flashvcpu(i_clk, i_rst,
517
                        fc_addr, fc_data, fc_we, fc_stb, fc_cyc,
518
                                        fc_ack, fc_stall,
519
                        cpu_addr, cpu_data, cpu_we,
520
                                ((cpu_stb)&&(~sys_stb)&&(~cache_stb)),
521
                                cpu_cyc, cpu_ext_ack, cpu_ext_stall,
522
                        ext_addr, ext_odata, ext_we, ext_stb,
523
                                ext_cyc, ext_ack, ext_stall);
524
 
525 3 dgisselq
`ifdef  DELAY_EXT_BUS
526 2 dgisselq
        busdelay #(32,32) extbus(i_clk,
527
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
528
                                ext_ack, ext_stall, ext_idata,
529
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
530
                                i_wb_ack, i_wb_stall, i_wb_data);
531 3 dgisselq
`else
532
        assign  o_wb_cyc   = ext_cyc;
533
        assign  o_wb_stb   = ext_stb;
534
        assign  o_wb_we    = ext_we;
535
        assign  o_wb_addr  = ext_addr;
536
        assign  o_wb_data  = ext_odata;
537
        assign  ext_ack    = i_wb_ack;
538
        assign  ext_stall  = i_wb_stall;
539
        assign  ext_idata  = i_wb_data;
540
`endif
541 2 dgisselq
 
542
        wire            tmr_ack;
543
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
544
        wire    [31:0]   tmr_data;
545
        assign  tmr_data = (tma_ack)?tma_data
546
                                :(tmb_ack ? tmb_data
547
                                :(tmc_ack ? tmc_data
548
                                :jif_data));
549
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
550
                        :((actr_ack|cache_ack)?((actr_ack)?actr_data:cache_data)
551
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
552
                        :(ext_idata)));
553
 
554
        assign  cpu_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
555
                                | wdt_stall | cache_stall
556
                                | cpu_ext_stall);
557
        assign  cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack);
558 18 dgisselq
 
559
        assign  o_ext_int = (cmd_halt) && (~cpu_stall);
560
 
561 2 dgisselq
endmodule

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