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[/] [zipcpu/] [trunk/] [rtl/] [zipsystem.v] - Blame information for rev 34

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1 2 dgisselq
///////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zipsystem.v
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     This portion of the ZIP CPU implements a number of soft
8
//              peripherals to the CPU nearby its CORE.  The functionality
9
//              sits on the data bus, and does not include any true
10
//              external hardware peripherals.  The peripherals included here
11
//              include:
12
//
13
//
14
//      Local interrupt controller--for any/all of the interrupts generated
15
//              here.  This would include a pin for interrupts generated
16
//              elsewhere, so this interrupt controller could be a master
17
//              handling all interrupts.  My interrupt controller would work
18
//              for this purpose.
19
//
20
//              The ZIP-CPU supports only one interrupt because, as I understand
21
//              modern systems (Linux), they tend to send all interrupts to the
22
//              same interrupt vector anyway.  Hence, that's what we do here.
23
//
24
//      Bus Error interrupts -- generates an interrupt any time the wishbone
25
//              bus produces an error on a given access, for whatever purpose
26
//              also records the address on the bus at the time of the error.
27
//
28
//      Trap instructions
29
//              Writing to this "register" will always create an interrupt.
30
//              After the interrupt, this register may be read to see what
31
//              value had been written to it.
32
//
33
//      Bit reverse register ... ?
34
//
35
//      (Potentially an eventual floating point co-processor ...)
36
//
37
//      Real-time clock
38
//
39
//      Interval timer(s) (Count down from fixed value, and either stop on
40
//              zero, or issue an interrupt and restart automatically on zero)
41
//              These can be implemented as watchdog timers if desired--the
42
//              only difference is that a watchdog timer's interrupt feeds the
43
//              reset line instead of the processor interrupt line.
44
//
45
//      Watch-dog timer: this is the same as an interval timer, only it's
46
//              interrupt/time-out line is wired to the reset line instead of
47
//              the interrupt line of the CPU.
48
//
49
//      ROM Memory map
50
//              Set a register to control this map, and a DMA will begin to
51
//              fill this memory from a slower FLASH.  Once filled, accesses
52
//              will be from this memory instead of 
53
//
54
//
55
//      Doing some market comparison, let's look at what peripherals a TI
56
//      MSP430 might offer: MSP's may have I2C ports, SPI, UART, DMA, ADC,
57
//      Comparators, 16,32-bit timers, 16x16 or 32x32 timers, AES, BSL,
58
//      brown-out-reset(s), real-time-clocks, temperature sensors, USB ports,
59
//      Spi-Bi-Wire, UART Boot-strap Loader (BSL), programmable digital I/O,
60
//      watchdog-timers,
61
//
62
// Creator:     Dan Gisselquist, Ph.D.
63
//              Gisselquist Tecnology, LLC
64
//
65
///////////////////////////////////////////////////////////////////////////
66
//
67
// Copyright (C) 2015, Gisselquist Technology, LLC
68
//
69
// This program is free software (firmware): you can redistribute it and/or
70
// modify it under the terms of  the GNU General Public License as published
71
// by the Free Software Foundation, either version 3 of the License, or (at
72
// your option) any later version.
73
//
74
// This program is distributed in the hope that it will be useful, but WITHOUT
75
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
76
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
77
// for more details.
78
//
79
// License:     GPL, v3, as defined and found on www.gnu.org,
80
//              http://www.gnu.org/licenses/gpl.html
81
//
82
//
83
///////////////////////////////////////////////////////////////////////////
84
//
85 3 dgisselq
// While I hate adding delays to any bus access, these two are required
86
// to make timing close in my Basys-3 design.
87
`define DELAY_EXT_BUS
88
`define DELAY_DBG_BUS
89
//
90
//
91
// Now, where am I placing all of my peripherals?
92 2 dgisselq
`define PERIPHBASE      32'hc0000000
93
`define INTCTRL         4'h0    // 
94
`define WATCHDOG        4'h1    // Interrupt generates reset signal
95
`define CACHECTRL       4'h2    // Sets IVEC[0]
96
`define CTRINT          4'h3    // Sets IVEC[5]
97
`define TIMER_A         4'h4    // Sets IVEC[4]
98
`define TIMER_B         4'h5    // Sets IVEC[3]
99
`define TIMER_C         4'h6    // Sets IVEC[2]
100
`define JIFFIES         4'h7    // Sets IVEC[1]
101
 
102
`define MSTR_TASK_CTR   4'h8
103
`define MSTR_MSTL_CTR   4'h9
104
`define MSTR_PSTL_CTR   4'ha
105 25 dgisselq
`define MSTR_INST_CTR   4'hb
106 2 dgisselq
`define USER_TASK_CTR   4'hc
107
`define USER_MSTL_CTR   4'hd
108
`define USER_PSTL_CTR   4'he
109 25 dgisselq
`define USER_INST_CTR   4'hf
110 2 dgisselq
 
111
`define CACHEBASE       16'hc010        //
112
// `define      RTC_CLOCK       32'hc0000008    // A global something
113
// `define      BITREV          32'hc0000003
114
//
115
//      DBGCTRL
116
//              10 HALT
117
//               9 HALT(ED)
118
//               8 STEP (W=1 steps, and returns to halted)
119
//               7 INTERRUPT-FLAG
120
//               6 RESET_FLAG
121
//              ADDRESS:
122
//               5      PERIPHERAL-BIT
123
//              [4:0]   REGISTER-ADDR
124
//      DBGDATA
125
//              read/writes internal registers
126
module  zipsystem(i_clk, i_rst,
127
                // Wishbone master interface from the CPU
128
                o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
129
                        i_wb_ack, i_wb_stall, i_wb_data,
130
                // Incoming interrupts
131
                i_ext_int,
132 18 dgisselq
                // Our one outgoing interrupt
133
                o_ext_int,
134 2 dgisselq
                // Wishbone slave interface for debugging purposes
135
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
136
                        o_dbg_ack, o_dbg_stall, o_dbg_data);
137 34 dgisselq
        parameter       RESET_ADDRESS=32'h0100000, START_HALTED=1,
138
                        EXTERNAL_INTERRUPTS=1;
139 2 dgisselq
        input   i_clk, i_rst;
140
        // Wishbone master
141
        output  wire            o_wb_cyc, o_wb_stb, o_wb_we;
142
        output  wire    [31:0]   o_wb_addr;
143
        output  wire    [31:0]   o_wb_data;
144
        input                   i_wb_ack, i_wb_stall;
145
        input           [31:0]   i_wb_data;
146
        // Incoming interrupts
147 34 dgisselq
        input           [(EXTERNAL_INTERRUPTS-1):0]      i_ext_int;
148 18 dgisselq
        // Outgoing interrupt
149
        output  wire            o_ext_int;
150 2 dgisselq
        // Wishbone slave
151
        input                   i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr;
152
        input           [31:0]   i_dbg_data;
153
        output  wire            o_dbg_ack;
154
        output  wire            o_dbg_stall;
155
        output  wire    [31:0]   o_dbg_data;
156
 
157
        wire    [31:0]   ext_idata;
158
 
159
        // Delay the debug port by one clock, to meet timing requirements
160
        wire            dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_stall;
161
        wire    [31:0]   dbg_idata, dbg_odata;
162
        reg             dbg_ack;
163 3 dgisselq
`ifdef  DELAY_DBG_BUS
164 2 dgisselq
        busdelay #(1,32) wbdelay(i_clk,
165
                i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data,
166
                        o_dbg_ack, o_dbg_stall, o_dbg_data,
167
                dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata,
168
                        dbg_ack, dbg_stall, dbg_odata);
169 3 dgisselq
`else
170
        assign  dbg_cyc     = i_dbg_cyc;
171
        assign  dbg_stb     = i_dbg_stb;
172
        assign  dbg_we      = i_dbg_we;
173
        assign  dbg_addr    = i_dbg_addr;
174
        assign  dbg_idata   = i_dbg_data;
175
        assign  o_dbg_ack   = dbg_ack;
176
        assign  o_dbg_stall = dbg_stall;
177
        assign  o_dbg_data  = dbg_odata;
178
`endif
179 2 dgisselq
 
180
        // 
181
        //
182
        //
183
        wire    sys_cyc, sys_stb, sys_we;
184
        wire    [3:0]    sys_addr;
185
        wire    [31:0]   cpu_addr;
186
        wire    [31:0]   sys_data;
187
        // wire         sys_ack, sys_stall;
188
 
189
        //
190
        // The external debug interface
191
        //
192
        // We offer only a limited interface here, requiring a pre-register
193
        // write to set the local address.  This interface allows access to
194
        // the Zip System on a debug basis only, and not to the rest of the
195
        // wishbone bus.  Further, to access these registers, the control
196
        // register must first be accessed to both stop the CPU and to 
197
        // set the following address in question.  Hence all accesses require
198
        // two accesses: write the address to the control register (and halt
199
        // the CPU if not halted), then read/write the data from the data
200
        // register.
201
        //
202 9 dgisselq
        wire            cpu_break, dbg_cmd_write;
203 18 dgisselq
        reg             cmd_reset, cmd_halt, cmd_step, cmd_clear_pf_cache;
204 2 dgisselq
        reg     [5:0]    cmd_addr;
205 25 dgisselq
        wire    [1:0]    cpu_dbg_cc;
206 9 dgisselq
        assign  dbg_cmd_write = (dbg_cyc)&&(dbg_stb)&&(dbg_we)&&(~dbg_addr);
207
        //
208 2 dgisselq
        initial cmd_reset = 1'b1;
209 9 dgisselq
        always @(posedge i_clk)
210
                cmd_reset <= ((dbg_cmd_write)&&(dbg_idata[6]));
211
        //
212 2 dgisselq
        initial cmd_halt  = 1'b1;
213
        always @(posedge i_clk)
214
                if (i_rst)
215 34 dgisselq
                        cmd_halt <= (START_HALTED == 1)? 1'b1 : 1'b0;
216 9 dgisselq
                else if (dbg_cmd_write)
217 2 dgisselq
                        cmd_halt <= dbg_idata[10];
218 9 dgisselq
                else if ((cmd_step)||(cpu_break))
219
                        cmd_halt  <= 1'b1;
220 18 dgisselq
 
221
        always @(posedge i_clk)
222
                if (i_rst)
223
                        cmd_clear_pf_cache <= 1'b0;
224
                else if (dbg_cmd_write)
225
                        cmd_clear_pf_cache <= dbg_idata[11];
226
                else
227
                        cmd_clear_pf_cache <= 1'b0;
228 9 dgisselq
        //
229
        initial cmd_step  = 1'b0;
230
        always @(posedge i_clk)
231
                cmd_step <= (dbg_cmd_write)&&(dbg_idata[8]);
232
        //
233
        always @(posedge i_clk)
234
                if (dbg_cmd_write)
235 2 dgisselq
                        cmd_addr <= dbg_idata[5:0];
236 9 dgisselq
 
237 2 dgisselq
        wire    cpu_reset;
238 34 dgisselq
        assign  cpu_reset = (cmd_reset)||(wdt_reset);
239 2 dgisselq
 
240
        wire    cpu_halt, cpu_dbg_stall;
241 34 dgisselq
        assign  cpu_halt = (i_rst)||((cmd_halt)&&(~cmd_step));
242 2 dgisselq
        wire    [31:0]   pic_data;
243
        wire    [31:0]   cmd_data;
244 18 dgisselq
        // Values:
245
        //      0x0003f -> cmd_addr mask
246
        //      0x00040 -> reset
247 34 dgisselq
        //      0x00080 -> PIC interrrupts enabled
248 18 dgisselq
        //      0x00100 -> cmd_step
249
        //      0x00200 -> cmd_stall
250
        //      0x00400 -> cmd_halt
251
        //      0x00800 -> cmd_clear_pf_cache
252
        //      0x01000 -> cc.sleep
253
        //      0x02000 -> cc.gie
254
        //      0x10000 -> External interrupt line is high
255 34 dgisselq
        assign  cmd_data = { 7'h00, {(9-EXTERNAL_INTERRUPTS){1'b0}}, i_ext_int,
256
                        2'b00, cpu_dbg_cc,
257 18 dgisselq
                        1'b0, cmd_halt, (~cpu_dbg_stall), 1'b0,
258
                        pic_data[15], cpu_reset, cmd_addr };
259 2 dgisselq
 
260
`ifdef  USE_TRAP
261
        //
262
        // The TRAP peripheral
263
        //
264
        wire            trap_ack, trap_stall, trap_int;
265
        wire    [31:0]   trap_data;
266
        ziptrap trapp(i_clk,
267
                        sys_cyc, (sys_stb)&&(sys_addr == `TRAP_ADDR), sys_we,
268
                                sys_data,
269
                                trap_ack, trap_stall, trap_data, trap_int);
270
`endif
271
 
272
        //
273
        // The WATCHDOG Timer
274
        //
275
        wire            wdt_ack, wdt_stall, wdt_reset;
276
        wire    [31:0]   wdt_data;
277
        ziptimer watchdog(i_clk, cpu_reset, ~cmd_halt,
278
                        sys_cyc, ((sys_stb)&&(sys_addr == `WATCHDOG)), sys_we,
279
                                sys_data,
280
                        wdt_ack, wdt_stall, wdt_data, wdt_reset);
281
 
282
        //
283
        // The Flash Cache, a pre-read cache to memory that can be used to
284
        // create a fast memory access area
285
        //
286
        wire            cache_int;
287
        wire    [31:0]   cache_data;
288
        wire            cache_stb, cache_ack, cache_stall;
289
        wire            fc_cyc, fc_stb, fc_we, fc_ack, fc_stall;
290
        wire    [31:0]   fc_data, fc_addr;
291
        flashcache      #(10) manualcache(i_clk,
292
                                sys_cyc, cache_stb,
293
                                ((sys_stb)&&(sys_addr == `CACHECTRL)),
294
                                sys_we, cpu_addr[9:0], sys_data,
295
                                        cache_ack, cache_stall, cache_data,
296
                                // Need the outgoing CACHE wishbone bus
297
                                fc_cyc, fc_stb, fc_we, fc_addr, fc_data,
298
                                        fc_ack, fc_stall, ext_idata,
299
                                // Cache interrupt, for upon completion
300
                                cache_int);
301
 
302
 
303
        // Counters -- for performance measurement and accounting
304
        //
305
        // Here's the stuff we'll be counting ....
306
        //
307 9 dgisselq
        wire            cpu_op_stall, cpu_pf_stall, cpu_i_count;
308 2 dgisselq
 
309
        //
310
        // The master counters will, in general, not be reset.  They'll be used
311
        // for an overall counter.
312
        //
313
        // Master task counter
314
        wire            mtc_ack, mtc_stall, mtc_int;
315
        wire    [31:0]   mtc_data;
316
        zipcounter      mtask_ctr(i_clk, (~cmd_halt), sys_cyc,
317
                                (sys_stb)&&(sys_addr == `MSTR_TASK_CTR),
318
                                        sys_we, sys_data,
319
                                mtc_ack, mtc_stall, mtc_data, mtc_int);
320
 
321 9 dgisselq
        // Master Operand Stall counter
322
        wire            moc_ack, moc_stall, moc_int;
323
        wire    [31:0]   moc_data;
324
        zipcounter      mmstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
325 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_MSTL_CTR),
326
                                        sys_we, sys_data,
327 9 dgisselq
                                moc_ack, moc_stall, moc_data, moc_int);
328 2 dgisselq
 
329
        // Master PreFetch-Stall counter
330
        wire            mpc_ack, mpc_stall, mpc_int;
331
        wire    [31:0]   mpc_data;
332 9 dgisselq
        zipcounter      mpstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
333 2 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_PSTL_CTR),
334
                                        sys_we, sys_data,
335
                                mpc_ack, mpc_stall, mpc_data, mpc_int);
336
 
337 9 dgisselq
        // Master Instruction counter
338
        wire            mic_ack, mic_stall, mic_int;
339
        wire    [31:0]   mic_data;
340
        zipcounter      mins_ctr(i_clk,(cpu_i_count), sys_cyc,
341 25 dgisselq
                                (sys_stb)&&(sys_addr == `MSTR_INST_CTR),
342 2 dgisselq
                                        sys_we, sys_data,
343 9 dgisselq
                                mic_ack, mic_stall, mic_data, mic_int);
344 2 dgisselq
 
345
        //
346
        // The user counters are different from those of the master.  They will
347
        // be reset any time a task is given control of the CPU.
348
        //
349
        // User task counter
350
        wire            utc_ack, utc_stall, utc_int;
351
        wire    [31:0]   utc_data;
352
        zipcounter      utask_ctr(i_clk,(~cmd_halt), sys_cyc,
353
                                (sys_stb)&&(sys_addr == `USER_TASK_CTR),
354
                                        sys_we, sys_data,
355
                                utc_ack, utc_stall, utc_data, utc_int);
356
 
357 9 dgisselq
        // User Op-Stall counter
358
        wire            uoc_ack, uoc_stall, uoc_int;
359
        wire    [31:0]   uoc_data;
360
        zipcounter      umstall_ctr(i_clk,(cpu_op_stall), sys_cyc,
361 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_MSTL_CTR),
362
                                        sys_we, sys_data,
363 9 dgisselq
                                uoc_ack, uoc_stall, uoc_data, uoc_int);
364 2 dgisselq
 
365
        // User PreFetch-Stall counter
366
        wire            upc_ack, upc_stall, upc_int;
367
        wire    [31:0]   upc_data;
368 9 dgisselq
        zipcounter      upstall_ctr(i_clk,(cpu_pf_stall), sys_cyc,
369 2 dgisselq
                                (sys_stb)&&(sys_addr == `USER_PSTL_CTR),
370
                                        sys_we, sys_data,
371
                                upc_ack, upc_stall, upc_data, upc_int);
372
 
373 9 dgisselq
        // User instruction counter
374
        wire            uic_ack, uic_stall, uic_int;
375
        wire    [31:0]   uic_data;
376
        zipcounter      uins_ctr(i_clk,(cpu_i_count), sys_cyc,
377 25 dgisselq
                                (sys_stb)&&(sys_addr == `USER_INST_CTR),
378 2 dgisselq
                                        sys_we, sys_data,
379 9 dgisselq
                                uic_ack, uic_stall, uic_data, uic_int);
380 2 dgisselq
 
381
        // A little bit of pre-cleanup (actr = accounting counters)
382
        wire            actr_ack, actr_stall;
383
        wire    [31:0]   actr_data;
384 9 dgisselq
        assign  actr_ack = ((mtc_ack | moc_ack | mpc_ack | mic_ack)
385
                                |(utc_ack | uoc_ack | upc_ack | uic_ack));
386
        assign  actr_stall = ((mtc_stall | moc_stall | mpc_stall | mic_stall)
387
                                |(utc_stall | uoc_stall | upc_stall|uic_stall));
388 2 dgisselq
        assign  actr_data = ((mtc_ack) ? mtc_data
389 9 dgisselq
                                : ((moc_ack) ? moc_data
390 2 dgisselq
                                : ((mpc_ack) ? mpc_data
391 9 dgisselq
                                : ((mic_ack) ? mic_data
392 2 dgisselq
                                : ((utc_ack) ? utc_data
393 9 dgisselq
                                : ((uoc_ack) ? uoc_data
394 2 dgisselq
                                : ((upc_ack) ? upc_data
395 9 dgisselq
                                : uic_data)))))));
396 2 dgisselq
 
397
 
398
 
399
        //
400
        // Counter Interrupt controller
401
        //
402
        reg             ctri_ack;
403
        wire            ctri_stall, ctri_int, ctri_sel;
404
        wire    [7:0]    ctri_vector;
405
        wire    [31:0]   ctri_data;
406
        assign  ctri_sel = (sys_cyc)&&(sys_stb)&&(sys_addr == `CTRINT);
407 9 dgisselq
        assign  ctri_vector = { mtc_int, moc_int, mpc_int, mic_int,
408
                                        utc_int, uoc_int, upc_int, uic_int };
409 2 dgisselq
        icontrol #(8)   ctri(i_clk, cpu_reset, (ctri_sel)&&(sys_addr==`CTRINT),
410
                                sys_data, ctri_data, ctri_vector, ctri_int);
411
        always @(posedge i_clk)
412
                ctri_ack <= ctri_sel;
413
 
414
 
415
        //
416
        // Timer A
417
        //
418
        wire            tma_ack, tma_stall, tma_int;
419
        wire    [31:0]   tma_data;
420
        ziptimer timer_a(i_clk, cpu_reset, ~cmd_halt,
421
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_A), sys_we,
422
                                sys_data,
423
                        tma_ack, tma_stall, tma_data, tma_int);
424
 
425
        //
426
        // Timer B
427
        //
428
        wire            tmb_ack, tmb_stall, tmb_int;
429
        wire    [31:0]   tmb_data;
430
        ziptimer timer_b(i_clk, cpu_reset, ~cmd_halt,
431
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_B), sys_we,
432
                                sys_data,
433
                        tmb_ack, tmb_stall, tmb_data, tmb_int);
434
 
435
        //
436
        // Timer C
437
        //
438
        wire            tmc_ack, tmc_stall, tmc_int;
439
        wire    [31:0]   tmc_data;
440
        ziptimer timer_c(i_clk, cpu_reset, ~cmd_halt,
441
                        sys_cyc, (sys_stb)&&(sys_addr == `TIMER_C), sys_we,
442
                                sys_data,
443
                        tmc_ack, tmc_stall, tmc_data, tmc_int);
444
 
445
        //
446
        // JIFFIES
447
        //
448
        wire            jif_ack, jif_stall, jif_int;
449
        wire    [31:0]   jif_data;
450
        zipjiffies jiffies(i_clk, ~cmd_halt,
451
                        sys_cyc, (sys_stb)&&(sys_addr == `JIFFIES), sys_we,
452
                                sys_data,
453
                        jif_ack, jif_stall, jif_data, jif_int);
454
 
455
        //
456
        // The programmable interrupt controller peripheral
457
        //
458
        wire            pic_interrupt;
459 34 dgisselq
        wire    [(5+EXTERNAL_INTERRUPTS):0]      int_vector;
460 2 dgisselq
        assign  int_vector = { i_ext_int, ctri_int, tma_int, tmb_int, tmc_int,
461
                                        jif_int, cache_int };
462 34 dgisselq
        icontrol #(6+EXTERNAL_INTERRUPTS)       pic(i_clk, cpu_reset,
463 2 dgisselq
                                (sys_cyc)&&(sys_stb)&&(sys_we)
464
                                        &&(sys_addr==`INTCTRL),
465
                                sys_data, pic_data,
466
                                int_vector, pic_interrupt);
467
        reg     pic_ack;
468
        always @(posedge i_clk)
469
                pic_ack <= (sys_cyc)&&(sys_stb)&&(sys_addr == `INTCTRL);
470
 
471
        //
472
        // The CPU itself
473
        //
474
        wire            cpu_cyc, cpu_stb, cpu_we, cpu_dbg_we;
475
        wire    [31:0]   cpu_data, wb_data;
476
        wire            cpu_ack, cpu_stall;
477
        wire    [31:0]   cpu_dbg_data;
478
        assign cpu_dbg_we = ((dbg_cyc)&&(dbg_stb)&&(~cmd_addr[5])
479
                                        &&(dbg_we)&&(dbg_addr));
480
        zipcpu  #(RESET_ADDRESS) thecpu(i_clk, cpu_reset, pic_interrupt,
481 18 dgisselq
                        cpu_halt, cmd_clear_pf_cache, cmd_addr[4:0], cpu_dbg_we,
482 2 dgisselq
                                dbg_idata, cpu_dbg_stall, cpu_dbg_data,
483 18 dgisselq
                                cpu_dbg_cc, cpu_break,
484 2 dgisselq
                        cpu_cyc, cpu_stb, cpu_we, cpu_addr, cpu_data,
485
                                cpu_ack, cpu_stall, wb_data,
486 9 dgisselq
                        cpu_op_stall, cpu_pf_stall, cpu_i_count);
487 2 dgisselq
 
488
        // Now, arbitrate the bus ... first for the local peripherals
489
        assign  sys_cyc = (cpu_cyc)||((cpu_halt)&&(~cpu_dbg_stall)&&(dbg_cyc));
490
        assign  sys_stb = (cpu_cyc)
491
                                ? ((cpu_stb)&&(cpu_addr[31:4] == 28'hc000000))
492
                                : ((dbg_stb)&&(dbg_addr)&&(cmd_addr[5]));
493
 
494
        assign  sys_we  = (cpu_cyc) ? cpu_we : dbg_we;
495
        assign  sys_addr= (cpu_cyc) ? cpu_addr[3:0] : cmd_addr[3:0];
496
        assign  sys_data= (cpu_cyc) ? cpu_data : dbg_idata;
497
        assign  cache_stb=((cpu_cyc)&&(cpu_stb)&&(cpu_addr[31:16]==`CACHEBASE));
498
 
499
        // Return debug response values
500
        assign  dbg_odata = (~dbg_addr)?cmd_data
501
                                :((~cmd_addr[5])?cpu_dbg_data : wb_data);
502
        initial dbg_ack = 1'b0;
503
        always @(posedge i_clk)
504
                dbg_ack <= (dbg_cyc)&&(dbg_stb)&&
505
                                ((~dbg_addr)||((cpu_halt)&&(~cpu_dbg_stall)));
506
        assign  dbg_stall=(dbg_addr)&&(dbg_cyc)
507 25 dgisselq
                                &&((cpu_cyc)||((cmd_halt)&&(~cpu_halt))
508
                                        ||(cpu_dbg_stall));
509 2 dgisselq
 
510
        // Now for the external wishbone bus
511
        //      Need to arbitrate between the flash cache and the CPU
512
        // The way this works, though, the CPU will stall once the flash 
513
        // cache gets access to the bus--the CPU will be stuck until the 
514
        // flash cache is finished with the bus.
515
        wire            ext_cyc, ext_stb, ext_we;
516
        wire            cpu_ext_ack, cpu_ext_stall, ext_ack, ext_stall;
517
        wire    [31:0]   ext_addr, ext_odata;
518
        wbarbiter #(32,32) flashvcpu(i_clk, i_rst,
519
                        fc_addr, fc_data, fc_we, fc_stb, fc_cyc,
520
                                        fc_ack, fc_stall,
521
                        cpu_addr, cpu_data, cpu_we,
522
                                ((cpu_stb)&&(~sys_stb)&&(~cache_stb)),
523
                                cpu_cyc, cpu_ext_ack, cpu_ext_stall,
524
                        ext_addr, ext_odata, ext_we, ext_stb,
525
                                ext_cyc, ext_ack, ext_stall);
526
 
527 3 dgisselq
`ifdef  DELAY_EXT_BUS
528 2 dgisselq
        busdelay #(32,32) extbus(i_clk,
529
                        ext_cyc, ext_stb, ext_we, ext_addr, ext_odata,
530
                                ext_ack, ext_stall, ext_idata,
531
                        o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
532
                                i_wb_ack, i_wb_stall, i_wb_data);
533 3 dgisselq
`else
534
        assign  o_wb_cyc   = ext_cyc;
535
        assign  o_wb_stb   = ext_stb;
536
        assign  o_wb_we    = ext_we;
537
        assign  o_wb_addr  = ext_addr;
538
        assign  o_wb_data  = ext_odata;
539
        assign  ext_ack    = i_wb_ack;
540
        assign  ext_stall  = i_wb_stall;
541
        assign  ext_idata  = i_wb_data;
542
`endif
543 2 dgisselq
 
544
        wire            tmr_ack;
545
        assign  tmr_ack = (tma_ack|tmb_ack|tmc_ack|jif_ack);
546
        wire    [31:0]   tmr_data;
547
        assign  tmr_data = (tma_ack)?tma_data
548
                                :(tmb_ack ? tmb_data
549
                                :(tmc_ack ? tmc_data
550
                                :jif_data));
551
        assign  wb_data = (tmr_ack|wdt_ack)?((tmr_ack)?tmr_data:wdt_data)
552
                        :((actr_ack|cache_ack)?((actr_ack)?actr_data:cache_data)
553
                        :((pic_ack|ctri_ack)?((pic_ack)?pic_data:ctri_data)
554
                        :(ext_idata)));
555
 
556
        assign  cpu_stall = (tma_stall | tmb_stall | tmc_stall | jif_stall
557
                                | wdt_stall | cache_stall
558
                                | cpu_ext_stall);
559
        assign  cpu_ack = (tmr_ack|wdt_ack|cache_ack|cpu_ext_ack|ctri_ack|actr_ack|pic_ack);
560 18 dgisselq
 
561
        assign  o_ext_int = (cmd_halt) && (~cpu_stall);
562
 
563 2 dgisselq
endmodule

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