OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sim/] [verilator/] [testb.h] - Blame information for rev 209

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 204 dgisselq
////////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    testb.h
4
//
5 209 dgisselq
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6 204 dgisselq
//
7
// Purpose:     A wrapper for a common interface to a clocked FPGA core
8
//              begin exercised in Verilator.
9
//
10
// Creator:     Dan Gisselquist, Ph.D.
11
//              Gisselquist Technology, LLC
12
//
13
////////////////////////////////////////////////////////////////////////////////
14
//
15
// Copyright (C) 2015,2017, Gisselquist Technology, LLC
16
//
17
// This program is free software (firmware): you can redistribute it and/or
18
// modify it under the terms of  the GNU General Public License as published
19
// by the Free Software Foundation, either version 3 of the License, or (at
20
// your option) any later version.
21
//
22
// This program is distributed in the hope that it will be useful, but WITHOUT
23
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
24
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
25
// for more details.
26
//
27
// You should have received a copy of the GNU General Public License along
28 208 dgisselq
// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
29 204 dgisselq
// target there if the PDF file isn't present.)  If not, see
30
// <http://www.gnu.org/licenses/> for a copy.
31
//
32
// License:     GPL, v3, as defined and found on www.gnu.org,
33
//              http://www.gnu.org/licenses/gpl.html
34
//
35
//
36
////////////////////////////////////////////////////////////////////////////////
37 209 dgisselq
//
38
//
39 204 dgisselq
#ifndef TESTB_H
40
#define TESTB_H
41
 
42
#include <stdio.h>
43
#include <stdint.h>
44
#include <verilated_vcd_c.h>
45
 
46 209 dgisselq
#define TBASSERT(TB,A) do { if (!(A)) { (TB).closetrace(); } assert(A); } while(0);
47
 
48 204 dgisselq
template <class VA>     class TESTB {
49
public:
50 209 dgisselq
        VA              *m_core;
51 204 dgisselq
        VerilatedVcdC*  m_trace;
52 209 dgisselq
        uint64_t        m_tickcount;
53 204 dgisselq
 
54
        TESTB(void) : m_trace(NULL), m_tickcount(0l) {
55
                m_core = new VA;
56
                Verilated::traceEverOn(true);
57 208 dgisselq
                m_core->i_clk = 0;
58
                eval(); // Get our initial values set properly.
59 204 dgisselq
        }
60
        virtual ~TESTB(void) {
61 209 dgisselq
                closetrace();
62 204 dgisselq
                delete m_core;
63
                m_core = NULL;
64
        }
65
 
66
        virtual void    opentrace(const char *vcdname) {
67 208 dgisselq
                if (!m_trace) {
68
                        m_trace = new VerilatedVcdC;
69
                        m_core->trace(m_trace, 99);
70
                        m_trace->open(vcdname);
71
                }
72 204 dgisselq
        }
73
 
74
        virtual void    closetrace(void) {
75
                if (m_trace) {
76
                        m_trace->close();
77 209 dgisselq
                        delete m_trace;
78 204 dgisselq
                        m_trace = NULL;
79
                }
80
        }
81
 
82
        virtual void    eval(void) {
83
                m_core->eval();
84
        }
85
 
86
        virtual void    tick(void) {
87
                m_tickcount++;
88
 
89 208 dgisselq
                // Make sure we have our evaluations straight before the top
90
                // of the clock.  This is necessary since some of the 
91
                // connection modules may have made changes, for which some
92
                // logic depends.  This forces that logic to be recalculated
93
                // before the top of the clock.
94 204 dgisselq
                eval();
95 209 dgisselq
                if (m_trace) m_trace->dump((vluint64_t)(10*m_tickcount-2));
96 204 dgisselq
                m_core->i_clk = 1;
97
                eval();
98 209 dgisselq
                if (m_trace) m_trace->dump((vluint64_t)(10*m_tickcount));
99 204 dgisselq
                m_core->i_clk = 0;
100
                eval();
101 209 dgisselq
                if (m_trace) {
102
                        m_trace->dump((vluint64_t)(10*m_tickcount+5));
103
                        m_trace->flush();
104
                }
105 204 dgisselq
        }
106
 
107
        virtual void    reset(void) {
108 209 dgisselq
                m_core->i_reset = 1;
109 204 dgisselq
                tick();
110 209 dgisselq
                m_core->i_reset = 0;
111 204 dgisselq
                // printf("RESET\n");
112
        }
113 209 dgisselq
 
114
        unsigned long   tickcount(void) {
115
                return m_tickcount;
116
        }
117 204 dgisselq
};
118
 
119
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.