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dgisselq |
////////////////////////////////////////////////////////////////////////////////
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//
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// Filename: zipcpu_tb.cpp
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose: A bench simulator for the CPU. Eventually, you should be
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// able to give this program the name of a piece of compiled
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// code to load into memory. For now, we hand assemble with the computers
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// help.
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015-2018, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program. (It's in the $(ROOT)/doc directory. Run make with no
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// target there if the PDF file isn't present.) If not, see
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// <http://www.gnu.org/licenses/> for a copy.
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <signal.h>
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#include <time.h>
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#include <unistd.h>
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#include <poll.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <string.h>
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#include <ctype.h>
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#include <ncurses.h>
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#ifdef ZIPBONES
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#include "Vzipbones.h"
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#define SIMCLASS Vzipbones
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#else
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#define ZIPSYSTEM
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#include "Vzipsystem.h"
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#define SIMCLASS Vzipsystem
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#endif
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#include "cpudefs.h"
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#include "testb.h"
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#include "zipelf.h"
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// #include "twoc.h"
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// #include "qspiflashsim.h"
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#include "byteswap.h"
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#include "memsim.h"
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#include "zopcodes.h"
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#define CMD_REG 0
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#define CMD_DATA 4
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#define CMD_GO 0
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#define CMD_GIE (1<<13)
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#define CMD_SLEEP (1<<12)
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#define CMD_CLEAR_CACHE (1<<11)
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#define CMD_HALT (1<<10)
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#define CMD_STALL (1<<9)
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#define CMD_INT (1<<7)
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#define CMD_RESET (1<<6)
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#define CMD_STEP ((1<<8)|CMD_HALT)
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#define CPU_HALT CMD_HALT
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#define CPU_sPC 15
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#define KEY_ESCAPE 27
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#define KEY_RETURN 10
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#define CTRL(X) ((X)&0x01f)
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#define MAXERR 10000
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// Some versions of Verilator require a prefix starting with the top level
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// module name, rather than v__DOT__.... For these versions of Verilator,
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// you will need to replace these variable prefixes with either
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// zipsystem__DOT__...
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// or
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// zipbones__DOT__...
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#ifdef NEW_VERILATOR
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#ifdef ZIPBONES
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#define VVAR(A) zipbones__DOT_ ## A
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#else
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#define VVAR(A) zipsystem__DOT_ ## A
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#endif
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#else
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#define VVAR(A) v__DOT_ ## A
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#endif
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#define CPUVAR(A) VVAR(_thecpu__DOT_ ##A)
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#ifdef OPT_DCACHE
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///
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// dcache
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#define MEMVAR(A) CPUVAR(_MEM_DCACHE__DOT__docache__DOT_ ## A)
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///
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#elif defined(OPT_PIPELINED_BUS_ACCESS)
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///
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// pipemem
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#define MEMVAR(A) CPUVAR(_NO_CACHE__DOT__MEM__DOT__domem__DOT_ ## A)
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#define mem_wraddr MEMVAR(_wraddr)
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#define mem_rdaddr MEMVAR(_rdaddr)
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///
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#else
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///
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// memops
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#define MEMVAR(A) CPUVAR(_NO_CACHE__DOT__MEM__DOT__domem__DOT_ ## A)
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#endif
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#define cpu_halt VVAR(_cmd_halt)
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#define cmd_reset VVAR(_cmd_reset)
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#define cmd_step VVAR(_cmd_step)
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#define cmd_addr VVAR(_cmd_addr)
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#ifdef OPT_SINGLE_FETCH
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#define early_branch VVAR(_thecpu__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch)
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#else
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#define early_branch VVAR(_thecpu__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch)
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#endif
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#define early_branch_pc VVAR(_thecpu__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc)
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#define dcdRmx VVAR(_thecpu__DOT____Vcellout__instruction_decoder____pinNumber15)
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#define dcdA VVAR(_thecpu__DOT____Vcellout__instruction_decoder____pinNumber15)
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#define dcdB VVAR(_thecpu__DOT____Vcellout__instruction_decoder____pinNumber16)
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#define new_pc VVAR(_thecpu__DOT__new_pc)
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#define cpu_ipc VVAR(_thecpu__DOT__ipc)
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#define cpu_upc VVAR(_thecpu__DOT__SET_USER_PC__DOT__r_upc)
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#define pf_pc VVAR(_thecpu__DOT__pf_pc)
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// PF
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#define pf_cyc VVAR(_thecpu__DOT__pf_cyc)
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#define pf_stb VVAR(_thecpu__DOT__pf_stb)
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#define pf_we VVAR(_thecpu__DOT__pf_we)
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#define pf_addr VVAR(_thecpu__DOT__pf_addr)
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#define pf_ack VVAR(_thecpu__DOT__pf_ack)
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#define pf_valid VVAR(_thecpu__DOT__pf_valid)
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#define pf_illegal VVAR(_thecpu__DOT__pf_illegal)
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#define pf_vmask VVAR(_thecpu__DOT__pf__DOT__valid_mask)
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#define pf_r_v VVAR(_thecpu__DOT__pf__DOT__r_v)
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// #define pf_illegal VVAR(_thecpu__DOT__pf__DOT__pf_illegal)
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#define pf_tagsrc VVAR(_thecpu__DOT__pf__DOT__rvsrc)
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#define pf_tagipc VVAR(_thecpu__DOT__pf__DOT__tagvalipc)
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#define pf_tagvallst VVAR(_thecpu__DOT__pf__DOT__tagvallst)
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#define pf_lastpc VVAR(_thecpu__DOT__pf__DOT__lastpc)
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#define pf_instruction VVAR(_thecpu__DOT__pf_instruction)
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// Decode
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#ifdef OPT_PIPELINED
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#define dcd_ce VVAR(_thecpu__DOT__dcd_ce)
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#else
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#define dcd_ce VVAR(_thecpu__DOT__dcd_stalled)^1
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#endif
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#define dcd_stalled VVAR(_thecpu__DOT__dcd_stalled)
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#define dcd_gie VVAR(_thecpu__DOT__SET_GIE__DOT__r_gie)
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#define dcd_illegal VVAR(_thecpu__DOT__dcd_illegal)
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#define dcd_valid VVAR(_thecpu__DOT__instruction_decoder__DOT__r_valid)
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#define dcd_opn VVAR(_thecpu__DOT__dcd_opn)
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#define dcd_rA VVAR(_thecpu__DOT__dcd_rA)
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#define dcd_rB VVAR(_thecpu__DOT__dcd_rB)
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#define dcdR VVAR(_thecpu__DOT__instruction_decoder__DOT__w_dcdR)
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#define dcdRpc VVAR(_thecpu__DOT__instruction_decoder__DOT__w_dcdR_pc)
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#define dcdRcc VVAR(_thecpu__DOT__instruction_decoder__DOT__w_dcdR_cc)
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#define dcd_wR VVAR(_thecpu__DOT__dcd_wR)
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#define dcd_pc VVAR(_thecpu__DOT__dcd_pc)
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#define dcd_wF VVAR(_thecpu__DOT__dcd_wF)
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#define dcd_M VVAR(_thecpu__DOT__dcd_M)
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// Op
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#define op_ce VVAR(_thecpu__DOT__op_ce)
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#define op_illegal VVAR(_thecpu__DOT__op_illegal)
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#define op_valid VVAR(_thecpu__DOT__op_valid)
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#define op_valid_mem VVAR(_thecpu__DOT__op_valid_mem)
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#define op_valid_alu VVAR(_thecpu__DOT__op_valid_alu)
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#ifdef OPT_PIPELINED
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#define op_R VVAR(_thecpu__DOT__op_R)
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#define op_stall VVAR(_thecpu__DOT__op_stall)
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#else
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#define op_R dcdR
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#endif
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#define op_wR VVAR(_thecpu__DOT__op_wR)
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#define op_wF VVAR(_thecpu__DOT__op_wF)
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#define master_stall VVAR(_thecpu__DOT__master_stall)
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// ALU
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#define alu_ce VVAR(_thecpu__DOT__alu_ce)
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#define alu_valid VVAR(_thecpu__DOT__alu_valid)
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// #define alu_stall VVAR(_thecpu__DOT__alu_stall)
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#define alu_wF VVAR(_thecpu__DOT__alu_wF)
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#define alu_pc_valid VVAR(_thecpu__DOT__alu_pc_valid)
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#define alu_flags VVAR(_thecpu__DOT__alu_flags)
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#define alu_wR VVAR(_thecpu__DOT__alu_wR)
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#ifdef OPT_PIPELINED
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#define alu_illegal VVAR(_thecpu__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal)
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#else
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#define alu_illegal op_illegal
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#endif
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#define set_cond VVAR(_thecpu__DOT__set_cond)
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// MEM
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#define mem_valid CPUVAR(_mem_valid)
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#define mem_pc_valid CPUVAR(_mem_pc_valid)
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#define mem_ce CPUVAR(_mem_ce)
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#define mem_cyc MEMVAR(_cyc)
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#define mem_rdbusy CPUVAR(_mem_rdbusy)
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#define mem_wreg CPUVAR(_mem_wreg)
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// DIV
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#ifdef OPT_DIVIDE
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#define div_valid CPUVAR(_div_valid)
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#define div_ce CPUVAR(_div_ce)
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#define div_busy CPUVAR(_div_busy)
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#endif
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//
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#define wr_reg_id CPUVAR(_wr_reg_id)
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#define wr_reg_ce CPUVAR(_wr_reg_ce)
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#define wr_gpreg_vl CPUVAR(_wr_gpreg_vl)
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#ifdef OPT_DIVIDE
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#define wr_spreg_vl CPUVAR(_wr_spreg_vl)
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#else
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#define wr_spreg_vl wr_gpreg_vl
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#endif
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#define wr_reg_ce CPUVAR(_wr_reg_ce)
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#define wr_flags_ce CPUVAR(_wr_flags_ce)
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#define w_iflags CPUVAR(_w_iflags)
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#define w_uflags CPUVAR(_w_uflags)
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// Op-Sim instructions
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#define cpu_sim VVAR(_thecpu__DOT__op_sim)
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#define cpu_sim_immv VVAR(_thecpu__DOT__op_sim_immv)
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//
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#define r_sleep VVAR(_thecpu__DOT__sleep)
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#define master_ce VVAR(_thecpu__DOT__master_ce)
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#define op_break VVAR(_thecpu__DOT__r_op_break)
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#define op_F VVAR(_thecpu__DOT__op_F)
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//
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#define regset VVAR(_thecpu__DOT__regset)
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#define cpu_regs regset
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#ifdef OPT_CIS
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#define dcd_phase VVAR(_thecpu__DOT__dcd_phase)
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#define op_phase VVAR(_thecpu__DOT__OPT_CIS_OP_PHASE__DOT__r_op_phase)
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#define alu_phase VVAR(_thecpu__DOT__GEN_ALU_PHASE__DOT__r_alu_phase)
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#endif
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#ifdef OPT_SINGLE_FETCH
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#define pf_instruction_pc VVAR(_thecpu__DOT__pf_addr)<<2
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#else
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#define pf_instruction_pc VVAR(_thecpu__DOT__pf_instruction_pc)
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#endif
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#ifdef OPT_PIPELINED
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#define op_Av VVAR(_thecpu__DOT__op_Av)
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#define op_Bv VVAR(_thecpu__DOT__op_Bv)
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#define alu_gie dcd_gie
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#define alu_pc VVAR(_thecpu__DOT__GEN_ALU_PC__DOT__r_alu_pc)
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#define op_Aid VVAR(_thecpu__DOT__op_Aid)
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#define op_Bid VVAR(_thecpu__DOT__op_Bid)
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#else
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#define op_Av VVAR(_thecpu__DOT__r_op_Av)
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#define op_Bv VVAR(_thecpu__DOT__r_op_Bv)
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#define alu_gie dcd_gie
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#define alu_pc VVAR(_thecpu__DOT__op_pc)
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#endif
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#define op_gie dcd_gie
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#define r_op_pc VVAR(_thecpu__DOT__op_pc)
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#ifdef ZIPSYSTEM
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#define dbg_cyc VVAR(_dbg_cyc)
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#define dbg_stb VVAR(_dbg_stb)
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#define dbg_we VVAR(_dbg_we)
|
| 302 |
|
|
#define dbg_idata VVAR(_dbg_idata)
|
| 303 |
|
|
#define cpu_stall VVAR(_cpu_stall)
|
| 304 |
|
|
#define cpu_interrupt VVAR(_MAIN_PIC__DOT__pic__DOT__r_interrupt)
|
| 305 |
|
|
#define cpu_idata VVAR(_cpu_idata)
|
| 306 |
|
|
#define tick_counter m_core->VVAR(_jiffies__DOT__r_counter)
|
| 307 |
|
|
#define dbg_addr VVAR(_dbg_addr)
|
| 308 |
|
|
#else
|
| 309 |
|
|
#define dbg_cyc i_dbg_cyc
|
| 310 |
|
|
#define dbg_stb i_dbg_stb
|
| 311 |
|
|
#define dbg_we i_dbg_we
|
| 312 |
|
|
#define dbg_idata i_dbg_data
|
| 313 |
|
|
#define cpu_stall i_wb_stall
|
| 314 |
|
|
#define cpu_interrupt i_ext_int
|
| 315 |
|
|
#define cpu_idata i_wb_data
|
| 316 |
|
|
#define tick_counter tickcount()
|
| 317 |
|
|
#define dbg_addr i_dbg_addr
|
| 318 |
|
|
#endif
|
| 319 |
|
|
|
| 320 |
|
|
#define r_gie VVAR(_thecpu__DOT__SET_GIE__DOT__r_gie)
|
| 321 |
|
|
#define pic_data VVAR(_pic_data)
|
| 322 |
|
|
#define r_value VVAR(_r_value)
|
| 323 |
|
|
#define watchbus VVAR(_watchbus__DOT__r_value)
|
| 324 |
|
|
#define watchdog VVAR(_watchdog__DOT__r_value)
|
| 325 |
|
|
#define wdbus_data VVAR(_r_wdbus_data)
|
| 326 |
|
|
#define int_state VVAR(_MAIN_PIC__DOT__pic__DOT__r_int_state)
|
| 327 |
|
|
#define alt_int_state VVAR(_ALT_PIC__DOT__ctri__DOT__r_int_state)
|
| 328 |
|
|
#define timer_a VVAR(_timer_a__DOT__r_value)
|
| 329 |
|
|
#define timer_b VVAR(_timer_b__DOT__r_value)
|
| 330 |
|
|
#define timer_c VVAR(_timer_c__DOT__r_value)
|
| 331 |
|
|
#define jiffies VVAR(_jiffies__DOT__r_counter)
|
| 332 |
|
|
#define utc_data VVAR(_utc_data)
|
| 333 |
|
|
#define uoc_data VVAR(_uoc_data)
|
| 334 |
|
|
#define upc_data VVAR(_upc_data)
|
| 335 |
|
|
#define uic_data VVAR(_uic_data)
|
| 336 |
|
|
#define mtc_data VVAR(_mtc_data)
|
| 337 |
|
|
#define moc_data VVAR(_moc_data)
|
| 338 |
|
|
#define mpc_data VVAR(_mpc_data)
|
| 339 |
|
|
#define mic_data VVAR(_mic_data)
|
| 340 |
|
|
|
| 341 |
|
|
#define r_wb_cyc_gbl MEMVAR(_r_wb_cyc_gbl)
|
| 342 |
|
|
#define r_wb_cyc_lcl MEMVAR(_r_wb_cyc_lcl)
|
| 343 |
|
|
#define r_wb_stb_gbl VVAR(_thecpu__DOT__mem_stb_gbl)
|
| 344 |
|
|
#define r_wb_stb_lcl VVAR(_thecpu__DOT__mem_stb_lcl)
|
| 345 |
|
|
#define mem_stb_gbl VVAR(_thecpu__DOT__mem_stb_gbl)
|
| 346 |
|
|
#define mem_stb_lcl VVAR(_thecpu__DOT__mem_stb_lcl)
|
| 347 |
|
|
#define mem_we VVAR(_thecpu__DOT__mem_we)
|
| 348 |
|
|
#define mem_ack VVAR(_thecpu__DOT__mem_ack)
|
| 349 |
|
|
#define mem_stall VVAR(_thecpu__DOT__mem_stall)
|
| 350 |
|
|
#define mem_data VVAR(_thecpu__DOT__mem_data)
|
| 351 |
|
|
#define mem_addr VVAR(_thecpu__DOT__mem_addr)
|
| 352 |
|
|
#define mem_result VVAR(_thecpu__DOT__mem_result)
|
| 353 |
|
|
#define op_pipe VVAR(_thecpu__DOT__GEN_OP_PIPE__DOT__r_op_pipe)
|
| 354 |
|
|
#define dcd_pipe VVAR(_thecpu__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe)
|
| 355 |
|
|
#define op_A_alu VVAR(_thecpu__DOT__op_A_alu)
|
| 356 |
|
|
#define op_B_alu VVAR(_thecpu__DOT__op_B_alu)
|
| 357 |
|
|
#define op_A_mem VVAR(_thecpu__DOT__op_A_mem)
|
| 358 |
|
|
#define op_B_mem VVAR(_thecpu__DOT__op_B_mem)
|
| 359 |
|
|
#ifdef OPT_PIPELINED
|
| 360 |
|
|
#define op_opn VVAR(_thecpu__DOT__r_op_opn)
|
| 361 |
|
|
#else
|
| 362 |
|
|
#define op_opn dcd_opn
|
| 363 |
|
|
#endif
|
| 364 |
|
|
#define alu_result VVAR(_thecpu__DOT__alu_result)
|
| 365 |
|
|
#define alu_busy VVAR(_thecpu__DOT__doalu__DOT__r_busy)
|
| 366 |
|
|
#define alu_reg VVAR(_thecpu__DOT__alu_reg)
|
| 367 |
|
|
#define switch_to_interrupt VVAR(_thecpu__DOT__w_switch_to_interrupt)
|
| 368 |
|
|
#define release_from_interrupt VVAR(_thecpu__DOT__w_release_from_interrupt)
|
| 369 |
|
|
#define break_en VVAR(_thecpu__DOT__break_en)
|
| 370 |
|
|
#define dcd_break VVAR(_thecpu__DOT__dcd_break)
|
| 371 |
|
|
|
| 372 |
|
|
/*
|
| 373 |
|
|
// We are just a raw CPU with memory. There is no flash.
|
| 374 |
|
|
#define LGFLASHLEN 24
|
| 375 |
|
|
#define FLASHBASE 0x01000000
|
| 376 |
|
|
#define FLASHWORDS (1<<LGFLASHLEN)
|
| 377 |
|
|
*/
|
| 378 |
|
|
|
| 379 |
|
|
#define LGRAMLEN 28
|
| 380 |
|
|
#define RAMBASE (1<<(LGRAMLEN))
|
| 381 |
|
|
#define RAMLEN (1<<(LGRAMLEN))
|
| 382 |
|
|
#define RAMWORDS ((RAMLEN)>>2)
|
| 383 |
|
|
|
| 384 |
|
|
class SPARSEMEM {
|
| 385 |
|
|
public:
|
| 386 |
|
|
bool m_valid;
|
| 387 |
|
|
unsigned int m_a, m_d;
|
| 388 |
|
|
};
|
| 389 |
|
|
|
| 390 |
|
|
class ZIPSTATE {
|
| 391 |
|
|
public:
|
| 392 |
|
|
bool m_valid, m_gie, m_last_pc_valid;
|
| 393 |
|
|
unsigned int m_sR[16], m_uR[16];
|
| 394 |
|
|
#ifdef ZIPSYSTEM
|
| 395 |
|
|
unsigned int m_p[20];
|
| 396 |
|
|
#endif
|
| 397 |
|
|
unsigned int m_last_pc, m_pc, m_sp;
|
| 398 |
|
|
SPARSEMEM m_smem[5]; // Nearby stack memory
|
| 399 |
|
|
SPARSEMEM m_imem[5]; // Nearby instruction memory
|
| 400 |
|
|
ZIPSTATE(void) : m_valid(false), m_last_pc_valid(false) {}
|
| 401 |
|
|
|
| 402 |
|
|
void step(void) {
|
| 403 |
|
|
m_last_pc_valid = true;
|
| 404 |
|
|
m_last_pc = m_pc;
|
| 405 |
|
|
}
|
| 406 |
|
|
};
|
| 407 |
|
|
|
| 408 |
|
|
extern FILE *gbl_dbgfp;
|
| 409 |
|
|
FILE *gbl_dbgfp = NULL;
|
| 410 |
|
|
|
| 411 |
|
|
// No particular "parameters" need definition or redefinition here.
|
| 412 |
|
|
class ZIPCPU_TB : public TESTB<SIMCLASS> {
|
| 413 |
|
|
public:
|
| 414 |
|
|
unsigned long m_mem_size;
|
| 415 |
|
|
MEMSIM m_mem;
|
| 416 |
|
|
// QSPIFLASHSIM m_flash;
|
| 417 |
|
|
FILE *m_dbgfp, *m_profile_fp;
|
| 418 |
|
|
bool dbg_flag, m_bomb, m_show_user_timers, m_console, m_exit;
|
| 419 |
|
|
int m_cursor, m_rcode;
|
| 420 |
|
|
unsigned long m_last_instruction_tickcount;
|
| 421 |
|
|
ZIPSTATE m_state;
|
| 422 |
|
|
|
| 423 |
|
|
ZIPCPU_TB(void) : m_mem_size(RAMWORDS), m_mem(m_mem_size) {
|
| 424 |
|
|
m_rcode = 0;
|
| 425 |
|
|
m_exit = false;
|
| 426 |
|
|
if (true) {
|
| 427 |
|
|
m_dbgfp = fopen("debug.txt", "w");
|
| 428 |
|
|
dbg_flag = true;
|
| 429 |
|
|
gbl_dbgfp = m_dbgfp;
|
| 430 |
|
|
} else {
|
| 431 |
|
|
m_dbgfp = NULL;
|
| 432 |
|
|
dbg_flag = false;
|
| 433 |
|
|
gbl_dbgfp = NULL;
|
| 434 |
|
|
}
|
| 435 |
|
|
|
| 436 |
|
|
if(true) {
|
| 437 |
|
|
opentrace("trace.vcd");
|
| 438 |
|
|
} else {
|
| 439 |
|
|
m_trace = NULL;
|
| 440 |
|
|
}
|
| 441 |
|
|
|
| 442 |
|
|
m_bomb = false;
|
| 443 |
|
|
m_cursor = 0;
|
| 444 |
|
|
m_show_user_timers = false;
|
| 445 |
|
|
|
| 446 |
|
|
m_last_instruction_tickcount = 0l;
|
| 447 |
|
|
if (true) {
|
| 448 |
|
|
m_profile_fp = fopen("pfile.bin","wb");
|
| 449 |
|
|
} else {
|
| 450 |
|
|
m_profile_fp = NULL;
|
| 451 |
|
|
}
|
| 452 |
|
|
}
|
| 453 |
|
|
|
| 454 |
|
|
~ZIPCPU_TB(void) {
|
| 455 |
|
|
if (m_dbgfp)
|
| 456 |
|
|
fclose(m_dbgfp);
|
| 457 |
|
|
if (m_profile_fp)
|
| 458 |
|
|
fclose(m_profile_fp);
|
| 459 |
|
|
if (m_trace)
|
| 460 |
|
|
m_trace->close();
|
| 461 |
|
|
}
|
| 462 |
|
|
|
| 463 |
|
|
void reset(void) {
|
| 464 |
|
|
// m_flash.debug(false);
|
| 465 |
|
|
TESTB<SIMCLASS>::reset();
|
| 466 |
|
|
}
|
| 467 |
|
|
|
| 468 |
|
|
void step(void) {
|
| 469 |
|
|
wb_write(CMD_REG, CMD_STEP);
|
| 470 |
|
|
m_state.step();
|
| 471 |
|
|
}
|
| 472 |
|
|
|
| 473 |
|
|
void read_raw_state(void) {
|
| 474 |
|
|
m_state.m_valid = false;
|
| 475 |
|
|
for(int i=0; i<16; i++)
|
| 476 |
|
|
m_state.m_sR[i] = cmd_read(i);
|
| 477 |
|
|
for(int i=0; i<16; i++)
|
| 478 |
|
|
m_state.m_uR[i] = cmd_read(i+16);
|
| 479 |
|
|
#ifdef ZIPSYSTEM
|
| 480 |
|
|
for(int i=0; i<20; i++)
|
| 481 |
|
|
m_state.m_p[i] = cmd_read(i+32);
|
| 482 |
|
|
#endif
|
| 483 |
|
|
|
| 484 |
|
|
m_state.m_gie = wb_read(CMD_REG) & CMD_GIE;
|
| 485 |
|
|
m_state.m_pc = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
|
| 486 |
|
|
m_state.m_sp = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
|
| 487 |
|
|
|
| 488 |
|
|
if (m_state.m_last_pc_valid)
|
| 489 |
|
|
m_state.m_imem[0].m_a = m_state.m_last_pc;
|
| 490 |
|
|
else
|
| 491 |
|
|
m_state.m_imem[0].m_a = m_state.m_pc - 1;
|
| 492 |
|
|
m_state.m_imem[0].m_d = m_mem[m_state.m_imem[0].m_a & 0x0fffff];
|
| 493 |
|
|
m_state.m_imem[0].m_valid = ((m_state.m_imem[0].m_a & 0xfff00000)==0x00100000);
|
| 494 |
|
|
m_state.m_imem[1].m_a = m_state.m_pc;
|
| 495 |
|
|
m_state.m_imem[1].m_valid = ((m_state.m_imem[1].m_a & 0xfff00000)==0x00100000);
|
| 496 |
|
|
m_state.m_imem[1].m_d = m_mem[m_state.m_imem[1].m_a & 0x0fffff];
|
| 497 |
|
|
|
| 498 |
|
|
for(int i=1; i<4; i++) {
|
| 499 |
|
|
if (!m_state.m_imem[i].m_valid) {
|
| 500 |
|
|
m_state.m_imem[i+1].m_valid = false;
|
| 501 |
|
|
m_state.m_imem[i+1].m_a = m_state.m_imem[i].m_a+1;
|
| 502 |
|
|
continue;
|
| 503 |
|
|
}
|
| 504 |
|
|
m_state.m_imem[i+1].m_a = zop_early_branch(
|
| 505 |
|
|
m_state.m_imem[i].m_a,
|
| 506 |
|
|
m_state.m_imem[i].m_d);
|
| 507 |
|
|
m_state.m_imem[i+1].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
|
| 508 |
|
|
m_state.m_imem[i+1].m_valid = ((m_state.m_imem[i].m_a&0xfff00000)==0x00100000);
|
| 509 |
|
|
}
|
| 510 |
|
|
|
| 511 |
|
|
m_state.m_smem[0].m_a = m_state.m_sp;
|
| 512 |
|
|
for(int i=1; i<5; i++)
|
| 513 |
|
|
m_state.m_smem[i].m_a = m_state.m_smem[i-1].m_a+1;
|
| 514 |
|
|
for(int i=0; i<5; i++) {
|
| 515 |
|
|
m_state.m_smem[i].m_valid =
|
| 516 |
|
|
(m_state.m_imem[i].m_a > 0x10000);
|
| 517 |
|
|
m_state.m_smem[i].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
|
| 518 |
|
|
}
|
| 519 |
|
|
m_state.m_valid = true;
|
| 520 |
|
|
}
|
| 521 |
|
|
|
| 522 |
|
|
void read_raw_state_cheating(void) {
|
| 523 |
|
|
m_state.m_valid = false;
|
| 524 |
|
|
for(int i=0; i<16; i++)
|
| 525 |
|
|
m_state.m_sR[i] = m_core->regset[i];
|
| 526 |
|
|
m_state.m_sR[14] = (m_state.m_sR[14]&0xffffe000)|m_core->w_iflags;
|
| 527 |
|
|
m_state.m_sR[15] = m_core->cpu_ipc;
|
| 528 |
|
|
for(int i=0; i<16; i++)
|
| 529 |
|
|
m_state.m_uR[i] = m_core->regset[i+16];
|
| 530 |
|
|
m_state.m_uR[14] = (m_state.m_uR[14]&0xffffe000)|m_core->w_uflags;
|
| 531 |
|
|
m_state.m_uR[15] = m_core->cpu_upc;
|
| 532 |
|
|
|
| 533 |
|
|
m_state.m_gie = m_core->r_gie;
|
| 534 |
|
|
m_state.m_pc = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
|
| 535 |
|
|
m_state.m_sp = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
|
| 536 |
|
|
|
| 537 |
|
|
#ifdef ZIPSYSTEM
|
| 538 |
|
|
m_state.m_p[0] = m_core->pic_data;
|
| 539 |
|
|
m_state.m_p[1] = m_core->watchdog;
|
| 540 |
|
|
if (!m_show_user_timers) {
|
| 541 |
|
|
m_state.m_p[2] = m_core->watchbus;
|
| 542 |
|
|
} else {
|
| 543 |
|
|
// The last bus error address
|
| 544 |
|
|
m_state.m_p[2] = m_core->wdbus_data;
|
| 545 |
|
|
}
|
| 546 |
|
|
|
| 547 |
|
|
m_state.m_p[3] = m_core->alt_int_state;
|
| 548 |
|
|
m_state.m_p[4] = m_core->timer_a;
|
| 549 |
|
|
m_state.m_p[5] = m_core->timer_b;
|
| 550 |
|
|
m_state.m_p[6] = m_core->timer_c;
|
| 551 |
|
|
m_state.m_p[7] = m_core->jiffies;
|
| 552 |
|
|
|
| 553 |
|
|
m_state.m_p[ 8] = m_core->utc_data;
|
| 554 |
|
|
m_state.m_p[ 9] = m_core->uoc_data;
|
| 555 |
|
|
m_state.m_p[10] = m_core->upc_data;
|
| 556 |
|
|
m_state.m_p[11] = m_core->uic_data;
|
| 557 |
|
|
|
| 558 |
|
|
m_state.m_p[12] = m_core->mtc_data;
|
| 559 |
|
|
m_state.m_p[13] = m_core->moc_data;
|
| 560 |
|
|
m_state.m_p[14] = m_core->mpc_data;
|
| 561 |
|
|
m_state.m_p[15] = m_core->mic_data;
|
| 562 |
|
|
#endif
|
| 563 |
|
|
}
|
| 564 |
|
|
|
| 565 |
|
|
void showval(int y, int x, const char *lbl, unsigned int v, bool c) {
|
| 566 |
|
|
if (c)
|
| 567 |
|
|
mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
|
| 568 |
|
|
else
|
| 569 |
|
|
mvprintw(y,x, " %s: 0x%08x ", lbl, v);
|
| 570 |
|
|
}
|
| 571 |
|
|
|
| 572 |
|
|
void dispreg(int y, int x, const char *n, unsigned int v, bool c) {
|
| 573 |
|
|
// 4,4,8,1 = 17 of 20, +3 = 19
|
| 574 |
|
|
if (c)
|
| 575 |
|
|
mvprintw(y, x, ">%s> 0x%08x<", n, v);
|
| 576 |
|
|
else
|
| 577 |
|
|
mvprintw(y, x, " %s: 0x%08x ", n, v);
|
| 578 |
|
|
}
|
| 579 |
|
|
|
| 580 |
|
|
void dbgreg(FILE *fp, int id, const char *n, unsigned int v) {
|
| 581 |
|
|
/*
|
| 582 |
|
|
if ((id == 14)||(id == 14+16)) {
|
| 583 |
|
|
//char buf[64];
|
| 584 |
|
|
//fprintf(fp, " %s:",
|
| 585 |
|
|
fprintf(fp, " %s: 0x%08x ", n, v);
|
| 586 |
|
|
} else
|
| 587 |
|
|
*/
|
| 588 |
|
|
fprintf(fp, " %s: 0x%08x ", n, v);
|
| 589 |
|
|
}
|
| 590 |
|
|
|
| 591 |
|
|
void showreg(int y, int x, const char *n, int r, bool c) {
|
| 592 |
|
|
if (r < 16)
|
| 593 |
|
|
dispreg(y, x, n, m_state.m_sR[r], c);
|
| 594 |
|
|
else
|
| 595 |
|
|
dispreg(y, x, n, m_state.m_uR[r-16], c);
|
| 596 |
|
|
move(y,x+17);
|
| 597 |
|
|
|
| 598 |
|
|
#ifdef OPT_PIPELINED
|
| 599 |
|
|
addch( ((r == (int)(dcd_Aid()&0x01f))&&(m_core->dcd_valid)
|
| 600 |
|
|
&&(m_core->dcd_rA))
|
| 601 |
|
|
?'a':((c)?'<':' '));
|
| 602 |
|
|
addch( ((r == (int)(dcd_Bid()&0x01f))&&(m_core->dcd_valid)
|
| 603 |
|
|
&&(m_core->dcd_rB))
|
| 604 |
|
|
?'b':' ');
|
| 605 |
|
|
addch( ((r == m_core->wr_reg_id)
|
| 606 |
|
|
&&(m_core->wr_reg_ce))
|
| 607 |
|
|
?'W':' ');
|
| 608 |
|
|
#else
|
| 609 |
|
|
addch( ((r == m_core->wr_reg_id)
|
| 610 |
|
|
&&(m_core->wr_reg_ce))
|
| 611 |
|
|
?'W':((c)?'<':' '));
|
| 612 |
|
|
#endif
|
| 613 |
|
|
}
|
| 614 |
|
|
|
| 615 |
|
|
void showins(int y, const char *lbl, const int ce, const int valid,
|
| 616 |
|
|
const int gie, const int stall, const unsigned int pc,
|
| 617 |
|
|
const bool phase) {
|
| 618 |
|
|
char la[80], lb[80];
|
| 619 |
|
|
unsigned iv = m_mem[pc >> 2];
|
| 620 |
|
|
bool cisw = (iv & 0x80000000)?true:false;
|
| 621 |
|
|
|
| 622 |
|
|
if (ce)
|
| 623 |
|
|
mvprintw(y, 0, "Ck ");
|
| 624 |
|
|
else
|
| 625 |
|
|
mvprintw(y, 0, " ");
|
| 626 |
|
|
if (stall)
|
| 627 |
|
|
printw("Stl ");
|
| 628 |
|
|
else
|
| 629 |
|
|
printw(" ");
|
| 630 |
|
|
printw("%s%c 0x%08x", lbl, ((cisw)&&(phase))?'/':':', pc);
|
| 631 |
|
|
|
| 632 |
|
|
if (valid) {
|
| 633 |
|
|
if (gie) attroff(A_BOLD);
|
| 634 |
|
|
else attron(A_BOLD);
|
| 635 |
|
|
zipi_to_double_string(pc, iv, la, lb);
|
| 636 |
|
|
if ((!cisw)||(phase))
|
| 637 |
|
|
printw(" %-24s", la);
|
| 638 |
|
|
else
|
| 639 |
|
|
printw(" %-24s", lb);
|
| 640 |
|
|
} else {
|
| 641 |
|
|
attroff(A_BOLD);
|
| 642 |
|
|
printw(" (0x%08x)%28s", iv,"");
|
| 643 |
|
|
}
|
| 644 |
|
|
attroff(A_BOLD);
|
| 645 |
|
|
}
|
| 646 |
|
|
|
| 647 |
|
|
void dbgins(const char *lbl, const int ce, const int valid,
|
| 648 |
|
|
const int gie, const int stall, const unsigned int pc,
|
| 649 |
|
|
const bool phase, const bool illegal) {
|
| 650 |
|
|
char la[80], lb[80];
|
| 651 |
|
|
|
| 652 |
|
|
if (!m_dbgfp)
|
| 653 |
|
|
return;
|
| 654 |
|
|
|
| 655 |
|
|
if (ce)
|
| 656 |
|
|
fprintf(m_dbgfp, "%s Ck ", lbl);
|
| 657 |
|
|
else
|
| 658 |
|
|
fprintf(m_dbgfp, "%s ", lbl);
|
| 659 |
|
|
if (stall)
|
| 660 |
|
|
fprintf(m_dbgfp, "Stl ");
|
| 661 |
|
|
else
|
| 662 |
|
|
fprintf(m_dbgfp, " ");
|
| 663 |
|
|
fprintf(m_dbgfp, "0x%08x%s: ", pc, (phase)?"/P":" ");
|
| 664 |
|
|
|
| 665 |
|
|
if (valid) {
|
| 666 |
|
|
zipi_to_double_string(pc, m_mem[pc>>2], la, lb);
|
| 667 |
|
|
if ((phase)||((m_mem[pc>>2]&0x80000000)==0))
|
| 668 |
|
|
fprintf(m_dbgfp, " %-24s", la);
|
| 669 |
|
|
else
|
| 670 |
|
|
fprintf(m_dbgfp, " %-24s", lb);
|
| 671 |
|
|
} else {
|
| 672 |
|
|
fprintf(m_dbgfp, " (0x%08x)", m_mem[pc]);
|
| 673 |
|
|
} if (illegal)
|
| 674 |
|
|
fprintf(m_dbgfp, " (Illegal)");
|
| 675 |
|
|
fprintf(m_dbgfp, "\n");
|
| 676 |
|
|
}
|
| 677 |
|
|
|
| 678 |
|
|
void show_state(void) {
|
| 679 |
|
|
int ln= 0;
|
| 680 |
|
|
|
| 681 |
|
|
read_raw_state_cheating();
|
| 682 |
|
|
|
| 683 |
|
|
mvprintw(ln,0, "Peripherals-SS"); ln++;
|
| 684 |
|
|
printw(" %s",
|
| 685 |
|
|
// (m_core->pf_illegal)?"PI":" ",
|
| 686 |
|
|
(m_core->dcd_illegal)?"DI":" "
|
| 687 |
|
|
);
|
| 688 |
|
|
|
| 689 |
|
|
#ifdef OPT_EARLY_BRANCHING
|
| 690 |
|
|
printw(" %s",
|
| 691 |
|
|
(m_core->early_branch)?"EB":" ");
|
| 692 |
|
|
if (m_core->early_branch)
|
| 693 |
|
|
printw(" 0x%08x", m_core->early_branch_pc);
|
| 694 |
|
|
else printw(" %10s", "");
|
| 695 |
|
|
// printw(" %s", (m_core->v__DOT__thecpu__DOT____Vcellinp__pf____pinNumber3)?"-> P3":" ");
|
| 696 |
|
|
#endif
|
| 697 |
|
|
|
| 698 |
|
|
#ifdef ZIPSYSTEM
|
| 699 |
|
|
showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
|
| 700 |
|
|
showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
|
| 701 |
|
|
// showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
|
| 702 |
|
|
|
| 703 |
|
|
if (!m_show_user_timers) {
|
| 704 |
|
|
showval(ln,40, "WBUS", m_core->watchbus, false);
|
| 705 |
|
|
} else {
|
| 706 |
|
|
// showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
|
| 707 |
|
|
showval(ln,40, "UBUS", m_core->watchbus, false);
|
| 708 |
|
|
}
|
| 709 |
|
|
|
| 710 |
|
|
showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
|
| 711 |
|
|
|
| 712 |
|
|
ln++;
|
| 713 |
|
|
showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
|
| 714 |
|
|
showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
|
| 715 |
|
|
showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
|
| 716 |
|
|
showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
|
| 717 |
|
|
|
| 718 |
|
|
|
| 719 |
|
|
if (!m_show_user_timers) {
|
| 720 |
|
|
ln++;
|
| 721 |
|
|
showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
|
| 722 |
|
|
showval(ln,20, "MOST", m_state.m_p[13], (m_cursor==9));
|
| 723 |
|
|
showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
|
| 724 |
|
|
showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
|
| 725 |
|
|
} else {
|
| 726 |
|
|
ln++;
|
| 727 |
|
|
showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
|
| 728 |
|
|
showval(ln,20, "UOST", m_state.m_p[ 9], (m_cursor==9));
|
| 729 |
|
|
showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
|
| 730 |
|
|
showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
|
| 731 |
|
|
}
|
| 732 |
|
|
#else
|
| 733 |
|
|
ln += 2;
|
| 734 |
|
|
#endif
|
| 735 |
|
|
|
| 736 |
|
|
ln++;
|
| 737 |
|
|
mvprintw(ln, 40, "%s %s",
|
| 738 |
|
|
(m_core->cpu_halt)? "CPU-HALT": " ",
|
| 739 |
|
|
(m_core->cmd_reset)?"CPU-RESET":" "); ln++;
|
| 740 |
|
|
mvprintw(ln, 40, "%s %s %s 0x%02x %s %s",
|
| 741 |
|
|
(m_core->cpu_halt)? "HALT": " ",
|
| 742 |
|
|
(m_core->cmd_reset)?"RESET":" ",
|
| 743 |
|
|
(m_core->cmd_step)? "STEP" :" ",
|
| 744 |
|
|
(m_core->cmd_addr)&0x3f,
|
| 745 |
|
|
(m_core->master_ce)? "*CE*" :"(ce)",
|
| 746 |
|
|
(m_core->cmd_reset)? "*RST*" :"(rst)");
|
| 747 |
|
|
if (m_core->r_gie)
|
| 748 |
|
|
attroff(A_BOLD);
|
| 749 |
|
|
else
|
| 750 |
|
|
attron(A_BOLD);
|
| 751 |
|
|
mvprintw(ln, 0, "Supervisor Registers");
|
| 752 |
|
|
ln++;
|
| 753 |
|
|
|
| 754 |
|
|
showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
|
| 755 |
|
|
showreg(ln,20, "sR1 ", 1, (m_cursor==13));
|
| 756 |
|
|
showreg(ln,40, "sR2 ", 2, (m_cursor==14));
|
| 757 |
|
|
showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
|
| 758 |
|
|
|
| 759 |
|
|
showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
|
| 760 |
|
|
showreg(ln,20, "sR5 ", 5, (m_cursor==17));
|
| 761 |
|
|
showreg(ln,40, "sR6 ", 6, (m_cursor==18));
|
| 762 |
|
|
showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
|
| 763 |
|
|
|
| 764 |
|
|
showreg(ln, 0, "sR8 ", 8, (m_cursor==20));
|
| 765 |
|
|
showreg(ln,20, "sR9 ", 9, (m_cursor==21));
|
| 766 |
|
|
showreg(ln,40, "sR10", 10, (m_cursor==22));
|
| 767 |
|
|
showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
|
| 768 |
|
|
|
| 769 |
|
|
showreg(ln, 0, "sR12", 12, (m_cursor==24));
|
| 770 |
|
|
showreg(ln,20, "sSP ", 13, (m_cursor==25));
|
| 771 |
|
|
|
| 772 |
|
|
unsigned int cc = m_state.m_sR[14];
|
| 773 |
|
|
if (false) {
|
| 774 |
|
|
mvprintw(ln,40, "%ssCC : 0x%08x",
|
| 775 |
|
|
(m_cursor==26)?">":" ", cc);
|
| 776 |
|
|
} else {
|
| 777 |
|
|
char cbuf[32];
|
| 778 |
|
|
|
| 779 |
|
|
sprintf(cbuf, "%ssCC :%s%s%s%s%s%s%s",
|
| 780 |
|
|
(m_cursor==26)?">":" ",
|
| 781 |
|
|
(cc&0x01000)?"FE":"",
|
| 782 |
|
|
(cc&0x00800)?"DE":"",
|
| 783 |
|
|
(cc&0x00400)?"BE":"",
|
| 784 |
|
|
(cc&0x00200)?"TP":"",
|
| 785 |
|
|
(cc&0x00100)?"IL":"",
|
| 786 |
|
|
(cc&0x00080)?"BK":"",
|
| 787 |
|
|
((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
|
| 788 |
|
|
mvprintw(ln,40, "%-14s",cbuf);
|
| 789 |
|
|
mvprintw(ln, 54, "%s%s%s%s",
|
| 790 |
|
|
(cc&8)?"V":" ",
|
| 791 |
|
|
(cc&4)?"N":" ",
|
| 792 |
|
|
(cc&2)?"C":" ",
|
| 793 |
|
|
(cc&1)?"Z":" ");
|
| 794 |
|
|
}
|
| 795 |
|
|
showval(ln,60, "sPC ", m_state.m_sR[15], (m_cursor==27));
|
| 796 |
|
|
mvprintw(ln,60,"%s",
|
| 797 |
|
|
(m_core->wr_reg_id == 0x0e)
|
| 798 |
|
|
&&(m_core->wr_reg_ce)
|
| 799 |
|
|
?"V"
|
| 800 |
|
|
:(((m_core->wr_flags_ce)
|
| 801 |
|
|
&&(!m_core->alu_gie))?"+"
|
| 802 |
|
|
:" "));
|
| 803 |
|
|
ln++;
|
| 804 |
|
|
|
| 805 |
|
|
if (m_core->r_gie)
|
| 806 |
|
|
attron(A_BOLD);
|
| 807 |
|
|
else
|
| 808 |
|
|
attroff(A_BOLD);
|
| 809 |
|
|
mvprintw(ln, 0, "User Registers");
|
| 810 |
|
|
mvprintw(ln, 42, "DCDR=%02x %s%s",
|
| 811 |
|
|
m_core->dcdR,
|
| 812 |
|
|
(m_core->dcd_wR)?"W":" ",
|
| 813 |
|
|
(m_core->dcd_wF)?"F":" ");
|
| 814 |
|
|
mvprintw(ln, 62, "OPR =%02x %s%s",
|
| 815 |
|
|
m_core->op_R,
|
| 816 |
|
|
(m_core->op_wR)?"W":" ",
|
| 817 |
|
|
(m_core->op_wF)?"F":" ");
|
| 818 |
|
|
ln++;
|
| 819 |
|
|
showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
|
| 820 |
|
|
showreg(ln,20, "uR1 ", 17, (m_cursor==29));
|
| 821 |
|
|
showreg(ln,40, "uR2 ", 18, (m_cursor==30));
|
| 822 |
|
|
showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
|
| 823 |
|
|
|
| 824 |
|
|
showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
|
| 825 |
|
|
showreg(ln,20, "uR5 ", 21, (m_cursor==33));
|
| 826 |
|
|
showreg(ln,40, "uR6 ", 22, (m_cursor==34));
|
| 827 |
|
|
showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
|
| 828 |
|
|
|
| 829 |
|
|
showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
|
| 830 |
|
|
showreg(ln,20, "uR9 ", 25, (m_cursor==37));
|
| 831 |
|
|
showreg(ln,40, "uR10", 26, (m_cursor==38));
|
| 832 |
|
|
showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
|
| 833 |
|
|
|
| 834 |
|
|
showreg(ln, 0, "uR12", 28, (m_cursor==40));
|
| 835 |
|
|
showreg(ln,20, "uSP ", 29, (m_cursor==41));
|
| 836 |
|
|
cc = m_state.m_uR[14];
|
| 837 |
|
|
if (false) {
|
| 838 |
|
|
mvprintw(ln,40, "%cuCC : 0x%08x",
|
| 839 |
|
|
(m_cursor == 42)?'>':' ', cc);
|
| 840 |
|
|
} else {
|
| 841 |
|
|
char cbuf[32];
|
| 842 |
|
|
sprintf(cbuf, "%cuCC :%s%s%s%s%s%s%s",
|
| 843 |
|
|
(m_cursor == 42)?'>':' ',
|
| 844 |
|
|
(cc & 0x1000)?"FE":"",
|
| 845 |
|
|
(cc & 0x0800)?"DE":"",
|
| 846 |
|
|
(cc & 0x0400)?"BE":"",
|
| 847 |
|
|
(cc & 0x0200)?"TP":"",
|
| 848 |
|
|
(cc & 0x0100)?"IL":"",
|
| 849 |
|
|
(cc & 0x0040)?"ST":"",
|
| 850 |
|
|
((m_state.m_gie)&&(cc & 0x010))?"SL":"");
|
| 851 |
|
|
mvprintw(ln,40, "%-14s",cbuf);
|
| 852 |
|
|
mvprintw(ln, 54, "%s%s%s%s",
|
| 853 |
|
|
(cc&8)?"V":" ",
|
| 854 |
|
|
(cc&4)?"N":" ",
|
| 855 |
|
|
(cc&2)?"C":" ",
|
| 856 |
|
|
(cc&1)?"Z":" ");
|
| 857 |
|
|
}
|
| 858 |
|
|
showval(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
|
| 859 |
|
|
mvprintw(ln,60,"%s",
|
| 860 |
|
|
(m_core->wr_reg_id == 0x1e)
|
| 861 |
|
|
&&(m_core->wr_reg_ce)
|
| 862 |
|
|
?"V"
|
| 863 |
|
|
:(((m_core->wr_flags_ce)
|
| 864 |
|
|
&&(m_core->alu_gie))?"+"
|
| 865 |
|
|
:" "));
|
| 866 |
|
|
|
| 867 |
|
|
attroff(A_BOLD);
|
| 868 |
|
|
ln+=1;
|
| 869 |
|
|
|
| 870 |
|
|
#ifdef OPT_SINGLE_FETCH
|
| 871 |
|
|
ln++;
|
| 872 |
|
|
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
| 873 |
|
|
(m_core->pf_cyc)?"CYC":" ",
|
| 874 |
|
|
(m_core->pf_stb)?"STB":" ",
|
| 875 |
|
|
" ", // (m_core->pf_we )?"WE":" ",
|
| 876 |
|
|
(m_core->pf_addr<<2),
|
| 877 |
|
|
0, // (m_core->v__DOT__thecpu__DOT__pf_data),
|
| 878 |
|
|
(m_core->pf_ack)?"ACK":" ",
|
| 879 |
|
|
" ",//(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":" ",
|
| 880 |
|
|
(m_core->cpu_idata)); ln++;
|
| 881 |
|
|
#else
|
| 882 |
|
|
#ifdef OPT_DOUBLE_FETCH
|
| 883 |
|
|
#else
|
| 884 |
|
|
|
| 885 |
|
|
mvprintw(ln, 0, "PFCACH: v=%08x, %s%s, tag=%08x, pf_pc=%08x, lastpc=%08x",
|
| 886 |
|
|
m_core->pf_vmask,
|
| 887 |
|
|
(m_core->pf_r_v)?"V":" ",
|
| 888 |
|
|
(m_core->pf_illegal)?"I":" ",
|
| 889 |
|
|
(m_core->pf_tagsrc)
|
| 890 |
|
|
?(m_core->pf_tagipc)
|
| 891 |
|
|
:(m_core->pf_tagvallst),
|
| 892 |
|
|
m_core->pf_pc,
|
| 893 |
|
|
m_core->pf_lastpc);
|
| 894 |
|
|
|
| 895 |
|
|
#endif
|
| 896 |
|
|
ln++;
|
| 897 |
|
|
mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
| 898 |
|
|
(m_core->pf_cyc)?"CYC":" ",
|
| 899 |
|
|
(m_core->pf_stb)?"STB":" ",
|
| 900 |
|
|
" ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":" ",
|
| 901 |
|
|
(m_core->pf_addr<<2),
|
| 902 |
|
|
0, // (m_core->v__DOT__thecpu__DOT__pf_data),
|
| 903 |
|
|
(m_core->pf_ack)?"ACK":" ",
|
| 904 |
|
|
(pfstall())?"STL":" ",
|
| 905 |
|
|
(m_core->cpu_idata)); ln++;
|
| 906 |
|
|
#endif
|
| 907 |
|
|
|
| 908 |
|
|
mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
|
| 909 |
|
|
(m_core->r_wb_cyc_gbl)?"GCY"
|
| 910 |
|
|
:((m_core->r_wb_cyc_lcl)?"LCY":" "),
|
| 911 |
|
|
(m_core->mem_stb_gbl)?"GSB"
|
| 912 |
|
|
:((m_core->mem_stb_lcl)?"LSB":" "),
|
| 913 |
|
|
(m_core->mem_we )?"WE":" ",
|
| 914 |
|
|
(m_core->mem_addr<<2),
|
| 915 |
|
|
(m_core->mem_data),
|
| 916 |
|
|
(m_core->mem_ack)?"ACK":" ",
|
| 917 |
|
|
(m_core->mem_stall)?"STL":" ",
|
| 918 |
|
|
(m_core->mem_result));
|
| 919 |
|
|
// #define OPT_PIPELINED_BUS_ACCESS
|
| 920 |
|
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
| 921 |
|
|
#ifndef OPT_DCACHE
|
| 922 |
|
|
printw(" %x%x%c%c",
|
| 923 |
|
|
(m_core->mem_wraddr),
|
| 924 |
|
|
(m_core->mem_rdaddr),
|
| 925 |
|
|
(m_core->op_pipe)?'P':'-',
|
| 926 |
|
|
(mem_pipe_stalled())?'S':'-'); ln++;
|
| 927 |
|
|
#else
|
| 928 |
|
|
ln++;
|
| 929 |
|
|
#endif
|
| 930 |
|
|
#else
|
| 931 |
|
|
ln++;
|
| 932 |
|
|
#endif
|
| 933 |
|
|
|
| 934 |
|
|
#define pformem_owner VVAR(_thecpu__DOT__pformem__DOT__r_a_owner)
|
| 935 |
|
|
mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x %s",
|
| 936 |
|
|
(m_core->pformem_owner)?'M':'P',
|
| 937 |
|
|
(m_core->o_wb_cyc)?"CYC":" ",
|
| 938 |
|
|
(m_core->o_wb_stb)?"STB":" ",
|
| 939 |
|
|
(m_core->o_wb_we )?"WE":" ",
|
| 940 |
|
|
(m_core->o_wb_addr<<2),
|
| 941 |
|
|
(m_core->o_wb_data),
|
| 942 |
|
|
(m_core->i_wb_ack)?"ACK":" ",
|
| 943 |
|
|
(m_core->i_wb_stall)?"STL":" ",
|
| 944 |
|
|
(m_core->i_wb_data),
|
| 945 |
|
|
(m_core->i_wb_err)?"(ER!)":" "); ln+=2;
|
| 946 |
|
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
| 947 |
|
|
mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
|
| 948 |
|
|
(m_core->mem_ce),
|
| 949 |
|
|
(m_core->master_ce), //1
|
| 950 |
|
|
(m_core->op_valid_mem), //0
|
| 951 |
|
|
(!m_core->new_pc), //1
|
| 952 |
|
|
// (!m_core->clear_pipeline), //1
|
| 953 |
|
|
(m_core->set_cond), //1
|
| 954 |
|
|
(!mem_stalled()), //1
|
| 955 |
|
|
|
| 956 |
|
|
(mem_stalled()),
|
| 957 |
|
|
(m_core->op_valid_mem),
|
| 958 |
|
|
(m_core->master_ce),
|
| 959 |
|
|
(mem_pipe_stalled()),
|
| 960 |
|
|
(!m_core->op_pipe),
|
| 961 |
|
|
(m_core->mem_cyc)
|
| 962 |
|
|
);
|
| 963 |
|
|
printw(" op_pipe = %d", m_core->dcd_pipe);
|
| 964 |
|
|
// mvprintw(4,4,"r_dcdI = 0x%06x",
|
| 965 |
|
|
// (m_core->v__DOT__thecpu__DOT__dcdI)&0x0ffffff);
|
| 966 |
|
|
#endif
|
| 967 |
|
|
mvprintw(4,42,"0x%08x", m_core->pf_instruction);
|
| 968 |
|
|
#ifdef OPT_SINGLE_CYCLE
|
| 969 |
|
|
printw(" A:%c%c B:%c%c",
|
| 970 |
|
|
(m_core->op_A_alu)?'A':'-',
|
| 971 |
|
|
(m_core->op_A_mem)?'M':'-',
|
| 972 |
|
|
(m_core->op_B_alu)?'A':'-',
|
| 973 |
|
|
(m_core->op_B_mem)?'M':'-');
|
| 974 |
|
|
#else
|
| 975 |
|
|
printw(" A:xx B:xx");
|
| 976 |
|
|
#endif
|
| 977 |
|
|
printw(" PFPC=%08x", m_core->pf_pc);
|
| 978 |
|
|
|
| 979 |
|
|
|
| 980 |
|
|
showins(ln, "I ",
|
| 981 |
|
|
#ifdef OPT_PIPELINED
|
| 982 |
|
|
!m_core->dcd_stalled,
|
| 983 |
|
|
#else
|
| 984 |
|
|
1,
|
| 985 |
|
|
#endif
|
| 986 |
|
|
m_core->pf_valid,
|
| 987 |
|
|
//m_core->v__DOT__thecpu__DOT__instruction_gie,
|
| 988 |
|
|
m_core->r_gie,
|
| 989 |
|
|
0,
|
| 990 |
|
|
(m_core->pf_instruction_pc),
|
| 991 |
|
|
true); ln++;
|
| 992 |
|
|
// m_core->pf_pc); ln++;
|
| 993 |
|
|
|
| 994 |
|
|
showins(ln, "Dc",
|
| 995 |
|
|
m_core->dcd_ce, m_core->dcd_valid,
|
| 996 |
|
|
m_core->dcd_gie,
|
| 997 |
|
|
#ifdef OPT_PIPELINED
|
| 998 |
|
|
m_core->dcd_stalled,
|
| 999 |
|
|
#else
|
| 1000 |
|
|
0,
|
| 1001 |
|
|
#endif
|
| 1002 |
|
|
#ifdef OPT_CIS
|
| 1003 |
|
|
((m_core->dcd_phase) ?
|
| 1004 |
|
|
(m_core->dcd_pc+2):m_core->dcd_pc) -4,
|
| 1005 |
|
|
m_core->dcd_phase
|
| 1006 |
|
|
#else
|
| 1007 |
|
|
m_core->dcd_pc - 4,
|
| 1008 |
|
|
false
|
| 1009 |
|
|
#endif
|
| 1010 |
|
|
); ln++;
|
| 1011 |
|
|
if (m_core->dcd_illegal)
|
| 1012 |
|
|
mvprintw(ln-1,10,"I");
|
| 1013 |
|
|
else if (m_core->dcd_M)
|
| 1014 |
|
|
mvprintw(ln-1,10,"M");
|
| 1015 |
|
|
|
| 1016 |
|
|
showins(ln, "Op",
|
| 1017 |
|
|
m_core->op_ce,
|
| 1018 |
|
|
m_core->op_valid,
|
| 1019 |
|
|
m_core->op_gie,
|
| 1020 |
|
|
#ifdef op_stall
|
| 1021 |
|
|
m_core->op_stall,
|
| 1022 |
|
|
#else
|
| 1023 |
|
|
0,
|
| 1024 |
|
|
#endif
|
| 1025 |
|
|
#ifdef OPT_CIS
|
| 1026 |
|
|
op_pc()+((m_core->op_phase)?4:0),
|
| 1027 |
|
|
m_core->op_phase
|
| 1028 |
|
|
#else
|
| 1029 |
|
|
op_pc(), false
|
| 1030 |
|
|
#endif
|
| 1031 |
|
|
); ln++;
|
| 1032 |
|
|
if (m_core->op_illegal)
|
| 1033 |
|
|
mvprintw(ln-1,10,"I");
|
| 1034 |
|
|
else if (m_core->op_valid_mem)
|
| 1035 |
|
|
mvprintw(ln-1,10,"M");
|
| 1036 |
|
|
else if (m_core->op_valid_alu)
|
| 1037 |
|
|
mvprintw(ln-1,10,"A");
|
| 1038 |
|
|
|
| 1039 |
|
|
if (m_core->op_valid_mem) {
|
| 1040 |
|
|
showins(ln, "Mm",
|
| 1041 |
|
|
m_core->mem_ce,
|
| 1042 |
|
|
m_core->mem_pc_valid,
|
| 1043 |
|
|
m_core->alu_gie,
|
| 1044 |
|
|
#ifdef OPT_PIPELINED
|
| 1045 |
|
|
m_core->mem_stall,
|
| 1046 |
|
|
#else
|
| 1047 |
|
|
0,
|
| 1048 |
|
|
#endif
|
| 1049 |
|
|
alu_pc(),
|
| 1050 |
|
|
#ifdef OPT_CIS
|
| 1051 |
|
|
m_core->alu_phase
|
| 1052 |
|
|
#else
|
| 1053 |
|
|
false
|
| 1054 |
|
|
#endif
|
| 1055 |
|
|
);
|
| 1056 |
|
|
} else {
|
| 1057 |
|
|
showins(ln, "Al",
|
| 1058 |
|
|
m_core->alu_ce,
|
| 1059 |
|
|
m_core->alu_pc_valid,
|
| 1060 |
|
|
m_core->alu_gie,
|
| 1061 |
|
|
#ifdef OPT_PIPELINED
|
| 1062 |
|
|
alu_stall(),
|
| 1063 |
|
|
#else
|
| 1064 |
|
|
0,
|
| 1065 |
|
|
#endif
|
| 1066 |
|
|
alu_pc(),
|
| 1067 |
|
|
#ifdef OPT_CIS
|
| 1068 |
|
|
m_core->alu_phase
|
| 1069 |
|
|
#else
|
| 1070 |
|
|
false
|
| 1071 |
|
|
#endif
|
| 1072 |
|
|
);
|
| 1073 |
|
|
} ln++;
|
| 1074 |
|
|
if (m_core->wr_reg_ce)
|
| 1075 |
|
|
mvprintw(ln-1,10,"W");
|
| 1076 |
|
|
else if (m_core->alu_valid)
|
| 1077 |
|
|
mvprintw(ln-1,10,(m_core->alu_wR)?"w":"V");
|
| 1078 |
|
|
else if (m_core->mem_valid)
|
| 1079 |
|
|
mvprintw(ln-1,10,"v");
|
| 1080 |
|
|
else if (m_core->alu_illegal)
|
| 1081 |
|
|
mvprintw(ln-1,10,"I");
|
| 1082 |
|
|
// else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
|
| 1083 |
|
|
// mvprintw(ln-1,10,"i");
|
| 1084 |
|
|
|
| 1085 |
|
|
mvprintw(ln-5, 65,"%s %s",
|
| 1086 |
|
|
(m_core->op_break)?"OB":" ",
|
| 1087 |
|
|
(m_core->new_pc)?"CLRP":" ");
|
| 1088 |
|
|
mvprintw(ln-4, 48,
|
| 1089 |
|
|
(m_core->new_pc)?"new-pc":" ");
|
| 1090 |
|
|
printw("(%s:%02x,%x)",
|
| 1091 |
|
|
(m_core->set_cond)?"SET":" ",
|
| 1092 |
|
|
(m_core->op_F&0x0ff),
|
| 1093 |
|
|
(m_core->op_gie)
|
| 1094 |
|
|
? (m_core->w_uflags)
|
| 1095 |
|
|
: (m_core->w_iflags));
|
| 1096 |
|
|
|
| 1097 |
|
|
printw("(%s%s%s:%02x)",
|
| 1098 |
|
|
(m_core->op_wF)?"OF":" ",
|
| 1099 |
|
|
(m_core->alu_wF)?"FL":" ",
|
| 1100 |
|
|
(m_core->wr_flags_ce)?"W":" ",
|
| 1101 |
|
|
(m_core->alu_flags));
|
| 1102 |
|
|
#ifdef OPT_PIPELINED
|
| 1103 |
|
|
mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
|
| 1104 |
|
|
m_core->op_opn,
|
| 1105 |
|
|
m_core->op_Aid, m_core->op_Bid);
|
| 1106 |
|
|
#else
|
| 1107 |
|
|
mvprintw(ln-3, 48, "");
|
| 1108 |
|
|
#endif
|
| 1109 |
|
|
if (m_core->alu_valid)
|
| 1110 |
|
|
printw("%08x", m_core->alu_result);
|
| 1111 |
|
|
else
|
| 1112 |
|
|
printw("%8s","");
|
| 1113 |
|
|
mvprintw(ln-1, 48, "%s%s%s ",
|
| 1114 |
|
|
(m_core->alu_valid)?"A"
|
| 1115 |
|
|
:((m_core->alu_busy)?"a":" "),
|
| 1116 |
|
|
#ifdef OPT_DIVIDE
|
| 1117 |
|
|
(m_core->div_valid)?"D"
|
| 1118 |
|
|
:((m_core->div_busy)?"d":" "),
|
| 1119 |
|
|
(m_core->div_valid)?"F"
|
| 1120 |
|
|
:((m_core->div_busy)?"f":" ")
|
| 1121 |
|
|
#else
|
| 1122 |
|
|
" ", " "
|
| 1123 |
|
|
#endif
|
| 1124 |
|
|
);
|
| 1125 |
|
|
if ((m_core->mem_ce)||(m_core->mem_valid)) {
|
| 1126 |
|
|
printw("MEM: %s%s %s%s %s %-5s",
|
| 1127 |
|
|
(m_core->op_valid_mem)?"M":" ",
|
| 1128 |
|
|
(m_core->mem_ce)?"CE":" ",
|
| 1129 |
|
|
(m_core->mem_we)?"Wr ":"Rd ",
|
| 1130 |
|
|
(mem_stalled())?"PIPE":" ",
|
| 1131 |
|
|
(m_core->mem_valid)?"V":" ",
|
| 1132 |
|
|
zip_regstr[(m_core->mem_wreg&0x1f)^0x10]);
|
| 1133 |
|
|
} else {
|
| 1134 |
|
|
printw("%18s", "");
|
| 1135 |
|
|
}
|
| 1136 |
|
|
}
|
| 1137 |
|
|
|
| 1138 |
|
|
void show_user_timers(bool v) {
|
| 1139 |
|
|
m_show_user_timers = v;
|
| 1140 |
|
|
}
|
| 1141 |
|
|
|
| 1142 |
|
|
unsigned int cmd_read(unsigned int a) {
|
| 1143 |
|
|
int errcount = 0;
|
| 1144 |
|
|
if (m_dbgfp) {
|
| 1145 |
|
|
dbg_flag= true;
|
| 1146 |
|
|
fprintf(m_dbgfp, "CMD-READ(%d)\n", a);
|
| 1147 |
|
|
}
|
| 1148 |
|
|
wb_write(CMD_REG, CMD_HALT|(a&0x3f));
|
| 1149 |
|
|
while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount<MAXERR))
|
| 1150 |
|
|
errcount++;
|
| 1151 |
|
|
if (errcount >= MAXERR) {
|
| 1152 |
|
|
endwin();
|
| 1153 |
|
|
|
| 1154 |
|
|
printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
|
| 1155 |
|
|
// printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
|
| 1156 |
|
|
#define r_halted VVAR(_thecpu__DOT__r_halted)
|
| 1157 |
|
|
printf("cpu-dbg-stall = %d\n", m_core->r_halted);
|
| 1158 |
|
|
printf("pf_cyc = %d\n", m_core->pf_cyc);
|
| 1159 |
|
|
printf("mem_cyc_gbl = %d\n", (m_core->r_wb_cyc_gbl));
|
| 1160 |
|
|
printf("mem_cyc_lcl = %d\n", m_core->r_wb_cyc_lcl);
|
| 1161 |
|
|
printf("op_valid = %d\n", m_core->op_valid);
|
| 1162 |
|
|
printf("dcd_valid = %d\n", m_core->dcd_valid);
|
| 1163 |
|
|
printf("dcd_ce = %d\n", m_core->dcd_ce);
|
| 1164 |
|
|
#ifdef OPT_PIPELINED
|
| 1165 |
|
|
printf("dcd_stalled = %d\n", m_core->dcd_stalled);
|
| 1166 |
|
|
#endif
|
| 1167 |
|
|
printf("pf_valid = %d\n", m_core->pf_valid);
|
| 1168 |
|
|
// #ifdef OPT_EARLY_BRANCHING
|
| 1169 |
|
|
// printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch);
|
| 1170 |
|
|
// #endif
|
| 1171 |
|
|
|
| 1172 |
|
|
exit(-2);
|
| 1173 |
|
|
}
|
| 1174 |
|
|
|
| 1175 |
|
|
assert(errcount < MAXERR);
|
| 1176 |
|
|
unsigned int v = wb_read(CMD_DATA);
|
| 1177 |
|
|
|
| 1178 |
|
|
if (dbg_flag)
|
| 1179 |
|
|
fprintf(m_dbgfp, "CMD-READ(%d) = 0x%08x\n", a, v);
|
| 1180 |
|
|
dbg_flag = false;
|
| 1181 |
|
|
return v;
|
| 1182 |
|
|
}
|
| 1183 |
|
|
|
| 1184 |
|
|
void cmd_write(unsigned int a, int v) {
|
| 1185 |
|
|
int errcount = 0;
|
| 1186 |
|
|
if ((a&0x0f)==0x0f)
|
| 1187 |
|
|
dbg_flag = true;
|
| 1188 |
|
|
wb_write(CMD_REG, CMD_HALT|(a&0x3f));
|
| 1189 |
|
|
while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount < MAXERR))
|
| 1190 |
|
|
errcount++;
|
| 1191 |
|
|
assert(errcount < MAXERR);
|
| 1192 |
|
|
if (dbg_flag)
|
| 1193 |
|
|
fprintf(m_dbgfp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
|
| 1194 |
|
|
wb_write(CMD_DATA, v);
|
| 1195 |
|
|
}
|
| 1196 |
|
|
|
| 1197 |
|
|
bool halted(void) {
|
| 1198 |
|
|
return (m_core->cpu_halt != 0);
|
| 1199 |
|
|
}
|
| 1200 |
|
|
|
| 1201 |
|
|
void read_state(void) {
|
| 1202 |
|
|
int ln= 0;
|
| 1203 |
|
|
bool gie;
|
| 1204 |
|
|
|
| 1205 |
|
|
read_raw_state();
|
| 1206 |
|
|
if (m_cursor < 0)
|
| 1207 |
|
|
m_cursor = 0;
|
| 1208 |
|
|
#ifdef ZIPBONES
|
| 1209 |
|
|
else if (m_cursor >= 32)
|
| 1210 |
|
|
m_cursor = 31;
|
| 1211 |
|
|
#else
|
| 1212 |
|
|
else if (m_cursor >= 44)
|
| 1213 |
|
|
m_cursor = 43;
|
| 1214 |
|
|
#endif
|
| 1215 |
|
|
|
| 1216 |
|
|
mvprintw(ln,0, "Peripherals-RS");
|
| 1217 |
|
|
mvprintw(ln,40,"%-40s", "CPU State: ");
|
| 1218 |
|
|
{
|
| 1219 |
|
|
unsigned int v = wb_read(CMD_REG);
|
| 1220 |
|
|
mvprintw(ln,51, "");
|
| 1221 |
|
|
if (v & 0x010000)
|
| 1222 |
|
|
printw("EXT-INT ");
|
| 1223 |
|
|
if ((v & 0x003000) == 0x03000)
|
| 1224 |
|
|
printw("Halted ");
|
| 1225 |
|
|
else if (v & 0x001000)
|
| 1226 |
|
|
printw("Sleeping ");
|
| 1227 |
|
|
else if (v & 0x002000)
|
| 1228 |
|
|
printw("User Mod ");
|
| 1229 |
|
|
if (v & 0x008000)
|
| 1230 |
|
|
printw("Break-Enabled ");
|
| 1231 |
|
|
if (v & 0x000080)
|
| 1232 |
|
|
printw("PIC Enabled ");
|
| 1233 |
|
|
} ln++;
|
| 1234 |
|
|
#ifdef ZIPSYSTEM
|
| 1235 |
|
|
showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
|
| 1236 |
|
|
showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
|
| 1237 |
|
|
showval(ln,40, "WBUS", m_state.m_p[2], false);
|
| 1238 |
|
|
showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
|
| 1239 |
|
|
ln++;
|
| 1240 |
|
|
showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
|
| 1241 |
|
|
showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
|
| 1242 |
|
|
showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
|
| 1243 |
|
|
showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
|
| 1244 |
|
|
|
| 1245 |
|
|
ln++;
|
| 1246 |
|
|
if (!m_show_user_timers) {
|
| 1247 |
|
|
showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
|
| 1248 |
|
|
showval(ln,20, "MMST", m_state.m_p[13], (m_cursor==9));
|
| 1249 |
|
|
showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
|
| 1250 |
|
|
showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
|
| 1251 |
|
|
} else {
|
| 1252 |
|
|
showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
|
| 1253 |
|
|
showval(ln,20, "UMST", m_state.m_p[ 9], (m_cursor==9));
|
| 1254 |
|
|
showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
|
| 1255 |
|
|
showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
|
| 1256 |
|
|
}
|
| 1257 |
|
|
#else
|
| 1258 |
|
|
ln += 2;
|
| 1259 |
|
|
#endif
|
| 1260 |
|
|
|
| 1261 |
|
|
ln++;
|
| 1262 |
|
|
ln++;
|
| 1263 |
|
|
unsigned int cc = m_state.m_sR[14];
|
| 1264 |
|
|
if (m_dbgfp) fprintf(m_dbgfp, "CC = %08x, gie = %d\n", cc,
|
| 1265 |
|
|
m_core->r_gie);
|
| 1266 |
|
|
gie = (cc & 0x020);
|
| 1267 |
|
|
if (gie)
|
| 1268 |
|
|
attroff(A_BOLD);
|
| 1269 |
|
|
else
|
| 1270 |
|
|
attron(A_BOLD);
|
| 1271 |
|
|
mvprintw(ln, 0, "Supervisor Registers");
|
| 1272 |
|
|
ln++;
|
| 1273 |
|
|
|
| 1274 |
|
|
dispreg(ln, 0, "sR0 ", m_state.m_sR[ 0], (m_cursor==12));
|
| 1275 |
|
|
dispreg(ln,20, "sR1 ", m_state.m_sR[ 1], (m_cursor==13));
|
| 1276 |
|
|
dispreg(ln,40, "sR2 ", m_state.m_sR[ 2], (m_cursor==14));
|
| 1277 |
|
|
dispreg(ln,60, "sR3 ", m_state.m_sR[ 3], (m_cursor==15)); ln++;
|
| 1278 |
|
|
|
| 1279 |
|
|
dispreg(ln, 0, "sR4 ", m_state.m_sR[ 4], (m_cursor==16));
|
| 1280 |
|
|
dispreg(ln,20, "sR5 ", m_state.m_sR[ 5], (m_cursor==17));
|
| 1281 |
|
|
dispreg(ln,40, "sR6 ", m_state.m_sR[ 6], (m_cursor==18));
|
| 1282 |
|
|
dispreg(ln,60, "sR7 ", m_state.m_sR[ 7], (m_cursor==19)); ln++;
|
| 1283 |
|
|
|
| 1284 |
|
|
dispreg(ln, 0, "sR8 ", m_state.m_sR[ 8], (m_cursor==20));
|
| 1285 |
|
|
dispreg(ln,20, "sR9 ", m_state.m_sR[ 9], (m_cursor==21));
|
| 1286 |
|
|
dispreg(ln,40, "sR10", m_state.m_sR[10], (m_cursor==22));
|
| 1287 |
|
|
dispreg(ln,60, "sR11", m_state.m_sR[11], (m_cursor==23)); ln++;
|
| 1288 |
|
|
|
| 1289 |
|
|
dispreg(ln, 0, "sR12", m_state.m_sR[12], (m_cursor==24));
|
| 1290 |
|
|
dispreg(ln,20, "sSP ", m_state.m_sR[13], (m_cursor==25));
|
| 1291 |
|
|
|
| 1292 |
|
|
if (true) {
|
| 1293 |
|
|
mvprintw(ln,40, "%ssCC : 0x%08x",
|
| 1294 |
|
|
(m_cursor==26)?">":" ", cc);
|
| 1295 |
|
|
} else {
|
| 1296 |
|
|
char cbuf[32];
|
| 1297 |
|
|
sprintf(cbuf, "%ssCC :%s%s%s%s%s%s%s",
|
| 1298 |
|
|
(m_cursor==26)?">":" ",
|
| 1299 |
|
|
(cc&0x01000)?"FE":"",
|
| 1300 |
|
|
(cc&0x00800)?"DE":"",
|
| 1301 |
|
|
(cc&0x00400)?"BE":"",
|
| 1302 |
|
|
(cc&0x00200)?"TP":"",
|
| 1303 |
|
|
(cc&0x00100)?"IL":"",
|
| 1304 |
|
|
(cc&0x00080)?"BK":"",
|
| 1305 |
|
|
((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
|
| 1306 |
|
|
mvprintw(ln,40, "%-14s",cbuf);
|
| 1307 |
|
|
mvprintw(ln, 54, "%s%s%s%s",
|
| 1308 |
|
|
(cc&8)?"V":" ",
|
| 1309 |
|
|
(cc&4)?"N":" ",
|
| 1310 |
|
|
(cc&2)?"C":" ",
|
| 1311 |
|
|
(cc&1)?"Z":" ");
|
| 1312 |
|
|
}
|
| 1313 |
|
|
dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
|
| 1314 |
|
|
ln++;
|
| 1315 |
|
|
|
| 1316 |
|
|
if (gie)
|
| 1317 |
|
|
attron(A_BOLD);
|
| 1318 |
|
|
else
|
| 1319 |
|
|
attroff(A_BOLD);
|
| 1320 |
|
|
mvprintw(ln, 0, "User Registers");
|
| 1321 |
|
|
mvprintw(ln, 42, "DCDR=%02x %s",
|
| 1322 |
|
|
m_core->dcdR, (m_core->dcd_wR)?"W":" ");
|
| 1323 |
|
|
mvprintw(ln, 62, "OPR =%02x %s%s",
|
| 1324 |
|
|
m_core->op_R,
|
| 1325 |
|
|
(m_core->op_wR)?"W":" ",
|
| 1326 |
|
|
(m_core->op_wF)?"F":" ");
|
| 1327 |
|
|
ln++;
|
| 1328 |
|
|
dispreg(ln, 0, "uR0 ", m_state.m_uR[ 0], (m_cursor==28));
|
| 1329 |
|
|
dispreg(ln,20, "uR1 ", m_state.m_uR[ 1], (m_cursor==29));
|
| 1330 |
|
|
dispreg(ln,40, "uR2 ", m_state.m_uR[ 2], (m_cursor==30));
|
| 1331 |
|
|
dispreg(ln,60, "uR3 ", m_state.m_uR[ 3], (m_cursor==31)); ln++;
|
| 1332 |
|
|
|
| 1333 |
|
|
dispreg(ln, 0, "uR4 ", m_state.m_uR[ 4], (m_cursor==32));
|
| 1334 |
|
|
dispreg(ln,20, "uR5 ", m_state.m_uR[ 5], (m_cursor==33));
|
| 1335 |
|
|
dispreg(ln,40, "uR6 ", m_state.m_uR[ 6], (m_cursor==34));
|
| 1336 |
|
|
dispreg(ln,60, "uR7 ", m_state.m_uR[ 7], (m_cursor==35)); ln++;
|
| 1337 |
|
|
|
| 1338 |
|
|
dispreg(ln, 0, "uR8 ", m_state.m_uR[ 8], (m_cursor==36));
|
| 1339 |
|
|
dispreg(ln,20, "uR9 ", m_state.m_uR[ 9], (m_cursor==37));
|
| 1340 |
|
|
dispreg(ln,40, "uR10", m_state.m_uR[10], (m_cursor==38));
|
| 1341 |
|
|
dispreg(ln,60, "uR11", m_state.m_uR[11], (m_cursor==39)); ln++;
|
| 1342 |
|
|
|
| 1343 |
|
|
dispreg(ln, 0, "uR12", m_state.m_uR[12], (m_cursor==40));
|
| 1344 |
|
|
dispreg(ln,20, "uSP ", m_state.m_uR[13], (m_cursor==41));
|
| 1345 |
|
|
cc = m_state.m_uR[14];
|
| 1346 |
|
|
if (false) {
|
| 1347 |
|
|
mvprintw(ln,40, "%cuCC : 0x%08x",
|
| 1348 |
|
|
(m_cursor == 42)?'>':' ', cc);
|
| 1349 |
|
|
} else {
|
| 1350 |
|
|
char cbuf[32];
|
| 1351 |
|
|
sprintf(cbuf, "%cuCC :%s%s%s%s%s%s%s",
|
| 1352 |
|
|
(m_cursor == 42)?'>':' ',
|
| 1353 |
|
|
(cc & 0x1000)?"FE":"",
|
| 1354 |
|
|
(cc & 0x0800)?"DE":"",
|
| 1355 |
|
|
(cc & 0x0400)?"BE":"",
|
| 1356 |
|
|
(cc & 0x0200)?"TP":"",
|
| 1357 |
|
|
(cc & 0x0100)?"IL":"",
|
| 1358 |
|
|
(cc & 0x0040)?"ST":"",
|
| 1359 |
|
|
((m_state.m_gie)&&(cc & 0x010))?"SL":"");
|
| 1360 |
|
|
mvprintw(ln,40, "%-14s", cbuf);
|
| 1361 |
|
|
mvprintw(ln, 54, "%s%s%s%s",
|
| 1362 |
|
|
(cc&8)?"V":" ",
|
| 1363 |
|
|
(cc&4)?"N":" ",
|
| 1364 |
|
|
(cc&2)?"C":" ",
|
| 1365 |
|
|
(cc&1)?"Z":" ");
|
| 1366 |
|
|
}
|
| 1367 |
|
|
dispreg(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
|
| 1368 |
|
|
|
| 1369 |
|
|
attroff(A_BOLD);
|
| 1370 |
|
|
ln+=2;
|
| 1371 |
|
|
|
| 1372 |
|
|
ln+=3;
|
| 1373 |
|
|
|
| 1374 |
|
|
showins(ln, "I ",
|
| 1375 |
|
|
#ifdef OPT_PIPELINED
|
| 1376 |
|
|
!m_core->dcd_stalled,
|
| 1377 |
|
|
#else
|
| 1378 |
|
|
1,
|
| 1379 |
|
|
#endif
|
| 1380 |
|
|
m_core->pf_valid,
|
| 1381 |
|
|
m_core->r_gie,
|
| 1382 |
|
|
0,
|
| 1383 |
|
|
m_core->pf_instruction_pc,
|
| 1384 |
|
|
true); ln++;
|
| 1385 |
|
|
// m_core->pf_pc); ln++;
|
| 1386 |
|
|
|
| 1387 |
|
|
showins(ln, "Dc",
|
| 1388 |
|
|
m_core->dcd_ce, m_core->dcd_valid,
|
| 1389 |
|
|
m_core->dcd_gie,
|
| 1390 |
|
|
#ifdef OPT_PIPELINED
|
| 1391 |
|
|
m_core->dcd_stalled,
|
| 1392 |
|
|
#else
|
| 1393 |
|
|
0,
|
| 1394 |
|
|
#endif
|
| 1395 |
|
|
#ifdef OPT_CIS
|
| 1396 |
|
|
((m_core->dcd_phase) ?
|
| 1397 |
|
|
(m_core->dcd_pc+2):m_core->dcd_pc) -4,
|
| 1398 |
|
|
m_core->dcd_phase
|
| 1399 |
|
|
#else
|
| 1400 |
|
|
m_core->dcd_pc-4,
|
| 1401 |
|
|
false
|
| 1402 |
|
|
#endif
|
| 1403 |
|
|
); ln++;
|
| 1404 |
|
|
|
| 1405 |
|
|
showins(ln, "Op",
|
| 1406 |
|
|
m_core->op_ce,
|
| 1407 |
|
|
m_core->op_valid,
|
| 1408 |
|
|
m_core->op_gie,
|
| 1409 |
|
|
#ifdef OPT_PIPELINED
|
| 1410 |
|
|
m_core->op_stall,
|
| 1411 |
|
|
#else
|
| 1412 |
|
|
0,
|
| 1413 |
|
|
#endif
|
| 1414 |
|
|
#ifdef OPT_CIS
|
| 1415 |
|
|
op_pc()+((m_core->op_phase)?4:0),
|
| 1416 |
|
|
m_core->op_phase
|
| 1417 |
|
|
#else
|
| 1418 |
|
|
op_pc(),
|
| 1419 |
|
|
false
|
| 1420 |
|
|
#endif
|
| 1421 |
|
|
); ln++;
|
| 1422 |
|
|
|
| 1423 |
|
|
if (m_core->op_valid_mem) {
|
| 1424 |
|
|
showins(ln, "Mm",
|
| 1425 |
|
|
m_core->mem_ce,
|
| 1426 |
|
|
m_core->mem_pc_valid,
|
| 1427 |
|
|
m_core->alu_gie,
|
| 1428 |
|
|
#ifdef OPT_PIPELINED
|
| 1429 |
|
|
m_core->mem_stall,
|
| 1430 |
|
|
#else
|
| 1431 |
|
|
0,
|
| 1432 |
|
|
#endif
|
| 1433 |
|
|
alu_pc(),
|
| 1434 |
|
|
#ifdef OPT_CIS
|
| 1435 |
|
|
m_core->alu_phase
|
| 1436 |
|
|
#else
|
| 1437 |
|
|
false
|
| 1438 |
|
|
#endif
|
| 1439 |
|
|
);
|
| 1440 |
|
|
} else {
|
| 1441 |
|
|
showins(ln, "Al",
|
| 1442 |
|
|
m_core->alu_ce,
|
| 1443 |
|
|
m_core->alu_pc_valid,
|
| 1444 |
|
|
m_core->alu_gie,
|
| 1445 |
|
|
#ifdef OPT_PIPELINED
|
| 1446 |
|
|
alu_stall(),
|
| 1447 |
|
|
#else
|
| 1448 |
|
|
0,
|
| 1449 |
|
|
#endif
|
| 1450 |
|
|
alu_pc(),
|
| 1451 |
|
|
#ifdef OPT_CIS
|
| 1452 |
|
|
m_core->alu_phase
|
| 1453 |
|
|
#else
|
| 1454 |
|
|
false
|
| 1455 |
|
|
#endif
|
| 1456 |
|
|
);
|
| 1457 |
|
|
} ln++;
|
| 1458 |
|
|
}
|
| 1459 |
|
|
|
| 1460 |
|
|
void tick(void) {
|
| 1461 |
|
|
int gie = m_core->r_gie;
|
| 1462 |
|
|
/*
|
| 1463 |
|
|
m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
|
| 1464 |
|
|
m_core->o_qspi_sck,
|
| 1465 |
|
|
m_core->o_qspi_dat);
|
| 1466 |
|
|
*/
|
| 1467 |
|
|
|
| 1468 |
|
|
int stb = m_core->o_wb_stb, maskb = (RAMBASE-1);
|
| 1469 |
|
|
unsigned addr = m_core->o_wb_addr<<2;
|
| 1470 |
|
|
|
| 1471 |
|
|
m_core->i_wb_err = 0;
|
| 1472 |
|
|
if ((addr & (~maskb))!=RAMBASE)
|
| 1473 |
|
|
stb = 0;
|
| 1474 |
|
|
if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb)) {
|
| 1475 |
|
|
m_core->i_wb_ack = 1;
|
| 1476 |
|
|
m_core->i_wb_err = 1;
|
| 1477 |
|
|
m_bomb = (m_tickcount > 20);
|
| 1478 |
|
|
if (m_dbgfp) fprintf(m_dbgfp,
|
| 1479 |
|
|
"BOMB!! (Attempting to access %08x/%08x->%08x)\n",
|
| 1480 |
|
|
addr, RAMBASE, ((addr)&(~maskb)));
|
| 1481 |
|
|
} else if ((!m_core->o_wb_cyc)&&(m_core->o_wb_stb)) {
|
| 1482 |
|
|
if (m_dbgfp) fprintf(m_dbgfp,
|
| 1483 |
|
|
"BOMB!! (Strobe high, CYC low)\n");
|
| 1484 |
|
|
m_bomb = true;
|
| 1485 |
|
|
}
|
| 1486 |
|
|
|
| 1487 |
|
|
if ((dbg_flag)&&(m_dbgfp)) {
|
| 1488 |
|
|
fprintf(m_dbgfp, "BUS %s %s %s @0x%08x/[0x%08x 0x%08x] %s %s\n",
|
| 1489 |
|
|
(m_core->o_wb_cyc)?"CYC":" ",
|
| 1490 |
|
|
(m_core->o_wb_stb)?"STB":" ",
|
| 1491 |
|
|
(m_core->o_wb_we)?"WE":" ",
|
| 1492 |
|
|
(m_core->o_wb_addr<<2),
|
| 1493 |
|
|
(m_core->o_wb_data),
|
| 1494 |
|
|
(m_core->i_wb_data),
|
| 1495 |
|
|
(m_core->i_wb_stall)?"STALL":" ",
|
| 1496 |
|
|
(m_core->i_wb_ack)?"ACK":" ");
|
| 1497 |
|
|
fprintf(m_dbgfp, "DBG %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
|
| 1498 |
|
|
(m_core->i_dbg_cyc)?"CYC":" ",
|
| 1499 |
|
|
(m_core->i_dbg_stb)?"STB":
|
| 1500 |
|
|
((m_core->dbg_stb)?"DBG":" "),
|
| 1501 |
|
|
((m_core->i_dbg_we)?"WE":" "),
|
| 1502 |
|
|
(m_core->i_dbg_addr),0,
|
| 1503 |
|
|
m_core->i_dbg_data,
|
| 1504 |
|
|
(m_core->o_dbg_ack)?"ACK":" ",
|
| 1505 |
|
|
(m_core->o_dbg_stall)?"STALL":" ",
|
| 1506 |
|
|
(m_core->o_dbg_data),
|
| 1507 |
|
|
(m_core->cpu_halt)?"CPU-HALT ":"",
|
| 1508 |
|
|
(m_core->r_halted)?"CPU-DBG_STALL":"",
|
| 1509 |
|
|
(m_core->dcd_valid)?"DCDV ":"",
|
| 1510 |
|
|
(m_core->op_valid)?"OPV ":"",
|
| 1511 |
|
|
(m_core->pf_cyc)?"PCYC ":"",
|
| 1512 |
|
|
(m_core->r_wb_cyc_gbl)?"GC":" ",
|
| 1513 |
|
|
(m_core->r_wb_cyc_lcl)?"LC":" ",
|
| 1514 |
|
|
(m_core->alu_wR)?"ALUW ":"",
|
| 1515 |
|
|
(m_core->alu_ce)?"ALCE ":"",
|
| 1516 |
|
|
(m_core->alu_valid)?"ALUV ":"",
|
| 1517 |
|
|
(m_core->mem_valid)?"MEMV ":"");
|
| 1518 |
|
|
#ifdef ZIPSYSTEM
|
| 1519 |
|
|
fprintf(m_dbgfp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
|
| 1520 |
|
|
#define sys_cyc VVAR(_sys_cyc)
|
| 1521 |
|
|
#define sys_stb VVAR(_sys_stb)
|
| 1522 |
|
|
#define sys_we VVAR(_sys_we)
|
| 1523 |
|
|
#define sys_addr VVAR(_sys_addr)
|
| 1524 |
|
|
#define sys_data VVAR(_sys_data)
|
| 1525 |
|
|
#define dbg_ack VVAR(_dbg_ack)
|
| 1526 |
|
|
#define dbg_addr VVAR(_dbg_addr)
|
| 1527 |
|
|
(m_core->sys_cyc)?"CYC":" ",
|
| 1528 |
|
|
(m_core->sys_stb)?"STB":" ",
|
| 1529 |
|
|
(m_core->sys_we)?"WE":" ",
|
| 1530 |
|
|
(m_core->sys_addr<<2),
|
| 1531 |
|
|
(m_core->dbg_addr<<2),
|
| 1532 |
|
|
(m_core->sys_data),
|
| 1533 |
|
|
(m_core->dbg_ack)?"ACK":" ",
|
| 1534 |
|
|
(m_core->cpu_idata));
|
| 1535 |
|
|
#endif
|
| 1536 |
|
|
}
|
| 1537 |
|
|
|
| 1538 |
|
|
if (m_dbgfp)
|
| 1539 |
|
|
fprintf(m_dbgfp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d ce=%d, valid=%d, wr=%d Reg=%02x, IPC=%08x, UPC=%08x\n",
|
| 1540 |
|
|
m_core->dcd_ce,
|
| 1541 |
|
|
m_core->dcd_pc,
|
| 1542 |
|
|
m_core->op_ce,
|
| 1543 |
|
|
op_pc(),
|
| 1544 |
|
|
dcd_Aid()&0x01f,
|
| 1545 |
|
|
m_core->op_R,
|
| 1546 |
|
|
m_core->cpu_halt,
|
| 1547 |
|
|
m_core->alu_ce,
|
| 1548 |
|
|
m_core->alu_valid,
|
| 1549 |
|
|
m_core->alu_wR,
|
| 1550 |
|
|
m_core->alu_reg,
|
| 1551 |
|
|
m_core->cpu_ipc,
|
| 1552 |
|
|
m_core->cpu_upc);
|
| 1553 |
|
|
|
| 1554 |
|
|
if ((m_dbgfp)&&(!gie)&&(m_core->release_from_interrupt)) {
|
| 1555 |
|
|
fprintf(m_dbgfp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
|
| 1556 |
|
|
m_core->cpu_interrupt,
|
| 1557 |
|
|
m_core->wr_reg_ce,
|
| 1558 |
|
|
m_core->wr_reg_id,
|
| 1559 |
|
|
m_core->wr_spreg_vl,
|
| 1560 |
|
|
m_core->cmd_addr<<2,
|
| 1561 |
|
|
m_core->dbg_idata,
|
| 1562 |
|
|
m_core->master_ce,
|
| 1563 |
|
|
m_core->alu_wR,
|
| 1564 |
|
|
m_core->alu_valid,
|
| 1565 |
|
|
m_core->mem_valid);
|
| 1566 |
|
|
} else if ((m_dbgfp)&&(gie)&&(m_core->switch_to_interrupt)) {
|
| 1567 |
|
|
fprintf(m_dbgfp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
|
| 1568 |
|
|
m_core->wr_reg_ce,
|
| 1569 |
|
|
m_core->wr_reg_id,
|
| 1570 |
|
|
m_core->wr_spreg_vl,
|
| 1571 |
|
|
m_core->cmd_addr<<2,
|
| 1572 |
|
|
m_core->dbg_idata,
|
| 1573 |
|
|
m_core->master_ce,
|
| 1574 |
|
|
m_core->alu_wR,
|
| 1575 |
|
|
m_core->alu_valid,
|
| 1576 |
|
|
m_core->mem_valid,
|
| 1577 |
|
|
m_core->w_iflags,
|
| 1578 |
|
|
m_core->w_uflags);
|
| 1579 |
|
|
fprintf(m_dbgfp, "\tbrk=%s %d,%d\n",
|
| 1580 |
|
|
(m_core->master_ce)?"CE":" ",
|
| 1581 |
|
|
m_core->break_en,
|
| 1582 |
|
|
m_core->op_break);
|
| 1583 |
|
|
} else if ((m_dbgfp)&&
|
| 1584 |
|
|
((m_core->op_break)
|
| 1585 |
|
|
||(m_core->alu_illegal)
|
| 1586 |
|
|
||(m_core->dcd_break))) {
|
| 1587 |
|
|
fprintf(m_dbgfp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
|
| 1588 |
|
|
fprintf(m_dbgfp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d,alu_illegal=%d\n",
|
| 1589 |
|
|
(m_core->master_ce)?"CE":" ",
|
| 1590 |
|
|
m_core->break_en,
|
| 1591 |
|
|
m_core->dcd_break,
|
| 1592 |
|
|
m_core->op_break,
|
| 1593 |
|
|
m_core->alu_illegal);
|
| 1594 |
|
|
}
|
| 1595 |
|
|
|
| 1596 |
|
|
if (m_dbgfp) {
|
| 1597 |
|
|
// if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
|
| 1598 |
|
|
// fprintf(m_dbgfp, "\tClear Pipeline\n");
|
| 1599 |
|
|
if(m_core->new_pc)
|
| 1600 |
|
|
fprintf(m_dbgfp, "\tNew PC\n");
|
| 1601 |
|
|
}
|
| 1602 |
|
|
|
| 1603 |
|
|
if (m_dbgfp) {
|
| 1604 |
|
|
unsigned long v = m_tickcount;
|
| 1605 |
|
|
fprintf(m_dbgfp, "----------- TICK (%08lx) ----------%s\n",
|
| 1606 |
|
|
v, (m_bomb)?" BOMBED!!":"");
|
| 1607 |
|
|
}
|
| 1608 |
|
|
m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
|
| 1609 |
|
|
m_core->o_wb_addr & (maskb>>2), m_core->o_wb_data, m_core->o_wb_sel & 0x0f,
|
| 1610 |
|
|
m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
|
| 1611 |
|
|
|
| 1612 |
|
|
TESTB<SIMCLASS>::tick();
|
| 1613 |
|
|
|
| 1614 |
|
|
if ((m_core->cpu_sim)
|
| 1615 |
|
|
&&(m_core->op_valid)
|
| 1616 |
|
|
&&(m_core->alu_ce)
|
| 1617 |
|
|
&&(!m_core->new_pc)) {
|
| 1618 |
|
|
execsim(m_core->cpu_sim_immv);
|
| 1619 |
|
|
}
|
| 1620 |
|
|
|
| 1621 |
|
|
if ((m_dbgfp)&&(gie != m_core->r_gie)) {
|
| 1622 |
|
|
fprintf(m_dbgfp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
|
| 1623 |
|
|
(gie)?"User":"Supervisor",
|
| 1624 |
|
|
(gie)?"Supervisor":"User",
|
| 1625 |
|
|
m_core->cpu_ipc,
|
| 1626 |
|
|
m_core->cpu_upc,
|
| 1627 |
|
|
m_core->pf_pc);
|
| 1628 |
|
|
} if (m_dbgfp) {
|
| 1629 |
|
|
#ifdef OPT_TRADITIONAL_PFCACHE
|
| 1630 |
|
|
fprintf(m_dbgfp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s%s\n",
|
| 1631 |
|
|
(m_core->new_pc)?"N":" ",
|
| 1632 |
|
|
m_core->pf_pc,
|
| 1633 |
|
|
m_core->early_branch_pc,
|
| 1634 |
|
|
((m_core->early_branch)
|
| 1635 |
|
|
&&(m_core->dcd_valid)
|
| 1636 |
|
|
&&(!m_core->new_pc))?"V":"-",
|
| 1637 |
|
|
m_core->pf_lastpc,
|
| 1638 |
|
|
m_core->pf_instruction_pc,
|
| 1639 |
|
|
(m_core->pf_r_v)?"R":" ",
|
| 1640 |
|
|
(m_core->pf_valid)?"V":" ",
|
| 1641 |
|
|
(m_core->pf_illegal)?"I":" ");
|
| 1642 |
|
|
#endif
|
| 1643 |
|
|
dbgins("Dc - ",
|
| 1644 |
|
|
m_core->dcd_ce, m_core->dcd_valid,
|
| 1645 |
|
|
m_core->dcd_gie,
|
| 1646 |
|
|
#ifdef OPT_PIPELINED
|
| 1647 |
|
|
m_core->dcd_stalled,
|
| 1648 |
|
|
#else
|
| 1649 |
|
|
0,
|
| 1650 |
|
|
#endif
|
| 1651 |
|
|
#ifdef OPT_CIS
|
| 1652 |
|
|
(m_core->dcd_phase)?(m_core->dcd_pc-2)
|
| 1653 |
|
|
:(m_core->dcd_pc-4),
|
| 1654 |
|
|
m_core->dcd_phase,
|
| 1655 |
|
|
#else
|
| 1656 |
|
|
m_core->dcd_pc-4, false,
|
| 1657 |
|
|
#endif
|
| 1658 |
|
|
m_core->dcd_illegal);
|
| 1659 |
|
|
if (m_dbgfp) {
|
| 1660 |
|
|
fprintf(m_dbgfp, "\t\t\tR[%2d] = (*Dc=%d%s)[ A[%2d], B[%2d] + %08x], dcd_pc = %08x\n",
|
| 1661 |
|
|
m_core->dcdR,
|
| 1662 |
|
|
m_core->dcd_opn,
|
| 1663 |
|
|
(m_core->dcd_M)?"M":" ",
|
| 1664 |
|
|
#define dcd_I VVAR(_thecpu__DOT__dcd_I)
|
| 1665 |
|
|
m_core->dcdB &0x0f,
|
| 1666 |
|
|
m_core->dcdA &0x0f,
|
| 1667 |
|
|
m_core->dcd_I,
|
| 1668 |
|
|
m_core->dcd_pc);
|
| 1669 |
|
|
}
|
| 1670 |
|
|
dbgins("Op - ",
|
| 1671 |
|
|
m_core->op_ce,
|
| 1672 |
|
|
m_core->op_valid,
|
| 1673 |
|
|
m_core->op_gie,
|
| 1674 |
|
|
#ifdef OPT_PIPELINED
|
| 1675 |
|
|
m_core->op_stall,
|
| 1676 |
|
|
#else
|
| 1677 |
|
|
0,
|
| 1678 |
|
|
#endif
|
| 1679 |
|
|
op_pc(),
|
| 1680 |
|
|
#ifdef OPT_CIS
|
| 1681 |
|
|
m_core->op_phase,
|
| 1682 |
|
|
#else
|
| 1683 |
|
|
false,
|
| 1684 |
|
|
#endif
|
| 1685 |
|
|
m_core->op_illegal);
|
| 1686 |
|
|
if (m_dbgfp) {
|
| 1687 |
|
|
fprintf(m_dbgfp, "\t\t\t(*OP=%d)[ A = 0x%08x , B = 0x%08x ], op_pc= %08x\n",
|
| 1688 |
|
|
m_core->op_opn,
|
| 1689 |
|
|
m_core->op_Av,
|
| 1690 |
|
|
m_core->op_Bv,
|
| 1691 |
|
|
m_core->r_op_pc);
|
| 1692 |
|
|
}
|
| 1693 |
|
|
dbgins("Al - ",
|
| 1694 |
|
|
m_core->alu_ce,
|
| 1695 |
|
|
m_core->alu_pc_valid,
|
| 1696 |
|
|
m_core->alu_gie,
|
| 1697 |
|
|
#ifdef OPT_PIPELINED
|
| 1698 |
|
|
alu_stall(),
|
| 1699 |
|
|
#else
|
| 1700 |
|
|
0,
|
| 1701 |
|
|
#endif
|
| 1702 |
|
|
alu_pc(),
|
| 1703 |
|
|
#ifdef OPT_CIS
|
| 1704 |
|
|
m_core->alu_phase,
|
| 1705 |
|
|
#else
|
| 1706 |
|
|
false,
|
| 1707 |
|
|
#endif
|
| 1708 |
|
|
m_core->alu_illegal);
|
| 1709 |
|
|
if (m_core->wr_reg_ce)
|
| 1710 |
|
|
fprintf(m_dbgfp, "WB::Reg[%2x] <= %08x\n",
|
| 1711 |
|
|
m_core->wr_reg_id,
|
| 1712 |
|
|
m_core->wr_gpreg_vl);
|
| 1713 |
|
|
if (m_core->wr_flags_ce)
|
| 1714 |
|
|
fprintf(m_dbgfp, "WB::Flags <= %02x\n",
|
| 1715 |
|
|
m_core->alu_flags);
|
| 1716 |
|
|
|
| 1717 |
|
|
}
|
| 1718 |
|
|
|
| 1719 |
|
|
#ifdef OPT_DIVIDE
|
| 1720 |
|
|
if ((m_dbgfp)&&((m_core->div_valid)
|
| 1721 |
|
|
||(m_core->div_ce)
|
| 1722 |
|
|
||(m_core->div_busy)
|
| 1723 |
|
|
)) {
|
| 1724 |
|
|
fprintf(m_dbgfp, "DIV: %s %s %s %s[%2x] GP:%08x/SP:%08x %s:0x%08x\n",
|
| 1725 |
|
|
(m_core->div_ce)?"CE":" ",
|
| 1726 |
|
|
(m_core->div_busy)?"BUSY":" ",
|
| 1727 |
|
|
(m_core->div_valid)?"VALID":" ",
|
| 1728 |
|
|
(m_core->wr_reg_ce)?"REG-CE":" ",
|
| 1729 |
|
|
m_core->wr_reg_id,
|
| 1730 |
|
|
m_core->wr_gpreg_vl,
|
| 1731 |
|
|
m_core->wr_spreg_vl,
|
| 1732 |
|
|
(m_core->alu_pc_valid)?"PCV":" ",
|
| 1733 |
|
|
alu_pc());
|
| 1734 |
|
|
|
| 1735 |
|
|
fprintf(m_dbgfp, "ALU-PC: %08x %s %s\n",
|
| 1736 |
|
|
alu_pc(),
|
| 1737 |
|
|
(m_core->alu_pc_valid)?"VALID":"",
|
| 1738 |
|
|
(m_core->alu_gie)?"ALU-GIE":"");
|
| 1739 |
|
|
}
|
| 1740 |
|
|
#endif
|
| 1741 |
|
|
|
| 1742 |
|
|
#ifdef ZIPSYSTEM
|
| 1743 |
|
|
#define dma_state VVAR(_dma_controller__DOT__dma_state)
|
| 1744 |
|
|
#define dc_cyc VVAR(_dc_cyc)
|
| 1745 |
|
|
#define dc_stb VVAR(_dc_stb)
|
| 1746 |
|
|
#define dc_ack VVAR(_dc_ack)
|
| 1747 |
|
|
#define dc_err VVAR(_dc_err)
|
| 1748 |
|
|
#define dc_addr VVAR(_dc_addr)
|
| 1749 |
|
|
#define dc_data VVAR(_dc_data)
|
| 1750 |
|
|
#define dma_last_read_req VVAR(_dma_controller__DOT__last_read_request)
|
| 1751 |
|
|
#define dma_last_read_ack VVAR(_dma_controller__DOT__last_read_ack)
|
| 1752 |
|
|
#define dma_nracks VVAR(_dma_controller__DOT__nracks)
|
| 1753 |
|
|
#define dma_nread VVAR(_dma_controller__DOT__nread)
|
| 1754 |
|
|
#define dma_last_write_req VVAR(_dma_controller__DOT__last_write_request)
|
| 1755 |
|
|
#define dma_last_write_ack VVAR(_dma_controller__DOT__last_write_ack)
|
| 1756 |
|
|
#define dma_nwacks VVAR(_dma_controller__DOT__nwacks)
|
| 1757 |
|
|
#define dma_nwritten VVAR(_dma_controller__DOT__nwritten)
|
| 1758 |
|
|
if (m_core->dma_state) {
|
| 1759 |
|
|
fprintf(m_dbgfp, "DMA[%d]%s%s%s%s@%08x,%08x [%d%d/%4d/%4d] -> [%d%d/%04d/%04d]\n",
|
| 1760 |
|
|
m_core->dma_state,
|
| 1761 |
|
|
(m_core->dc_cyc)?"C":" ",
|
| 1762 |
|
|
(m_core->dc_stb)?"S":" ",
|
| 1763 |
|
|
(m_core->dc_ack)?"A":" ",
|
| 1764 |
|
|
(m_core->dc_err)?"E":" ",
|
| 1765 |
|
|
m_core->dc_addr<<2,
|
| 1766 |
|
|
(m_core->dc_data),
|
| 1767 |
|
|
m_core->dma_last_read_req,
|
| 1768 |
|
|
m_core->dma_last_read_ack,
|
| 1769 |
|
|
m_core->dma_nracks,
|
| 1770 |
|
|
m_core->dma_nread,
|
| 1771 |
|
|
m_core->dma_last_write_req,
|
| 1772 |
|
|
m_core->dma_last_write_ack,
|
| 1773 |
|
|
m_core->dma_nwacks,
|
| 1774 |
|
|
m_core->dma_nwritten);
|
| 1775 |
|
|
}
|
| 1776 |
|
|
#endif
|
| 1777 |
|
|
if (((m_core->alu_pc_valid)
|
| 1778 |
|
|
||(m_core->mem_pc_valid))
|
| 1779 |
|
|
&&(!m_core->new_pc)) {
|
| 1780 |
|
|
unsigned long iticks = m_tickcount - m_last_instruction_tickcount;
|
| 1781 |
|
|
if (m_profile_fp) {
|
| 1782 |
|
|
unsigned buf[2];
|
| 1783 |
|
|
buf[0] = alu_pc();
|
| 1784 |
|
|
buf[1] = iticks;
|
| 1785 |
|
|
fwrite(buf, sizeof(unsigned), 2, m_profile_fp);
|
| 1786 |
|
|
}
|
| 1787 |
|
|
m_last_instruction_tickcount = m_tickcount;
|
| 1788 |
|
|
}
|
| 1789 |
|
|
}
|
| 1790 |
|
|
|
| 1791 |
|
|
bool test_success(void) {
|
| 1792 |
|
|
if ((m_exit)&&(m_rcode == 0))
|
| 1793 |
|
|
return true;
|
| 1794 |
|
|
return ((!m_core->r_gie)
|
| 1795 |
|
|
&&(m_core->r_sleep));
|
| 1796 |
|
|
}
|
| 1797 |
|
|
|
| 1798 |
|
|
unsigned op_pc(void) {
|
| 1799 |
|
|
return m_core->r_op_pc-4;
|
| 1800 |
|
|
}
|
| 1801 |
|
|
|
| 1802 |
|
|
bool pfstall(void) {
|
| 1803 |
|
|
return((!(m_core->pformem_owner))
|
| 1804 |
|
|
||(m_core->cpu_stall));
|
| 1805 |
|
|
}
|
| 1806 |
|
|
unsigned dcd_Aid(void) {
|
| 1807 |
|
|
return (m_core->dcdA);
|
| 1808 |
|
|
}
|
| 1809 |
|
|
unsigned dcd_Bid(void) {
|
| 1810 |
|
|
return (m_core->dcdB);
|
| 1811 |
|
|
}
|
| 1812 |
|
|
|
| 1813 |
|
|
bool op_valid(void) {
|
| 1814 |
|
|
return (m_core->op_valid !=0);
|
| 1815 |
|
|
}
|
| 1816 |
|
|
|
| 1817 |
|
|
bool mem_busy(void) {
|
| 1818 |
|
|
// return m_core->v__DOT__thecpu__DOT__mem_busy;
|
| 1819 |
|
|
#ifdef OPT_PIPELINED
|
| 1820 |
|
|
return m_core->mem_cyc;
|
| 1821 |
|
|
#else
|
| 1822 |
|
|
return 0;
|
| 1823 |
|
|
#endif
|
| 1824 |
|
|
}
|
| 1825 |
|
|
|
| 1826 |
|
|
bool mem_stalled(void) {
|
| 1827 |
|
|
bool a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
|
| 1828 |
|
|
|
| 1829 |
|
|
wr_write_cc=((m_core->wr_reg_id&0x0f)==0x0e);
|
| 1830 |
|
|
wr_write_pc=((m_core->wr_reg_id&0x0f)==0x0f);
|
| 1831 |
|
|
op_gie = m_core->op_gie;
|
| 1832 |
|
|
|
| 1833 |
|
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
| 1834 |
|
|
//a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
|
| 1835 |
|
|
a = mem_pipe_stalled();
|
| 1836 |
|
|
b = (!m_core->op_pipe)&&(mem_busy());
|
| 1837 |
|
|
#else
|
| 1838 |
|
|
a = false;
|
| 1839 |
|
|
b = false;
|
| 1840 |
|
|
#endif
|
| 1841 |
|
|
d = ((wr_write_pc)||(wr_write_cc));
|
| 1842 |
|
|
c = ((m_core->wr_reg_ce)
|
| 1843 |
|
|
&&(((m_core->wr_reg_id&0x010)?true:false)==op_gie)
|
| 1844 |
|
|
&&d);
|
| 1845 |
|
|
d =(m_core->op_valid_mem)&&((a)||(b)||(c));
|
| 1846 |
|
|
return ((!m_core->master_ce)||(d));
|
| 1847 |
|
|
}
|
| 1848 |
|
|
|
| 1849 |
|
|
unsigned alu_pc(void) {
|
| 1850 |
|
|
/*
|
| 1851 |
|
|
unsigned r = op_pc();
|
| 1852 |
|
|
if (m_core->op_valid)
|
| 1853 |
|
|
r--;
|
| 1854 |
|
|
return r;
|
| 1855 |
|
|
*/
|
| 1856 |
|
|
return m_core->alu_pc-4;
|
| 1857 |
|
|
}
|
| 1858 |
|
|
|
| 1859 |
|
|
int alu_stall(void) {
|
| 1860 |
|
|
bool stall;
|
| 1861 |
|
|
#ifdef OP_PIPELINED
|
| 1862 |
|
|
stall = (m_core->master_stall)||(m_core->mem_rdbusy);
|
| 1863 |
|
|
stall = (stall)&& m_core->op_valid_alu;
|
| 1864 |
|
|
stall = (stall)|| ((m_core->wr_reg_ce)&&(m_core->wr_write_cc));
|
| 1865 |
|
|
#else
|
| 1866 |
|
|
stall = (m_core->master_stall)&&(m_core->op_valid_alu);
|
| 1867 |
|
|
#endif
|
| 1868 |
|
|
/*
|
| 1869 |
|
|
unsigned r = op_pc();
|
| 1870 |
|
|
if (m_core->op_valid)
|
| 1871 |
|
|
r--;
|
| 1872 |
|
|
return r;
|
| 1873 |
|
|
*/
|
| 1874 |
|
|
return (stall)?1:0;
|
| 1875 |
|
|
}
|
| 1876 |
|
|
|
| 1877 |
|
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
| 1878 |
|
|
bool mem_pipe_stalled(void) {
|
| 1879 |
|
|
int r = 0;
|
| 1880 |
|
|
r = ((m_core->r_wb_cyc_gbl)
|
| 1881 |
|
|
||(m_core->r_wb_cyc_lcl));
|
| 1882 |
|
|
r = r && ((m_core->mem_stall)
|
| 1883 |
|
|
||(
|
| 1884 |
|
|
((!m_core->mem_stb_gbl)
|
| 1885 |
|
|
&&(!m_core->mem_stb_lcl))));
|
| 1886 |
|
|
return r;
|
| 1887 |
|
|
// return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
|
| 1888 |
|
|
}
|
| 1889 |
|
|
#endif
|
| 1890 |
|
|
|
| 1891 |
|
|
bool test_failure(void) {
|
| 1892 |
|
|
if ((m_exit)&&(m_rcode != 0))
|
| 1893 |
|
|
return true;
|
| 1894 |
|
|
if (m_core->r_sleep)
|
| 1895 |
|
|
return false;
|
| 1896 |
|
|
return false;
|
| 1897 |
|
|
}
|
| 1898 |
|
|
|
| 1899 |
|
|
void wb_write(unsigned a, unsigned int v) {
|
| 1900 |
|
|
int errcount = 0;
|
| 1901 |
|
|
mvprintw(0,35, "%40s", "");
|
| 1902 |
|
|
mvprintw(0,40, "wb_write(%d,%x)", a, v);
|
| 1903 |
|
|
m_core->i_dbg_cyc = 1;
|
| 1904 |
|
|
m_core->i_dbg_stb = 1;
|
| 1905 |
|
|
m_core->i_dbg_we = 1;
|
| 1906 |
|
|
m_core->i_dbg_addr = (a>>2) & 1;
|
| 1907 |
|
|
m_core->i_dbg_data = v;
|
| 1908 |
|
|
|
| 1909 |
|
|
while((errcount++ < 100)&&(m_core->o_dbg_stall))
|
| 1910 |
|
|
tick();
|
| 1911 |
|
|
tick();
|
| 1912 |
|
|
|
| 1913 |
|
|
m_core->i_dbg_stb = 0;
|
| 1914 |
|
|
while((errcount++ < 100)&&(!m_core->o_dbg_ack))
|
| 1915 |
|
|
tick();
|
| 1916 |
|
|
|
| 1917 |
|
|
// Release the bus
|
| 1918 |
|
|
m_core->i_dbg_cyc = 0;
|
| 1919 |
|
|
m_core->i_dbg_stb = 0;
|
| 1920 |
|
|
tick();
|
| 1921 |
|
|
mvprintw(0,35, "%40s", "");
|
| 1922 |
|
|
mvprintw(0,40, "wb_write -- complete");
|
| 1923 |
|
|
|
| 1924 |
|
|
|
| 1925 |
|
|
if (errcount >= 100) {
|
| 1926 |
|
|
if (m_dbgfp) fprintf(m_dbgfp, "WB-WRITE: ERRCount = %d, BOMB!!\n", errcount);
|
| 1927 |
|
|
m_bomb = true;
|
| 1928 |
|
|
}
|
| 1929 |
|
|
}
|
| 1930 |
|
|
|
| 1931 |
|
|
unsigned long wb_read(unsigned a) {
|
| 1932 |
|
|
unsigned int v;
|
| 1933 |
|
|
int errcount = 0;
|
| 1934 |
|
|
mvprintw(0,35, "%40s", "");
|
| 1935 |
|
|
mvprintw(0,40, "wb_read(0x%08x)", a);
|
| 1936 |
|
|
m_core->i_dbg_cyc = 1;
|
| 1937 |
|
|
m_core->i_dbg_stb = 1;
|
| 1938 |
|
|
m_core->i_dbg_we = 0;
|
| 1939 |
|
|
m_core->i_dbg_addr = (a>>2) & 1;
|
| 1940 |
|
|
|
| 1941 |
|
|
while((errcount++<100)&&(m_core->o_dbg_stall))
|
| 1942 |
|
|
tick();
|
| 1943 |
|
|
tick();
|
| 1944 |
|
|
|
| 1945 |
|
|
m_core->i_dbg_stb = 0;
|
| 1946 |
|
|
while((errcount++<100)&&(!m_core->o_dbg_ack))
|
| 1947 |
|
|
tick();
|
| 1948 |
|
|
v = m_core->o_dbg_data;
|
| 1949 |
|
|
|
| 1950 |
|
|
// Release the bus
|
| 1951 |
|
|
m_core->i_dbg_cyc = 0;
|
| 1952 |
|
|
m_core->i_dbg_stb = 0;
|
| 1953 |
|
|
tick();
|
| 1954 |
|
|
|
| 1955 |
|
|
mvprintw(0,35, "%40s", "");
|
| 1956 |
|
|
mvprintw(0,40, "wb_read = 0x%08x", v);
|
| 1957 |
|
|
|
| 1958 |
|
|
if (errcount >= 100) {
|
| 1959 |
|
|
if (m_dbgfp) fprintf(m_dbgfp, "WB-READ: ERRCount = %d, BOMB!!\n", errcount);
|
| 1960 |
|
|
m_bomb = true;
|
| 1961 |
|
|
}
|
| 1962 |
|
|
return v;
|
| 1963 |
|
|
}
|
| 1964 |
|
|
|
| 1965 |
|
|
void cursor_up(void) {
|
| 1966 |
|
|
#ifdef ZIPSYSTEM
|
| 1967 |
|
|
if (m_cursor > 3)
|
| 1968 |
|
|
m_cursor -= 4;
|
| 1969 |
|
|
#else
|
| 1970 |
|
|
if (m_cursor > 12+3)
|
| 1971 |
|
|
m_cursor =- 4;
|
| 1972 |
|
|
#endif
|
| 1973 |
|
|
} void cursor_down(void) {
|
| 1974 |
|
|
if (m_cursor < 40)
|
| 1975 |
|
|
m_cursor += 4;
|
| 1976 |
|
|
} void cursor_left(void) {
|
| 1977 |
|
|
#ifdef ZIPSYSTEM
|
| 1978 |
|
|
if (m_cursor > 0)
|
| 1979 |
|
|
m_cursor--;
|
| 1980 |
|
|
#else
|
| 1981 |
|
|
if (m_cursor > 12)
|
| 1982 |
|
|
m_cursor--;
|
| 1983 |
|
|
#endif
|
| 1984 |
|
|
else m_cursor = 43;
|
| 1985 |
|
|
} void cursor_right(void) {
|
| 1986 |
|
|
#ifdef ZIPSYSTEM
|
| 1987 |
|
|
if (m_cursor < 43)
|
| 1988 |
|
|
m_cursor++;
|
| 1989 |
|
|
else m_cursor = 0;
|
| 1990 |
|
|
#else
|
| 1991 |
|
|
if (m_cursor < 43)
|
| 1992 |
|
|
m_cursor++;
|
| 1993 |
|
|
else m_cursor = 12;
|
| 1994 |
|
|
#endif
|
| 1995 |
|
|
}
|
| 1996 |
|
|
|
| 1997 |
|
|
int cursor(void) { return m_cursor; }
|
| 1998 |
|
|
|
| 1999 |
|
|
void jump_to(ZIPI address) {
|
| 2000 |
|
|
if (m_dbgfp)
|
| 2001 |
|
|
fprintf(m_dbgfp, "JUMP_TO(%08x) ... Setting PC to %08x\n", address, address & -4);
|
| 2002 |
|
|
#ifdef OPT_SINGLE_FETCH
|
| 2003 |
|
|
m_core->new_pc = 1;
|
| 2004 |
|
|
m_core->pf_pc = address;
|
| 2005 |
|
|
#else
|
| 2006 |
|
|
m_core->pf_pc = address & -4;
|
| 2007 |
|
|
#define pf_request_address VVAR(_thecpu__DOT__pf_request_address)
|
| 2008 |
|
|
m_core->pf_request_address = address;
|
| 2009 |
|
|
#endif
|
| 2010 |
|
|
// m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
|
| 2011 |
|
|
m_core->new_pc = 1;
|
| 2012 |
|
|
}
|
| 2013 |
|
|
|
| 2014 |
|
|
void dump_state(void) {
|
| 2015 |
|
|
if (m_dbgfp)
|
| 2016 |
|
|
dump_state(m_dbgfp);
|
| 2017 |
|
|
}
|
| 2018 |
|
|
|
| 2019 |
|
|
void dump_state(FILE *fp) {
|
| 2020 |
|
|
if (!fp)
|
| 2021 |
|
|
return;
|
| 2022 |
|
|
fprintf(fp, "FINAL STATE: %s\n",
|
| 2023 |
|
|
(m_state.m_gie)?"GIE(User-Mode)":"Supervisor-mode");
|
| 2024 |
|
|
fprintf(fp, "Supervisor Registers\n");
|
| 2025 |
|
|
for(int i=0; i<16; i++) {
|
| 2026 |
|
|
char str[16];
|
| 2027 |
|
|
if (i==13)
|
| 2028 |
|
|
sprintf(str, "sSP");
|
| 2029 |
|
|
else if (i==14)
|
| 2030 |
|
|
sprintf(str, "sCC");
|
| 2031 |
|
|
else if (i==15)
|
| 2032 |
|
|
sprintf(str, "sPC");
|
| 2033 |
|
|
else // if (i<=12)
|
| 2034 |
|
|
sprintf(str, "s-%2d", i);
|
| 2035 |
|
|
dbgreg(fp, i, str, m_state.m_sR[i]);
|
| 2036 |
|
|
if ((i&3)==3)
|
| 2037 |
|
|
fprintf(fp, "\n");
|
| 2038 |
|
|
}
|
| 2039 |
|
|
fprintf(fp, "User Registers\n");
|
| 2040 |
|
|
for(int i=0; i<16; i++) {
|
| 2041 |
|
|
char str[16];
|
| 2042 |
|
|
if (i==13)
|
| 2043 |
|
|
sprintf(str, "uSP");
|
| 2044 |
|
|
else if (i==14)
|
| 2045 |
|
|
sprintf(str, "uCC");
|
| 2046 |
|
|
else if (i==15)
|
| 2047 |
|
|
sprintf(str, "uPC");
|
| 2048 |
|
|
else // if (i<=12)
|
| 2049 |
|
|
sprintf(str, "u-%2d", i);
|
| 2050 |
|
|
dbgreg(fp, i, str, m_state.m_uR[i]);
|
| 2051 |
|
|
if ((i&3)==3)
|
| 2052 |
|
|
fprintf(fp, "\n");
|
| 2053 |
|
|
}
|
| 2054 |
|
|
}
|
| 2055 |
|
|
|
| 2056 |
|
|
void dump(const uint32_t *regp) {
|
| 2057 |
|
|
uint32_t uccv, iccv;
|
| 2058 |
|
|
|
| 2059 |
|
|
if (!m_console)
|
| 2060 |
|
|
return;
|
| 2061 |
|
|
|
| 2062 |
|
|
fflush(stderr);
|
| 2063 |
|
|
fflush(stdout);
|
| 2064 |
|
|
printf("ZIPM--DUMP: ");
|
| 2065 |
|
|
if (m_core->r_gie)
|
| 2066 |
|
|
printf("Interrupts-enabled\n");
|
| 2067 |
|
|
else
|
| 2068 |
|
|
printf("Supervisor mode\n");
|
| 2069 |
|
|
printf("\n");
|
| 2070 |
|
|
|
| 2071 |
|
|
iccv = m_core->w_iflags;
|
| 2072 |
|
|
uccv = m_core->w_uflags;
|
| 2073 |
|
|
|
| 2074 |
|
|
printf("sR0 : %08x ", regp[0]);
|
| 2075 |
|
|
printf("sR1 : %08x ", regp[1]);
|
| 2076 |
|
|
printf("sR2 : %08x ", regp[2]);
|
| 2077 |
|
|
printf("sR3 : %08x\n",regp[3]);
|
| 2078 |
|
|
printf("sR4 : %08x ", regp[4]);
|
| 2079 |
|
|
printf("sR5 : %08x ", regp[5]);
|
| 2080 |
|
|
printf("sR6 : %08x ", regp[6]);
|
| 2081 |
|
|
printf("sR7 : %08x\n",regp[7]);
|
| 2082 |
|
|
printf("sR8 : %08x ", regp[8]);
|
| 2083 |
|
|
printf("sR9 : %08x ", regp[9]);
|
| 2084 |
|
|
printf("sR10: %08x ", regp[10]);
|
| 2085 |
|
|
printf("sR11: %08x\n",regp[11]);
|
| 2086 |
|
|
printf("sR12: %08x ", regp[12]);
|
| 2087 |
|
|
printf("sSP : %08x ", regp[13]);
|
| 2088 |
|
|
printf("sCC : %08x ", iccv);
|
| 2089 |
|
|
printf("sPC : %08x\n",regp[15]);
|
| 2090 |
|
|
|
| 2091 |
|
|
printf("\n");
|
| 2092 |
|
|
|
| 2093 |
|
|
printf("uR0 : %08x ", regp[16]);
|
| 2094 |
|
|
printf("uR1 : %08x ", regp[17]);
|
| 2095 |
|
|
printf("uR2 : %08x ", regp[18]);
|
| 2096 |
|
|
printf("uR3 : %08x\n",regp[19]);
|
| 2097 |
|
|
printf("uR4 : %08x ", regp[20]);
|
| 2098 |
|
|
printf("uR5 : %08x ", regp[21]);
|
| 2099 |
|
|
printf("uR6 : %08x ", regp[22]);
|
| 2100 |
|
|
printf("uR7 : %08x\n",regp[23]);
|
| 2101 |
|
|
printf("uR8 : %08x ", regp[24]);
|
| 2102 |
|
|
printf("uR9 : %08x ", regp[25]);
|
| 2103 |
|
|
printf("uR10: %08x ", regp[26]);
|
| 2104 |
|
|
printf("uR11: %08x\n",regp[27]);
|
| 2105 |
|
|
printf("uR12: %08x ", regp[28]);
|
| 2106 |
|
|
printf("uSP : %08x ", regp[29]);
|
| 2107 |
|
|
printf("uCC : %08x ", uccv);
|
| 2108 |
|
|
printf("uPC : %08x\n",regp[31]);
|
| 2109 |
|
|
printf("\n");
|
| 2110 |
|
|
fflush(stderr);
|
| 2111 |
|
|
fflush(stdout);
|
| 2112 |
|
|
}
|
| 2113 |
|
|
|
| 2114 |
|
|
|
| 2115 |
|
|
void execsim(const uint32_t imm) {
|
| 2116 |
|
|
uint32_t *regp = m_core->cpu_regs;
|
| 2117 |
|
|
int rbase;
|
| 2118 |
|
|
rbase = (m_core->r_gie)?16:0;
|
| 2119 |
|
|
|
| 2120 |
|
|
fflush(stdout);
|
| 2121 |
|
|
if ((imm & 0x03fffff)==0)
|
| 2122 |
|
|
// Ignore a NOOP
|
| 2123 |
|
|
return;
|
| 2124 |
|
|
// fprintf(stderr, "SIM-INSN(0x%08x)\n", imm);
|
| 2125 |
|
|
if ((imm & 0x0fffff)==0x00100) {
|
| 2126 |
|
|
// SIM Exit(0)
|
| 2127 |
|
|
m_rcode = 0;
|
| 2128 |
|
|
m_exit = true;
|
| 2129 |
|
|
} else if ((imm & 0x0ffff0)==0x00310) {
|
| 2130 |
|
|
// SIM Exit(User-Reg)
|
| 2131 |
|
|
int rcode;
|
| 2132 |
|
|
rcode = regp[(imm&0x0f)+16] & 0x0ff;
|
| 2133 |
|
|
m_rcode = rcode;
|
| 2134 |
|
|
m_exit = true;
|
| 2135 |
|
|
} else if ((imm & 0x0ffff0)==0x00300) {
|
| 2136 |
|
|
// SIM Exit(Reg)
|
| 2137 |
|
|
int rcode;
|
| 2138 |
|
|
rcode = regp[(imm&0x0f)+rbase] & 0x0ff;
|
| 2139 |
|
|
m_rcode = rcode;
|
| 2140 |
|
|
m_exit = true;
|
| 2141 |
|
|
} else if ((imm & 0x0fff00)==0x00100) {
|
| 2142 |
|
|
// SIM Exit(Imm)
|
| 2143 |
|
|
int rcode;
|
| 2144 |
|
|
rcode = imm & 0x0ff;
|
| 2145 |
|
|
m_exit = true;
|
| 2146 |
|
|
m_rcode = rcode;
|
| 2147 |
|
|
} else if ((imm & 0x0fffff)==0x002ff) {
|
| 2148 |
|
|
// Full/unconditional dump
|
| 2149 |
|
|
if (m_console) {
|
| 2150 |
|
|
printf("SIM-DUMP\n");
|
| 2151 |
|
|
dump(regp);
|
| 2152 |
|
|
}
|
| 2153 |
|
|
} else if ((imm & 0x0ffff0)==0x00200) {
|
| 2154 |
|
|
// Dump a register
|
| 2155 |
|
|
if (m_console) {
|
| 2156 |
|
|
int rid = (imm&0x0f)+rbase;
|
| 2157 |
|
|
//printf("%8lu @%08x R[%2d] = 0x%08x\n",
|
| 2158 |
|
|
// m_time_ps/1000,
|
| 2159 |
|
|
// m_core->cpu_ipc, rid, regp[rid]);
|
| 2160 |
|
|
printf("R[%2d] = 0x%08x\n", rid&0x0f,regp[rid]);
|
| 2161 |
|
|
}
|
| 2162 |
|
|
} else if ((imm & 0x0ffff0)==0x00210) {
|
| 2163 |
|
|
// Dump a user register
|
| 2164 |
|
|
if (m_console) {
|
| 2165 |
|
|
int rid = (imm&0x0f);
|
| 2166 |
|
|
/*
|
| 2167 |
|
|
printf("%8lu @%08x uR[%2d] = 0x%08x\n",
|
| 2168 |
|
|
m_time_ps/1000, m_core->cpu_ipc,
|
| 2169 |
|
|
rid, regp[rid+16]);
|
| 2170 |
|
|
*/
|
| 2171 |
|
|
printf("uR[%2d] = 0x%08x\n",
|
| 2172 |
|
|
rid, regp[rid+16]);
|
| 2173 |
|
|
}
|
| 2174 |
|
|
} else if ((imm & 0x0ffff0)==0x00230) {
|
| 2175 |
|
|
// SOUT[User Reg]
|
| 2176 |
|
|
if (m_console) {
|
| 2177 |
|
|
int rid = (imm&0x0f)+16;
|
| 2178 |
|
|
printf("%c", regp[rid]&0x0ff);
|
| 2179 |
|
|
}
|
| 2180 |
|
|
} else if ((imm & 0x0fffe0)==0x00220) {
|
| 2181 |
|
|
// SOUT[User Reg]
|
| 2182 |
|
|
if (m_console) {
|
| 2183 |
|
|
int rid = (imm&0x0f)+rbase;
|
| 2184 |
|
|
printf("%c", regp[rid]&0x0ff);
|
| 2185 |
|
|
}
|
| 2186 |
|
|
} else if ((imm & 0x0fff00)==0x00400) {
|
| 2187 |
|
|
if (m_console) {
|
| 2188 |
|
|
// SOUT[Imm]
|
| 2189 |
|
|
printf("%c", imm&0x0ff);
|
| 2190 |
|
|
}
|
| 2191 |
|
|
} else { // if ((insn & 0x0f7c00000)==0x77800000)
|
| 2192 |
|
|
if (m_console) {
|
| 2193 |
|
|
uint32_t immv = imm & 0x03fffff;
|
| 2194 |
|
|
// Simm instruction that we dont recognize
|
| 2195 |
|
|
// if (imm)
|
| 2196 |
|
|
// printf("SIM 0x%08x\n", immv);
|
| 2197 |
|
|
printf("SIM 0x%08x (ipc = %08x, upc = %08x)\n", immv,
|
| 2198 |
|
|
m_core->cpu_ipc,
|
| 2199 |
|
|
m_core->cpu_upc);
|
| 2200 |
|
|
}
|
| 2201 |
|
|
} if (m_console)
|
| 2202 |
|
|
fflush(stdout);
|
| 2203 |
|
|
}
|
| 2204 |
|
|
|
| 2205 |
|
|
|
| 2206 |
|
|
};
|
| 2207 |
|
|
|
| 2208 |
|
|
void get_value(ZIPCPU_TB *tb) {
|
| 2209 |
|
|
int wy, wx, ra;
|
| 2210 |
|
|
int c = tb->cursor();
|
| 2211 |
|
|
|
| 2212 |
|
|
wx = (c & 0x03) * 20 + 9;
|
| 2213 |
|
|
wy = (c>>2);
|
| 2214 |
|
|
if (wy >= 3+4)
|
| 2215 |
|
|
wy++;
|
| 2216 |
|
|
if (wy > 3)
|
| 2217 |
|
|
wy += 2;
|
| 2218 |
|
|
wy++;
|
| 2219 |
|
|
|
| 2220 |
|
|
if (c >= 12)
|
| 2221 |
|
|
ra = c - 12;
|
| 2222 |
|
|
else
|
| 2223 |
|
|
ra = c + 32;
|
| 2224 |
|
|
|
| 2225 |
|
|
bool done = false;
|
| 2226 |
|
|
char str[16];
|
| 2227 |
|
|
int pos = 0; str[pos] = '\0';
|
| 2228 |
|
|
while(!done) {
|
| 2229 |
|
|
int chv = getch();
|
| 2230 |
|
|
switch(chv) {
|
| 2231 |
|
|
case KEY_ESCAPE:
|
| 2232 |
|
|
pos = 0; str[pos] = '\0'; done = true;
|
| 2233 |
|
|
break;
|
| 2234 |
|
|
case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
|
| 2235 |
|
|
done = true;
|
| 2236 |
|
|
break;
|
| 2237 |
|
|
case KEY_LEFT: case KEY_BACKSPACE:
|
| 2238 |
|
|
if (pos > 0) pos--;
|
| 2239 |
|
|
break;
|
| 2240 |
|
|
case CTRL('L'): redrawwin(stdscr); break;
|
| 2241 |
|
|
case KEY_CLEAR:
|
| 2242 |
|
|
pos = 0;
|
| 2243 |
|
|
break;
|
| 2244 |
|
|
case '0': case ' ': str[pos++] = '0'; break;
|
| 2245 |
|
|
case '1': str[pos++] = '1'; break;
|
| 2246 |
|
|
case '2': str[pos++] = '2'; break;
|
| 2247 |
|
|
case '3': str[pos++] = '3'; break;
|
| 2248 |
|
|
case '4': str[pos++] = '4'; break;
|
| 2249 |
|
|
case '5': str[pos++] = '5'; break;
|
| 2250 |
|
|
case '6': str[pos++] = '6'; break;
|
| 2251 |
|
|
case '7': str[pos++] = '7'; break;
|
| 2252 |
|
|
case '8': str[pos++] = '8'; break;
|
| 2253 |
|
|
case '9': str[pos++] = '9'; break;
|
| 2254 |
|
|
case 'A': case 'a': str[pos++] = 'A'; break;
|
| 2255 |
|
|
case 'B': case 'b': str[pos++] = 'B'; break;
|
| 2256 |
|
|
case 'C': case 'c': str[pos++] = 'C'; break;
|
| 2257 |
|
|
case 'D': case 'd': str[pos++] = 'D'; break;
|
| 2258 |
|
|
case 'E': case 'e': str[pos++] = 'E'; break;
|
| 2259 |
|
|
case 'F': case 'f': str[pos++] = 'F'; break;
|
| 2260 |
|
|
}
|
| 2261 |
|
|
|
| 2262 |
|
|
if (pos > 8)
|
| 2263 |
|
|
pos = 8;
|
| 2264 |
|
|
str[pos] = '\0';
|
| 2265 |
|
|
|
| 2266 |
|
|
attron(A_NORMAL | A_UNDERLINE);
|
| 2267 |
|
|
mvprintw(wy, wx, "%-8s", str);
|
| 2268 |
|
|
if (pos > 0) {
|
| 2269 |
|
|
attron(A_NORMAL | A_UNDERLINE | A_BLINK);
|
| 2270 |
|
|
mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
|
| 2271 |
|
|
}
|
| 2272 |
|
|
attrset(A_NORMAL);
|
| 2273 |
|
|
}
|
| 2274 |
|
|
|
| 2275 |
|
|
if (pos > 0) {
|
| 2276 |
|
|
int v;
|
| 2277 |
|
|
v = strtoul(str, NULL, 16);
|
| 2278 |
|
|
if (!tb->halted()) {
|
| 2279 |
|
|
switch(ra) {
|
| 2280 |
|
|
case 15:
|
| 2281 |
|
|
tb->m_core->cpu_ipc = v;
|
| 2282 |
|
|
if (!tb->m_core->r_gie) {
|
| 2283 |
|
|
tb->jump_to(v);
|
| 2284 |
|
|
// tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
|
| 2285 |
|
|
tb->m_core->alu_pc_valid = 0;
|
| 2286 |
|
|
#ifdef OPT_PIPELINED
|
| 2287 |
|
|
// tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
|
| 2288 |
|
|
tb->m_core->dcd_valid = 0;
|
| 2289 |
|
|
#endif
|
| 2290 |
|
|
tb->m_core->op_valid = 0;
|
| 2291 |
|
|
}
|
| 2292 |
|
|
break;
|
| 2293 |
|
|
case 31:
|
| 2294 |
|
|
tb->m_core->cpu_upc = v;
|
| 2295 |
|
|
if (tb->m_core->r_gie) {
|
| 2296 |
|
|
tb->jump_to(v);
|
| 2297 |
|
|
// tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
|
| 2298 |
|
|
tb->m_core->alu_pc_valid = 0;
|
| 2299 |
|
|
#ifdef OPT_PIPELINED
|
| 2300 |
|
|
tb->m_core->dcd_valid = 0;
|
| 2301 |
|
|
#endif
|
| 2302 |
|
|
tb->m_core->op_valid = 0;
|
| 2303 |
|
|
}
|
| 2304 |
|
|
break;
|
| 2305 |
|
|
#ifdef ZIPSYSTEM
|
| 2306 |
|
|
case 32: tb->m_core->pic_data = v; break;
|
| 2307 |
|
|
case 33: tb->m_core->watchdog = v; break;
|
| 2308 |
|
|
// case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
|
| 2309 |
|
|
case 35: tb->m_core->int_state = v; break;
|
| 2310 |
|
|
case 36: tb->m_core->timer_a = v; break;
|
| 2311 |
|
|
case 37: tb->m_core->timer_b = v; break;
|
| 2312 |
|
|
case 38: tb->m_core->timer_c = v; break;
|
| 2313 |
|
|
case 39: tb->m_core->jiffies = v; break;
|
| 2314 |
|
|
case 44: tb->m_core->utc_data = v; break;
|
| 2315 |
|
|
case 45: tb->m_core->uoc_data = v; break;
|
| 2316 |
|
|
case 46: tb->m_core->upc_data = v; break;
|
| 2317 |
|
|
case 47: tb->m_core->uic_data = v; break;
|
| 2318 |
|
|
#else
|
| 2319 |
|
|
case 32: case 33: case 34: case 35:
|
| 2320 |
|
|
case 36: case 37: case 38: case 39:
|
| 2321 |
|
|
case 40: case 41: case 42: case 43:
|
| 2322 |
|
|
case 44: case 45: case 46: case 47:
|
| 2323 |
|
|
break;
|
| 2324 |
|
|
#endif
|
| 2325 |
|
|
default:
|
| 2326 |
|
|
tb->m_core->regset[ra] = v;
|
| 2327 |
|
|
break;
|
| 2328 |
|
|
}
|
| 2329 |
|
|
} else
|
| 2330 |
|
|
tb->cmd_write(ra, v);
|
| 2331 |
|
|
}
|
| 2332 |
|
|
}
|
| 2333 |
|
|
|
| 2334 |
|
|
|
| 2335 |
|
|
|
| 2336 |
|
|
void usage(void) {
|
| 2337 |
|
|
printf("USAGE: zippy_tb [-a] <testfile.out>\n");
|
| 2338 |
|
|
printf("\n");
|
| 2339 |
|
|
printf("\tWhere testfile.out is an output file from the assembler.\n");
|
| 2340 |
|
|
printf("\tThis file needs to be in a raw format and not an ELF\n");
|
| 2341 |
|
|
printf("\texecutable. It will be inserted into memory at a memory\n");
|
| 2342 |
|
|
printf("\taddress of 0x0100000. The memory device itself, the only\n");
|
| 2343 |
|
|
printf("\tdevice supported by this simulator, occupies addresses from\n");
|
| 2344 |
|
|
printf("\t0x0100000 to 0x01fffff.\n");
|
| 2345 |
|
|
printf("\n");
|
| 2346 |
|
|
printf("\t-a\tSets the testbench to run automatically without any\n");
|
| 2347 |
|
|
printf("\t\tuser interaction.\n");
|
| 2348 |
|
|
printf("\n");
|
| 2349 |
|
|
printf("\tUser Commands:\n");
|
| 2350 |
|
|
printf("\t\tWhen the test bench is run interactively, the following\n");
|
| 2351 |
|
|
printf("\t\tkey strokes are recognized:\n");
|
| 2352 |
|
|
printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
|
| 2353 |
|
|
printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
|
| 2354 |
|
|
printf("\t\t\tuser intervention.\n");
|
| 2355 |
|
|
printf("\t\t\'q\'\tQuit the simulation.\n");
|
| 2356 |
|
|
printf("\t\t\'r\'\tReset the processor.\n");
|
| 2357 |
|
|
printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
|
| 2358 |
|
|
printf("\t\t\tThis may consume more than one tick.\n");
|
| 2359 |
|
|
printf("\t\t\'t\'\tClock a single tick through the system.\n");
|
| 2360 |
|
|
}
|
| 2361 |
|
|
|
| 2362 |
|
|
bool signalled = false;
|
| 2363 |
|
|
|
| 2364 |
|
|
void sigint(int v) {
|
| 2365 |
|
|
signalled = true;
|
| 2366 |
|
|
}
|
| 2367 |
|
|
|
| 2368 |
|
|
int main(int argc, char **argv) {
|
| 2369 |
|
|
Verilated::commandArgs(argc, argv);
|
| 2370 |
|
|
ZIPCPU_TB *tb = new ZIPCPU_TB();
|
| 2371 |
|
|
bool autorun = false, exit_on_done = false, autostep=false;
|
| 2372 |
|
|
ZIPI entry = RAMBASE;
|
| 2373 |
|
|
|
| 2374 |
|
|
signal(SIGINT, sigint);
|
| 2375 |
|
|
|
| 2376 |
|
|
if (argc <= 1) {
|
| 2377 |
|
|
usage();
|
| 2378 |
|
|
exit(-1);
|
| 2379 |
|
|
} else {
|
| 2380 |
|
|
for(int argn=1; argn<argc; argn++) {
|
| 2381 |
|
|
if (argv[argn][0] == '-') {
|
| 2382 |
|
|
switch(argv[argn][1]) {
|
| 2383 |
|
|
case 'a':
|
| 2384 |
|
|
autorun = true;
|
| 2385 |
|
|
break;
|
| 2386 |
|
|
case 'e':
|
| 2387 |
|
|
exit_on_done = true;
|
| 2388 |
|
|
break;
|
| 2389 |
|
|
case 'h':
|
| 2390 |
|
|
usage();
|
| 2391 |
|
|
exit(0);
|
| 2392 |
|
|
break;
|
| 2393 |
|
|
case 's':
|
| 2394 |
|
|
autostep = true;
|
| 2395 |
|
|
break;
|
| 2396 |
|
|
default:
|
| 2397 |
|
|
usage();
|
| 2398 |
|
|
exit(-1);
|
| 2399 |
|
|
break;
|
| 2400 |
|
|
}
|
| 2401 |
|
|
} else if ((access(argv[argn], R_OK)==0)
|
| 2402 |
|
|
&&(iself(argv[argn]))) {
|
| 2403 |
|
|
ELFSECTION **secpp = NULL, *secp;
|
| 2404 |
|
|
|
| 2405 |
|
|
elfread(argv[argn], entry, secpp);
|
| 2406 |
|
|
|
| 2407 |
|
|
for(int i=0; secpp[i]->m_len; i++) {
|
| 2408 |
|
|
const char *data;
|
| 2409 |
|
|
|
| 2410 |
|
|
secp = secpp[i];
|
| 2411 |
|
|
assert(secp->m_start >= RAMBASE);
|
| 2412 |
|
|
assert(secp->m_start+secp->m_len <= RAMBASE+RAMWORDS);
|
| 2413 |
|
|
assert((secp->m_len & 3)==0);
|
| 2414 |
|
|
|
| 2415 |
|
|
data = &secp->m_data[0];
|
| 2416 |
|
|
tb->m_mem.load((secp->m_start-RAMBASE)>>2, data, secp->m_len);
|
| 2417 |
|
|
}
|
| 2418 |
|
|
} else {
|
| 2419 |
|
|
fprintf(stderr, "No access to %s, or unknown arg\n", argv[argn]);
|
| 2420 |
|
|
exit(-2);
|
| 2421 |
|
|
}
|
| 2422 |
|
|
}
|
| 2423 |
|
|
}
|
| 2424 |
|
|
|
| 2425 |
|
|
|
| 2426 |
|
|
if (autorun) {
|
| 2427 |
|
|
bool done = false;
|
| 2428 |
|
|
|
| 2429 |
|
|
printf("Running in non-interactive mode\n");
|
| 2430 |
|
|
tb->m_console = true;
|
| 2431 |
|
|
tb->reset();
|
| 2432 |
|
|
tb->m_core->cpu_halt = 1;
|
| 2433 |
|
|
tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET|15);
|
| 2434 |
|
|
tb->wb_write(CMD_DATA, entry);
|
| 2435 |
|
|
tb->wb_write(CMD_REG, 15);
|
| 2436 |
|
|
tb->m_bomb = false;
|
| 2437 |
|
|
while(!done) {
|
| 2438 |
|
|
tb->tick();
|
| 2439 |
|
|
|
| 2440 |
|
|
/*
|
| 2441 |
|
|
printf("PC = %08x:%08x (%08x)\n",
|
| 2442 |
|
|
tb->m_core->cpu_ipc,
|
| 2443 |
|
|
tb->m_core->cpu_upc,
|
| 2444 |
|
|
tb->m_core->alu_pc);
|
| 2445 |
|
|
*/
|
| 2446 |
|
|
|
| 2447 |
|
|
done = (tb->test_success())||(tb->test_failure());
|
| 2448 |
|
|
done = done || signalled;
|
| 2449 |
|
|
}
|
| 2450 |
|
|
} else if (autostep) {
|
| 2451 |
|
|
bool done = false;
|
| 2452 |
|
|
|
| 2453 |
|
|
printf("Running in non-interactive mode, via step commands\n");
|
| 2454 |
|
|
tb->m_console = true;
|
| 2455 |
|
|
tb->reset();
|
| 2456 |
|
|
tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET|CPU_sPC);
|
| 2457 |
|
|
tb->wb_write(CMD_DATA, entry);
|
| 2458 |
|
|
tb->wb_write(CMD_REG, CPU_sPC);
|
| 2459 |
|
|
tb->m_bomb = false;
|
| 2460 |
|
|
while(!done) {
|
| 2461 |
|
|
tb->wb_write(CMD_REG, CMD_STEP);
|
| 2462 |
|
|
/*
|
| 2463 |
|
|
printf("PC = %08x:%08x (%08x)\n",
|
| 2464 |
|
|
tb->m_core->cpu_ipc, tb->m_core->cpu_upc,
|
| 2465 |
|
|
tb->m_core->alu_pc);
|
| 2466 |
|
|
*/
|
| 2467 |
|
|
done = (tb->test_success())||(tb->test_failure());
|
| 2468 |
|
|
done = done || signalled;
|
| 2469 |
|
|
}
|
| 2470 |
|
|
} else { // Interactive
|
| 2471 |
|
|
initscr();
|
| 2472 |
|
|
raw();
|
| 2473 |
|
|
noecho();
|
| 2474 |
|
|
keypad(stdscr, true);
|
| 2475 |
|
|
|
| 2476 |
|
|
// tb->reset();
|
| 2477 |
|
|
// for(int i=0; i<2; i++)
|
| 2478 |
|
|
// tb->tick();
|
| 2479 |
|
|
tb->m_core->cmd_reset = 1;
|
| 2480 |
|
|
tb->m_core->cpu_halt = 1;
|
| 2481 |
|
|
tb->tick();
|
| 2482 |
|
|
|
| 2483 |
|
|
tb->m_core->cmd_reset = 0;
|
| 2484 |
|
|
tb->m_core->cpu_halt = 0;
|
| 2485 |
|
|
tb->tick();
|
| 2486 |
|
|
tb->jump_to(entry);
|
| 2487 |
|
|
tb->tick();
|
| 2488 |
|
|
tb->jump_to(entry);
|
| 2489 |
|
|
tb->tick();
|
| 2490 |
|
|
tb->jump_to(entry);
|
| 2491 |
|
|
|
| 2492 |
|
|
|
| 2493 |
|
|
// For debugging purposes: do we wish to skip some number of
|
| 2494 |
|
|
// instructions to fast forward to a time of interest??
|
| 2495 |
|
|
for(int i=0; i<0; i++) {
|
| 2496 |
|
|
tb->m_core->cpu_halt = 0;
|
| 2497 |
|
|
tb->tick();
|
| 2498 |
|
|
}
|
| 2499 |
|
|
|
| 2500 |
|
|
int chv = 'q';
|
| 2501 |
|
|
|
| 2502 |
|
|
bool done = false, halted = true, manual = true,
|
| 2503 |
|
|
high_speed = false;
|
| 2504 |
|
|
|
| 2505 |
|
|
halfdelay(1);
|
| 2506 |
|
|
// tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
|
| 2507 |
|
|
// while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
|
| 2508 |
|
|
// tb->show_state();
|
| 2509 |
|
|
|
| 2510 |
|
|
while(!done) {
|
| 2511 |
|
|
if ((high_speed)&&(!manual)&&(!halted)) {
|
| 2512 |
|
|
// chv = getch();
|
| 2513 |
|
|
|
| 2514 |
|
|
struct pollfd fds[1];
|
| 2515 |
|
|
fds[0].fd = STDIN_FILENO;
|
| 2516 |
|
|
fds[0].events = POLLIN;
|
| 2517 |
|
|
|
| 2518 |
|
|
if (poll(fds, 1, 0) > 0)
|
| 2519 |
|
|
chv = getch();
|
| 2520 |
|
|
else
|
| 2521 |
|
|
chv = ERR;
|
| 2522 |
|
|
|
| 2523 |
|
|
} else {
|
| 2524 |
|
|
chv = getch();
|
| 2525 |
|
|
}
|
| 2526 |
|
|
switch(chv) {
|
| 2527 |
|
|
case 'h': case 'H':
|
| 2528 |
|
|
tb->wb_write(CMD_REG, CMD_HALT);
|
| 2529 |
|
|
if (!halted)
|
| 2530 |
|
|
erase();
|
| 2531 |
|
|
halted = true;
|
| 2532 |
|
|
break;
|
| 2533 |
|
|
case 'G':
|
| 2534 |
|
|
high_speed = true;
|
| 2535 |
|
|
// cbreak();
|
| 2536 |
|
|
case 'g':
|
| 2537 |
|
|
tb->wb_write(CMD_REG, 0);
|
| 2538 |
|
|
if (halted)
|
| 2539 |
|
|
erase();
|
| 2540 |
|
|
halted = false;
|
| 2541 |
|
|
manual = false;
|
| 2542 |
|
|
break;
|
| 2543 |
|
|
case 'm':
|
| 2544 |
|
|
tb->show_user_timers(false);
|
| 2545 |
|
|
break;
|
| 2546 |
|
|
case 'q': case 'Q':
|
| 2547 |
|
|
done = true;
|
| 2548 |
|
|
break;
|
| 2549 |
|
|
case 'r': case 'R':
|
| 2550 |
|
|
if (manual)
|
| 2551 |
|
|
tb->reset();
|
| 2552 |
|
|
else
|
| 2553 |
|
|
tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
|
| 2554 |
|
|
halted = true;
|
| 2555 |
|
|
erase();
|
| 2556 |
|
|
break;
|
| 2557 |
|
|
case 's':
|
| 2558 |
|
|
if (!halted)
|
| 2559 |
|
|
erase();
|
| 2560 |
|
|
tb->step();
|
| 2561 |
|
|
manual = false;
|
| 2562 |
|
|
halted = true;
|
| 2563 |
|
|
// if (high_speed)
|
| 2564 |
|
|
// halfdelay(1);
|
| 2565 |
|
|
high_speed = false;
|
| 2566 |
|
|
break;
|
| 2567 |
|
|
case 'S':
|
| 2568 |
|
|
if ((!manual)||(halted))
|
| 2569 |
|
|
erase();
|
| 2570 |
|
|
manual = true;
|
| 2571 |
|
|
halted = true;
|
| 2572 |
|
|
// if (high_speed)
|
| 2573 |
|
|
// halfdelay(1);
|
| 2574 |
|
|
high_speed = false;
|
| 2575 |
|
|
tb->m_core->cpu_halt = 0;
|
| 2576 |
|
|
tb->m_core->cmd_step = 1;
|
| 2577 |
|
|
tb->eval();
|
| 2578 |
|
|
tb->tick();
|
| 2579 |
|
|
break;
|
| 2580 |
|
|
case 'T': //
|
| 2581 |
|
|
if ((!manual)||(halted))
|
| 2582 |
|
|
erase();
|
| 2583 |
|
|
manual = true;
|
| 2584 |
|
|
halted = true;
|
| 2585 |
|
|
// if (high_speed)
|
| 2586 |
|
|
// halfdelay(1);
|
| 2587 |
|
|
high_speed = false;
|
| 2588 |
|
|
tb->m_core->cpu_halt = 1;
|
| 2589 |
|
|
tb->m_core->cmd_step = 0;
|
| 2590 |
|
|
tb->eval();
|
| 2591 |
|
|
tb->tick();
|
| 2592 |
|
|
break;
|
| 2593 |
|
|
case 't':
|
| 2594 |
|
|
if ((!manual)||(halted))
|
| 2595 |
|
|
erase();
|
| 2596 |
|
|
manual = true;
|
| 2597 |
|
|
halted = false;
|
| 2598 |
|
|
// if (high_speed)
|
| 2599 |
|
|
// halfdelay(1);
|
| 2600 |
|
|
high_speed = false;
|
| 2601 |
|
|
tb->m_core->cpu_halt = 0;
|
| 2602 |
|
|
tb->tick();
|
| 2603 |
|
|
break;
|
| 2604 |
|
|
case 'u':
|
| 2605 |
|
|
tb->show_user_timers(true);
|
| 2606 |
|
|
break;
|
| 2607 |
|
|
case KEY_IC: case KEY_ENTER: case KEY_RETURN:
|
| 2608 |
|
|
get_value(tb);
|
| 2609 |
|
|
break;
|
| 2610 |
|
|
case KEY_UP: tb->cursor_up(); break;
|
| 2611 |
|
|
case KEY_DOWN: tb->cursor_down(); break;
|
| 2612 |
|
|
case KEY_LEFT: tb->cursor_left(); break;
|
| 2613 |
|
|
case KEY_RIGHT: tb->cursor_right(); break;
|
| 2614 |
|
|
case CTRL('L'): redrawwin(stdscr); break;
|
| 2615 |
|
|
case ERR: case KEY_CLEAR:
|
| 2616 |
|
|
default:
|
| 2617 |
|
|
if (!manual)
|
| 2618 |
|
|
tb->tick();
|
| 2619 |
|
|
}
|
| 2620 |
|
|
|
| 2621 |
|
|
if (manual) {
|
| 2622 |
|
|
tb->show_state();
|
| 2623 |
|
|
} else if (halted) {
|
| 2624 |
|
|
if (tb->m_dbgfp)
|
| 2625 |
|
|
fprintf(tb->m_dbgfp, "\n\nREAD-STATE ******\n");
|
| 2626 |
|
|
tb->read_state();
|
| 2627 |
|
|
} else
|
| 2628 |
|
|
tb->show_state();
|
| 2629 |
|
|
|
| 2630 |
|
|
if (tb->m_core->i_reset)
|
| 2631 |
|
|
done =true;
|
| 2632 |
|
|
if ((tb->m_bomb)||(signalled))
|
| 2633 |
|
|
done = true;
|
| 2634 |
|
|
|
| 2635 |
|
|
if (exit_on_done) {
|
| 2636 |
|
|
if (tb->test_success())
|
| 2637 |
|
|
done = true;
|
| 2638 |
|
|
if (tb->test_failure())
|
| 2639 |
|
|
done = true;
|
| 2640 |
|
|
}
|
| 2641 |
|
|
}
|
| 2642 |
|
|
endwin();
|
| 2643 |
|
|
}
|
| 2644 |
|
|
#ifdef MANUAL_STEPPING_MODE
|
| 2645 |
|
|
else { // Manual stepping mode
|
| 2646 |
|
|
tb->jump_to(entry);
|
| 2647 |
|
|
tb->show_state();
|
| 2648 |
|
|
|
| 2649 |
|
|
while('q' != tolower(chv = getch())) {
|
| 2650 |
|
|
tb->tick();
|
| 2651 |
|
|
tb->show_state();
|
| 2652 |
|
|
|
| 2653 |
|
|
if (tb->test_success())
|
| 2654 |
|
|
break;
|
| 2655 |
|
|
else if (tb->test_failure())
|
| 2656 |
|
|
break;
|
| 2657 |
|
|
else if (signalled)
|
| 2658 |
|
|
break;
|
| 2659 |
|
|
}
|
| 2660 |
|
|
}
|
| 2661 |
|
|
#endif
|
| 2662 |
|
|
|
| 2663 |
|
|
printf("\n");
|
| 2664 |
|
|
if (tb->test_failure()) {
|
| 2665 |
|
|
tb->dump_state();
|
| 2666 |
|
|
}
|
| 2667 |
|
|
|
| 2668 |
|
|
#ifdef ZIPSYSTEM
|
| 2669 |
|
|
printf("Clocks used : %08x\n", tb->m_core->mtc_data);
|
| 2670 |
|
|
printf("Instructions Issued : %08x\n", tb->m_core->mic_data);
|
| 2671 |
|
|
printf("Tick Count : %08lx\n", tb->m_tickcount);
|
| 2672 |
|
|
if (tb->m_core->mtc_data != 0)
|
| 2673 |
|
|
printf("Instructions / Clock: %.2f\n",
|
| 2674 |
|
|
(double)tb->m_core->mic_data
|
| 2675 |
|
|
/ (double)tb->m_core->mtc_data);
|
| 2676 |
|
|
#endif
|
| 2677 |
|
|
|
| 2678 |
|
|
int rcode = 0;
|
| 2679 |
|
|
if (tb->m_bomb) {
|
| 2680 |
|
|
printf("TEST BOMBED\n");
|
| 2681 |
|
|
rcode = -1;
|
| 2682 |
|
|
} else if (tb->test_success()) {
|
| 2683 |
|
|
printf("SUCCESS!\n");
|
| 2684 |
|
|
} else if (tb->test_failure()) {
|
| 2685 |
|
|
rcode = -2;
|
| 2686 |
|
|
printf("TEST FAILED!\n");
|
| 2687 |
|
|
} else
|
| 2688 |
|
|
printf("User quit\n");
|
| 2689 |
|
|
delete tb;
|
| 2690 |
|
|
exit(rcode);
|
| 2691 |
|
|
}
|
| 2692 |
|
|
|
