OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sim/] [verilator/] [zippy_tb.cpp] - Blame information for rev 204

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 204 dgisselq
///////////////////////////////////////////////////////////////////////////////
2
//
3
// Filename:    zippy_tb.cpp
4
//
5
// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
6
//
7
// Purpose:     A bench simulator for the CPU.  Eventually, you should be
8
//              able to give this program the name of a piece of compiled
9
//      code to load into memory.  For now, we hand assemble with the computers
10
//      help.
11
//
12
//
13
// Creator:     Dan Gisselquist, Ph.D.
14
//              Gisselquist Technology, LLC
15
//
16
///////////////////////////////////////////////////////////////////////////////
17
//
18
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
19
//
20
// This program is free software (firmware): you can redistribute it and/or
21
// modify it under the terms of  the GNU General Public License as published
22
// by the Free Software Foundation, either version 3 of the License, or (at
23
// your option) any later version.
24
//
25
// This program is distributed in the hope that it will be useful, but WITHOUT
26
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
27
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
28
// for more details.
29
//
30
// License:     GPL, v3, as defined and found on www.gnu.org,
31
//              http://www.gnu.org/licenses/gpl.html
32
//
33
//
34
///////////////////////////////////////////////////////////////////////////////
35
//
36
//
37
#include <signal.h>
38
#include <time.h>
39
#include <unistd.h>
40
#include <poll.h>
41
#include <sys/types.h>
42
#include <sys/stat.h>
43
#include <fcntl.h>
44
#include <string.h>
45
#include <ctype.h>
46
 
47
#include <ncurses.h>
48
 
49
#include "verilated.h"
50
#include "verilated_vcd_c.h"
51
#include "Vzipsystem.h"
52
#include "cpudefs.h"
53
 
54
#include "testb.h"
55
#include "zipelf.h"
56
// #include "twoc.h"
57
// #include "qspiflashsim.h"
58
#include "byteswap.h"
59
#include "memsim.h"
60
#include "zopcodes.h"
61
 
62
#define CMD_REG         0
63
#define CMD_DATA        1
64
#define CMD_GIE         (1<<13)
65
#define CMD_SLEEP       (1<<12)
66
#define CMD_CLEAR_CACHE (1<<11)
67
#define CMD_HALT        (1<<10)
68
#define CMD_STALL       (1<<9)
69
#define CMD_INT         (1<<7)
70
#define CMD_RESET       (1<<6)
71
#define CMD_STEP        ((1<<8)|CMD_HALT)
72
 
73
#define KEY_ESCAPE      27
74
#define KEY_RETURN      10
75
#define CTRL(X)         ((X)&0x01f)
76
 
77
#define MAXERR          10000
78
 
79
/*
80
// We are just a raw CPU with memory.  There is no flash.
81
#define LGFLASHLEN      24
82
#define FLASHBASE       0x01000000
83
#define FLASHWORDS      (1<<LGFLASHLEN)
84
*/
85
 
86
#define LGRAMLEN        28
87
#define RAMBASE         0x10000000
88
#define RAMLEN          (1<<(LGRAMLEN))
89
#define RAMWORDS        ((RAMLEN)>>2)
90
 
91
class   SPARSEMEM {
92
public:
93
        bool    m_valid;
94
        unsigned int    m_a, m_d;
95
};
96
 
97
class   ZIPSTATE {
98
public:
99
        bool            m_valid, m_gie, m_last_pc_valid;
100
        unsigned int    m_sR[16], m_uR[16];
101
        unsigned int    m_p[20];
102
        unsigned int    m_last_pc, m_pc, m_sp;
103
        SPARSEMEM       m_smem[5]; // Nearby stack memory
104
        SPARSEMEM       m_imem[5]; // Nearby instruction memory
105
        ZIPSTATE(void) : m_valid(false), m_last_pc_valid(false) {}
106
 
107
        void    step(void) {
108
                m_last_pc_valid = true;
109
                m_last_pc = m_pc;
110
        }
111
};
112
 
113
extern  FILE    *gbl_dbgfp;
114
FILE    *gbl_dbgfp = NULL;
115
 
116
// No particular "parameters" need definition or redefinition here.
117
class   ZIPPY_TB : public TESTB<Vzipsystem> {
118
public:
119
        unsigned long   m_mem_size;
120
        MEMSIM          m_mem;
121
        // QSPIFLASHSIM m_flash;
122
        FILE            *m_dbgfp, *m_profile_fp;
123
        bool            dbg_flag, m_bomb, m_show_user_timers;
124
        int             m_cursor;
125
        unsigned long   m_last_instruction_tickcount;
126
        ZIPSTATE        m_state;
127
 
128
        ZIPPY_TB(void) : m_mem_size(RAMWORDS), m_mem(m_mem_size) {
129
                if (true) {
130
                        m_dbgfp = fopen("debug.txt", "w");
131
                        dbg_flag = true;
132
                        gbl_dbgfp = m_dbgfp;
133
                } else {
134
                        m_dbgfp = NULL;
135
                        dbg_flag = false;
136
                        gbl_dbgfp = NULL;
137
                }
138
 
139
                if(true) {
140
                        // TESTB<Vzipsystem>::opentrace("trace.vcd");
141
                        opentrace("trace.vcd");
142
                } else {
143
                        m_trace = NULL;
144
                }
145
 
146
                m_bomb = false;
147
                m_cursor = 0;
148
                m_show_user_timers = false;
149
 
150
                m_last_instruction_tickcount = 0l;
151
                if (true) {
152
                        m_profile_fp = fopen("pfile.bin","wb");
153
                } else {
154
                        m_profile_fp = NULL;
155
                }
156
        }
157
 
158
        ~ZIPPY_TB(void) {
159
                if (m_dbgfp)
160
                        fclose(m_dbgfp);
161
                if (m_profile_fp)
162
                        fclose(m_profile_fp);
163
                if (m_trace)
164
                        m_trace->close();
165
        }
166
 
167
        void    reset(void) {
168
                // m_flash.debug(false);
169
                TESTB<Vzipsystem>::reset();
170
        }
171
 
172
        void    step(void) {
173
                wb_write(CMD_REG, CMD_STEP);
174
                m_state.step();
175
        }
176
 
177
        void    read_raw_state(void) {
178
                m_state.m_valid = false;
179
                for(int i=0; i<16; i++)
180
                        m_state.m_sR[i] = cmd_read(i);
181
                for(int i=0; i<16; i++)
182
                        m_state.m_uR[i] = cmd_read(i+16);
183
                for(int i=0; i<20; i++)
184
                        m_state.m_p[i]  = cmd_read(i+32);
185
 
186
                m_state.m_gie = wb_read(CMD_REG) & CMD_GIE;
187
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
188
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
189
 
190
                if (m_state.m_last_pc_valid)
191
                        m_state.m_imem[0].m_a = m_state.m_last_pc;
192
                else
193
                        m_state.m_imem[0].m_a = m_state.m_pc - 1;
194
                m_state.m_imem[0].m_d = m_mem[m_state.m_imem[0].m_a & 0x0fffff];
195
                m_state.m_imem[0].m_valid = ((m_state.m_imem[0].m_a & 0xfff00000)==0x00100000);
196
                m_state.m_imem[1].m_a = m_state.m_pc;
197
                m_state.m_imem[1].m_valid = ((m_state.m_imem[1].m_a & 0xfff00000)==0x00100000);
198
                m_state.m_imem[1].m_d = m_mem[m_state.m_imem[1].m_a & 0x0fffff];
199
 
200
                for(int i=1; i<4; i++) {
201
                        if (!m_state.m_imem[i].m_valid) {
202
                                m_state.m_imem[i+1].m_valid = false;
203
                                m_state.m_imem[i+1].m_a = m_state.m_imem[i].m_a+1;
204
                                continue;
205
                        }
206
                        m_state.m_imem[i+1].m_a = zop_early_branch(
207
                                        m_state.m_imem[i].m_a,
208
                                        m_state.m_imem[i].m_d);
209
                        m_state.m_imem[i+1].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
210
                        m_state.m_imem[i+1].m_valid = ((m_state.m_imem[i].m_a&0xfff00000)==0x00100000);
211
                }
212
 
213
                m_state.m_smem[0].m_a = m_state.m_sp;
214
                for(int i=1; i<5; i++)
215
                        m_state.m_smem[i].m_a = m_state.m_smem[i-1].m_a+1;
216
                for(int i=0; i<5; i++) {
217
                        m_state.m_smem[i].m_valid =
218
                                (m_state.m_imem[i].m_a > 0x10000);
219
                        m_state.m_smem[i].m_d = m_mem[m_state.m_imem[i].m_a & 0x0fffff];
220
                }
221
                m_state.m_valid = true;
222
        }
223
 
224
        void    read_raw_state_cheating(void) {
225
                m_state.m_valid = false;
226
                for(int i=0; i<16; i++)
227
                        m_state.m_sR[i] = m_core->v__DOT__thecpu__DOT__regset[i];
228
                m_state.m_sR[14] = (m_state.m_sR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_iflags;
229
                m_state.m_sR[15] = m_core->v__DOT__thecpu__DOT__ipc;
230
                for(int i=0; i<16; i++)
231
                        m_state.m_uR[i] = m_core->v__DOT__thecpu__DOT__regset[i+16];
232
                m_state.m_uR[14] = (m_state.m_uR[14]&0xffffe000)|m_core->v__DOT__thecpu__DOT__w_uflags;
233
                m_state.m_uR[15] = m_core->v__DOT__thecpu__DOT__r_upc;
234
 
235
                m_state.m_gie = m_core->v__DOT__thecpu__DOT__r_gie;
236
                m_state.m_pc  = (m_state.m_gie) ? (m_state.m_uR[15]):(m_state.m_sR[15]);
237
                m_state.m_sp  = (m_state.m_gie) ? (m_state.m_uR[13]):(m_state.m_sR[13]);
238
 
239
                m_state.m_p[0] = m_core->v__DOT__pic_data;
240
                m_state.m_p[1] = m_core->v__DOT__watchdog__DOT__r_value;
241
                if (!m_show_user_timers) {
242
                        m_state.m_p[2] = m_core->v__DOT__watchbus__DOT__r_value;
243
                } else {
244
                        m_state.m_p[2] = m_core->v__DOT__r_wdbus_data;
245
                }
246
 
247
                m_state.m_p[3] = m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state;
248
                m_state.m_p[4] = m_core->v__DOT__timer_a__DOT__r_value;
249
                m_state.m_p[5] = m_core->v__DOT__timer_b__DOT__r_value;
250
                m_state.m_p[6] = m_core->v__DOT__timer_c__DOT__r_value;
251
                m_state.m_p[7] = m_core->v__DOT__jiffies__DOT__r_counter;
252
 
253
                m_state.m_p[ 8] = m_core->v__DOT__utc_data;
254
                m_state.m_p[ 9] = m_core->v__DOT__uoc_data;
255
                m_state.m_p[10] = m_core->v__DOT__upc_data;
256
                m_state.m_p[11] = m_core->v__DOT__uic_data;
257
 
258
                m_state.m_p[12] = m_core->v__DOT__mtc_data;
259
                m_state.m_p[13] = m_core->v__DOT__moc_data;
260
                m_state.m_p[14] = m_core->v__DOT__mpc_data;
261
                m_state.m_p[15] = m_core->v__DOT__mic_data;
262
 
263
        }
264
 
265
        void    showval(int y, int x, const char *lbl, unsigned int v, bool c) {
266
                if (c)
267
                        mvprintw(y,x, ">%s> 0x%08x<", lbl, v);
268
                else
269
                        mvprintw(y,x, " %s: 0x%08x ", lbl, v);
270
        }
271
 
272
        void    dispreg(int y, int x, const char *n, unsigned int v, bool c) {
273
                // 4,4,8,1 = 17 of 20, +3 = 19
274
                if (c)
275
                        mvprintw(y, x, ">%s> 0x%08x<", n, v);
276
                else
277
                        mvprintw(y, x, " %s: 0x%08x ", n, v);
278
        }
279
 
280
        void    dbgreg(FILE *fp, int id, const char *n, unsigned int v) {
281
                /*
282
                if ((id == 14)||(id == 14+16)) {
283
                        //char  buf[64];
284
                        //fprintf(fp, " %s:",
285
                        fprintf(fp, " %s: 0x%08x ", n, v);
286
                } else
287
                */
288
                        fprintf(fp, " %s: 0x%08x ", n, v);
289
        }
290
 
291
        void    showreg(int y, int x, const char *n, int r, bool c) {
292
                if (r < 16)
293
                        dispreg(y, x, n, m_state.m_sR[r], c);
294
                else
295
                        dispreg(y, x, n, m_state.m_uR[r-16], c);
296
                move(y,x+17);
297
 
298
#ifdef  OPT_PIPELINED
299
                addch( ((r == (int)(dcd_Aid()&0x01f))&&(dcd_valid())
300
                                &&(m_core->v__DOT__thecpu__DOT__dcd_rA))
301
                        ?'a':((c)?'<':' '));
302
                addch( ((r == (int)(dcd_Bid()&0x01f))&&(dcd_valid())
303
                                &&(m_core->v__DOT__thecpu__DOT__dcd_rB))
304
                        ?'b':' ');
305
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
306
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
307
                        ?'W':' ');
308
#else
309
                addch( ((r == m_core->v__DOT__thecpu__DOT__wr_reg_id)
310
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce))
311
                        ?'W':((c)?'<':' '));
312
#endif
313
        }
314
 
315
        void    showins(int y, const char *lbl, const int ce, const int valid,
316
                        const int gie, const int stall, const unsigned int pc,
317
                        const bool phase) {
318
                char    la[80], lb[80];
319
 
320
                if (ce)
321
                        mvprintw(y, 0, "Ck ");
322
                else
323
                        mvprintw(y, 0, "   ");
324
                if (stall)
325
                        printw("Stl ");
326
                else
327
                        printw("    ");
328
                printw("%s%c 0x%08x", lbl, (phase)?'/':':', pc);
329
 
330
                if (valid) {
331
                        if (gie) attroff(A_BOLD);
332
                        else    attron(A_BOLD);
333
                        zipi_to_double_string(pc, m_mem[pc>>2], la, lb);
334
                        if (((m_mem[pc>>2]&0x80000000)==0)||(phase))
335
                                printw("  %-24s", la);
336
                        else
337
                                printw("  %-24s", lb);
338
                } else {
339
                        attroff(A_BOLD);
340
                        printw("  (0x%08x)%28s", m_mem[pc>>2],"");
341
                }
342
                attroff(A_BOLD);
343
        }
344
 
345
        void    dbgins(const char *lbl, const int ce, const int valid,
346
                        const int gie, const int stall, const unsigned int pc,
347
                        const bool phase, const bool illegal) {
348
                char    la[80], lb[80];
349
 
350
                if (!m_dbgfp)
351
                        return;
352
 
353
                if (ce)
354
                        fprintf(m_dbgfp, "%s Ck ", lbl);
355
                else
356
                        fprintf(m_dbgfp, "%s    ", lbl);
357
                if (stall)
358
                        fprintf(m_dbgfp, "Stl ");
359
                else
360
                        fprintf(m_dbgfp, "    ");
361
                fprintf(m_dbgfp, "0x%08x%s:  ", pc, (phase)?"/P":"  ");
362
 
363
                if (valid) {
364
                        zipi_to_double_string(pc, m_mem[pc>>2], la, lb);
365
                        if ((phase)||((m_mem[pc>>2]&0x80000000)==0))
366
                                fprintf(m_dbgfp, "  %-24s", la);
367
                        else
368
                                fprintf(m_dbgfp, "  %-24s", lb);
369
                } else {
370
                        fprintf(m_dbgfp, "  (0x%08x)", m_mem[pc]);
371
                } if (illegal)
372
                        fprintf(m_dbgfp, " (Illegal)");
373
                fprintf(m_dbgfp, "\n");
374
        }
375
 
376
        void    show_state(void) {
377
                int     ln= 0;
378
 
379
                read_raw_state_cheating();
380
 
381
                mvprintw(ln,0, "Peripherals-SS"); ln++;
382
#ifdef  OPT_ILLEGAL_INSTRUCTION
383
                printw(" %s",
384
                        // (m_core->v__DOT__thecpu__DOT__pf_illegal)?"PI":"  ",
385
                        (m_core->v__DOT__thecpu__DOT__dcd_illegal)?"DI":"  "
386
                        );
387
#endif
388
 
389
#ifdef  OPT_EARLY_BRANCHING
390
                printw(" %s",
391
                        (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)?"EB":"  ");
392
                if (m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
393
                        printw(" 0x%08x", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc);
394
                else    printw(" %10s", "");
395
                printw(" %s",
396
                        (m_core->v__DOT__thecpu__DOT____Vcellinp__pf____pinNumber3)?"-> P3":"     ");
397
#endif
398
 
399
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
400
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
401
                // showval(ln,40, "CACH", m_core->v__DOT__manualcache__DOT__cache_base, (m_cursor==2));
402
 
403
                if (!m_show_user_timers) {
404
                showval(ln,40, "WBUS", m_core->v__DOT__watchbus__DOT__r_value, false);
405
                } else {
406
                showval(ln,40, "UBUS", m_core->v__DOT__r_wdbus_data, false);
407
                }
408
 
409
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
410
 
411
                ln++;
412
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
413
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
414
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
415
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
416
 
417
 
418
                if (!m_show_user_timers) {
419
                        ln++;
420
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
421
                        showval(ln,20, "MOST", m_state.m_p[13], (m_cursor==9));
422
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
423
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
424
                } else {
425
                        ln++;
426
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
427
                        showval(ln,20, "UOST", m_state.m_p[ 9], (m_cursor==9));
428
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
429
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
430
                }
431
 
432
                ln++;
433
                mvprintw(ln, 40, "%s %s",
434
                        (m_core->v__DOT__cpu_halt)? "CPU-HALT": "        ",
435
                        (m_core->v__DOT__cpu_reset)?"CPU-RESET":"         "); ln++;
436
                mvprintw(ln, 40, "%s %s %s 0x%02x %s %s",
437
                        (m_core->v__DOT__cmd_halt)? "HALT": "    ",
438
                        (m_core->v__DOT__cmd_reset)?"RESET":"     ",
439
                        (m_core->v__DOT__cmd_step)? "STEP" :"    ",
440
                        (m_core->v__DOT__cmd_addr)&0x3f,
441
                        (m_core->v__DOT__thecpu__DOT__master_ce)? "*CE*" :"(ce)",
442
                        (m_core->v__DOT__cpu_reset)? "*RST*" :"(rst)");
443
                if (m_core->v__DOT__thecpu__DOT__r_gie)
444
                        attroff(A_BOLD);
445
                else
446
                        attron(A_BOLD);
447
                mvprintw(ln, 0, "Supervisor Registers");
448
                ln++;
449
 
450
                showreg(ln, 0, "sR0 ", 0, (m_cursor==12));
451
                showreg(ln,20, "sR1 ", 1, (m_cursor==13));
452
                showreg(ln,40, "sR2 ", 2, (m_cursor==14));
453
                showreg(ln,60, "sR3 ", 3, (m_cursor==15)); ln++;
454
 
455
                showreg(ln, 0, "sR4 ", 4, (m_cursor==16));
456
                showreg(ln,20, "sR5 ", 5, (m_cursor==17));
457
                showreg(ln,40, "sR6 ", 6, (m_cursor==18));
458
                showreg(ln,60, "sR7 ", 7, (m_cursor==19)); ln++;
459
 
460
                showreg(ln, 0, "sR8 ",  8, (m_cursor==20));
461
                showreg(ln,20, "sR9 ",  9, (m_cursor==21));
462
                showreg(ln,40, "sR10", 10, (m_cursor==22));
463
                showreg(ln,60, "sR11", 11, (m_cursor==23)); ln++;
464
 
465
                showreg(ln, 0, "sR12", 12, (m_cursor==24));
466
                showreg(ln,20, "sSP ", 13, (m_cursor==25));
467
 
468
                unsigned int cc = m_state.m_sR[14];
469
                if (false) {
470
                        mvprintw(ln,40, "%ssCC : 0x%08x",
471
                                (m_cursor==26)?">":" ", cc);
472
                } else {
473
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
474
                                (m_cursor==26)?">":" ",
475
                                (cc&0x01000)?"FE":"",
476
                                (cc&0x00800)?"DE":"",
477
                                (cc&0x00400)?"BE":"",
478
                                (cc&0x00200)?"TP":"",
479
                                (cc&0x00100)?"IL":"",
480
                                (cc&0x00080)?"BK":"",
481
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
482
                        mvprintw(ln, 54, "%s%s%s%s",
483
                                (cc&8)?"V":" ",
484
                                (cc&4)?"N":" ",
485
                                (cc&2)?"C":" ",
486
                                (cc&1)?"Z":" ");
487
                }
488
                showval(ln,60, "sPC ", m_state.m_sR[15], (m_cursor==27));
489
                mvprintw(ln,60,"%s",
490
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x0e)
491
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
492
                                ?"V"
493
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
494
                                &&(!m_core->v__DOT__thecpu__DOT__r_alu_gie))?"+"
495
                        :" "));
496
                ln++;
497
 
498
                if (m_core->v__DOT__thecpu__DOT__r_gie)
499
                        attron(A_BOLD);
500
                else
501
                        attroff(A_BOLD);
502
                mvprintw(ln, 0, "User Registers");
503
                mvprintw(ln, 42, "DCDR=%02x %s%s",
504
                        dcd_R(),
505
                        (m_core->v__DOT__thecpu__DOT__dcd_wR)?"W":" ",
506
                        (m_core->v__DOT__thecpu__DOT__dcd_wF)?"F":" ");
507
                mvprintw(ln, 62, "OPR =%02x %s%s",
508
                        m_core->v__DOT__thecpu__DOT__r_op_R,
509
                        (m_core->v__DOT__thecpu__DOT__op_wR)?"W":" ",
510
                        (m_core->v__DOT__thecpu__DOT__op_wF)?"F":" ");
511
                ln++;
512
                showreg(ln, 0, "uR0 ", 16, (m_cursor==28));
513
                showreg(ln,20, "uR1 ", 17, (m_cursor==29));
514
                showreg(ln,40, "uR2 ", 18, (m_cursor==30));
515
                showreg(ln,60, "uR3 ", 19, (m_cursor==31)); ln++;
516
 
517
                showreg(ln, 0, "uR4 ", 20, (m_cursor==32));
518
                showreg(ln,20, "uR5 ", 21, (m_cursor==33));
519
                showreg(ln,40, "uR6 ", 22, (m_cursor==34));
520
                showreg(ln,60, "uR7 ", 23, (m_cursor==35)); ln++;
521
 
522
                showreg(ln, 0, "uR8 ", 24, (m_cursor==36));
523
                showreg(ln,20, "uR9 ", 25, (m_cursor==37));
524
                showreg(ln,40, "uR10", 26, (m_cursor==38));
525
                showreg(ln,60, "uR11", 27, (m_cursor==39)); ln++;
526
 
527
                showreg(ln, 0, "uR12", 28, (m_cursor==40));
528
                showreg(ln,20, "uSP ", 29, (m_cursor==41));
529
                cc = m_state.m_uR[14];
530
                if (false) {
531
                        mvprintw(ln,40, "%cuCC : 0x%08x",
532
                                (m_cursor == 42)?'>':' ', cc);
533
                } else {
534
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
535
                                (m_cursor == 42)?'>':' ',
536
                                (cc & 0x1000)?"FE":"",
537
                                (cc & 0x0800)?"DE":"",
538
                                (cc & 0x0400)?"BE":"",
539
                                (cc & 0x0200)?"TP":"",
540
                                (cc & 0x0100)?"IL":"",
541
                                (cc & 0x0040)?"ST":"",
542
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
543
                        mvprintw(ln, 54, "%s%s%s%s",
544
                                (cc&8)?"V":" ",
545
                                (cc&4)?"N":" ",
546
                                (cc&2)?"C":" ",
547
                                (cc&1)?"Z":" ");
548
                }
549
                showval(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
550
                mvprintw(ln,60,"%s",
551
                        (m_core->v__DOT__thecpu__DOT__wr_reg_id == 0x1e)
552
                                &&(m_core->v__DOT__thecpu__DOT__wr_reg_ce)
553
                                ?"V"
554
                        :(((m_core->v__DOT__thecpu__DOT__wr_flags_ce)
555
                                &&(m_core->v__DOT__thecpu__DOT__r_alu_gie))?"+"
556
                        :" "));
557
 
558
                attroff(A_BOLD);
559
                ln+=1;
560
 
561
#ifdef  OPT_SINGLE_FETCH
562
                ln++;
563
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
564
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
565
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
566
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
567
                        (m_core->v__DOT__thecpu__DOT__pf_addr<<2),
568
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
569
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
570
                        "   ",//(m_core->v__DOT__thecpu__DOT__pf_stall)?"STL":"   ",
571
                        (m_core->v__DOT__wb_data)); ln++;
572
#else
573
 
574
                mvprintw(ln, 0, "PFCACH: v=%08x, %s%s, tag=%08x, pf_pc=%08x, lastpc=%08x",
575
                        m_core->v__DOT__thecpu__DOT__pf__DOT__vmask,
576
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"V":" ",
577
                        (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ",
578
                        (m_core->v__DOT__thecpu__DOT__pf__DOT__tagsrc)
579
                        ?(m_core->v__DOT__thecpu__DOT__pf__DOT__tagvalipc)
580
                        :(m_core->v__DOT__thecpu__DOT__pf__DOT__tagvallst),
581
                        m_core->v__DOT__thecpu__DOT__pf_pc,
582
                        m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc);
583
 
584
                ln++;
585
                mvprintw(ln, 0, "PF BUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
586
                        (m_core->v__DOT__thecpu__DOT__pf_cyc)?"CYC":"   ",
587
                        (m_core->v__DOT__thecpu__DOT__pf_stb)?"STB":"   ",
588
                        "  ", // (m_core->v__DOT__thecpu__DOT__pf_we )?"WE":"  ",
589
                        (m_core->v__DOT__thecpu__DOT__pf_addr<<2),
590
                        0, // (m_core->v__DOT__thecpu__DOT__pf_data),
591
                        (m_core->v__DOT__thecpu__DOT__pf_ack)?"ACK":"   ",
592
                        (pfstall())?"STL":"   ",
593
                        (m_core->v__DOT__wb_data)); ln++;
594
#endif
595
 
596
                mvprintw(ln, 0, "MEMBUS: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x",
597
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)?"GCY"
598
                                :((m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl)?"LCY":"   "),
599
                        (m_core->v__DOT__thecpu__DOT__mem_stb_gbl)?"GSB"
600
                                :((m_core->v__DOT__thecpu__DOT__mem_stb_lcl)?"LSB":"   "),
601
                        (m_core->v__DOT__thecpu__DOT__mem_we )?"WE":"  ",
602
                        (m_core->v__DOT__thecpu__DOT__mem_addr<<2),
603
                        (m_core->v__DOT__thecpu__DOT__mem_data),
604
                        (m_core->v__DOT__thecpu__DOT__mem_ack)?"ACK":"   ",
605
                        (m_core->v__DOT__thecpu__DOT__mem_stall)?"STL":"   ",
606
                        (m_core->v__DOT__thecpu__DOT__mem_result));
607
// #define      OPT_PIPELINED_BUS_ACCESS
608
#ifdef  OPT_PIPELINED_BUS_ACCESS
609
                printw(" %x%x%c%c",
610
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
611
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
612
                        (m_core->v__DOT__thecpu__DOT__r_op_pipe)?'P':'-',
613
                        (mem_pipe_stalled())?'S':'-'); ln++;
614
#else
615
                ln++;
616
#endif
617
 
618
                mvprintw(ln, 0, "SYSBS%c: %3s %3s %s @0x%08x[0x%08x] -> %s %s %08x %s",
619
                        (m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner)?'M':'P',
620
                        (m_core->o_wb_cyc)?"CYC":"   ",
621
                        (m_core->o_wb_stb)?"STB":"   ",
622
                        (m_core->o_wb_we )?"WE":"  ",
623
                        (m_core->o_wb_addr<<2),
624
                        (m_core->o_wb_data),
625
                        (m_core->i_wb_ack)?"ACK":"   ",
626
                        (m_core->i_wb_stall)?"STL":"   ",
627
                        (m_core->i_wb_data),
628
                        (m_core->i_wb_err)?"(ER!)":"     "); ln+=2;
629
#ifdef  OPT_PIPELINED_BUS_ACCESS
630
                mvprintw(ln-1, 0, "Mem CE: %d = %d%d%d%d%d, stall: %d = %d%d(%d|%d%d|..)",
631
                        (m_core->v__DOT__thecpu__DOT__mem_ce),
632
                        (m_core->v__DOT__thecpu__DOT__master_ce),       //1
633
                        (m_core->v__DOT__thecpu__DOT__op_valid_mem),    //0
634
                        (!m_core->v__DOT__thecpu__DOT__new_pc), //1
635
                        // (!m_core->v__DOT__thecpu__DOT__clear_pipeline),      //1
636
                        (m_core->v__DOT__thecpu__DOT__set_cond),        //1
637
                        (!mem_stalled()),       //1
638
 
639
                        (mem_stalled()),
640
                        (m_core->v__DOT__thecpu__DOT__op_valid_mem),
641
                        (m_core->v__DOT__thecpu__DOT__master_ce),
642
                        (mem_pipe_stalled()),
643
                        (!m_core->v__DOT__thecpu__DOT__r_op_pipe),
644
                        (m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
645
                        );
646
                printw(" op_pipe = %d", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_pipe);
647
                // mvprintw(4,4,"r_dcdI = 0x%06x",
648
                        // (m_core->v__DOT__thecpu__DOT__dcdI)&0x0ffffff);
649
#endif
650
                mvprintw(4,42,"0x%08x", m_core->v__DOT__thecpu__DOT__pf_instruction);
651
#ifdef  OPT_SINGLE_CYCLE
652
                printw(" A:%c%c B:%c%c",
653
                        (m_core->v__DOT__thecpu__DOT__op_A_alu)?'A':'-',
654
                        (m_core->v__DOT__thecpu__DOT__op_A_mem)?'M':'-',
655
                        (m_core->v__DOT__thecpu__DOT__op_B_alu)?'A':'-',
656
                        (m_core->v__DOT__thecpu__DOT__op_B_mem)?'M':'-');
657
#else
658
                printw(" A:xx B:xx");
659
#endif
660
                printw(" PFPC=%08x", m_core->v__DOT__thecpu__DOT__pf_pc);
661
 
662
 
663
                showins(ln, "I ",
664
#ifdef  OPT_PIPELINED
665
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
666
#else
667
                        1,
668
#endif
669
                        m_core->v__DOT__thecpu__DOT__pf_valid,
670
                        //m_core->v__DOT__thecpu__DOT__instruction_gie,
671
                        m_core->v__DOT__thecpu__DOT__r_gie,
672
                        0,
673
                        (m_core->v__DOT__thecpu__DOT__pf_instruction_pc)<<2,
674
                        false); ln++;
675
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
676
 
677
                showins(ln, "Dc",
678
                        dcd_ce(), dcd_valid(),
679
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
680
#ifdef  OPT_PIPELINED
681
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
682
#else
683
                        0,
684
#endif
685
                        (m_core->v__DOT__thecpu__DOT__dcd_pc-1)<<2,
686
#ifdef  OPT_CIS
687
                        m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase
688
#else
689
                        false
690
#endif
691
                        ); ln++;
692
#ifdef  OPT_ILLEGAL_INSTRUCTION
693
                if (m_core->v__DOT__thecpu__DOT__dcd_illegal)
694
                        mvprintw(ln-1,10,"I");
695
                else
696
#endif
697
                if (m_core->v__DOT__thecpu__DOT__dcd_M)
698
                        mvprintw(ln-1,10,"M");
699
 
700
                showins(ln, "Op",
701
                        op_ce(),
702
                        m_core->v__DOT__thecpu__DOT__op_valid,
703
                        m_core->v__DOT__thecpu__DOT__r_op_gie,
704
                        m_core->v__DOT__thecpu__DOT__op_stall,
705
                        op_pc(),
706
#ifdef  OPT_CIS
707
                        m_core->v__DOT__thecpu__DOT__r_op_phase
708
#else
709
                        false
710
#endif
711
                        ); ln++;
712
#ifdef  OPT_ILLEGAL_INSTRUCTION
713
                if (m_core->v__DOT__thecpu__DOT__op_illegal)
714
                        mvprintw(ln-1,10,"I");
715
                else
716
#endif
717
                if (m_core->v__DOT__thecpu__DOT__op_valid_mem)
718
                        mvprintw(ln-1,10,"M");
719
                else if (m_core->v__DOT__thecpu__DOT__op_valid_alu)
720
                        mvprintw(ln-1,10,"A");
721
 
722
                if (m_core->v__DOT__thecpu__DOT__op_valid_mem) {
723
                        showins(ln, "Mm",
724
                                m_core->v__DOT__thecpu__DOT__mem_ce,
725
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
726
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
727
#ifdef  OPT_PIPELINED
728
                                m_core->v__DOT__thecpu__DOT__mem_stall,
729
#else
730
                                0,
731
#endif
732
                                alu_pc(),
733
#ifdef  OPT_CIS
734
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
735
#else
736
                                false
737
#endif
738
                        );
739
                } else {
740
                        showins(ln, "Al",
741
                                m_core->v__DOT__thecpu__DOT__alu_ce,
742
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
743
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
744
#ifdef  OPT_PIPELINED
745
                                m_core->v__DOT__thecpu__DOT__alu_stall,
746
#else
747
                                0,
748
#endif
749
                                alu_pc(),
750
#ifdef  OPT_CIS
751
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
752
#else
753
                                false
754
#endif
755
                        );
756
                } ln++;
757
                if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
758
                        mvprintw(ln-1,10,"W");
759
                else if (m_core->v__DOT__thecpu__DOT__alu_valid)
760
                        mvprintw(ln-1,10,(m_core->v__DOT__thecpu__DOT__alu_wR)?"w":"V");
761
                else if (m_core->v__DOT__thecpu__DOT__mem_valid)
762
                        mvprintw(ln-1,10,"v");
763
#ifdef  OPT_ILLEGAL_INSTRUCTION
764
                else if (m_core->v__DOT__thecpu__DOT__r_alu_illegal)
765
                        mvprintw(ln-1,10,"I");
766
#endif
767
                // else if (m_core->v__DOT__thecpu__DOT__alu_illegal_op)
768
                        // mvprintw(ln-1,10,"i");
769
 
770
                mvprintw(ln-5, 65,"%s %s",
771
                        (m_core->v__DOT__thecpu__DOT__r_op_break)?"OB":"  ",
772
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"CLRP":"    ");
773
                mvprintw(ln-4, 48,
774
                        (m_core->v__DOT__thecpu__DOT__new_pc)?"new-pc":"      ");
775
                printw("(%s:%02x,%x)",
776
                        (m_core->v__DOT__thecpu__DOT__set_cond)?"SET":"   ",
777
                        (m_core->v__DOT__thecpu__DOT__op_F&0x0ff),
778
                        (m_core->v__DOT__thecpu__DOT__r_op_gie)
779
                                ?  (m_core->v__DOT__thecpu__DOT__w_uflags)
780
                                : (m_core->v__DOT__thecpu__DOT__w_iflags));
781
 
782
                printw("(%s%s%s:%02x)",
783
                        (m_core->v__DOT__thecpu__DOT__op_wF)?"OF":"  ",
784
                        (m_core->v__DOT__thecpu__DOT__alu_wF)?"FL":"  ",
785
                        (m_core->v__DOT__thecpu__DOT__wr_flags_ce)?"W":" ",
786
                        (m_core->v__DOT__thecpu__DOT__alu_flags));
787
                mvprintw(ln-3, 48, "Op(%x)%8x,%8x->",
788
                        m_core->v__DOT__thecpu__DOT__r_op_opn,
789
                        m_core->v__DOT__thecpu__DOT__op_Aid,
790
                        m_core->v__DOT__thecpu__DOT__op_Bid);
791
                if (m_core->v__DOT__thecpu__DOT__alu_valid)
792
                        printw("%08x", m_core->v__DOT__thecpu__DOT__alu_result);
793
                else
794
                        printw("%8s","");
795
                mvprintw(ln-1, 48, "%s%s%s ",
796
                        (m_core->v__DOT__thecpu__DOT__alu_valid)?"A"
797
                          :((m_core->v__DOT__thecpu__DOT__doalu__DOT__r_busy)?"a":" "),
798
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"D"
799
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"d":" "),
800
                        (m_core->v__DOT__thecpu__DOT__div_valid)?"F"
801
                          :((m_core->v__DOT__thecpu__DOT__div_busy)?"f":" "));
802
                printw("MEM: %s%s %s%s %s %-5s",
803
                        (m_core->v__DOT__thecpu__DOT__op_valid_mem)?"M":" ",
804
                        (m_core->v__DOT__thecpu__DOT__mem_ce)?"CE":"  ",
805
                        (m_core->v__DOT__thecpu__DOT__mem_we)?"Wr ":"Rd ",
806
                        (mem_stalled())?"PIPE":"    ",
807
                        (m_core->v__DOT__thecpu__DOT__mem_valid)?"V":" ",
808
                        zip_regstr[(m_core->v__DOT__thecpu__DOT__mem_wreg&0x1f)^0x10]);
809
        }
810
 
811
        void    show_user_timers(bool v) {
812
                m_show_user_timers = v;
813
        }
814
 
815
        unsigned int    cmd_read(unsigned int a) {
816
                int     errcount = 0;
817
                if (m_dbgfp) {
818
                        dbg_flag= true;
819
                        fprintf(m_dbgfp, "CMD-READ(%d)\n", a);
820
                }
821
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
822
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount<MAXERR))
823
                        errcount++;
824
                if (errcount >= MAXERR) {
825
                        endwin();
826
 
827
                        printf("ERR: errcount >= MAXERR on wb_read(a=%x)\n", a);
828
                        // printf("Clear-Pipeline = %d\n", m_core->v__DOT__thecpu__DOT__clear_pipeline);
829
                        printf("cpu-dbg-stall  = %d\n", m_core->v__DOT__thecpu__DOT__r_halted);
830
                        printf("pf_cyc         = %d\n", m_core->v__DOT__thecpu__DOT__pf_cyc);
831
                        printf("mem_cyc_gbl    = %d\n", (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl));
832
                        printf("mem_cyc_lcl    = %d\n", m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl);
833
                        printf("op_valid       = %d\n", m_core->v__DOT__thecpu__DOT__op_valid);
834
                        printf("dcd_valid      = %d\n", dcd_valid()?1:0);
835
                        printf("dcd_ce         = %d\n", dcd_ce()?1:0);
836
#ifdef  OPT_PIPELINED
837
                        printf("dcd_stalled    = %d\n", m_core->v__DOT__thecpu__DOT__dcd_stalled);
838
#endif
839
                        printf("pf_valid       = %d\n", m_core->v__DOT__thecpu__DOT__pf_valid);
840
// #ifdef       OPT_EARLY_BRANCHING
841
                        // printf("dcd_early_branch=%d\n", m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk1__DOT__r_early_branch);
842
// #endif
843
 
844
                        exit(-2);
845
                }
846
 
847
                assert(errcount < MAXERR);
848
                unsigned int v = wb_read(CMD_DATA);
849
 
850
                if (dbg_flag)
851
                        fprintf(m_dbgfp, "CMD-READ(%d) = 0x%08x\n", a, v);
852
                dbg_flag = false;
853
                return v;
854
        }
855
 
856
        void    cmd_write(unsigned int a, int v) {
857
                int     errcount = 0;
858
                if ((a&0x0f)==0x0f)
859
                        dbg_flag = true;
860
                wb_write(CMD_REG, CMD_HALT|(a&0x3f));
861
                while(((wb_read(CMD_REG) & CMD_STALL) == 0)&&(errcount < MAXERR))
862
                        errcount++;
863
                assert(errcount < MAXERR);
864
                if (dbg_flag)
865
                        fprintf(m_dbgfp, "CMD-WRITE(%d) <= 0x%08x\n", a, v);
866
                wb_write(CMD_DATA, v);
867
        }
868
 
869
        bool    halted(void) {
870
                return (m_core->v__DOT__cmd_halt != 0);
871
        }
872
 
873
        void    read_state(void) {
874
                int     ln= 0;
875
                bool    gie;
876
 
877
                read_raw_state();
878
                if (m_cursor < 0)
879
                        m_cursor = 0;
880
                else if (m_cursor >= 44)
881
                        m_cursor = 43;
882
 
883
                mvprintw(ln,0, "Peripherals-RS");
884
                mvprintw(ln,40,"%-40s", "CPU State: ");
885
                {
886
                        unsigned int v = wb_read(CMD_REG);
887
                        mvprintw(ln,51, "");
888
                        if (v & 0x010000)
889
                                printw("EXT-INT ");
890
                        if ((v & 0x003000) == 0x03000)
891
                                printw("Halted ");
892
                        else if (v & 0x001000)
893
                                printw("Sleeping ");
894
                        else if (v & 0x002000)
895
                                printw("User Mod ");
896
                        if (v & 0x008000)
897
                                printw("Break-Enabled ");
898
                        if (v & 0x000080)
899
                                printw("PIC Enabled ");
900
                } ln++;
901
                showval(ln, 0, "PIC ", m_state.m_p[0], (m_cursor==0));
902
                showval(ln,20, "WDT ", m_state.m_p[1], (m_cursor==1));
903
                showval(ln,40, "WBUS", m_state.m_p[2], false);
904
                showval(ln,60, "PIC2", m_state.m_p[3], (m_cursor==3));
905
                ln++;
906
                showval(ln, 0, "TMRA", m_state.m_p[4], (m_cursor==4));
907
                showval(ln,20, "TMRB", m_state.m_p[5], (m_cursor==5));
908
                showval(ln,40, "TMRC", m_state.m_p[6], (m_cursor==6));
909
                showval(ln,60, "JIF ", m_state.m_p[7], (m_cursor==7));
910
 
911
                ln++;
912
                if (!m_show_user_timers) {
913
                        showval(ln, 0, "MTSK", m_state.m_p[12], (m_cursor==8));
914
                        showval(ln,20, "MMST", m_state.m_p[13], (m_cursor==9));
915
                        showval(ln,40, "MPST", m_state.m_p[14], (m_cursor==10));
916
                        showval(ln,60, "MICT", m_state.m_p[15], (m_cursor==11));
917
                } else {
918
                        showval(ln, 0, "UTSK", m_state.m_p[ 8], (m_cursor==8));
919
                        showval(ln,20, "UMST", m_state.m_p[ 9], (m_cursor==9));
920
                        showval(ln,40, "UPST", m_state.m_p[10], (m_cursor==10));
921
                        showval(ln,60, "UICT", m_state.m_p[11], (m_cursor==11));
922
                }
923
 
924
                ln++;
925
                ln++;
926
                unsigned int cc = m_state.m_sR[14];
927
                if (m_dbgfp) fprintf(m_dbgfp, "CC = %08x, gie = %d\n", cc,
928
                        m_core->v__DOT__thecpu__DOT__r_gie);
929
                gie = (cc & 0x020);
930
                if (gie)
931
                        attroff(A_BOLD);
932
                else
933
                        attron(A_BOLD);
934
                mvprintw(ln, 0, "Supervisor Registers");
935
                ln++;
936
 
937
                dispreg(ln, 0, "sR0 ", m_state.m_sR[ 0], (m_cursor==12));
938
                dispreg(ln,20, "sR1 ", m_state.m_sR[ 1], (m_cursor==13));
939
                dispreg(ln,40, "sR2 ", m_state.m_sR[ 2], (m_cursor==14));
940
                dispreg(ln,60, "sR3 ", m_state.m_sR[ 3], (m_cursor==15)); ln++;
941
 
942
                dispreg(ln, 0, "sR4 ", m_state.m_sR[ 4], (m_cursor==16));
943
                dispreg(ln,20, "sR5 ", m_state.m_sR[ 5], (m_cursor==17));
944
                dispreg(ln,40, "sR6 ", m_state.m_sR[ 6], (m_cursor==18));
945
                dispreg(ln,60, "sR7 ", m_state.m_sR[ 7], (m_cursor==19)); ln++;
946
 
947
                dispreg(ln, 0, "sR8 ", m_state.m_sR[ 8], (m_cursor==20));
948
                dispreg(ln,20, "sR9 ", m_state.m_sR[ 9], (m_cursor==21));
949
                dispreg(ln,40, "sR10", m_state.m_sR[10], (m_cursor==22));
950
                dispreg(ln,60, "sR11", m_state.m_sR[11], (m_cursor==23)); ln++;
951
 
952
                dispreg(ln, 0, "sR12", m_state.m_sR[12], (m_cursor==24));
953
                dispreg(ln,20, "sSP ", m_state.m_sR[13], (m_cursor==25));
954
 
955
                if (true) {
956
                        mvprintw(ln,40, "%ssCC : 0x%08x",
957
                                (m_cursor==26)?">":" ", cc);
958
                } else {
959
                        mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
960
                                (m_cursor==26)?">":" ",
961
                                (cc&0x01000)?"FE":"",
962
                                (cc&0x00800)?"DE":"",
963
                                (cc&0x00400)?"BE":"",
964
                                (cc&0x00200)?"TP":"",
965
                                (cc&0x00100)?"IL":"",
966
                                (cc&0x00080)?"BK":"",
967
                                ((m_state.m_gie==0)&&(cc&0x010))?"HLT":"");
968
                        mvprintw(ln, 54, "%s%s%s%s",
969
                                (cc&8)?"V":" ",
970
                                (cc&4)?"N":" ",
971
                                (cc&2)?"C":" ",
972
                                (cc&1)?"Z":" ");
973
                }
974
                dispreg(ln,60, "sPC ", cmd_read(15), (m_cursor==27));
975
                ln++;
976
 
977
                if (gie)
978
                        attron(A_BOLD);
979
                else
980
                        attroff(A_BOLD);
981
                mvprintw(ln, 0, "User Registers");
982
                mvprintw(ln, 42, "DCDR=%02x %s",
983
                        dcd_R(), (m_core->v__DOT__thecpu__DOT__dcd_wR)?"W":" ");
984
                mvprintw(ln, 62, "OPR =%02x %s%s",
985
                        m_core->v__DOT__thecpu__DOT__r_op_R,
986
                        (m_core->v__DOT__thecpu__DOT__op_wR)?"W":" ",
987
                        (m_core->v__DOT__thecpu__DOT__op_wF)?"F":" ");
988
                ln++;
989
                dispreg(ln, 0, "uR0 ", m_state.m_uR[ 0], (m_cursor==28));
990
                dispreg(ln,20, "uR1 ", m_state.m_uR[ 1], (m_cursor==29));
991
                dispreg(ln,40, "uR2 ", m_state.m_uR[ 2], (m_cursor==30));
992
                dispreg(ln,60, "uR3 ", m_state.m_uR[ 3], (m_cursor==31)); ln++;
993
 
994
                dispreg(ln, 0, "uR4 ", m_state.m_uR[ 4], (m_cursor==32));
995
                dispreg(ln,20, "uR5 ", m_state.m_uR[ 5], (m_cursor==33));
996
                dispreg(ln,40, "uR6 ", m_state.m_uR[ 6], (m_cursor==34));
997
                dispreg(ln,60, "uR7 ", m_state.m_uR[ 7], (m_cursor==35)); ln++;
998
 
999
                dispreg(ln, 0, "uR8 ", m_state.m_uR[ 8], (m_cursor==36));
1000
                dispreg(ln,20, "uR9 ", m_state.m_uR[ 9], (m_cursor==37));
1001
                dispreg(ln,40, "uR10", m_state.m_uR[10], (m_cursor==38));
1002
                dispreg(ln,60, "uR11", m_state.m_uR[11], (m_cursor==39)); ln++;
1003
 
1004
                dispreg(ln, 0, "uR12", m_state.m_uR[12], (m_cursor==40));
1005
                dispreg(ln,20, "uSP ", m_state.m_uR[13], (m_cursor==41));
1006
                cc = m_state.m_uR[14];
1007
                if (false) {
1008
                        mvprintw(ln,40, "%cuCC : 0x%08x",
1009
                                (m_cursor == 42)?'>':' ', cc);
1010
                } else {
1011
                        mvprintw(ln,40, "%cuCC :%s%s%s%s%s%s%s",
1012
                                (m_cursor == 42)?'>':' ',
1013
                                (cc & 0x1000)?"FE":"",
1014
                                (cc & 0x0800)?"DE":"",
1015
                                (cc & 0x0400)?"BE":"",
1016
                                (cc & 0x0200)?"TP":"",
1017
                                (cc & 0x0100)?"IL":"",
1018
                                (cc & 0x0040)?"ST":"",
1019
                                ((m_state.m_gie)&&(cc & 0x010))?"SL":"");
1020
                        mvprintw(ln, 54, "%s%s%s%s",
1021
                                (cc&8)?"V":" ",
1022
                                (cc&4)?"N":" ",
1023
                                (cc&2)?"C":" ",
1024
                                (cc&1)?"Z":" ");
1025
                }
1026
                dispreg(ln,60, "uPC ", m_state.m_uR[15], (m_cursor==43));
1027
 
1028
                attroff(A_BOLD);
1029
                ln+=2;
1030
 
1031
                ln+=3;
1032
 
1033
                showins(ln, "I ",
1034
#ifdef  OPT_PIPELINED
1035
                        !m_core->v__DOT__thecpu__DOT__dcd_stalled,
1036
#else
1037
                        1,
1038
#endif
1039
                        m_core->v__DOT__thecpu__DOT__pf_valid,
1040
                        m_core->v__DOT__thecpu__DOT__r_gie,
1041
                        0,
1042
                        m_core->v__DOT__thecpu__DOT__pf_instruction_pc,
1043
                        true); ln++;
1044
                        // m_core->v__DOT__thecpu__DOT__pf_pc); ln++;
1045
 
1046
                showins(ln, "Dc",
1047
                        dcd_ce(), dcd_valid(),
1048
                        m_core->v__DOT__thecpu__DOT__dcd_gie,
1049
#ifdef  OPT_PIPELINED
1050
                        m_core->v__DOT__thecpu__DOT__dcd_stalled,
1051
#else
1052
                        0,
1053
#endif
1054
                        m_core->v__DOT__thecpu__DOT__dcd_pc-1,
1055
#ifdef  OPT_CIS
1056
                        m_core->v__DOT__thecpu__DOT__dcd_phase
1057
#else
1058
                        false
1059
#endif
1060
                        ); ln++;
1061
 
1062
                showins(ln, "Op",
1063
                        op_ce(),
1064
                        m_core->v__DOT__thecpu__DOT__op_valid,
1065
                        m_core->v__DOT__thecpu__DOT__r_op_gie,
1066
                        m_core->v__DOT__thecpu__DOT__op_stall,
1067
                        op_pc(),
1068
#ifdef  OPT_CIS
1069
                        m_core->v__DOT__thecpu__DOT__r_op_phase
1070
#else
1071
                        false
1072
#endif
1073
                        ); ln++;
1074
 
1075
                if (m_core->v__DOT__thecpu__DOT__op_valid_mem) {
1076
                        showins(ln, "Mm",
1077
                                m_core->v__DOT__thecpu__DOT__mem_ce,
1078
                                m_core->v__DOT__thecpu__DOT__mem_pc_valid,
1079
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
1080
#ifdef  OPT_PIPELINED
1081
                                m_core->v__DOT__thecpu__DOT__mem_stall,
1082
#else
1083
                                0,
1084
#endif
1085
                                alu_pc(),
1086
#ifdef  OPT_CIS
1087
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
1088
#else
1089
                                false
1090
#endif
1091
                        );
1092
                } else {
1093
                        showins(ln, "Al",
1094
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1095
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1096
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
1097
#ifdef  OPT_PIPELINED
1098
                                m_core->v__DOT__thecpu__DOT__alu_stall,
1099
#else
1100
                                0,
1101
#endif
1102
                                alu_pc(),
1103
#ifdef  OPT_CIS
1104
                                m_core->v__DOT__thecpu__DOT__r_alu_phase
1105
#else
1106
                                false
1107
#endif
1108
                        );
1109
                } ln++;
1110
        }
1111
 
1112
        void    tick(void) {
1113
                int gie = m_core->v__DOT__thecpu__DOT__r_gie;
1114
                /*
1115
                m_core->i_qspi_dat = m_flash(m_core->o_qspi_cs_n,
1116
                                                m_core->o_qspi_sck,
1117
                                                m_core->o_qspi_dat);
1118
                */
1119
 
1120
                int stb = m_core->o_wb_stb, mask = (RAMBASE-1);
1121
                unsigned addr = m_core->o_wb_addr<<2;
1122
 
1123
                m_core->i_wb_err = 0;
1124
                if ((addr & (~mask))!=RAMBASE)
1125
                        stb = 0;
1126
                if ((m_core->o_wb_cyc)&&(m_core->o_wb_stb)&&(!stb)) {
1127
                        m_core->i_wb_ack = 1;
1128
                        m_core->i_wb_err = 1;
1129
                        m_bomb = true;
1130
                        if (m_dbgfp) fprintf(m_dbgfp,
1131
                                "BOMB!! (Attempting to access %08x/%08x->%08x)\n",
1132
                                addr, RAMBASE, ((addr)&(~mask)));
1133
                } else if ((!m_core->o_wb_cyc)&&(m_core->o_wb_stb)) {
1134
                        if (m_dbgfp) fprintf(m_dbgfp,
1135
                                "BOMB!! (Strobe high, CYC low)\n");
1136
                        m_bomb = true;
1137
                }
1138
 
1139
                if ((dbg_flag)&&(m_dbgfp)) {
1140
                        fprintf(m_dbgfp, "BUS  %s %s %s @0x%08x/[0x%08x 0x%08x] %s %s\n",
1141
                                (m_core->o_wb_cyc)?"CYC":"   ",
1142
                                (m_core->o_wb_stb)?"STB":"   ",
1143
                                (m_core->o_wb_we)?"WE":"  ",
1144
                                (m_core->o_wb_addr<<2),
1145
                                (m_core->o_wb_data),
1146
                                (m_core->i_wb_data),
1147
                                (m_core->i_wb_stall)?"STALL":"     ",
1148
                                (m_core->i_wb_ack)?"ACK":"   ");
1149
                        fprintf(m_dbgfp, "DBG  %s %s %s @0x%08x/%d[0x%08x] %s %s [0x%08x] %s %s %s%s%s%s%s%s%s%s%s\n",
1150
                                (m_core->i_dbg_cyc)?"CYC":"   ",
1151
                                (m_core->i_dbg_stb)?"STB":
1152
                                        ((m_core->v__DOT__dbg_stb)?"DBG":"   "),
1153
                                ((m_core->i_dbg_we)?"WE":"  "),
1154
                                (m_core->i_dbg_addr),0,
1155
                                m_core->i_dbg_data,
1156
                                (m_core->o_dbg_ack)?"ACK":"   ",
1157
                                (m_core->o_dbg_stall)?"STALL":"     ",
1158
                                (m_core->o_dbg_data),
1159
                                (m_core->v__DOT__cpu_halt)?"CPU-HALT ":"",
1160
                                (m_core->v__DOT__thecpu__DOT__r_halted)?"CPU-DBG_STALL":"",
1161
                                (dcd_valid())?"DCDV ":"",
1162
                                (m_core->v__DOT__thecpu__DOT__op_valid)?"OPV ":"",
1163
                                (m_core->v__DOT__thecpu__DOT__pf_cyc)?"PCYC ":"",
1164
                                (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)?"GC":"  ",
1165
                                (m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl)?"LC":"  ",
1166
                                (m_core->v__DOT__thecpu__DOT__alu_wR)?"ALUW ":"",
1167
                                (m_core->v__DOT__thecpu__DOT__alu_ce)?"ALCE ":"",
1168
                                (m_core->v__DOT__thecpu__DOT__alu_valid)?"ALUV ":"",
1169
                                (m_core->v__DOT__thecpu__DOT__mem_valid)?"MEMV ":"");
1170
                        fprintf(m_dbgfp, " SYS %s %s %s @0x%08x/%d[0x%08x] %s [0x%08x]\n",
1171
                                (m_core->v__DOT__sys_cyc)?"CYC":"   ",
1172
                                (m_core->v__DOT__sys_stb)?"STB":"   ",
1173
                                (m_core->v__DOT__sys_we)?"WE":"  ",
1174
                                (m_core->v__DOT__sys_addr<<2),
1175
                                (m_core->v__DOT__dbg_addr<<2),
1176
                                (m_core->v__DOT__sys_data),
1177
                                (m_core->v__DOT__dbg_ack)?"ACK":"   ",
1178
                                (m_core->v__DOT__wb_data));
1179
                }
1180
 
1181
                if (m_dbgfp)
1182
                        fprintf(m_dbgfp, "CEs %d/0x%08x,%d/0x%08x DCD: ->%02x, OP: ->%02x, ALU: halt=%d,%d ce=%d, valid=%d, wr=%d  Reg=%02x, IPC=%08x, UPC=%08x\n",
1183
                                dcd_ce(),
1184
                                m_core->v__DOT__thecpu__DOT__dcd_pc,
1185
                                op_ce(),
1186
                                op_pc(),
1187
                                dcd_Aid()&0x01f,
1188
                                m_core->v__DOT__thecpu__DOT__r_op_R,
1189
                                m_core->v__DOT__cmd_halt,
1190
                                m_core->v__DOT__cpu_halt,
1191
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1192
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1193
                                m_core->v__DOT__thecpu__DOT__alu_wR,
1194
                                m_core->v__DOT__thecpu__DOT__alu_reg,
1195
                                m_core->v__DOT__thecpu__DOT__ipc,
1196
                                m_core->v__DOT__thecpu__DOT__r_upc);
1197
 
1198
                if ((m_dbgfp)&&(!gie)&&(m_core->v__DOT__thecpu__DOT__w_release_from_interrupt)) {
1199
                        fprintf(m_dbgfp, "RELEASE: int=%d, %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d\n",
1200
                                m_core->v__DOT__genblk9__DOT__pic__DOT__r_interrupt,
1201
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1202
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1203
                                m_core->v__DOT__thecpu__DOT__wr_spreg_vl,
1204
                                m_core->v__DOT__cmd_addr<<2,
1205
                                m_core->v__DOT__dbg_idata,
1206
                                m_core->v__DOT__thecpu__DOT__master_ce,
1207
                                m_core->v__DOT__thecpu__DOT__alu_wR,
1208
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1209
                                m_core->v__DOT__thecpu__DOT__mem_valid);
1210
                } else if ((m_dbgfp)&&(gie)&&(m_core->v__DOT__thecpu__DOT__w_switch_to_interrupt)) {
1211
                        fprintf(m_dbgfp, "SWITCH: %d/%02x[%08x] ?/%02x[0x%08x], ce=%d %d,%d,%d, F%02x,%02x\n",
1212
                                m_core->v__DOT__thecpu__DOT__wr_reg_ce,
1213
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1214
                                m_core->v__DOT__thecpu__DOT__wr_spreg_vl,
1215
                                m_core->v__DOT__cmd_addr<<2,
1216
                                m_core->v__DOT__dbg_idata,
1217
                                m_core->v__DOT__thecpu__DOT__master_ce,
1218
                                m_core->v__DOT__thecpu__DOT__alu_wR,
1219
                                m_core->v__DOT__thecpu__DOT__alu_valid,
1220
                                m_core->v__DOT__thecpu__DOT__mem_valid,
1221
                                m_core->v__DOT__thecpu__DOT__w_iflags,
1222
                                m_core->v__DOT__thecpu__DOT__w_uflags);
1223
                        fprintf(m_dbgfp, "\tbrk=%s %d,%d\n",
1224
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1225
                                m_core->v__DOT__thecpu__DOT__break_en,
1226
                                m_core->v__DOT__thecpu__DOT__r_op_break);
1227
                } else if ((m_dbgfp)&&
1228
                                ((m_core->v__DOT__thecpu__DOT__r_op_break)
1229
                                ||(m_core->v__DOT__thecpu__DOT__r_alu_illegal)
1230
                                ||(m_core->v__DOT__thecpu__DOT__dcd_break))) {
1231
                        fprintf(m_dbgfp, "NOT SWITCHING TO GIE (gie = %d)\n", gie);
1232
                        fprintf(m_dbgfp, "\tbrk=%s breaken=%d,dcdbreak=%d,opbreak=%d,alu_illegal=%d\n",
1233
                                (m_core->v__DOT__thecpu__DOT__master_ce)?"CE":"  ",
1234
                                m_core->v__DOT__thecpu__DOT__break_en,
1235
                                m_core->v__DOT__thecpu__DOT__dcd_break,
1236
                                m_core->v__DOT__thecpu__DOT__r_op_break,
1237
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal);
1238
                }
1239
 
1240
                if (m_dbgfp) {
1241
                        // if(m_core->v__DOT__thecpu__DOT__clear_pipeline)
1242
                                // fprintf(m_dbgfp, "\tClear Pipeline\n");
1243
                        if(m_core->v__DOT__thecpu__DOT__new_pc)
1244
                                fprintf(m_dbgfp, "\tNew PC\n");
1245
                }
1246
 
1247
                if (m_dbgfp)
1248
                        fprintf(m_dbgfp, "-----------  TICK (%08x) ----------%s\n",
1249
                                m_core->v__DOT__jiffies__DOT__r_counter,
1250
                                (m_bomb)?" BOMBED!!":"");
1251
                m_mem(m_core->o_wb_cyc, m_core->o_wb_stb, m_core->o_wb_we,
1252
                        m_core->o_wb_addr & mask, m_core->o_wb_data, m_core->o_wb_sel & 0x0f,
1253
                        m_core->i_wb_ack, m_core->i_wb_stall,m_core->i_wb_data);
1254
 
1255
 
1256
                TESTB<Vzipsystem>::tick();
1257
 
1258
                if ((m_dbgfp)&&(gie != m_core->v__DOT__thecpu__DOT__r_gie)) {
1259
                        fprintf(m_dbgfp, "SWITCH FROM %s to %s: sPC = 0x%08x uPC = 0x%08x pf_pc = 0x%08x\n",
1260
                                (gie)?"User":"Supervisor",
1261
                                (gie)?"Supervisor":"User",
1262
                                m_core->v__DOT__thecpu__DOT__ipc,
1263
                                m_core->v__DOT__thecpu__DOT__r_upc,
1264
                                m_core->v__DOT__thecpu__DOT__pf_pc);
1265
                } if (m_dbgfp) {
1266
#ifdef  OPT_TRADITIONAL_PFCACHE
1267
                        fprintf(m_dbgfp, "PFCACHE %s(%08x,%08x%s),%08x - %08x %s%s%s\n",
1268
                                (m_core->v__DOT__thecpu__DOT__new_pc)?"N":" ",
1269
                                m_core->v__DOT__thecpu__DOT__pf_pc,
1270
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_branch_pc,
1271
                                ((m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__genblk3__DOT__r_early_branch)
1272
                                &&(dcd_valid())
1273
                                &&(!m_core->v__DOT__thecpu__DOT__new_pc))?"V":"-",
1274
                                m_core->v__DOT__thecpu__DOT__pf__DOT__lastpc,
1275
                                m_core->v__DOT__thecpu__DOT__pf_instruction_pc,
1276
                                (m_core->v__DOT__thecpu__DOT__pf__DOT__r_v)?"R":" ",
1277
                                (m_core->v__DOT__thecpu__DOT__pf_valid)?"V":" ",
1278
                                (m_core->v__DOT__thecpu__DOT__pf_illegal)?"I":" ");
1279
#endif
1280
                        dbgins("Dc - ",
1281
                                dcd_ce(), dcd_valid(),
1282
                                m_core->v__DOT__thecpu__DOT__dcd_gie,
1283
#ifdef  OPT_PIPELINED
1284
                                m_core->v__DOT__thecpu__DOT__dcd_stalled,
1285
#else
1286
                                0,
1287
#endif
1288
                                (m_core->v__DOT__thecpu__DOT__dcd_pc-1)<<2,
1289
#ifdef  OPT_CIS
1290
                                m_core->v__DOT__thecpu__DOT__instruction_decoder__DOT__r_phase,
1291
#else
1292
                                false,
1293
#endif
1294
#ifdef  OPT_ILLEGAL_INSTRUCTION
1295
                                m_core->v__DOT__thecpu__DOT__dcd_illegal
1296
#else
1297
                                false
1298
#endif
1299
                                );
1300
                        if (m_dbgfp) {
1301
                                fprintf(m_dbgfp, "\t\t\tR[%2d] = (*Dc=%d%s)[ A[%2d], B[%2d] + %08x], dcd_pc = %08x\n",
1302
                                        m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber14,
1303
                                        m_core->v__DOT__thecpu__DOT__dcd_opn,
1304
                                        (m_core->v__DOT__thecpu__DOT__dcd_M)?"M":" ",
1305
                                        m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber15&0x0f,
1306
                                        m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber16&0x0f,
1307
                                        m_core->v__DOT__thecpu__DOT__dcd_I,
1308
                                        m_core->v__DOT__thecpu__DOT__dcd_pc);
1309
                        }
1310
                        dbgins("Op - ",
1311
                                op_ce(),
1312
                                m_core->v__DOT__thecpu__DOT__op_valid,
1313
                                m_core->v__DOT__thecpu__DOT__r_op_gie,
1314
                                m_core->v__DOT__thecpu__DOT__op_stall,
1315
                                op_pc(),
1316
#ifdef  OPT_CIS
1317
                                m_core->v__DOT__thecpu__DOT__r_op_phase,
1318
#else
1319
                                false,
1320
#endif
1321
#ifdef  OPT_ILLEGAL_INSTRUCTION
1322
                                m_core->v__DOT__thecpu__DOT__op_illegal
1323
#else
1324
                                false
1325
#endif
1326
                                );
1327
                        if (m_dbgfp) {
1328
                                fprintf(m_dbgfp, "\t\t\t(*OP=%d)[ A = 0x%08x , B = 0x%08x ], op_pc= %08x\n",
1329
                                        m_core->v__DOT__thecpu__DOT__r_op_opn,
1330
                                        m_core->v__DOT__thecpu__DOT__op_Av,
1331
                                        m_core->v__DOT__thecpu__DOT__op_Bv,
1332
                                        m_core->v__DOT__thecpu__DOT__op_pc);
1333
                        }
1334
                        dbgins("Al - ",
1335
                                m_core->v__DOT__thecpu__DOT__alu_ce,
1336
                                m_core->v__DOT__thecpu__DOT__alu_pc_valid,
1337
                                m_core->v__DOT__thecpu__DOT__r_alu_gie,
1338
#ifdef  OPT_PIPELINED
1339
                                m_core->v__DOT__thecpu__DOT__alu_stall,
1340
#else
1341
                                0,
1342
#endif
1343
                                alu_pc(),
1344
#ifdef  OPT_CIS
1345
                                m_core->v__DOT__thecpu__DOT__r_alu_phase,
1346
#else
1347
                                false,
1348
#endif
1349
#ifdef  OPT_ILLEGAL_INSTRUCTION
1350
                                m_core->v__DOT__thecpu__DOT__r_alu_illegal
1351
#else
1352
                                false
1353
#endif
1354
                                );
1355
                        if (m_core->v__DOT__thecpu__DOT__wr_reg_ce)
1356
                                fprintf(m_dbgfp, "WB::Reg[%2x] <= %08x\n",
1357
                                        m_core->v__DOT__thecpu__DOT__wr_reg_id,
1358
                                        m_core->v__DOT__thecpu__DOT__wr_gpreg_vl);
1359
 
1360
                }
1361
 
1362
                if ((m_dbgfp)&&((m_core->v__DOT__thecpu__DOT__div_valid)
1363
                        ||(m_core->v__DOT__thecpu__DOT__div_ce)
1364
                        ||(m_core->v__DOT__thecpu__DOT__div_busy)
1365
                        )) {
1366
                        fprintf(m_dbgfp, "DIV: %s %s %s %s[%2x] GP:%08x/SP:%08x %s:0x%08x\n",
1367
                                (m_core->v__DOT__thecpu__DOT__div_ce)?"CE":"  ",
1368
                                (m_core->v__DOT__thecpu__DOT__div_busy)?"BUSY":"    ",
1369
                                (m_core->v__DOT__thecpu__DOT__div_valid)?"VALID":"     ",
1370
                                (m_core->v__DOT__thecpu__DOT__wr_reg_ce)?"REG-CE":"      ",
1371
                                m_core->v__DOT__thecpu__DOT__wr_reg_id,
1372
                                m_core->v__DOT__thecpu__DOT__wr_gpreg_vl,
1373
                                m_core->v__DOT__thecpu__DOT__wr_spreg_vl,
1374
                                (m_core->v__DOT__thecpu__DOT__alu_pc_valid)?"PCV":"   ",
1375
                                alu_pc());
1376
 
1377
                        fprintf(m_dbgfp, "ALU-PC: %08x %s %s\n",
1378
                                alu_pc(),
1379
                                (m_core->v__DOT__thecpu__DOT__r_alu_pc_valid)?"VALID":"",
1380
                                (m_core->v__DOT__thecpu__DOT__r_alu_gie)?"ALU-GIE":"");
1381
                }
1382
 
1383
                if (m_core->v__DOT__dma_controller__DOT__dma_state) {
1384
                        fprintf(m_dbgfp, "DMA[%d]%s%s%s%s@%08x,%08x [%d%d/%4d/%4d] -> [%d%d/%04d/%04d]\n",
1385
                                m_core->v__DOT__dma_controller__DOT__dma_state,
1386
                                (m_core->v__DOT__dc_cyc)?"C":" ",
1387
                                (m_core->v__DOT__dc_stb)?"S":" ",
1388
                                (m_core->v__DOT__dc_ack)?"A":" ",
1389
                                (m_core->v__DOT__dc_err)?"E":" ",
1390
                                m_core->v__DOT__dc_addr<<2,
1391
                                (m_core->v__DOT__dc_data),
1392
                                m_core->v__DOT__dma_controller__DOT__last_read_request,
1393
                                m_core->v__DOT__dma_controller__DOT__last_read_ack,
1394
                                m_core->v__DOT__dma_controller__DOT__nracks,
1395
                                m_core->v__DOT__dma_controller__DOT__nread,
1396
                                m_core->v__DOT__dma_controller__DOT__last_write_request,
1397
                                m_core->v__DOT__dma_controller__DOT__last_write_ack,
1398
                                m_core->v__DOT__dma_controller__DOT__nwacks,
1399
                                m_core->v__DOT__dma_controller__DOT__nwritten);
1400
                }
1401
                if (((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1402
                        ||(m_core->v__DOT__thecpu__DOT__mem_pc_valid))
1403
                        &&(!m_core->v__DOT__thecpu__DOT__new_pc)) {
1404
                        unsigned long iticks = m_tickcount - m_last_instruction_tickcount;
1405
                        if (m_profile_fp) {
1406
                                unsigned buf[2];
1407
                                buf[0] = alu_pc();
1408
                                buf[1] = iticks;
1409
                                fwrite(buf, sizeof(unsigned), 2, m_profile_fp);
1410
                        }
1411
                        m_last_instruction_tickcount = m_tickcount;
1412
                }
1413
        }
1414
 
1415
        bool    test_success(void) {
1416
                return ((!m_core->v__DOT__thecpu__DOT__r_gie)
1417
                        &&(m_core->v__DOT__thecpu__DOT__sleep));
1418
        }
1419
 
1420
        unsigned        op_pc(void) {
1421
                return (m_core->v__DOT__thecpu__DOT__op_pc<<2)-4;
1422
        }
1423
 
1424
        bool    dcd_ce(void) {
1425
                if (m_core->v__DOT__thecpu__DOT__new_pc)
1426
                        return false;
1427
                if (!dcd_valid())
1428
                        return true;
1429
                if (!m_core->v__DOT__thecpu__DOT__dcd_stalled)
1430
                        return true;
1431
                return false;
1432
        } bool  dcd_valid(void) {
1433
                return (m_core->v__DOT__thecpu__DOT__r_dcd_valid !=0);
1434
        }
1435
        bool    pfstall(void) {
1436
                return((!(m_core->v__DOT__thecpu__DOT__pformem__DOT__r_a_owner))
1437
                        ||(m_core->v__DOT__cpu_stall));
1438
        }
1439
        unsigned        dcd_R(void) {
1440
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber14);
1441
        }
1442
        unsigned        dcd_Aid(void) {
1443
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber15);
1444
        }
1445
        unsigned        dcd_Bid(void) {
1446
                return (m_core->v__DOT__thecpu__DOT____Vcellout__instruction_decoder____pinNumber16);
1447
        }
1448
 
1449
        bool    op_ce(void) {
1450
                return  dcd_valid();
1451
        } bool  op_valid(void) {
1452
                return (m_core->v__DOT__thecpu__DOT__op_valid !=0);
1453
        }
1454
 
1455
        bool    mem_busy(void) {
1456
                // return m_core->v__DOT__thecpu__DOT__mem_busy;
1457
#ifdef  OPT_PIPELINED
1458
                return m_core->v__DOT__thecpu__DOT__domem__DOT__cyc;
1459
#else
1460
                return 0;
1461
#endif
1462
        }
1463
 
1464
        bool    mem_stalled(void) {
1465
                bool    a, b, c, d, wr_write_cc, wr_write_pc, op_gie;
1466
 
1467
                wr_write_cc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0e);
1468
                wr_write_pc=((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x0f)==0x0f);
1469
                op_gie = m_core->v__DOT__thecpu__DOT__r_op_gie;
1470
 
1471
#ifdef  OPT_PIPELINED_BUS_ACCESS
1472
                //a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1473
                a = mem_pipe_stalled();
1474
                b = (!m_core->v__DOT__thecpu__DOT__r_op_pipe)&&(mem_busy());
1475
#else
1476
                a = false;
1477
                b = false;
1478
#endif
1479
                d = ((wr_write_pc)||(wr_write_cc));
1480
                c = ((m_core->v__DOT__thecpu__DOT__wr_reg_ce)
1481
                        &&(((m_core->v__DOT__thecpu__DOT__wr_reg_id&0x010)?true:false)==op_gie)
1482
                        &&d);
1483
                d =(m_core->v__DOT__thecpu__DOT__op_valid_mem)&&((a)||(b)||(c));
1484
                return ((!m_core->v__DOT__thecpu__DOT__master_ce)||(d));
1485
        }
1486
 
1487
        unsigned        alu_pc(void) {
1488
                /*
1489
                unsigned        r = op_pc();
1490
                if (m_core->v__DOT__thecpu__DOT__op_valid)
1491
                        r--;
1492
                return r;
1493
                */
1494
                return (m_core->v__DOT__thecpu__DOT__r_alu_pc<<2)-4;
1495
        }
1496
 
1497
#ifdef  OPT_PIPELINED_BUS_ACCESS
1498
        bool    mem_pipe_stalled(void) {
1499
                int     r = 0;
1500
                r = ((m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_gbl)
1501
                 ||(m_core->v__DOT__thecpu__DOT__domem__DOT__r_wb_cyc_lcl));
1502
                r = r && ((m_core->v__DOT__thecpu__DOT__mem_stall)
1503
                        ||(
1504
                                ((!m_core->v__DOT__thecpu__DOT__mem_stb_gbl)
1505
                                &&(!m_core->v__DOT__thecpu__DOT__mem_stb_lcl))));
1506
                return r;
1507
                // return m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
1508
        }
1509
#endif
1510
 
1511
        bool    test_failure(void) {
1512
                if (m_core->v__DOT__thecpu__DOT__sleep)
1513
                        return 0;
1514
                else if (m_core->v__DOT__thecpu__DOT__r_gie)
1515
                        return (m_mem[m_core->v__DOT__thecpu__DOT__r_upc] == 0x7bc3dfff);
1516
                else if (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7883ffff)
1517
                        return true; // ADD to PC instruction
1518
                else // MOV to PC instruction
1519
                        return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7bc3dfff);
1520
                /*
1521
                return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
1522
                        &&(m_mem[alu_pc()] == 0x2f0f7fff)
1523
                        &&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
1524
                */
1525
        }
1526
 
1527
        void    wb_write(unsigned a, unsigned int v) {
1528
                int     errcount = 0;
1529
                mvprintw(0,35, "%40s", "");
1530
                mvprintw(0,40, "wb_write(%d,%x)", a, v);
1531
                m_core->i_dbg_cyc = 1;
1532
                m_core->i_dbg_stb = 1;
1533
                m_core->i_dbg_we  = 1;
1534
                m_core->i_dbg_addr = (a>>2) & 1;
1535
                m_core->i_dbg_data = v;
1536
 
1537
                while((errcount++ < 100)&&(m_core->o_dbg_stall))
1538
                        tick();
1539
                tick();
1540
 
1541
                m_core->i_dbg_stb = 0;
1542
                while((errcount++ < 100)&&(!m_core->o_dbg_ack))
1543
                        tick();
1544
 
1545
                // Release the bus
1546
                m_core->i_dbg_cyc = 0;
1547
                m_core->i_dbg_stb = 0;
1548
                tick();
1549
                mvprintw(0,35, "%40s", "");
1550
                mvprintw(0,40, "wb_write -- complete");
1551
 
1552
 
1553
                if (errcount >= 100) {
1554
                        if (m_dbgfp) fprintf(m_dbgfp, "WB-WRITE: ERRCount = %d, BOMB!!\n", errcount);
1555
                        m_bomb = true;
1556
                }
1557
        }
1558
 
1559
        unsigned long   wb_read(unsigned a) {
1560
                unsigned int    v;
1561
                int     errcount = 0;
1562
                mvprintw(0,35, "%40s", "");
1563
                mvprintw(0,40, "wb_read(0x%08x)", a);
1564
                m_core->i_dbg_cyc = 1;
1565
                m_core->i_dbg_stb = 1;
1566
                m_core->i_dbg_we  = 0;
1567
                m_core->i_dbg_addr = (a>>2) & 1;
1568
 
1569
                while((errcount++<100)&&(m_core->o_dbg_stall))
1570
                        tick();
1571
                tick();
1572
 
1573
                m_core->i_dbg_stb = 0;
1574
                while((errcount++<100)&&(!m_core->o_dbg_ack))
1575
                        tick();
1576
                v = m_core->o_dbg_data;
1577
 
1578
                // Release the bus
1579
                m_core->i_dbg_cyc = 0;
1580
                m_core->i_dbg_stb = 0;
1581
                tick();
1582
 
1583
                mvprintw(0,35, "%40s", "");
1584
                mvprintw(0,40, "wb_read = 0x%08x", v);
1585
 
1586
                if (errcount >= 100) {
1587
                        if (m_dbgfp) fprintf(m_dbgfp, "WB-READ: ERRCount = %d, BOMB!!\n", errcount);
1588
                        m_bomb = true;
1589
                }
1590
                return v;
1591
        }
1592
 
1593
        void    cursor_up(void) {
1594
                if (m_cursor > 3)
1595
                        m_cursor -= 4;
1596
        } void  cursor_down(void) {
1597
                if (m_cursor < 40)
1598
                        m_cursor += 4;
1599
        } void  cursor_left(void) {
1600
                if (m_cursor > 0)
1601
                        m_cursor--;
1602
                else    m_cursor = 43;
1603
        } void  cursor_right(void) {
1604
                if (m_cursor < 43)
1605
                        m_cursor++;
1606
                else    m_cursor = 0;
1607
        }
1608
 
1609
        int     cursor(void) { return m_cursor; }
1610
 
1611
        void    jump_to(ZIPI address) {
1612
                if (m_dbgfp)
1613
                        fprintf(m_dbgfp, "JUMP_TO(%08x) ... Setting PC to %08x\n", address, address & -4);
1614
                m_core->v__DOT__thecpu__DOT__pf_pc = address & -4;
1615
                m_core->v__DOT__thecpu__DOT__pf_request_address = address >> 2;
1616
                // m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1617
                m_core->v__DOT__thecpu__DOT__new_pc = 1;
1618
        }
1619
 
1620
        void    dump_state(void) {
1621
                if (m_dbgfp)
1622
                        dump_state(m_dbgfp);
1623
        }
1624
 
1625
        void    dump_state(FILE *fp) {
1626
                if (!fp)
1627
                        return;
1628
                fprintf(fp, "FINAL STATE: %s\n",
1629
                        (m_state.m_gie)?"GIE(User-Mode)":"Supervisor-mode");
1630
                fprintf(fp, "Supervisor Registers\n");
1631
                for(int i=0; i<16; i++) {
1632
                        char str[16];
1633
                        if (i==13)
1634
                                sprintf(str, "sSP");
1635
                        else if (i==14)
1636
                                sprintf(str, "sCC");
1637
                        else if (i==15)
1638
                                sprintf(str, "sPC");
1639
                        else // if (i<=12)
1640
                                sprintf(str, "s-%2d", i);
1641
                        dbgreg(fp, i, str, m_state.m_sR[i]);
1642
                        if ((i&3)==3)
1643
                                fprintf(fp, "\n");
1644
                }
1645
                fprintf(fp, "User Registers\n");
1646
                for(int i=0; i<16; i++) {
1647
                        char str[16];
1648
                        if (i==13)
1649
                                sprintf(str, "uSP");
1650
                        else if (i==14)
1651
                                sprintf(str, "uCC");
1652
                        else if (i==15)
1653
                                sprintf(str, "uPC");
1654
                        else // if (i<=12)
1655
                                sprintf(str, "u-%2d", i);
1656
                        dbgreg(fp, i, str, m_state.m_uR[i]);
1657
                        if ((i&3)==3)
1658
                                fprintf(fp, "\n");
1659
                }
1660
        }
1661
};
1662
 
1663
void    get_value(ZIPPY_TB *tb) {
1664
        int     wy, wx, ra;
1665
        int     c = tb->cursor();
1666
 
1667
        wx = (c & 0x03) * 20 + 9;
1668
        wy = (c>>2);
1669
        if (wy >= 3+4)
1670
                wy++;
1671
        if (wy > 3)
1672
                wy += 2;
1673
        wy++;
1674
 
1675
        if (c >= 12)
1676
                ra = c - 12;
1677
        else
1678
                ra = c + 32;
1679
 
1680
        bool    done = false;
1681
        char    str[16];
1682
        int     pos = 0; str[pos] = '\0';
1683
        while(!done) {
1684
                int     chv = getch();
1685
                switch(chv) {
1686
                case KEY_ESCAPE:
1687
                        pos = 0; str[pos] = '\0'; done = true;
1688
                        break;
1689
                case KEY_RETURN: case KEY_ENTER: case KEY_UP: case KEY_DOWN:
1690
                        done = true;
1691
                        break;
1692
                case KEY_LEFT: case KEY_BACKSPACE:
1693
                        if (pos > 0) pos--;
1694
                        break;
1695
                case CTRL('L'): redrawwin(stdscr); break;
1696
                case KEY_CLEAR:
1697
                        pos = 0;
1698
                        break;
1699
                case '0': case ' ': str[pos++] = '0'; break;
1700
                case '1': str[pos++] = '1'; break;
1701
                case '2': str[pos++] = '2'; break;
1702
                case '3': str[pos++] = '3'; break;
1703
                case '4': str[pos++] = '4'; break;
1704
                case '5': str[pos++] = '5'; break;
1705
                case '6': str[pos++] = '6'; break;
1706
                case '7': str[pos++] = '7'; break;
1707
                case '8': str[pos++] = '8'; break;
1708
                case '9': str[pos++] = '9'; break;
1709
                case 'A': case 'a': str[pos++] = 'A'; break;
1710
                case 'B': case 'b': str[pos++] = 'B'; break;
1711
                case 'C': case 'c': str[pos++] = 'C'; break;
1712
                case 'D': case 'd': str[pos++] = 'D'; break;
1713
                case 'E': case 'e': str[pos++] = 'E'; break;
1714
                case 'F': case 'f': str[pos++] = 'F'; break;
1715
                }
1716
 
1717
                if (pos > 8)
1718
                        pos = 8;
1719
                str[pos] = '\0';
1720
 
1721
                attron(A_NORMAL | A_UNDERLINE);
1722
                mvprintw(wy, wx, "%-8s", str);
1723
                if (pos > 0) {
1724
                        attron(A_NORMAL | A_UNDERLINE | A_BLINK);
1725
                        mvprintw(wy, wx+pos-1, "%c", str[pos-1]);
1726
                }
1727
                attrset(A_NORMAL);
1728
        }
1729
 
1730
        if (pos > 0) {
1731
                int     v;
1732
                v = strtoul(str, NULL, 16);
1733
                if (!tb->halted()) {
1734
                        switch(ra) {
1735
                        case 15:
1736
                                tb->m_core->v__DOT__thecpu__DOT__ipc = v;
1737
                                if (!tb->m_core->v__DOT__thecpu__DOT__r_gie) {
1738
                                        tb->jump_to(v);
1739
                                        // tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1740
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1741
#ifdef  OPT_PIPELINED
1742
                                        // tb->m_core->v__DOT__thecpu__DOT__dcd_ce = 0;
1743
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcd_valid = 0;
1744
#endif
1745
                                        tb->m_core->v__DOT__thecpu__DOT__op_valid = 0;
1746
                                }
1747
                                break;
1748
                        case 31:
1749
                                tb->m_core->v__DOT__thecpu__DOT__r_upc = v;
1750
                                if (tb->m_core->v__DOT__thecpu__DOT__r_gie) {
1751
                                        tb->jump_to(v);
1752
                                        // tb->m_core->v__DOT__thecpu__DOT__clear_pipeline = 1;
1753
                                        tb->m_core->v__DOT__thecpu__DOT__alu_pc_valid = 0;
1754
#ifdef  OPT_PIPELINED
1755
                                        tb->m_core->v__DOT__thecpu__DOT__r_dcd_valid = 0;
1756
#endif
1757
                                        tb->m_core->v__DOT__thecpu__DOT__op_valid = 0;
1758
                                }
1759
                                break;
1760
                        case 32: tb->m_core->v__DOT__pic_data = v; break;
1761
                        case 33: tb->m_core->v__DOT__watchdog__DOT__r_value = v; break;
1762
                        // case 34: tb->m_core->v__DOT__manualcache__DOT__cache_base = v; break;
1763
                        case 35: tb->m_core->v__DOT__genblk7__DOT__ctri__DOT__r_int_state = v; break;
1764
                        case 36: tb->m_core->v__DOT__timer_a__DOT__r_value = v; break;
1765
                        case 37: tb->m_core->v__DOT__timer_b__DOT__r_value = v; break;
1766
                        case 38: tb->m_core->v__DOT__timer_c__DOT__r_value = v; break;
1767
                        case 39: tb->m_core->v__DOT__jiffies__DOT__r_counter = v; break;
1768
                        case 44: tb->m_core->v__DOT__utc_data = v; break;
1769
                        case 45: tb->m_core->v__DOT__uoc_data = v; break;
1770
                        case 46: tb->m_core->v__DOT__upc_data = v; break;
1771
                        case 47: tb->m_core->v__DOT__uic_data = v; break;
1772
                        default:
1773
                                tb->m_core->v__DOT__thecpu__DOT__regset[ra] = v;
1774
                                break;
1775
                        }
1776
                } else
1777
                        tb->cmd_write(ra, v);
1778
        }
1779
}
1780
 
1781
 
1782
 
1783
void    usage(void) {
1784
        printf("USAGE: zippy_tb [-a] <testfile.out>\n");
1785
        printf("\n");
1786
        printf("\tWhere testfile.out is an output file from the assembler.\n");
1787
        printf("\tThis file needs to be in a raw format and not an ELF\n");
1788
        printf("\texecutable.  It will be inserted into memory at a memory\n");
1789
        printf("\taddress of 0x0100000.  The memory device itself, the only\n");
1790
        printf("\tdevice supported by this simulator, occupies addresses from\n");
1791
        printf("\t0x0100000 to 0x01fffff.\n");
1792
        printf("\n");
1793
        printf("\t-a\tSets the testbench to run automatically without any\n");
1794
        printf("\t\tuser interaction.\n");
1795
        printf("\n");
1796
        printf("\tUser Commands:\n");
1797
        printf("\t\tWhen the test bench is run interactively, the following\n");
1798
        printf("\t\tkey strokes are recognized:\n");
1799
        printf("\t\t\'h\'\tHalt the processor using the external interface.\n");
1800
        printf("\t\t\'g\'\tLet the processor run at full throttle with no.\n");
1801
        printf("\t\t\tuser intervention.\n");
1802
        printf("\t\t\'q\'\tQuit the simulation.\n");
1803
        printf("\t\t\'r\'\tReset the processor.\n");
1804
        printf("\t\t\'s\'\tStep the CPU using the external stepping command\n");
1805
        printf("\t\t\tThis may consume more than one tick.\n");
1806
        printf("\t\t\'t\'\tClock a single tick through the system.\n");
1807
}
1808
 
1809
bool    signalled = false;
1810
 
1811
void    sigint(int v) {
1812
        signalled = true;
1813
}
1814
 
1815
int     main(int argc, char **argv) {
1816
        Verilated::commandArgs(argc, argv);
1817
        ZIPPY_TB        *tb = new ZIPPY_TB();
1818
        bool            autorun = false, exit_on_done = false, autostep=false;
1819
        ZIPI            entry = RAMBASE;
1820
 
1821
        signal(SIGINT, sigint);
1822
 
1823
        if (argc <= 1) {
1824
                usage();
1825
                exit(-1);
1826
        } else {
1827
                for(int argn=1; argn<argc; argn++) {
1828
                        if (argv[argn][0] == '-') {
1829
                                switch(argv[argn][1]) {
1830
                                case 'a':
1831
                                        autorun = true;
1832
                                        break;
1833
                                case 'e':
1834
                                        exit_on_done = true;
1835
                                        break;
1836
                                case 'h':
1837
                                        usage();
1838
                                        exit(0);
1839
                                        break;
1840
                                case 's':
1841
                                        autostep = true;
1842
                                        break;
1843
                                default:
1844
                                        usage();
1845
                                        exit(-1);
1846
                                        break;
1847
                                }
1848
                        } else if ((access(argv[argn], R_OK)==0)
1849
                                                &&(iself(argv[argn]))) {
1850
                                ELFSECTION **secpp = NULL, *secp;
1851
 
1852
                                elfread(argv[argn], entry, secpp);
1853
 
1854
                                for(int i=0; secpp[i]->m_len; i++) {
1855
                                        const char *data;
1856
 
1857
                                        secp = secpp[i];
1858
                                        assert(secp->m_start >= RAMBASE);
1859
                                        assert(secp->m_start+secp->m_len <= RAMBASE+RAMWORDS);
1860
                                        assert((secp->m_len & 3)==0);
1861
 
1862
                                        data = &secp->m_data[0];
1863
                                        tb->m_mem.load((secp->m_start-RAMBASE)>>2, data, secp->m_len);
1864
                                }
1865
                        } else {
1866
                                fprintf(stderr, "No access to %s, or unknown arg\n", argv[argn]);
1867
                                exit(-2);
1868
                        }
1869
                }
1870
        }
1871
 
1872
 
1873
        if (autorun) {
1874
                bool    done = false;
1875
 
1876
                printf("Running in non-interactive mode\n");
1877
                tb->reset();
1878
                for(int i=0; i<2; i++)
1879
                        tb->tick();
1880
                tb->m_core->v__DOT__cmd_halt = 0;
1881
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET|15);
1882
                tb->wb_write(CMD_DATA, entry);
1883
                tb->wb_write(CMD_REG, 15);
1884
                while(!done) {
1885
                        tb->tick();
1886
 
1887
                                // tb->m_core->v__DOT__thecpu__DOT__step = 0;
1888
                                // tb->m_core->v__DOT__cmd_halt = 0;
1889
                                // tb->m_core->v__DOT__cmd_step = 0;
1890
 
1891
                        /*
1892
                        printf("PC = %08x:%08x (%08x)\n",
1893
                                tb->m_core->v__DOT__thecpu__DOT__ipc,
1894
                                tb->m_core->v__DOT__thecpu__DOT__r_upc,
1895
                                tb->m_core->v__DOT__thecpu__DOT__alu_pc);
1896
                        */
1897
 
1898
                        done = (tb->test_success())||(tb->test_failure());
1899
                        done = done || signalled;
1900
                }
1901
        } else if (autostep) {
1902
                bool    done = false;
1903
 
1904
                printf("Running in non-interactive mode, via step commands\n");
1905
                tb->wb_write(CMD_REG, CMD_HALT|CMD_RESET|15);
1906
                tb->wb_write(CMD_DATA, entry);
1907
                tb->wb_write(CMD_REG, 15);
1908
                while(!done) {
1909
                        tb->wb_write(CMD_REG, CMD_STEP);
1910
                        done = (tb->test_success())||(tb->test_failure());
1911
                        done = done || signalled;
1912
                }
1913
        } else { // Interactive
1914
                initscr();
1915
                raw();
1916
                noecho();
1917
                keypad(stdscr, true);
1918
 
1919
                // tb->reset();
1920
                // for(int i=0; i<2; i++)
1921
                        // tb->tick();
1922
                tb->m_core->v__DOT__cmd_reset = 1;
1923
                tb->m_core->v__DOT__cmd_halt = 1;
1924
                tb->tick();
1925
 
1926
                tb->m_core->v__DOT__cmd_reset = 0;
1927
                tb->m_core->v__DOT__cmd_halt = 0;
1928
                tb->tick();
1929
                tb->jump_to(entry);
1930
                tb->tick();
1931
                tb->jump_to(entry);
1932
                tb->tick();
1933
                tb->jump_to(entry);
1934
 
1935
 
1936
                // For debugging purposes: do we wish to skip some number of
1937
                // instructions to fast forward to a time of interest??
1938
                for(int i=0; i<0; i++) {
1939
                        tb->m_core->v__DOT__cmd_halt = 0;
1940
                        tb->tick();
1941
                }
1942
 
1943
                int     chv = 'q';
1944
 
1945
                bool    done = false, halted = true, manual = true,
1946
                        high_speed = false;
1947
 
1948
                halfdelay(1);
1949
                // tb->wb_write(CMD_REG, CMD_HALT | CMD_RESET);
1950
                // while((tb->wb_read(CMD_REG) & (CMD_HALT|CMD_STALL))==(CMD_HALT|CMD_STALL))
1951
                        // tb->show_state();
1952
 
1953
                while(!done) {
1954
                        if ((high_speed)&&(!manual)&&(!halted)) {
1955
                                // chv = getch();
1956
 
1957
                                struct  pollfd  fds[1];
1958
                                fds[0].fd = STDIN_FILENO;
1959
                                fds[0].events = POLLIN;
1960
 
1961
                                if (poll(fds, 1, 0) > 0)
1962
                                        chv = getch();
1963
                                else
1964
                                        chv = ERR;
1965
 
1966
                        } else {
1967
                                chv = getch();
1968
                        }
1969
                        switch(chv) {
1970
                        case 'h': case 'H':
1971
                                tb->wb_write(CMD_REG, CMD_HALT);
1972
                                if (!halted)
1973
                                        erase();
1974
                                halted = true;
1975
                                break;
1976
                        case 'G':
1977
                                high_speed = true;
1978
                                // cbreak();
1979
                        case 'g':
1980
                                tb->wb_write(CMD_REG, 0);
1981
                                if (halted)
1982
                                        erase();
1983
                                halted = false;
1984
                                manual = false;
1985
                                break;
1986
                        case 'm':
1987
                                tb->show_user_timers(false);
1988
                                break;
1989
                        case 'q': case 'Q':
1990
                                done = true;
1991
                                break;
1992
                        case 'r': case 'R':
1993
                                if (manual)
1994
                                        tb->reset();
1995
                                else
1996
                                        tb->wb_write(CMD_REG, CMD_RESET|CMD_HALT);
1997
                                halted = true;
1998
                                erase();
1999
                                break;
2000
                        case 's':
2001
                                if (!halted)
2002
                                        erase();
2003
                                tb->step();
2004
                                manual = false;
2005
                                halted = true;
2006
                                // if (high_speed)
2007
                                        // halfdelay(1);
2008
                                high_speed = false;
2009
                                break;
2010
                        case 'S':
2011
                                if ((!manual)||(halted))
2012
                                        erase();
2013
                                manual = true;
2014
                                halted = true;
2015
                                // if (high_speed)
2016
                                        // halfdelay(1);
2017
                                high_speed = false;
2018
                                tb->m_core->v__DOT__cmd_halt = 0;
2019
                                tb->m_core->v__DOT__cmd_step = 1;
2020
                                tb->eval();
2021
                                tb->tick();
2022
                                break;
2023
                        case 'T': //
2024
                                if ((!manual)||(halted))
2025
                                        erase();
2026
                                manual = true;
2027
                                halted = true;
2028
                                // if (high_speed)
2029
                                        // halfdelay(1);
2030
                                high_speed = false;
2031
                                tb->m_core->v__DOT__cmd_halt = 1;
2032
                                tb->m_core->v__DOT__cmd_step = 0;
2033
                                tb->eval();
2034
                                tb->tick();
2035
                                break;
2036
                        case 't':
2037
                                if ((!manual)||(halted))
2038
                                        erase();
2039
                                manual = true;
2040
                                halted = false;
2041
                                // if (high_speed)
2042
                                        // halfdelay(1);
2043
                                high_speed = false;
2044
                //              tb->m_core->v__DOT__thecpu__DOT__step = 0;
2045
                                tb->m_core->v__DOT__cmd_halt = 0;
2046
                //              tb->m_core->v__DOT__cmd_step = 0;
2047
                                tb->tick();
2048
                                break;
2049
                        case 'u':
2050
                                tb->show_user_timers(true);
2051
                                break;
2052
                        case    KEY_IC: case KEY_ENTER: case KEY_RETURN:
2053
                                get_value(tb);
2054
                                break;
2055
                        case    KEY_UP:         tb->cursor_up();        break;
2056
                        case    KEY_DOWN:       tb->cursor_down();      break;
2057
                        case    KEY_LEFT:       tb->cursor_left();      break;
2058
                        case    KEY_RIGHT:      tb->cursor_right();     break;
2059
                        case CTRL('L'): redrawwin(stdscr); break;
2060
                        case ERR: case KEY_CLEAR:
2061
                        default:
2062
                                if (!manual)
2063
                                        tb->tick();
2064
                        }
2065
 
2066
                        if (manual) {
2067
                                tb->show_state();
2068
                        } else if (halted) {
2069
                                if (tb->m_dbgfp)
2070
                                        fprintf(tb->m_dbgfp, "\n\nREAD-STATE ******\n");
2071
                                tb->read_state();
2072
                        } else
2073
                                tb->show_state();
2074
 
2075
                        if (tb->m_core->i_rst)
2076
                                done =true;
2077
                        if ((tb->m_bomb)||(signalled))
2078
                                done = true;
2079
 
2080
                        if (exit_on_done) {
2081
                                if (tb->test_success())
2082
                                        done = true;
2083
                                if (tb->test_failure())
2084
                                        done = true;
2085
                        }
2086
                }
2087
                endwin();
2088
        }
2089
#ifdef  MANUAL_STEPPING_MODE
2090
         else { // Manual stepping mode
2091
                tb->jump_to(entry);
2092
                tb->show_state();
2093
 
2094
                while('q' != tolower(chv = getch())) {
2095
                        tb->tick();
2096
                        tb->show_state();
2097
 
2098
                        if (tb->test_success())
2099
                                break;
2100
                        else if (tb->test_failure())
2101
                                break;
2102
                        else if (signalled)
2103
                                break;
2104
                }
2105
        }
2106
#endif
2107
 
2108
        printf("\n");
2109
        if (tb->test_failure()) {
2110
                tb->dump_state();
2111
        }
2112
 
2113
        printf("Clocks used         : %08x\n", tb->m_core->v__DOT__mtc_data);
2114
        printf("Instructions Issued : %08x\n", tb->m_core->v__DOT__mic_data);
2115
        printf("Tick Count          : %08lx\n", tb->m_tickcount);
2116
        if (tb->m_core->v__DOT__mtc_data != 0)
2117
                printf("Instructions / Clock: %.2f\n",
2118
                        (double)tb->m_core->v__DOT__mic_data
2119
                        / (double)tb->m_core->v__DOT__mtc_data);
2120
 
2121
        int     rcode = 0;
2122
        if (tb->m_bomb) {
2123
                printf("TEST BOMBED\n");
2124
                rcode = -1;
2125
        } else if (tb->test_success()) {
2126
                printf("SUCCESS!\n");
2127
        } else if (tb->test_failure()) {
2128
                rcode = -2;
2129
                printf("TEST FAILED!\n");
2130
        } else
2131
                printf("User quit\n");
2132
        delete tb;
2133
        exit(rcode);
2134
}
2135
 

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.