OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [sw/] [gcc-zippatch.patch] - Blame information for rev 200

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Line No. Rev Author Line
1 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/config.sub gcc-5.3.0-zip/config.sub
2
--- gcc-5.3.0-original/config.sub       2015-01-02 04:30:21.000000000 -0500
3
+++ gcc-5.3.0-zip/config.sub    2016-01-30 12:27:56.023073747 -0500
4
@@ -316,7 +316,7 @@
5
        | visium \
6
        | we32k \
7
        | x86 | xc16x | xstormy16 | xtensa \
8
-       | z8k | z80)
9
+       | z8k | z80 | zip)
10
                basic_machine=$basic_machine-unknown
11
                ;;
12
        c54x)
13
@@ -1547,6 +1547,9 @@
14
 # system, and we'll never get to this point.
15
 
16
 case $basic_machine in
17
+       zip-*)
18
+               os=-elf
19
+               ;;
20
        score-*)
21
                os=-elf
22
                ;;
23
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/configure gcc-5.3.0-zip/configure
24
--- gcc-5.3.0-original/configure        2015-05-03 13:29:57.000000000 -0400
25
+++ gcc-5.3.0-zip/configure     2016-01-30 16:19:48.264867231 -0500
26
@@ -3927,6 +3927,8 @@
27
   vax-*-*)
28
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
29
     ;;
30
+  zip*)
31
+    noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
32
 esac
33
 
34
 # If we aren't building newlib, then don't build libgloss, since libgloss
35
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/configure.ac gcc-5.3.0-zip/configure.ac
36
--- gcc-5.3.0-original/configure.ac     2015-05-03 13:29:57.000000000 -0400
37
+++ gcc-5.3.0-zip/configure.ac  2016-02-12 10:47:23.847194843 -0500
38
@@ -1274,6 +1274,10 @@
39
   vax-*-*)
40
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
41
     ;;
42
+  zip*)
43
+    noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
44
+    unsupported_languages="$unsupported_languages fortran java"
45
+    ;;
46
 esac
47
 
48
 # If we aren't building newlib, then don't build libgloss, since libgloss
49 117 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cfgexpand.c gcc-5.3.0-zip/gcc/cfgexpand.c
50
--- gcc-5.3.0-original/gcc/cfgexpand.c  2015-07-23 06:39:26.000000000 -0400
51
+++ gcc-5.3.0-zip/gcc/cfgexpand.c       2016-04-01 06:40:17.288326711 -0400
52
@@ -108,6 +108,14 @@
53
 #include "tree-chkp.h"
54
 #include "rtl-chkp.h"
55
 
56
+#ifdef DO_ZIP_DEBUGS
57
+#include <stdio.h>
58
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
59
+extern void    zip_debug_rtx(const_rtx);
60
+#else
61
+#define        ZIP_DEBUG_LINE(STR,RTX)
62
+#endif
63
+
64
 /* Some systems use __main in a way incompatible with its use in gcc, in these
65
    cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
66
    give the same symbol without quotes for an alternative entry point.  You
67 111 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cgraphbuild.c gcc-5.3.0-zip/gcc/cgraphbuild.c
68
--- gcc-5.3.0-original/gcc/cgraphbuild.c        2015-01-09 15:18:42.000000000 -0500
69
+++ gcc-5.3.0-zip/gcc/cgraphbuild.c     2016-03-24 22:13:24.815287808 -0400
70
@@ -62,6 +62,13 @@
71
 #include "ipa-prop.h"
72
 #include "ipa-inline.h"
73
 
74
+#ifdef DO_ZIP_DEBUGS
75
+extern void zip_debug_rtx(const_rtx);
76
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
77
+#else
78
+#define        ZIP_DEBUG_LINE(STR,RTX)
79
+#endif
80
+
81
 /* Context of record_reference.  */
82
 struct record_reference_ctx
83
 {
84 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/common/config/zip/zip-common.c gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c
85
--- gcc-5.3.0-original/gcc/common/config/zip/zip-common.c       1969-12-31 19:00:00.000000000 -0500
86
+++ gcc-5.3.0-zip/gcc/common/config/zip/zip-common.c    2016-02-14 00:54:31.821055716 -0500
87
@@ -0,0 +1,52 @@
88
+////////////////////////////////////////////////////////////////////////////////
89
+//
90
+// Filename:   common/config/zip/zip-common.c
91
+//
92
+// Project:    Zip CPU backend for the GNU Compiler Collection
93
+//
94
+// Purpose:    To eliminate the frame register automatically.
95
+//
96
+// Creator:    Dan Gisselquist, Ph.D.
97
+//             Gisselquist Technology, LLC
98
+//
99
+////////////////////////////////////////////////////////////////////////////////
100
+//
101
+// Copyright (C) 2016, Gisselquist Technology, LLC
102
+//
103
+// This program is free software (firmware): you can redistribute it and/or
104
+// modify it under the terms of  the GNU General Public License as published
105
+// by the Free Software Foundation, either version 3 of the License, or (at
106
+// your option) any later version.
107
+//
108
+// This program is distributed in the hope that it will be useful, but WITHOUT
109
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
110
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
111
+// for more details.
112
+//
113
+// You should have received a copy of the GNU General Public License along
114
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
115
+// target there if the PDF file isn't present.)  If not, see
116
+// <http://www.gnu.org/licenses/> for a copy.
117
+//
118
+// License:    GPL, v3, as defined and found on www.gnu.org,
119
+//             http://www.gnu.org/licenses/gpl.html
120
+//
121
+//
122
+////////////////////////////////////////////////////////////////////////////////
123
+#include "config.h"
124
+#include "system.h"
125
+#include "coretypes.h"
126
+#include "tm.h"
127
+#include "common/common-target.h"
128
+#include "common/common-target-def.h"
129
+
130
+static const struct default_options zip_option_optimization_table[] =
131
+  {
132
+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
133
+    { OPT_LEVELS_NONE, 0, NULL, 0 }
134
+  };
135
+
136
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
137
+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table
138
+
139
+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;
140
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h
141 200 dgisselq
--- gcc-5.3.0-original/gcc/config/aarch64/aarch64-linux.h       2016-11-28 18:14:19.382586425 -0500
142 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/aarch64/aarch64-linux.h    2015-07-24 12:00:26.000000000 -0400
143
@@ -21,7 +21,7 @@
144
 #ifndef GCC_AARCH64_LINUX_H
145
 #define GCC_AARCH64_LINUX_H
146
 
147
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
148
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
149
 
150
 #undef  ASAN_CC1_SPEC
151
 #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
152
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/alpha/linux-elf.h gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h
153 200 dgisselq
--- gcc-5.3.0-original/gcc/config/alpha/linux-elf.h     2016-11-28 18:14:19.382586425 -0500
154 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/alpha/linux-elf.h  2015-01-05 07:33:28.000000000 -0500
155
@@ -23,8 +23,8 @@
156
 #define EXTRA_SPECS \
157
 { "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
158
 
159
-#define GLIBC_DYNAMIC_LINKER   "/tools/lib/ld-linux.so.2"
160
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
161
+#define GLIBC_DYNAMIC_LINKER   "/lib/ld-linux.so.2"
162
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
163
 #if DEFAULT_LIBC == LIBC_UCLIBC
164
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
165
 #elif DEFAULT_LIBC == LIBC_GLIBC
166
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-eabi.h gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h
167 200 dgisselq
--- gcc-5.3.0-original/gcc/config/arm/linux-eabi.h      2016-11-28 18:14:19.382586425 -0500
168 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/arm/linux-eabi.h   2015-01-05 07:33:28.000000000 -0500
169
@@ -68,8 +68,8 @@
170
    GLIBC_DYNAMIC_LINKER_DEFAULT and TARGET_DEFAULT_FLOAT_ABI.  */
171
 
172
 #undef  GLIBC_DYNAMIC_LINKER
173
-#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "/tools/lib/ld-linux.so.3"
174
-#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/tools/lib/ld-linux-armhf.so.3"
175
+#define GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "/lib/ld-linux.so.3"
176
+#define GLIBC_DYNAMIC_LINKER_HARD_FLOAT "/lib/ld-linux-armhf.so.3"
177
 #define GLIBC_DYNAMIC_LINKER_DEFAULT GLIBC_DYNAMIC_LINKER_SOFT_FLOAT
178
 
179
 #define GLIBC_DYNAMIC_LINKER \
180
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/arm/linux-elf.h gcc-5.3.0-zip/gcc/config/arm/linux-elf.h
181 200 dgisselq
--- gcc-5.3.0-original/gcc/config/arm/linux-elf.h       2016-11-28 18:14:19.382586425 -0500
182 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/arm/linux-elf.h    2015-06-23 05:26:54.000000000 -0400
183
@@ -62,7 +62,7 @@
184
 
185
 #define LIBGCC_SPEC "%{mfloat-abi=soft*:-lfloat} -lgcc"
186
 
187
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
188
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
189
 
190
 #define LINUX_TARGET_LINK_SPEC  "%{h*} \
191
    %{static:-Bstatic} \
192
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/bfin/linux.h gcc-5.3.0-zip/gcc/config/bfin/linux.h
193 200 dgisselq
--- gcc-5.3.0-original/gcc/config/bfin/linux.h  2016-11-28 18:14:19.382586425 -0500
194 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/bfin/linux.h       2015-01-05 07:33:28.000000000 -0500
195
@@ -45,7 +45,7 @@
196
   %{shared:-G -Bdynamic} \
197
   %{!shared: %{!static: \
198
    %{rdynamic:-export-dynamic} \
199
-   -dynamic-linker /tools/lib/ld-uClibc.so.0} \
200
+   -dynamic-linker /lib/ld-uClibc.so.0} \
201
    %{static}} -init __init -fini __fini"
202
 
203
 #undef TARGET_SUPPORTS_SYNC_CALLS
204
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/cris/linux.h gcc-5.3.0-zip/gcc/config/cris/linux.h
205 200 dgisselq
--- gcc-5.3.0-original/gcc/config/cris/linux.h  2016-11-28 18:14:19.382586425 -0500
206 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/cris/linux.h       2015-01-05 07:33:28.000000000 -0500
207
@@ -102,7 +102,7 @@
208
 #undef CRIS_DEFAULT_CPU_VERSION
209
 #define CRIS_DEFAULT_CPU_VERSION CRIS_CPU_NG
210
 
211
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
212
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
213
 
214
 #undef CRIS_LINK_SUBTARGET_SPEC
215
 #define CRIS_LINK_SUBTARGET_SPEC \
216
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/freebsd-spec.h gcc-5.3.0-zip/gcc/config/freebsd-spec.h
217 200 dgisselq
--- gcc-5.3.0-original/gcc/config/freebsd-spec.h        2016-11-28 18:14:19.382586425 -0500
218 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/freebsd-spec.h     2015-06-25 13:53:14.000000000 -0400
219
@@ -129,9 +129,9 @@
220
 #endif
221
 
222
 #if FBSD_MAJOR < 6
223
-#define FBSD_DYNAMIC_LINKER "/tools/libexec/ld-elf.so.1"
224
+#define FBSD_DYNAMIC_LINKER "/usr/libexec/ld-elf.so.1"
225
 #else
226
-#define FBSD_DYNAMIC_LINKER "/tools/libexec/ld-elf.so.1"
227
+#define FBSD_DYNAMIC_LINKER "/libexec/ld-elf.so.1"
228
 #endif
229
 
230
 /* NOTE: The freebsd-spec.h header is included also for various
231
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/frv/linux.h gcc-5.3.0-zip/gcc/config/frv/linux.h
232 200 dgisselq
--- gcc-5.3.0-original/gcc/config/frv/linux.h   2016-11-28 18:14:19.382586425 -0500
233 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/frv/linux.h        2015-01-05 07:33:28.000000000 -0500
234
@@ -34,7 +34,7 @@
235
 #define ENDFILE_SPEC \
236
   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
237
 
238
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
239
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
240
 
241
 #undef LINK_SPEC
242
 #define LINK_SPEC "\
243
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/gnu.h gcc-5.3.0-zip/gcc/config/i386/gnu.h
244 200 dgisselq
--- gcc-5.3.0-original/gcc/config/i386/gnu.h    2016-11-28 18:14:19.382586425 -0500
245 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/i386/gnu.h 2015-01-05 07:33:28.000000000 -0500
246
@@ -22,7 +22,7 @@
247
 #define GNU_USER_LINK_EMULATION "elf_i386"
248
 
249
 #undef GNU_USER_DYNAMIC_LINKER
250
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so"
251
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so"
252
 
253
 #undef STARTFILE_SPEC
254
 #if defined HAVE_LD_PIE
255
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h
256 200 dgisselq
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu64.h 2016-11-28 18:14:19.386586394 -0500
257 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu64.h      2015-01-05 07:33:28.000000000 -0500
258
@@ -22,6 +22,6 @@
259
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64_fbsd"
260
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64_fbsd"
261
 
262
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
263
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib/ld-kfreebsd-x86-64.so.1"
264
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/lib/ld-kfreebsd-x32.so.1"
265
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
266
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld-kfreebsd-x86-64.so.1"
267
+#define GLIBC_DYNAMIC_LINKERX32 "/lib/ld-kfreebsd-x32.so.1"
268
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h
269 200 dgisselq
--- gcc-5.3.0-original/gcc/config/i386/kfreebsd-gnu.h   2016-11-28 18:14:19.386586394 -0500
270 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/i386/kfreebsd-gnu.h        2015-01-05 07:33:28.000000000 -0500
271
@@ -19,4 +19,4 @@
272
 <http://www.gnu.org/licenses/>.  */
273
 
274
 #define GNU_USER_LINK_EMULATION "elf_i386_fbsd"
275
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
276
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
277
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux64.h gcc-5.3.0-zip/gcc/config/i386/linux64.h
278 200 dgisselq
--- gcc-5.3.0-original/gcc/config/i386/linux64.h        2016-11-28 18:14:19.386586394 -0500
279 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/i386/linux64.h     2015-01-05 07:33:28.000000000 -0500
280
@@ -27,6 +27,6 @@
281
 #define GNU_USER_LINK_EMULATION64 "elf_x86_64"
282
 #define GNU_USER_LINK_EMULATIONX32 "elf32_x86_64"
283
 
284
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-linux.so.2"
285
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib64/ld-linux-x86-64.so.2"
286
-#define GLIBC_DYNAMIC_LINKERX32 "/tools/libx32/ld-linux-x32.so.2"
287
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
288
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
289
+#define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
290
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/i386/linux.h gcc-5.3.0-zip/gcc/config/i386/linux.h
291 200 dgisselq
--- gcc-5.3.0-original/gcc/config/i386/linux.h  2016-11-28 18:14:19.386586394 -0500
292 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/i386/linux.h       2015-01-05 07:33:28.000000000 -0500
293
@@ -20,4 +20,4 @@
294
 <http://www.gnu.org/licenses/>.  */
295
 
296
 #define GNU_USER_LINK_EMULATION "elf_i386"
297
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
298
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
299
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/ia64/linux.h gcc-5.3.0-zip/gcc/config/ia64/linux.h
300 200 dgisselq
--- gcc-5.3.0-original/gcc/config/ia64/linux.h  2016-11-28 18:14:19.386586394 -0500
301 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/ia64/linux.h       2015-01-05 07:33:28.000000000 -0500
302
@@ -55,7 +55,7 @@
303
 /* Define this for shared library support because it isn't in the main
304
    linux.h file.  */
305
 
306
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux-ia64.so.2"
307
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-ia64.so.2"
308
 
309
 #undef LINK_SPEC
310
 #define LINK_SPEC "\
311
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/knetbsd-gnu.h gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h
312 200 dgisselq
--- gcc-5.3.0-original/gcc/config/knetbsd-gnu.h 2016-11-28 18:14:19.386586394 -0500
313 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/knetbsd-gnu.h      2015-01-05 07:33:28.000000000 -0500
314
@@ -32,4 +32,4 @@
315
 
316
 
317
 #undef GNU_USER_DYNAMIC_LINKER
318
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
319
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
320
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h
321 200 dgisselq
--- gcc-5.3.0-original/gcc/config/kopensolaris-gnu.h    2016-11-28 18:14:19.386586394 -0500
322 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/kopensolaris-gnu.h 2015-01-05 07:33:28.000000000 -0500
323
@@ -31,5 +31,4 @@
324
   while (0)
325
 
326
 #undef GNU_USER_DYNAMIC_LINKER
327
-#define GNU_USER_DYNAMIC_LINKER "/tools/lib/ld.so.1"
328
-
329
+#define GNU_USER_DYNAMIC_LINKER "/lib/ld.so.1"
330
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/linux.h gcc-5.3.0-zip/gcc/config/linux.h
331 200 dgisselq
--- gcc-5.3.0-original/gcc/config/linux.h       2016-11-28 18:14:19.386586394 -0500
332 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/linux.h    2015-01-05 07:33:28.000000000 -0500
333
@@ -73,10 +73,10 @@
334
    GLIBC_DYNAMIC_LINKER must be defined for each target using them, or
335
    GLIBC_DYNAMIC_LINKER32 and GLIBC_DYNAMIC_LINKER64 for targets
336
    supporting both 32-bit and 64-bit compilation.  */
337
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
338
-#define UCLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-uClibc.so.0"
339
-#define UCLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64-uClibc.so.0"
340
-#define UCLIBC_DYNAMIC_LINKERX32 "/tools/lib/ldx32-uClibc.so.0"
341
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
342
+#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
343
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
344
+#define UCLIBC_DYNAMIC_LINKERX32 "/lib/ldx32-uClibc.so.0"
345
 #define BIONIC_DYNAMIC_LINKER "/system/bin/linker"
346
 #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
347
 #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
348
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h
349 200 dgisselq
--- gcc-5.3.0-original/gcc/config/lm32/uclinux-elf.h    2016-11-28 18:14:19.386586394 -0500
350 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/lm32/uclinux-elf.h 2015-01-05 07:33:28.000000000 -0500
351
@@ -67,7 +67,7 @@
352
    %{shared:-shared} \
353
    %{symbolic:-Bsymbolic} \
354
    %{rdynamic:-export-dynamic} \
355
-   -dynamic-linker /tools/lib/ld-linux.so.2"
356
+   -dynamic-linker /lib/ld-linux.so.2"
357
 
358
 #define TARGET_OS_CPP_BUILTINS() GNU_USER_TARGET_OS_CPP_BUILTINS()
359
 
360
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/m68k/linux.h gcc-5.3.0-zip/gcc/config/m68k/linux.h
361 200 dgisselq
--- gcc-5.3.0-original/gcc/config/m68k/linux.h  2016-11-28 18:14:19.386586394 -0500
362 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/m68k/linux.h       2015-01-05 07:33:28.000000000 -0500
363
@@ -71,7 +71,7 @@
364
    When the -shared link option is used a final link is not being
365
    done.  */
366
 
367
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
368
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
369
 
370
 #undef LINK_SPEC
371
 #define LINK_SPEC "-m m68kelf %{shared} \
372
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/microblaze/linux.h gcc-5.3.0-zip/gcc/config/microblaze/linux.h
373 200 dgisselq
--- gcc-5.3.0-original/gcc/config/microblaze/linux.h    2016-11-28 18:14:19.386586394 -0500
374 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/microblaze/linux.h 2015-05-28 10:08:19.000000000 -0400
375
@@ -28,7 +28,7 @@
376
 #undef TLS_NEEDS_GOT
377
 #define TLS_NEEDS_GOT 1
378
 
379
-#define DYNAMIC_LINKER "/tools/lib/ld.so.1"
380
+#define DYNAMIC_LINKER "/lib/ld.so.1"
381
 #undef  SUBTARGET_EXTRA_SPECS
382
 #define SUBTARGET_EXTRA_SPECS \
383
   { "dynamic_linker", DYNAMIC_LINKER }
384
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mips/linux.h gcc-5.3.0-zip/gcc/config/mips/linux.h
385 200 dgisselq
--- gcc-5.3.0-original/gcc/config/mips/linux.h  2016-11-28 18:14:19.386586394 -0500
386 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/mips/linux.h       2015-01-05 07:33:28.000000000 -0500
387
@@ -22,20 +22,20 @@
388
 #define GNU_USER_LINK_EMULATIONN32 "elf32%{EB:b}%{EL:l}tsmipn32"
389
 
390
 #define GLIBC_DYNAMIC_LINKER32 \
391
-  "%{mnan=2008:/tools/lib/ld-linux-mipsn8.so.1;:/tools/lib/ld.so.1}"
392
+  "%{mnan=2008:/lib/ld-linux-mipsn8.so.1;:/lib/ld.so.1}"
393
 #define GLIBC_DYNAMIC_LINKER64 \
394
-  "%{mnan=2008:/tools/lib64/ld-linux-mipsn8.so.1;:/tools/lib64/ld.so.1}"
395
+  "%{mnan=2008:/lib64/ld-linux-mipsn8.so.1;:/lib64/ld.so.1}"
396
 #define GLIBC_DYNAMIC_LINKERN32 \
397
-  "%{mnan=2008:/tools/lib32/ld-linux-mipsn8.so.1;:/tools/lib32/ld.so.1}"
398
+  "%{mnan=2008:/lib32/ld-linux-mipsn8.so.1;:/lib32/ld.so.1}"
399
 
400
 #undef UCLIBC_DYNAMIC_LINKER32
401
 #define UCLIBC_DYNAMIC_LINKER32 \
402
-  "%{mnan=2008:/tools/lib/ld-uClibc-mipsn8.so.0;:/tools/lib/ld-uClibc.so.0}"
403
+  "%{mnan=2008:/lib/ld-uClibc-mipsn8.so.0;:/lib/ld-uClibc.so.0}"
404
 #undef UCLIBC_DYNAMIC_LINKER64
405
 #define UCLIBC_DYNAMIC_LINKER64 \
406
-  "%{mnan=2008:/tools/lib/ld64-uClibc-mipsn8.so.0;:/tools/lib/ld64-uClibc.so.0}"
407
+  "%{mnan=2008:/lib/ld64-uClibc-mipsn8.so.0;:/lib/ld64-uClibc.so.0}"
408
 #define UCLIBC_DYNAMIC_LINKERN32 \
409
-  "%{mnan=2008:/tools/lib32/ld-uClibc-mipsn8.so.0;:/tools/lib32/ld-uClibc.so.0}"
410
+  "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
411
 
412
 #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
413
 #define GNU_USER_DYNAMIC_LINKERN32 \
414
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/mn10300/linux.h gcc-5.3.0-zip/gcc/config/mn10300/linux.h
415 200 dgisselq
--- gcc-5.3.0-original/gcc/config/mn10300/linux.h       2016-11-28 18:14:19.386586394 -0500
416 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/mn10300/linux.h    2015-01-05 07:33:28.000000000 -0500
417
@@ -32,7 +32,7 @@
418
 #undef  ASM_SPEC
419
 #define ASM_SPEC ""
420
 
421
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
422
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
423
 
424
 #undef  LINK_SPEC
425
 #define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
426
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/pa/pa-linux.h gcc-5.3.0-zip/gcc/config/pa/pa-linux.h
427 200 dgisselq
--- gcc-5.3.0-original/gcc/config/pa/pa-linux.h 2016-11-28 18:14:19.386586394 -0500
428 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/pa/pa-linux.h      2015-09-24 20:04:26.000000000 -0400
429
@@ -37,7 +37,7 @@
430
 /* Define this for shared library support because it isn't in the main
431
    linux.h file.  */
432
 
433
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
434
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
435
 
436
 #undef LINK_SPEC
437
 #define LINK_SPEC "\
438
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/linux64.h gcc-5.3.0-zip/gcc/config/rs6000/linux64.h
439 200 dgisselq
--- gcc-5.3.0-original/gcc/config/rs6000/linux64.h      2016-11-28 18:14:19.386586394 -0500
440 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/rs6000/linux64.h   2015-03-09 19:18:57.000000000 -0400
441
@@ -357,14 +357,14 @@
442
 #undef LINK_OS_DEFAULT_SPEC
443
 #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
444
 
445
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
446
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
447
 #ifdef LINUX64_DEFAULT_ABI_ELFv2
448
-#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/tools/lib64/ld64.so.1;:/tools/lib64/ld64.so.2}"
449
+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv1:/lib64/ld64.so.1;:/lib64/ld64.so.2}"
450
 #else
451
-#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/tools/lib64/ld64.so.2;:/tools/lib64/ld64.so.1}"
452
+#define GLIBC_DYNAMIC_LINKER64 "%{mabi=elfv2:/lib64/ld64.so.2;:/lib64/ld64.so.1}"
453
 #endif
454
-#define UCLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-uClibc.so.0"
455
-#define UCLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64-uClibc.so.0"
456
+#define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
457
+#define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
458
 #if DEFAULT_LIBC == LIBC_UCLIBC
459
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
460
 #elif DEFAULT_LIBC == LIBC_GLIBC
461
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/rs6000/sysv4.h gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h
462 200 dgisselq
--- gcc-5.3.0-original/gcc/config/rs6000/sysv4.h        2016-11-28 18:14:19.386586394 -0500
463 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/rs6000/sysv4.h     2015-09-24 09:46:45.000000000 -0400
464
@@ -757,8 +757,8 @@
465
 
466
 #define LINK_START_LINUX_SPEC ""
467
 
468
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
469
-#define UCLIBC_DYNAMIC_LINKER "/tools/lib/ld-uClibc.so.0"
470
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
471
+#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
472
 #if DEFAULT_LIBC == LIBC_UCLIBC
473
 #define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
474
 #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
475
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/s390/linux.h gcc-5.3.0-zip/gcc/config/s390/linux.h
476 200 dgisselq
--- gcc-5.3.0-original/gcc/config/s390/linux.h  2016-11-28 18:14:19.386586394 -0500
477 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/s390/linux.h       2015-05-11 03:14:10.000000000 -0400
478
@@ -60,8 +60,8 @@
479
 #define MULTILIB_DEFAULTS { "m31" }
480
 #endif
481
 
482
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld.so.1"
483
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib/ld64.so.1"
484
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1"
485
+#define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1"
486
 
487
 #undef  LINK_SPEC
488
 #define LINK_SPEC \
489
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sh/linux.h gcc-5.3.0-zip/gcc/config/sh/linux.h
490 200 dgisselq
--- gcc-5.3.0-original/gcc/config/sh/linux.h    2016-11-28 18:14:19.386586394 -0500
491 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/sh/linux.h 2015-01-05 07:33:28.000000000 -0500
492
@@ -43,7 +43,7 @@
493
 
494
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
495
 
496
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
497
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
498
 
499
 #undef SUBTARGET_LINK_EMUL_SUFFIX
500
 #define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
501
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux64.h gcc-5.3.0-zip/gcc/config/sparc/linux64.h
502 200 dgisselq
--- gcc-5.3.0-original/gcc/config/sparc/linux64.h       2016-11-28 18:14:19.386586394 -0500
503 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/sparc/linux64.h    2015-01-05 07:33:28.000000000 -0500
504
@@ -84,8 +84,8 @@
505
    When the -shared link option is used a final link is not being
506
    done.  */
507
 
508
-#define GLIBC_DYNAMIC_LINKER32 "/tools/lib/ld-linux.so.2"
509
-#define GLIBC_DYNAMIC_LINKER64 "/tools/lib64/ld-linux.so.2"
510
+#define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
511
+#define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux.so.2"
512
 
513
 #ifdef SPARC_BI_ARCH
514
 
515
@@ -193,7 +193,7 @@
516
 #else /* !SPARC_BI_ARCH */
517
 
518
 #undef LINK_SPEC
519
-#define LINK_SPEC "-m elf64_sparc -Y P,%R/tools/lib64 %{shared:-shared} \
520
+#define LINK_SPEC "-m elf64_sparc -Y P,%R/usr/lib64 %{shared:-shared} \
521
   %{!shared: \
522
     %{!static: \
523
       %{rdynamic:-export-dynamic} \
524
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/sparc/linux.h gcc-5.3.0-zip/gcc/config/sparc/linux.h
525 200 dgisselq
--- gcc-5.3.0-original/gcc/config/sparc/linux.h 2016-11-28 18:14:19.386586394 -0500
526 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/sparc/linux.h      2015-01-05 07:33:28.000000000 -0500
527
@@ -83,7 +83,7 @@
528
    When the -shared link option is used a final link is not being
529
    done.  */
530
 
531
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld-linux.so.2"
532
+#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
533
 
534
 #undef  LINK_SPEC
535
 #define LINK_SPEC "-m elf32_sparc %{shared:-shared} \
536
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/vax/linux.h gcc-5.3.0-zip/gcc/config/vax/linux.h
537 200 dgisselq
--- gcc-5.3.0-original/gcc/config/vax/linux.h   2016-11-28 18:14:19.386586394 -0500
538 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/vax/linux.h        2015-01-05 07:33:28.000000000 -0500
539
@@ -41,7 +41,7 @@
540
   %{!shared: \
541
     %{!static: \
542
       %{rdynamic:-export-dynamic} \
543
-      -dynamic-linker /tools/lib/ld.so.1} \
544
+      -dynamic-linker /lib/ld.so.1} \
545
     %{static:-static}}"
546
 
547
 #undef  WCHAR_TYPE
548
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/xtensa/linux.h gcc-5.3.0-zip/gcc/config/xtensa/linux.h
549 200 dgisselq
--- gcc-5.3.0-original/gcc/config/xtensa/linux.h        2016-11-28 18:14:19.386586394 -0500
550 102 dgisselq
+++ gcc-5.3.0-zip/gcc/config/xtensa/linux.h     2015-01-05 07:33:28.000000000 -0500
551
@@ -44,7 +44,7 @@
552
   %{mlongcalls:--longcalls} \
553
   %{mno-longcalls:--no-longcalls}"
554
 
555
-#define GLIBC_DYNAMIC_LINKER "/tools/lib/ld.so.1"
556
+#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
557
 
558
 #undef LINK_SPEC
559
 #define LINK_SPEC \
560
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/netbsd.h gcc-5.3.0-zip/gcc/config/zip/netbsd.h
561
--- gcc-5.3.0-original/gcc/config/zip/netbsd.h  1969-12-31 19:00:00.000000000 -0500
562
+++ gcc-5.3.0-zip/gcc/config/zip/netbsd.h       2016-01-30 15:04:14.796899050 -0500
563
@@ -0,0 +1,82 @@
564
+////////////////////////////////////////////////////////////////////////////////
565
+//
566
+// Filename:   netbsd.h
567
+//
568
+// Project:    Zip CPU backend for the GNU Compiler Collection
569
+//
570
+// Purpose:
571
+//
572
+// Creator:    Dan Gisselquist, Ph.D.
573
+//             Gisselquist Technology, LLC
574
+//
575
+////////////////////////////////////////////////////////////////////////////////
576
+//
577
+// Copyright (C) 2016, Gisselquist Technology, LLC
578
+//
579
+// This program is free software (firmware): you can redistribute it and/or
580
+// modify it under the terms of  the GNU General Public License as published
581
+// by the Free Software Foundation, either version 3 of the License, or (at
582
+// your option) any later version.
583
+//
584
+// This program is distributed in the hope that it will be useful, but WITHOUT
585
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
586
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
587
+// for more details.
588
+//
589
+// You should have received a copy of the GNU General Public License along
590
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
591
+// target there if the PDF file isn't present.)  If not, see
592
+// <http://www.gnu.org/licenses/> for a copy.
593
+//
594
+// License:    GPL, v3, as defined and found on www.gnu.org,
595
+//             http://www.gnu.org/licenses/gpl.html
596
+//
597
+//
598
+////////////////////////////////////////////////////////////////////////////////
599
+#ifndef        ZIP_NETBSD_H
600
+#define        ZIP_NETBSD_H
601
+
602
+/* Define default target values. */
603
+
604
+#undef MACHINE_TYPE
605
+#define        MACHINE_TYPE    "NetBSD/Zip ELF"
606
+
607
+#undef TARGET_OS_CPP_BUILTINS
608
+#define        TARGET_OS_CPP_BUILTINS()        \
609
+       do { NETBSD_OS_CPP_BUILTINS_ELF();              \
610
+       builtin_define("__ZIPCPU__");                   \
611
+       builtin_assert("cpu=zip");                      \
612
+       builtin_assert("machine=zip");                  \
613
+       } while(0);
614
+
615
+#undef CPP_SPEC
616
+#define        CPP_SPEC        NETBSD_CPP_SPEC
617
+
618
+#undef STARTFILE_SPEC
619
+#define        STARTFILE_SPEC  NETBSD_STARTFILE_SPEC
620
+
621
+#undef ENDFILE_SPEC
622
+#define        ENDFILE_SPEC    NETBSD_ENDFILE_SPEC
623
+
624
+#undef LIB_SPEC
625
+#define        LIB_SPEC        NETBSD_LIB_SPEC
626
+
627
+#undef TARGET_VERSION
628
+#define        TARGET_VERSION  fprintf(stderr, " (%s)", MACHINE_TYPE);
629
+
630
+/* Make gcc agree with <machine/ansi.h> */
631
+
632
+#undef WCHAR_TYPE
633
+#define        WCHAR_TYPE      "int"
634
+
635
+#undef WCHAR_TYPE_SIZE
636
+#define        WCHAR_TYPE_SIZE 32
637
+
638
+#undef WINT_TYPE
639
+#define        WINT_TYPE       "int"
640
+
641
+/* Clean up after the generic Zip/ELF configuration. */
642
+#undef MD_EXEC_PREFIX
643
+#undef MD_STARTFILE_PREFIX
644
+
645
+#endif /* ZIP_NETBSD_H */
646 171 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/notes.txt gcc-5.3.0-zip/gcc/config/zip/notes.txt
647
--- gcc-5.3.0-original/gcc/config/zip/notes.txt 1969-12-31 19:00:00.000000000 -0500
648
+++ gcc-5.3.0-zip/gcc/config/zip/notes.txt      2016-08-17 23:00:25.714139174 -0400
649
@@ -0,0 +1,6 @@
650
+signum:
651
+       CMP       0,%1
652
+       LDILO.GT  1,%1
653
+       LDILO.LT -1,%1
654
+
655
+
656 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/t-zip gcc-5.3.0-zip/gcc/config/zip/t-zip
657
--- gcc-5.3.0-original/gcc/config/zip/t-zip     1969-12-31 19:00:00.000000000 -0500
658
+++ gcc-5.3.0-zip/gcc/config/zip/t-zip  2016-02-04 19:00:59.939652587 -0500
659
@@ -0,0 +1,47 @@
660
+################################################################################
661
+##
662
+## Filename:   t-zip
663
+##
664
+## Project:    Zip CPU backend for the GNU Compiler Collection
665
+##
666
+## Purpose:
667
+##
668
+## Creator:    Dan Gisselquist, Ph.D.
669
+##             Gisselquist Technology, LLC
670
+##
671
+################################################################################
672
+##
673
+## Copyright (C) 2016, Gisselquist Technology, LLC
674
+##
675
+## This program is free software (firmware): you can redistribute it and/or
676
+## modify it under the terms of  the GNU General Public License as published
677
+## by the Free Software Foundation, either version 3 of the License, or (at
678
+## your option) any later version.
679
+##
680
+## This program is distributed in the hope that it will be useful, but WITHOUT
681
+## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
682
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
683
+## for more details.
684
+##
685
+## You should have received a copy of the GNU General Public License along
686
+## with this program.  (It's in the $(ROOT)/doc directory, run make with no
687
+## target there if the PDF file isn't present.)  If not, see
688
+## <http://www.gnu.org/licenses/> for a copy.
689
+##
690
+## License:    GPL, v3, as defined and found on www.gnu.org,
691
+##             http://www.gnu.org/licenses/gpl.html
692
+##
693
+##
694
+################################################################################
695
+
696
+FPBIT = fp-bit.c
697
+DPBIT = dp-bit.c
698
+
699
+# dp-bit.c: $(srcdir)/config/fp-bit.c
700
+       # cat $(srcdir)/config/fp-bit.c > dp-bit.c
701
+#
702
+# fp-bit.c: $(srcdir)/config/fp-bit.c
703
+       # echo '#define FLOAT" > fp-bit.c
704
+       # cat $(srcdir)/config/fp-bit.c >> fp-bit.c
705
+
706
+
707
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.c gcc-5.3.0-zip/gcc/config/zip/zip.c
708
--- gcc-5.3.0-original/gcc/config/zip/zip.c     1969-12-31 19:00:00.000000000 -0500
709 200 dgisselq
+++ gcc-5.3.0-zip/gcc/config/zip/zip.c  2016-11-19 08:28:56.703678695 -0500
710
@@ -0,0 +1,2293 @@
711 102 dgisselq
+////////////////////////////////////////////////////////////////////////////////
712
+//
713
+// Filename:   zip.c
714
+//
715
+// Project:    Zip CPU backend for the GNU Compiler Collection
716
+//
717
+// Purpose:
718
+//
719
+// Creator:    Dan Gisselquist, Ph.D.
720
+//             Gisselquist Technology, LLC
721
+//
722
+////////////////////////////////////////////////////////////////////////////////
723
+//
724
+// Copyright (C) 2016, Gisselquist Technology, LLC
725
+//
726
+// This program is free software (firmware): you can redistribute it and/or
727
+// modify it under the terms of  the GNU General Public License as published
728
+// by the Free Software Foundation, either version 3 of the License, or (at
729
+// your option) any later version.
730
+//
731
+// This program is distributed in the hope that it will be useful, but WITHOUT
732
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
733
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
734
+// for more details.
735
+//
736
+// You should have received a copy of the GNU General Public License along
737
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
738
+// target there if the PDF file isn't present.)  If not, see
739
+// <http://www.gnu.org/licenses/> for a copy.
740
+//
741
+// License:    GPL, v3, as defined and found on www.gnu.org,
742
+//             http://www.gnu.org/licenses/gpl.html
743
+//
744
+//
745
+////////////////////////////////////////////////////////////////////////////////
746
+#include "config.h"
747
+#include "system.h"
748
+#include "coretypes.h"
749
+#include "tm.h"
750
+#include "rtl.h"
751
+#include "dominance.h"
752
+#include "cfg.h"
753
+#include "cfgrtl.h"
754
+#include "cfganal.h"
755
+#include "lcm.h"
756
+#include "cfgbuild.h"
757
+#include "cfgcleanup.h"
758
+#include "predict.h"
759
+#include "basic-block.h"
760
+#include "df.h"
761
+#include "hashtab.h"
762
+#include "hash-set.h"
763
+#include "machmode.h"
764
+#include "symtab.h"
765
+#include "rtlhash.h"
766
+#include "tree.h"
767
+#include "regs.h"
768
+#include "hard-reg-set.h"
769
+#include "real.h"
770
+#include "insn-config.h"
771
+#include "conditions.h"
772
+#include "output.h"
773
+#include "insn-attr.h"
774
+#include "flags.h"
775
+#include "expr.h"
776
+#include "function.h"
777
+#include "recog.h"
778
+#include "toplev.h"
779
+#include "ggc.h"
780
+#include "builtins.h"
781
+#include "calls.h"
782
+#include "langhooks.h"
783
+#include "optabs.h"
784
+#include "explow.h"
785
+#include "emit-rtl.h"
786 122 dgisselq
+#include "ifcvt.h"
787 102 dgisselq
+
788
+// #include "tmp_p.h"
789
+#include "target.h"
790
+#include "target-def.h"
791
+// #include "tm-constrs.h"
792 122 dgisselq
+#include "tm-preds.h"
793 102 dgisselq
+
794
+#include "diagnostic.h"
795
+// #include "integrate.h"
796
+
797 200 dgisselq
+#include "zip-protos.h"
798
+
799 102 dgisselq
+// static int  zip_arg_partial_bytes(CUMULATIVE_ARGS *, enum machine_mode, tree, bool);
800
+// static      bool    zip_pass_by_reference(CUMULATIVE_ARGS *, enum machine_mode, const_tree, bool);
801
+static bool    zip_return_in_memory(const_tree, const_tree);
802
+static bool    zip_frame_pointer_required(void);
803
+
804
+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode,
805
+               const_tree type, bool named);
806
+static rtx zip_function_arg(cumulative_args_t ca, enum machine_mode mode, const_tree type, bool named);
807
+
808
+static void    zip_asm_trampoline_template(FILE *);
809
+static void    zip_trampoline_init(rtx, tree, rtx);
810
+static void    zip_init_builtins(void);
811
+static tree zip_builtin_decl(unsigned, bool);
812
+// static void zip_asm_output_anchor(rtx x);
813
+       void    zip_asm_output_def(FILE *s, const char *n, const char *v);
814
+static rtx     zip_expand_builtin(tree exp, rtx target, rtx subtarget,
815
+                       enum machine_mode tmode, int    ignore);
816
+static bool    zip_scalar_mode_supported_p(enum machine_mode mode);
817
+static bool    zip_libgcc_floating_mode_supported_p(enum machine_mode mode);
818
+static int     zip_address_cost(rtx addr, enum machine_mode mode, addr_space_t as, bool spd);
819
+static bool    zip_mode_dependent_address_p(const_rtx addr, addr_space_t);
820
+static unsigned HOST_WIDE_INT  zip_const_anchor = 0x20000;
821 122 dgisselq
+static          HOST_WIDE_INT  zip_min_opb_imm = -0x20000;
822
+static          HOST_WIDE_INT  zip_max_opb_imm =  0x1ffff;
823 142 dgisselq
+static          HOST_WIDE_INT  zip_min_anchor_offset = -0x2000;
824
+static          HOST_WIDE_INT  zip_max_anchor_offset =  0x1fff;
825 102 dgisselq
+static          HOST_WIDE_INT  zip_min_mov_offset = -0x1000;
826
+static          HOST_WIDE_INT  zip_max_mov_offset =  0x0fff;
827
+static int     zip_sched_issue_rate(void) { return 1; }
828
+static bool    zip_legitimate_address_p(machine_mode, rtx, bool);
829
+static bool    zip_legitimate_move_operand_p(machine_mode, rtx, bool);
830
+       void    zip_debug_rtx_pfx(const char *, const_rtx x);
831
+       void    zip_debug_rtx(const_rtx x);
832
+static void    zip_override_options(void);
833
+static bool    zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
834
+static int     zip_memory_move_cost(machine_mode, reg_class_t, bool);
835 111 dgisselq
+static rtx     zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
836 117 dgisselq
+static bool    zip_cannot_modify_jumps_p(void);
837 122 dgisselq
+#ifdef HAVE_cc0
838
+       void    zip_update_cc_notice(rtx exp, rtx_insn *insn);
839
+#error "We're not supposed to have CC0 anymore"
840
+#else
841
+static bool    zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b);
842
+#endif
843 102 dgisselq
+
844
+
845 103 dgisselq
+#define        ALL_DEBUG_OFF   false
846 102 dgisselq
+#define        ALL_DEBUG_ON    false
847
+
848
+enum ZIP_BUILTIN_ID_CODE {
849
+       ZIP_BUILTIN_RTU,
850
+       ZIP_BUILTIN_HALT,
851
+       ZIP_BUILTIN_IDLE,
852
+       ZIP_BUILTIN_SYSCALL,
853
+       ZIP_BUILTIN_SAVE_CONTEXT,
854
+       ZIP_BUILTIN_RESTORE_CONTEXT,
855
+       ZIP_BUILTIN_BITREV,
856
+       ZIP_BUILTIN_CC,
857 117 dgisselq
+       ZIP_BUILTIN_UCC,
858 171 dgisselq
+       ZIP_BUILTIN_BUSY,
859 102 dgisselq
+       ZIP_BUILTIN_MAX
860
+};
861
+
862
+static GTY (()) tree   zip_builtins[(int)ZIP_BUILTIN_MAX];
863
+static enum insn_code  zip_builtins_icode[(int)ZIP_BUILTIN_MAX];
864
+
865
+
866
+#include "gt-zip.h"
867
+
868
+/* The Global 'targetm' Variable. */
869
+struct gcc_target      targetm = TARGET_INITIALIZER;
870
+
871
+
872
+enum   reg_class zip_reg_class(int);
873
+
874
+#define        LOSE_AND_RETURN(msgid, x)               \
875
+       do {                                    \
876
+               zip_operand_lossage(msgid, x);  \
877
+               return;                         \
878
+       } while(0)
879
+
880
+/* Per-function machine data. */
881
+struct GTY(()) machine_function
882
+{
883
+       /* number of pretented arguments for varargs */
884
+       int     pretend_size;
885
+
886
+       /* Number of bytes saved on the stack for local variables. */
887
+       int     local_vars_size;
888
+
889
+       /* Number of bytes saved on stack for register save area */
890
+       int     saved_reg_size;
891
+       int     save_ret;
892
+
893
+       int     sp_fp_offset;
894
+       bool    fp_needed;
895
+       int     size_for_adjusting_sp;
896
+};
897
+
898
+/* Allocate a chunk of memory for per-function machine-dependent data. */
899
+
900
+static struct machine_function *
901
+zip_init_machine_status(void) {
902
+       return ggc_cleared_alloc<machine_function>();
903
+}
904
+
905
+static void
906
+zip_override_options(void)
907
+{
908
+       init_machine_status = zip_init_machine_status;
909
+}
910
+
911
+enum   reg_class
912
+zip_reg_class(int regno)
913
+{
914
+       if (is_ZIP_GENERAL_REG(regno)) {
915
+               return GENERAL_REGS;
916
+       } else if (is_ZIP_REG(regno)) {
917
+               return ALL_REGS;
918
+       } return NO_REGS;
919
+}
920
+
921
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
922
+static bool
923
+zip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED) {
924
+       const   HOST_WIDE_INT size = int_size_in_bytes(type);
925
+       return (size == -1)||(size > UNITS_PER_WORD);
926
+}
927
+
928
+/* Emit an error emssage when we're in an asm, and a fatal error for "normal"
929
+ * insn.  Formatted output isn't easily implemented, since we use output operand
930
+ * lossage to output the actual message and handle the categorization of the
931
+ * error.  */
932
+
933
+static void
934
+zip_operand_lossage(const char *msgid, rtx op) {
935
+       fprintf(stderr, "Operand lossage??\n");
936
+       debug_rtx(op);
937
+       zip_debug_rtx(op);
938
+       output_operand_lossage("%s", msgid);
939
+}
940
+
941
+/* The PRINT_OPERAND_ADDRESS worker.   */
942
+void
943
+zip_print_operand_address(FILE *file, rtx x) {
944
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
945
+
946
+       if (dbg) zip_debug_rtx(x);
947
+       switch(GET_CODE(x)) {
948
+               case REG:
949 127 dgisselq
+                       gcc_assert(is_ZIP_REG(REGNO(x)));
950 171 dgisselq
+                       gcc_assert(REGNO(x) < 16);
951 102 dgisselq
+                       fprintf(file, "(%s)", reg_names[REGNO(x)]);
952
+                       break;
953
+               case SYMBOL_REF:
954
+                       fprintf(file, "%s", XSTR(x,0));
955
+                       break;
956
+               case LABEL_REF:
957
+                       x = LABEL_REF_LABEL(x);
958
+               case CODE_LABEL:
959
+                       { char buf[256];
960
+                       ASM_GENERATE_INTERNAL_LABEL(buf, "L", CODE_LABEL_NUMBER(x));
961
+#ifdef ASM_OUTPUT_LABEL_REF
962
+                       ASM_OUTPUT_LABEL_REF(file, buf);
963
+#else
964
+                       assemble_name(file, buf);
965
+#endif
966
+                       }
967
+                       break;
968
+               case PLUS:
969 111 dgisselq
+                       if (!REG_P(XEXP(x, 0))) {
970
+                               fprintf(stderr, "Unsupported address construct\n");
971
+                               zip_debug_rtx(x);
972 102 dgisselq
+                               abort();
973 127 dgisselq
+                       } gcc_assert(is_ZIP_REG(REGNO(XEXP(x,0))));
974 171 dgisselq
+                       gcc_assert(REGNO(XEXP(x,0))<16);
975 127 dgisselq
+                       if (CONST_INT_P(XEXP(x, 1))) {
976 102 dgisselq
+                               if (INTVAL(XEXP(x,1))!=0) {
977
+                                       fprintf(file, "%ld(%s)",
978 135 dgisselq
+                                       (long)INTVAL(XEXP(x, 1)),
979 102 dgisselq
+                                       reg_names[REGNO(XEXP(x, 0))]);
980
+                               } else {
981
+                                       fprintf(file, "(%s)",
982
+                                       reg_names[REGNO(XEXP(x, 0))]);
983
+                               }
984
+                       } else if (GET_CODE(XEXP(x,1)) == SYMBOL_REF) {
985
+                               fprintf(file, "%s(%s)", XSTR(x,0),
986
+                                       reg_names[REGNO(XEXP(x, 0))]);
987
+                       } else if ((GET_CODE(XEXP(x, 1)) == MINUS)
988
+                               && (GET_CODE(XEXP(XEXP(x, 1), 0))==SYMBOL_REF)
989
+                               && (GET_CODE(XEXP(XEXP(x, 1), 1))==SYMBOL_REF)) {
990
+                               fprintf(file, "%s-%s(%s)",
991
+                                       XSTR(XEXP(XEXP(x, 1),0),0),
992
+                                       XSTR(XEXP(XEXP(x, 1),1),0),
993
+                                       reg_names[REGNO(XEXP(x, 0))]);
994
+                       } else
995
+                               fprintf(file, "#INVALID(%s)",
996
+                                       reg_names[REGNO(XEXP(x, 0))]);
997
+                       /*
998
+                       else if (GET_CODE(XEXP(addr, 1)) == LABEL)
999
+                               fprintf(file, "%s(%s)",
1000
+                                       GET_CODE(XEXP(addr, 1)),
1001
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
1002
+                       else if ((GET_CODE(XEXP(addr, 1)) == MINUS)
1003
+                               && (GET_CODE(XEXP(GET_CODE(XEXP(addr, 1)), 0))==LABEL)
1004
+                               && (GET_CODE(XEXP(GET_CODE(XEXP(addr, 1)), 1))==LABEL)) {
1005
+                               fprintf(file, "%s-%s(%s)",
1006
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
1007
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
1008
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
1009
+                       }
1010
+                       */
1011
+                       break;
1012
+               // We don't support direct memory addressing within our
1013
+               // instruction set, even though the instructions themselves
1014
+               // would support direct memory addressing of the lower 18 bits
1015
+               // of memory space.
1016
+               case MEM:
1017
+                       if (dbg) zip_debug_rtx(x);
1018
+                       zip_print_operand_address(file, XEXP(x, 0));
1019
+                       break;
1020 111 dgisselq
+               case CONST_INT:
1021 135 dgisselq
+                       fprintf(file, "%ld",(long)INTVAL(x));
1022 111 dgisselq
+                       break;
1023 102 dgisselq
+               default:
1024 111 dgisselq
+                       fprintf(stderr, "Unknown address format\n");
1025
+                       zip_debug_rtx(x);
1026 102 dgisselq
+                       abort(); break;
1027
+                       // output_addr_const(file, x);
1028
+               break;
1029
+       }
1030
+}
1031
+
1032
+/* The PRINT_OPERAND worker. */
1033
+
1034
+void
1035
+zip_print_operand(FILE *file, rtx x, int code)
1036
+{
1037
+       rtx operand = x;
1038
+       int     rgoff = 0;
1039
+
1040
+       // fprintf(file, "Print Operand!\n");
1041
+
1042
+       /* New code entries should just be added to the switch below.  If
1043
+        * handling is finished, just return.  If handling was just a
1044
+        * modification of the operand, the modified operand should be put in
1045
+        * "operand", and then do a break to let default handling
1046
+        * (zero-modifier) output the operand.
1047
+        */
1048
+       switch(code) {
1049
+               case 0:
1050
+                       /* No code, print as usual. */
1051
+                       break;
1052
+               case 'L':
1053
+                       /* Lower of two registers, print one up */
1054
+                       rgoff = 1;
1055
+                       break;
1056
+               case 'R':
1057
+               case 'H':
1058
+                       /* Higher of a register pair, print normal */
1059
+                       break;
1060
+
1061
+               default:
1062
+                       LOSE_AND_RETURN("invalid operand modifier letter", x);
1063
+       }
1064
+
1065
+       /* Print an operand as without a modifier letter. */
1066
+       switch (GET_CODE(operand)) {
1067
+       case REG:
1068
+               if (REGNO(operand)+rgoff >= FIRST_PSEUDO_REGISTER)
1069
+                       internal_error("internal error: bad register: %d", REGNO(operand));
1070
+               fprintf(file, "%s", reg_names[REGNO(operand)+rgoff]);
1071
+               return;
1072
+       case SCRATCH:
1073
+               LOSE_AND_RETURN("Need a scratch register", x);
1074
+               return;
1075
+
1076
+       case CODE_LABEL:
1077
+       case LABEL_REF:
1078
+       case SYMBOL_REF:
1079
+       case PLUS:
1080
+               PRINT_OPERAND_ADDRESS(file, operand);
1081
+               return;
1082
+       case MEM:
1083
+               PRINT_OPERAND_ADDRESS(file, XEXP(operand, 0));
1084
+               return;
1085
+
1086
+       default:
1087
+               /* No need to handle all strange variants, let
1088
+                * output_addr_const do it for us.
1089
+                */
1090
+               if (CONSTANT_P(operand)) {
1091
+                       output_addr_const(file, operand);
1092
+                       return;
1093
+               }
1094
+
1095
+               LOSE_AND_RETURN("unexpected operand", x);
1096
+       }
1097
+}
1098
+
1099
+static bool
1100
+zip_frame_pointer_required(void)
1101
+{
1102
+       // This should really depend upon whether we have variable sized
1103
+       // arguments in our frame or not.  Once this fails, let's look
1104
+       // at what the problem was and then whether or not we can detect
1105
+       // it.
1106
+       //
1107
+       // Use a GCC global to determine our answer
1108 103 dgisselq
+       if (cfun->calls_alloca)
1109
+               return true;
1110 102 dgisselq
+       return (frame_pointer_needed);
1111
+/*
1112
+*/
1113
+}
1114
+
1115
+/* Determine whether or not a register needs to be saved on the stack or not.
1116
+ */
1117
+static bool
1118
+zip_save_reg(int regno) {
1119
+       if (regno == 0)
1120
+               return ((!crtl->is_leaf)
1121
+                       ||((df_regs_ever_live_p(0))&&(!call_used_regs[0])));
1122
+       else if ((regno == zip_GOT)&&(!ZIP_PIC))
1123
+               return  ((df_regs_ever_live_p(regno))
1124
+                               &&(!call_used_regs[regno]));
1125
+       else if (regno == zip_FP)
1126
+               return((zip_frame_pointer_required())||((df_regs_ever_live_p(regno))
1127
+                               &&(!call_used_regs[regno])));
1128
+       else if (regno < zip_FP)
1129
+               return  ((df_regs_ever_live_p(regno))
1130
+                               &&(!call_used_regs[regno]));
1131
+       return false;
1132
+}
1133
+
1134
+/* Compute the size of the local area and the size to be adjusted by the
1135
+ * prologue and epilogue.
1136
+ *
1137
+ * Here's what we are looking at (top is the current, bottom is the last ...)
1138
+ *
1139
+ *     Stack Pointer ->
1140 124 dgisselq
+ *                     Outgoing arguments
1141 102 dgisselq
+ *                     Local variables (could be variable size)
1142
+ *     Frame Pointer ->        (= Stack Pointer + sp_fp_offset)
1143
+ *                     Saved return address, if saved
1144
+ *                     Other Saved registers
1145
+ *                     Saved frame pointer (if used)
1146
+ *                     Saved R12, if used
1147
+ *                     (Stack pointer is not saved)
1148 171 dgisselq
+ *                     (PRETEND-ARGS)
1149 102 dgisselq
+ *     Original stack pointer ->       (= Stack_Pointer +size_for_adjusting_sp)
1150
+ *                     Called arguments (not passed in registers)
1151
+ *                     Return arguments (not R1, args.pretend_args_size)
1152
+ *             (Prior function's stack frame ... )
1153
+ *
1154
+ */
1155
+static void
1156
+zip_compute_frame(void) {
1157
+       int     regno;
1158
+       int     args_size;
1159 124 dgisselq
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
1160 102 dgisselq
+
1161 171 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-COMPUTE-FRAME: %s\n", current_function_name());
1162 102 dgisselq
+       // gcc_assert(crtl);
1163
+       gcc_assert(cfun);
1164
+       gcc_assert(cfun->machine);
1165
+
1166
+       args_size=(ACCUMULATE_OUTGOING_ARGS ? crtl->outgoing_args_size : 0);
1167
+
1168
+       if(crtl->args.pretend_args_size > 0) {
1169
+               args_size += crtl->args.pretend_args_size;
1170 171 dgisselq
+               if (dbg) fprintf(stderr, "%s pretend_args_size : %d\n", current_function_name(),
1171
+                       crtl->args.pretend_args_size);
1172 102 dgisselq
+               cfun->machine->pretend_size = crtl->args.pretend_args_size;
1173
+       }
1174
+
1175
+       cfun->machine->local_vars_size = get_frame_size();
1176
+
1177
+       // Save callee-saved registers.
1178
+       cfun->machine->saved_reg_size = 0;
1179
+       for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
1180
+               if (zip_save_reg(regno))
1181
+                       cfun->machine->saved_reg_size ++;
1182
+       }
1183
+
1184
+       cfun->machine->fp_needed = (zip_frame_pointer_required());
1185
+
1186
+       if ((cfun->machine->fp_needed)&&
1187
+                       (!df_regs_ever_live_p(zip_FP))) {
1188
+               cfun->machine->saved_reg_size ++;
1189
+       }
1190
+
1191 171 dgisselq
+       cfun->machine->sp_fp_offset = crtl->outgoing_args_size
1192
+                               + cfun->machine->local_vars_size;
1193 102 dgisselq
+       cfun->machine->size_for_adjusting_sp = cfun->machine->local_vars_size
1194
+                       + cfun->machine->saved_reg_size
1195
+                       + args_size;
1196 124 dgisselq
+       if(dbg) {
1197 171 dgisselq
+               fprintf(stderr, "\t---- STACK PTR ----\n");
1198
+               fprintf(stderr, "\tOUTGOIN-SIZE: %d\n",
1199
+                       crtl->outgoing_args_size);
1200 124 dgisselq
+               fprintf(stderr, "\tLOCALS-SIZE : %d\n",
1201
+                       cfun->machine->local_vars_size);
1202 171 dgisselq
+               fprintf(stderr, "\t---- FRAME PTR ----%s\n",
1203
+                       cfun->machine->fp_needed?"":" (Eliminated)");
1204 124 dgisselq
+               fprintf(stderr, "\tREGISTERS   : %d\n",
1205
+                       cfun->machine->saved_reg_size);
1206 171 dgisselq
+               fprintf(stderr, "\tPRETEND SIZE: %d\n",
1207
+                       crtl->args.pretend_args_size);
1208
+               fprintf(stderr, "\t---- ARG PTR (Original SP, should be eliminated) ----\n");
1209
+               fprintf(stderr, "\t----\n");
1210
+               fprintf(stderr, "\tARGS-SIZE   : %d\n", args_size);
1211 124 dgisselq
+               fprintf(stderr, "\tSP_FP_OFFSET: %d\n",
1212
+                       cfun->machine->sp_fp_offset);
1213
+               fprintf(stderr, "\tSP-ADJUSTMNT: %d\n",
1214
+                       cfun->machine->size_for_adjusting_sp);
1215
+       }
1216 102 dgisselq
+}
1217
+
1218
+void
1219
+zip_expand_prologue(void) {
1220
+       rtx     insn;
1221
+
1222
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
1223
+       zip_compute_frame();
1224
+
1225 124 dgisselq
+       if (dbg)  fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n");
1226 127 dgisselq
+       if (dbg)  fprintf(stderr, "PROLOGUE: SP-FP offset is %d\n",
1227
+                       cfun->machine->sp_fp_offset);
1228 102 dgisselq
+       if (cfun->machine->size_for_adjusting_sp != 0) {
1229 138 dgisselq
+               insn = emit_insn(gen_subsi3_reg_clobber(stack_pointer_rtx,
1230 102 dgisselq
+                               stack_pointer_rtx,
1231
+                       gen_int_mode(cfun->machine->size_for_adjusting_sp,
1232
+                               SImode)));
1233
+                       // cfun->machine->sp_fp_offset
1234
+
1235
+               RTX_FRAME_RELATED_P(insn) = 1;
1236
+       }
1237
+
1238
+       {
1239
+               int offset = 0, regno;
1240
+               for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
1241
+                       if (zip_save_reg(regno)) {
1242 127 dgisselq
+                               if (dbg) fprintf(stderr,
1243
+                                       "PROLOGUE: Saving R%d in %d+%d(SP)\n",
1244
+                                       regno, cfun->machine->sp_fp_offset,
1245
+                                       offset);
1246 124 dgisselq
+                               insn=emit_insn(gen_movsi_sto_off(
1247
+                                       stack_pointer_rtx,
1248
+                                       GEN_INT(cfun->machine->sp_fp_offset
1249
+                                               +offset++),
1250 102 dgisselq
+                                       gen_rtx_REG(SImode, regno)));
1251
+                               RTX_FRAME_RELATED_P(insn) = 1;
1252
+                       }
1253
+               }
1254 103 dgisselq
+               if (dbg)  fprintf(stderr, "%d registers saved%s\n", offset,
1255
+                       (crtl->saves_all_registers)?", should be all of them":", less than all");
1256 102 dgisselq
+       }
1257
+
1258
+       if (cfun->machine->fp_needed) {
1259
+               if (dbg) zip_debug_rtx(stack_pointer_rtx);
1260
+               if (dbg) zip_debug_rtx(frame_pointer_rtx);
1261
+               insn = emit_insn(gen_movsi_reg_off(frame_pointer_rtx,
1262 124 dgisselq
+                               stack_pointer_rtx,
1263
+                               GEN_INT(cfun->machine->sp_fp_offset)));
1264 102 dgisselq
+               RTX_FRAME_RELATED_P(insn) = 1;
1265 103 dgisselq
+               if (dbg)  fprintf(stderr, "sp_fp_offset is %d\n", cfun->machine->sp_fp_offset);
1266 102 dgisselq
+       }
1267
+}
1268
+
1269 200 dgisselq
+int
1270 102 dgisselq
+zip_use_return_insn(void)
1271
+{
1272
+       if ((!reload_completed)||(cfun->machine->fp_needed)
1273
+                       ||(get_frame_size()!=0)) {
1274
+               // If R0 ever gets pushed to the stack, then we cannot
1275
+               // use a master return from anywhere.  We need to clean up the
1276
+               // stack first.
1277
+               if ((!crtl->is_leaf)||((df_regs_ever_live_p(0))
1278
+                                               &&(!call_used_regs[0]))) {
1279 200 dgisselq
+                       return 0;
1280 102 dgisselq
+               }
1281
+       }
1282
+       zip_compute_frame();
1283 200 dgisselq
+       return (cfun->machine->size_for_adjusting_sp == 0)?1:0;
1284 102 dgisselq
+}
1285
+
1286
+/* As per the notes in M68k.c, quote the function epilogue should not depend
1287
+ * upon the current stack pointer.  It should use the frame poitner only,
1288
+ * if there is a frame pointer.  This is mandatory because of alloca; we also
1289
+ * take advantage of it to omit stack adjustments before returning ...
1290
+ *
1291
+ * Let's see if we can use their approach here.
1292
+ *
1293
+ * We can't.  Consider our choices:
1294
+ *     LOD (FP),R0
1295
+ *     LOD 1(FP),R4
1296
+ *     LOD 2(FP),R5
1297
+ *     LOD 3(FP),R6
1298
+ *     LOD 4(FP),FP
1299
+ *     ... Then what is the stack pointer?
1300
+ * or
1301
+ *     LOD (FP),R0
1302
+ *     LOD 1(FP),R4
1303
+ *     LOD 2(FP),R5
1304
+ *     LOD 3(FP),R6
1305
+ *     MOV FP,SP
1306
+ *     LOD 4(SP),FP
1307
+ *     ... Which suffers unnecessary pipeline stalls, and certainly doesn't
1308
+ *     exploit our pipeline memory function
1309
+ * or
1310
+ *     MOV FP,SP
1311
+ *     LOD (SP),R0
1312
+ *     LOD 1(SP),R4
1313
+ *     LOD 2(SP),R5
1314
+ *     LOD 3(SP),R6
1315
+ *     LOD 4(SP),FP
1316
+ * Which will be our choice.  Note that we do use the stack pointer, eventually.
1317
+ *
1318
+ */
1319
+void
1320
+zip_expand_epilogue(void) {
1321
+       int     regno, offset;
1322
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
1323 138 dgisselq
+       rtx     insn;
1324 102 dgisselq
+
1325
+       zip_compute_frame();
1326
+
1327
+       if (dbg) fprintf(stderr, "EPILOG::\n");
1328
+       if (cfun->machine->fp_needed) {
1329 124 dgisselq
+               // This is done special--if you can't trust the stack pointer
1330
+               // enough so that you must have a frame pointer, then you can't
1331
+               // trust its offset enough to restore from it.  Hence, we start
1332
+               // by moving the frame pointer to the stack pointer to recover
1333
+               // the stack pointer back to a usable value.
1334 102 dgisselq
+               if (dbg) fprintf(stderr, "EPILOG::Moving frame pointer to stack register\n");
1335 138 dgisselq
+               insn = emit_insn(gen_movsi_reg(stack_pointer_rtx, frame_pointer_rtx));
1336
+               RTX_FRAME_RELATED_P(insn) = 1;
1337 102 dgisselq
+       }
1338
+
1339
+       if (cfun->machine->saved_reg_size != 0) {
1340 124 dgisselq
+               if (cfun->machine->fp_needed)
1341
+                       offset = 0;
1342
+               else
1343
+                       offset = cfun->machine->sp_fp_offset;
1344 102 dgisselq
+               if (dbg) fprintf(stderr, "EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
1345
+               for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
1346
+                       if (zip_save_reg(regno)) {
1347
+                               if (dbg) fprintf(stderr, "EPILOG::RESTORING R%d\n", regno);
1348 138 dgisselq
+                               rtx reg = gen_rtx_REG(SImode, regno);
1349
+                               insn = emit_insn(gen_movsi_lod_off(
1350
+                                               reg,
1351 124 dgisselq
+                                               stack_pointer_rtx,
1352
+                                               GEN_INT(offset++)));
1353 138 dgisselq
+                               add_reg_note(insn, REG_CFA_RESTORE, reg);
1354
+                               RTX_FRAME_RELATED_P(insn) = 1;
1355 102 dgisselq
+                       }
1356
+               }
1357
+       }
1358
+
1359 124 dgisselq
+       if (cfun->machine->fp_needed) {
1360
+               // Restore the stack pointer back to the original, the
1361
+               // difference being the difference from the frame pointer
1362
+               // to the original stack
1363 138 dgisselq
+               insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
1364
+                       stack_pointer_rtx,
1365 124 dgisselq
+                       GEN_INT(cfun->machine->size_for_adjusting_sp
1366
+                               -cfun->machine->sp_fp_offset)));
1367 138 dgisselq
+               RTX_FRAME_RELATED_P(insn) = 1;
1368 124 dgisselq
+       } else {
1369
+               // else now the difference is between the stack pointer and
1370
+               // the original stack pointer.
1371 102 dgisselq
+               if (dbg) fprintf(stderr, "EPILOG::ADDSI3(StackPtr, %d)\n",
1372
+                               cfun->machine->size_for_adjusting_sp);
1373 138 dgisselq
+               insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
1374
+                       stack_pointer_rtx,
1375 124 dgisselq
+                       GEN_INT(cfun->machine->size_for_adjusting_sp)));
1376 138 dgisselq
+               RTX_FRAME_RELATED_P(insn) = 1;
1377 102 dgisselq
+       }
1378
+       if (dbg) fprintf(stderr, "EPILOG::EMITTING-RETURN\n");
1379
+
1380 138 dgisselq
+       // The return RTX is not allowed to be frame related
1381
+       insn = emit_jump_insn(ret_rtx);
1382
+       // RTX_FRAME_RELATED_P(insn) = 1;
1383 102 dgisselq
+}
1384
+
1385 191 dgisselq
+void
1386
+zip_sibcall_epilogue(void) {
1387
+       int     regno, offset;
1388
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
1389
+       rtx     insn;
1390
+
1391
+       zip_compute_frame();
1392
+
1393
+       if (dbg) fprintf(stderr, "EPILOG::\n");
1394
+       if (cfun->machine->fp_needed) {
1395
+               // This is done special--if you can't trust the stack pointer
1396
+               // enough so that you must have a frame pointer, then you can't
1397
+               // trust its offset enough to restore from it.  Hence, we start
1398
+               // by moving the frame pointer to the stack pointer to recover
1399
+               // the stack pointer back to a usable value.
1400
+               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::Moving frame pointer to stack register\n");
1401
+               insn = emit_insn(gen_movsi_reg(stack_pointer_rtx, frame_pointer_rtx));
1402
+               RTX_FRAME_RELATED_P(insn) = 1;
1403
+       }
1404
+
1405
+       if (cfun->machine->saved_reg_size != 0) {
1406
+               if (cfun->machine->fp_needed)
1407
+                       offset = 0;
1408
+               else
1409
+                       offset = cfun->machine->sp_fp_offset;
1410
+               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
1411
+               for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
1412
+                       if (zip_save_reg(regno)) {
1413
+                               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::RESTORING R%d\n", regno);
1414
+                               rtx reg = gen_rtx_REG(SImode, regno);
1415
+                               insn = emit_insn(gen_movsi_lod_off(
1416
+                                               reg,
1417
+                                               stack_pointer_rtx,
1418
+                                               GEN_INT(offset++)));
1419
+                               add_reg_note(insn, REG_CFA_RESTORE, reg);
1420
+                               RTX_FRAME_RELATED_P(insn) = 1;
1421
+                       }
1422
+               }
1423
+       }
1424
+
1425
+       if (cfun->machine->fp_needed) {
1426
+               // Restore the stack pointer back to the original, the
1427
+               // difference being the difference from the frame pointer
1428
+               // to the original stack
1429
+               insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
1430
+                       stack_pointer_rtx,
1431
+                       GEN_INT(cfun->machine->size_for_adjusting_sp
1432
+                               -cfun->machine->sp_fp_offset)));
1433
+               RTX_FRAME_RELATED_P(insn) = 1;
1434
+       } else {
1435
+               // else now the difference is between the stack pointer and
1436
+               // the original stack pointer.
1437
+               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::ADDSI3(StackPtr, %d)\n",
1438
+                               cfun->machine->size_for_adjusting_sp);
1439
+               insn = emit_insn(gen_addsi3_reg_clobber(stack_pointer_rtx,
1440
+                       stack_pointer_rtx,
1441
+                       GEN_INT(cfun->machine->size_for_adjusting_sp)));
1442
+               RTX_FRAME_RELATED_P(insn) = 1;
1443
+       }
1444
+}
1445
+
1446 102 dgisselq
+/* Implement RETURN_ADDR_RTX(COUNT, FRAMEADDR).
1447
+ *
1448
+ * We currently only support calculating the return address for the current
1449
+ * frame.
1450
+ */
1451
+
1452
+/*
1453
+rtx
1454
+zip_return_addr_rtx(int count, rtx frame ATTRIBUTE_UNUSED)
1455
+{
1456
+       if (count)
1457
+               return NULL_RTX;
1458
+
1459
+       zip_compute_frame();
1460
+
1461
+       // saved return address for current function is at fp - 1
1462
+       if (cfun->machine->save_ret)
1463
+               return gen_rtx_MEM(Pmode, plus_constant(frame_pointer_rtx,
1464
+                               -UNITS_PER_WORD));
1465
+       return get_hard_reg_initial_val(Pmode, RETURN_ADDRESS_REGNUM);
1466
+}
1467
+*/
1468
+
1469
+/* Implements the macro INITIAL_ELIMINATION_OFFSET,
1470
+ * return the OFFSET.
1471
+ */
1472
+int
1473
+zip_initial_elimination_offset(int from, int to) {
1474
+       int     ret = 0;
1475
+       zip_compute_frame();
1476
+
1477 171 dgisselq
+/*
1478 102 dgisselq
+       if (((from) == FRAME_POINTER_REGNUM)&&((to) == STACK_POINTER_REGNUM)) {
1479
+               ret = cfun->machine->sp_fp_offset;
1480 117 dgisselq
+       } else if (((from)=ARG_POINTER_REGNUM)&&((to)==STACK_POINTER_REGNUM)) {
1481 171 dgisselq
+               // Since the ARG_POINTER_REGNUM is defined to be identical
1482
+               // to the FRAME_POINTER_REGNUM, this "if" will never ever
1483
+               // get called.
1484 117 dgisselq
+               ret = cfun->machine->sp_fp_offset;
1485 102 dgisselq
+       } else if (((from)=ARG_POINTER_REGNUM)&&((to)==FRAME_POINTER_REGNUM)) {
1486 171 dgisselq
+               // Since we define ARG_POINTER_REGNUM to be FRAME_POINTER_REGNUM
1487
+               // we're asked for the offset between the frame pointer and
1488
+               // itself.  The result had better be zero.
1489
+               //
1490 117 dgisselq
+               ret = 0;
1491 102 dgisselq
+       } else {
1492
+               abort();
1493
+       }
1494 171 dgisselq
+*/
1495 102 dgisselq
+
1496 171 dgisselq
+       // Let's try using an ARG_POINTER != FRAME_POINTER
1497
+       if (((from) == FRAME_POINTER_REGNUM)&&((to) == STACK_POINTER_REGNUM)) {
1498
+               ret = cfun->machine->sp_fp_offset;
1499
+       } else if (((from)=ARG_POINTER_REGNUM)&&((to)==STACK_POINTER_REGNUM)) {
1500
+               // Since the ARG_POINTER_REGNUM is defined to be identical
1501
+               // to the FRAME_POINTER_REGNUM, this "if" will never ever
1502
+               // get called.
1503
+               ret = cfun->machine->size_for_adjusting_sp;
1504
+       } else if (((from)=ARG_POINTER_REGNUM)&&((to)==FRAME_POINTER_REGNUM)) {
1505
+               ret = cfun->machine->size_for_adjusting_sp
1506
+                       - cfun->machine->sp_fp_offset;
1507
+       } else {
1508
+               abort();
1509
+       }
1510
+
1511 102 dgisselq
+       return ret;
1512
+}
1513
+
1514
+/*
1515
+ * Code taken from m68k ...
1516
+ */
1517
+static bool
1518
+zip_can_eliminate(int from, int to)
1519
+{
1520
+       // fprintf(stderr, "CAN_ELIMINATE::QUERYING(%d,%d)\n", from, to);
1521
+       if ((from == zip_FP)&&(to == zip_SP))
1522
+               return !cfun->machine->fp_needed;
1523
+       return true;
1524
+}
1525
+
1526
+/*
1527
+static void
1528
+zip_basic_check(void)
1529
+{
1530
+       gcc_assert(mode_base_align[SImode]==4);
1531
+       if ((BITS_PER_UNIT != 32)
1532
+                       ||(GET_MODE_SIZE(SImode)!=1)
1533
+                       ||(GET_MODE_SIZE(DImode)!=1)
1534
+                       ||(HARD_REGNO_NREGS(0,SImode)!=1)) {
1535
+               printf("SIZEOF(SIMode) == %d\n", GET_MODE_SIZE(SImode));
1536
+               printf("BITS_PER_UNIT  == %d\n", BITS_PER_UNIT);
1537
+               gcc_assert(BITS_PER_UNIT==32);
1538
+               gcc_assert(GET_MODE_SIZE(SImode)==1);
1539
+               gcc_assert(HARD_REGNO_NREGS(0,SImode)==1);
1540
+       }
1541
+}
1542
+*/
1543
+
1544
+#define        zip_basic_check()
1545
+
1546 171 dgisselq
+/* Compute the number of word sized registers needed to hold a function
1547 102 dgisselq
+ * argument of mode INT_MODE and tree type TYPE.
1548
+ */
1549
+int
1550
+zip_num_arg_regs(enum machine_mode mode, const_tree type) {
1551
+       int     size;
1552
+
1553
+       zip_basic_check();
1554
+
1555
+       if (targetm.calls.must_pass_in_stack(mode, type))
1556
+               return 0;
1557
+
1558
+       if ((type)&&(mode == BLKmode))
1559
+               size = int_size_in_bytes(type);
1560
+       else
1561
+               size = GET_MODE_SIZE(mode);
1562
+
1563
+       return (size + UNITS_PER_WORD - 1)/UNITS_PER_WORD;
1564
+}
1565
+
1566
+static void
1567
+zip_function_arg_advance(cumulative_args_t ca, machine_mode mode,
1568
+               const_tree type, bool named ATTRIBUTE_UNUSED) {
1569
+       CUMULATIVE_ARGS *cum;
1570
+       int     nreg;
1571
+
1572
+       zip_basic_check();
1573
+
1574
+       cum = get_cumulative_args(ca);
1575
+       nreg = zip_num_arg_regs(mode, type);
1576
+       if (((*cum)+nreg) > NUM_ARG_REGS)
1577
+               (*cum) = NUM_ARG_REGS;
1578
+       else
1579
+               (*cum) += nreg;
1580
+}
1581
+
1582
+static rtx
1583
+zip_function_arg(cumulative_args_t ca, machine_mode mode,
1584
+               const_tree type ATTRIBUTE_UNUSED, bool named) {
1585
+       CUMULATIVE_ARGS *cum;
1586
+
1587
+       zip_basic_check();
1588
+
1589
+
1590
+       if (!named)
1591
+               return NULL_RTX;
1592
+       //if (targetm.calls.must_pass_in_stack(mode, type))
1593
+               //return NULL_RTX;
1594
+       cum = get_cumulative_args(ca);
1595
+
1596
+       if ((*cum) >= NUM_ARG_REGS)
1597
+               return NULL_RTX;
1598
+       return
1599
+               gen_rtx_REG(mode, (*cum)+1);
1600
+}
1601
+
1602 191 dgisselq
+/* DECL is the declaration of the function being targeted by the call, and EXP
1603
+ * is the CALL_EXPR representing the call.
1604
+ */
1605
+bool   zip_function_ok_for_sibcall(ATTRIBUTE_UNUSED tree decl, tree exp) {
1606
+       // calls.c already checks whether or not the parameter stack space
1607
+       // is identical, so ... let's hope this all works and find out.
1608
+
1609
+       //
1610
+       // Actually, this will fail:  If the sibling uses R5 to pass registers
1611
+       // in and we don't, then there will be no way to restore R5.  This is
1612
+       // true for the current configuration.  It will be true for future
1613
+       // configurations if the sibling ever uses a register that must be
1614
+       // saved as a parameter register.
1615
+       //
1616
+       // We can check this ... if we can count how many registers the
1617
+       // sibling call will use.
1618
+       //
1619
+       CUMULATIVE_ARGS cum_v;
1620
+       cumulative_args_t       cum;
1621
+       tree            parameter;
1622
+       machine_mode    mode;
1623
+       tree            ttype;
1624
+       rtx             parm_rtx;
1625
+       int             i;
1626
+       static const char zip_call_used_register[] = CALL_USED_REGISTERS;
1627
+
1628
+       INIT_CUMULATIVE_ARGS(cum_v, NULL, NULL, 0,0);
1629
+       cum = pack_cumulative_args(&cum_v);
1630
+       for (i=0; i<call_expr_nargs(exp); i++) {
1631
+
1632
+               parameter = CALL_EXPR_ARG(exp, i);
1633
+
1634
+               if ((!parameter) || (TREE_CODE(parameter)==ERROR_MARK))
1635
+                       return true;
1636
+               ttype = TREE_TYPE(parameter);
1637
+               gcc_assert(ttype);
1638
+               mode = ttype->type_common.mode;
1639
+
1640
+               if (pass_by_reference(&cum_v, mode, ttype, true)) {
1641
+                       mode = Pmode;
1642
+                       ttype = build_pointer_type(ttype);
1643
+               }
1644
+
1645
+               parm_rtx = zip_function_arg(cum, mode, ttype, 0);
1646
+               zip_function_arg_advance(cum, mode, ttype, 0);
1647
+               if (!parm_rtx)
1648
+                       continue;
1649
+
1650
+               // If it is a register
1651
+               //      and it is *NOT* a CALL_USED_REGISTER
1652
+               //      then we can't do this.
1653
+               //
1654
+               // Example: func(R1,..R4,R5)
1655
+               //      can be followed by func2(R1,.., up to R5)
1656
+               //      (not supported, though... just to simplify our test
1657
+               //      below)
1658
+               // Example: func(R1,..R4)
1659
+               //      cannot be followed by func2(R1,..,R5)
1660
+               //      We would blow R5 away by our prologue, even if it was
1661
+               //      properly set.
1662
+               // Example: func(R1,..R5)
1663
+               //      can be followed by func2(R1,.., up to R4)
1664
+               //      func2 may save R5 (which doesn't need saving) but that's
1665
+               //              irrelevant
1666
+               // Example: func(R1,..up to R4)
1667
+               //      can be followed by func2(R1,.., up to R4)
1668
+               //
1669
+               if (REG_P(parm_rtx)&&(REGNO(parm_rtx))
1670
+                               &&(REGNO(parm_rtx)<sizeof(zip_call_used_register))
1671
+                               &&(!zip_call_used_register[REGNO(parm_rtx)]))
1672
+                       return false;
1673
+       }
1674
+
1675
+       return true;
1676
+
1677
+       // We also need to check if the return types are the same ... or
1678
+       // will GCC handle that for us?
1679
+}
1680
+
1681 122 dgisselq
+void   zip_canonicalize_comparison(int *code, rtx *op0, rtx *op1,
1682
+               bool preserve_op0)
1683
+{
1684
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
1685 102 dgisselq
+
1686 122 dgisselq
+       if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
1687
+       if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, gen_rtx_REG(CCmode,zip_CC), const0_rtx));
1688
+       if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
1689
+       if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
1690
+
1691
+       if ((!preserve_op0)&&((*code == LE)||(*code == GTU)||(*code == GEU))) {
1692
+               rtx tem = *op0;
1693
+               *op0 = *op1;
1694
+               *op1 = tem;
1695
+               *code = (int)swap_condition((enum rtx_code)*code);
1696
+       }
1697
+
1698
+       if ((*code == LE)||(*code == LEU)||(*code == GTU)) {
1699
+               int offset = 1; // (*code == GTU) ? 1 : -1;
1700
+               bool    swap = false;
1701
+
1702
+               if (CONST_INT_P(*op1)) {
1703
+                       *op1 = GEN_INT(INTVAL(*op1)+offset);
1704
+                       swap = true;
1705
+               } else if (REG_P(*op1)) {
1706 138 dgisselq
+                       *op1 = plus_constant(GET_MODE(*op1), *op1, offset, true);
1707 122 dgisselq
+                       swap = true;
1708
+               } else if ((GET_CODE(*op1)==PLUS)&&(CONST_INT_P(XEXP(*op1,1)))){
1709
+                       *op1 = plus_constant(GET_MODE(*op1),XEXP(*op1,0),
1710
+                               INTVAL(XEXP(*op1,1))+offset);
1711
+                       swap = true;
1712
+               } if (swap) {
1713
+                       if (*code == LE)
1714
+                               (*code)= LT;
1715
+                       else if (*code == LEU)
1716
+                               (*code)= LTU;
1717
+                       else // (*code == GTU)
1718
+                               (*code) = GEU;
1719
+               }
1720
+       }
1721
+}
1722
+
1723
+static bool
1724
+zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b) {
1725
+       *a = zip_CC;
1726
+       *b = INVALID_REGNUM;
1727
+       return true;
1728
+}
1729
+
1730
+
1731 102 dgisselq
+/* totally buggy - we can't return pointers to nested functions */
1732
+static void
1733
+zip_asm_trampoline_template(FILE *f) {
1734
+       // Whereas at one time I thought I wouldn't need it, now I know I
1735
+       // need this trampoline function, although it is for a completely
1736
+       // different purpose than the one I was familiar with.
1737 138 dgisselq
+       fprintf(f, "\tbrev\t0,r1\n");
1738
+       fprintf(f, "\tldilo\t0,r1\n");
1739 102 dgisselq
+       fprintf(f, "\tjmp r1\n");
1740
+}
1741
+
1742
+/* Worker function for TARGET_TRAMPOLINE_INIT. */
1743
+static void
1744
+zip_trampoline_init(rtx m_tramp ATTRIBUTE_UNUSED,
1745
+       tree fndecl ATTRIBUTE_UNUSED,
1746
+       rtx chain_value ATTRIBUTE_UNUSED) {
1747
+// #warning "This needs to be filled out"
1748
+       abort();
1749
+}
1750
+
1751
+static tree
1752
+def_builtin(const char *name, enum insn_code icode, enum ZIP_BUILTIN_ID_CODE code,
1753
+       tree type)
1754
+{
1755
+       tree t = add_builtin_function(name,type,code,BUILT_IN_MD, NULL, NULL_TREE);
1756
+       zip_basic_check();
1757
+
1758
+       if(t) {
1759
+               zip_builtins[code] = t;
1760
+               zip_builtins_icode[code] = icode;
1761
+       }
1762
+
1763
+       return t;
1764
+
1765
+}
1766
+
1767
+void   zip_init_builtins(void) {
1768
+       zip_basic_check();
1769
+
1770
+  tree void_ftype_void = build_function_type_list(void_type_node, NULL_TREE);
1771
+#ifdef HAVE_zip_rtu
1772
+  def_builtin("zip_rtu", CODE_FOR_zip_rtu, ZIP_BUILTIN_RTU, void_ftype_void);
1773
+#endif
1774
+#ifdef HAVE_zip_halt
1775
+  def_builtin("zip_halt",  CODE_FOR_zip_halt,  ZIP_BUILTIN_HALT, void_ftype_void);
1776
+#endif
1777 171 dgisselq
+#ifdef HAVE_zip_busy
1778
+  def_builtin("zip_busy",  CODE_FOR_zip_busy,  ZIP_BUILTIN_BUSY, void_ftype_void);
1779
+#endif
1780 102 dgisselq
+#ifdef HAVE_zip_idle
1781
+  def_builtin("zip_idle", CODE_FOR_zip_idle, ZIP_BUILTIN_IDLE, void_ftype_void);
1782
+#endif
1783
+
1784
+#ifdef HAVE_zip_syscall
1785
+// Support int SYSCALL(callID, int a, int b, int c);
1786
+  def_builtin("zip_syscall", CODE_FOR_zip_syscall, ZIP_BUILTIN_SYSCALL,
1787
+                       build_function_type_list(void_type_node, NULL_TREE));
1788
+#endif
1789
+
1790
+#ifdef HAVE_zip_save_context
1791
+  def_builtin("zip_save_context", CODE_FOR_zip_save_context, ZIP_BUILTIN_SAVE_CONTEXT,
1792
+               build_function_type_list(void_type_node, ptr_type_node, 0));
1793
+#endif
1794
+
1795
+#ifdef HAVE_zip_restore_context
1796
+  def_builtin("zip_restore_context", CODE_FOR_zip_restore_context, ZIP_BUILTIN_RESTORE_CONTEXT,
1797
+       build_function_type_list(void_type_node, ptr_type_node, 0));
1798
+#endif
1799
+
1800
+#ifdef HAVE_zip_bitrev
1801
+  def_builtin("zip_bitrev", CODE_FOR_zip_bitrev, ZIP_BUILTIN_BITREV,
1802
+       build_function_type_list(unsigned_type_node, unsigned_type_node,
1803
+               NULL_TREE));
1804
+#endif
1805
+
1806
+#ifdef HAVE_zip_cc
1807
+  def_builtin("zip_cc", CODE_FOR_zip_cc, ZIP_BUILTIN_CC,
1808
+       build_function_type_list(unsigned_type_node, NULL_TREE));
1809
+#endif
1810
+
1811 117 dgisselq
+#ifdef HAVE_zip_ucc
1812
+  def_builtin("zip_ucc", CODE_FOR_zip_ucc, ZIP_BUILTIN_UCC,
1813
+       build_function_type_list(unsigned_type_node, NULL_TREE));
1814
+#endif
1815
+
1816 102 dgisselq
+}
1817
+
1818
+static tree
1819
+zip_builtin_decl(unsigned zip_builtin_code, bool initialize_p ATTRIBUTE_UNUSED)
1820
+{
1821
+  if (zip_builtin_code >= ZIP_BUILTIN_MAX)
1822
+    return error_mark_node;
1823
+
1824
+  return zip_builtins[zip_builtin_code];
1825
+}
1826
+
1827
+static rtx
1828
+zip_expand_builtin(tree exp, rtx target,
1829
+               rtx subtarget ATTRIBUTE_UNUSED,
1830
+               machine_mode tmode ATTRIBUTE_UNUSED,
1831
+               int     ignore ATTRIBUTE_UNUSED) {
1832
+
1833
+       tree    fndecl = TREE_OPERAND(CALL_EXPR_FN(exp), 0);
1834
+       bool    nonvoid = (TREE_TYPE(TREE_TYPE(fndecl)) != void_type_node);
1835
+       enum    ZIP_BUILTIN_ID_CODE code=(enum ZIP_BUILTIN_ID_CODE)DECL_FUNCTION_CODE(fndecl);
1836
+       enum    insn_code icode = zip_builtins_icode[code];
1837
+       rtx     pat, op[5];
1838
+       call_expr_arg_iterator  iter;
1839
+       tree    arg;
1840
+
1841
+       if ((code == ZIP_BUILTIN_SAVE_CONTEXT)
1842
+                       ||(code == ZIP_BUILTIN_RESTORE_CONTEXT)) {
1843
+               arg = first_call_expr_arg(exp, &iter);
1844
+               if (arg == error_mark_node)
1845
+                       return NULL_RTX;
1846
+               op[0] = expand_normal(arg);
1847
+               if (GET_CODE(op[0]) != REG)
1848
+                       op[0] = force_reg(Pmode, op[0]);
1849
+               pat = GEN_FCN(icode)(op[0]);
1850
+       } else if (code == ZIP_BUILTIN_BITREV) {
1851
+               arg = first_call_expr_arg(exp, &iter);
1852
+               if (arg == error_mark_node) {
1853
+                       return NULL_RTX;
1854
+               }
1855
+               op[0] = expand_normal(arg);
1856
+               if (!target)
1857
+                       target = gen_reg_rtx(SImode);
1858
+               pat = GEN_FCN(icode)(target, op[0]);
1859 117 dgisselq
+       } else if ((code == ZIP_BUILTIN_CC)||(code == ZIP_BUILTIN_UCC)) {
1860 102 dgisselq
+               if (!target)
1861
+                       target = gen_reg_rtx(SImode);
1862
+               pat = GEN_FCN(icode)(target);
1863
+       } else // RTU, HALT, IDLE
1864
+               pat = GEN_FCN(icode)();
1865
+       if (!pat)
1866
+               return NULL_RTX;
1867
+       emit_insn(pat);
1868
+       return (nonvoid ? target : const0_rtx);
1869
+}
1870
+
1871
+static bool
1872
+zip_scalar_mode_supported_p(enum machine_mode mode) {
1873
+       zip_basic_check();
1874
+
1875
+       return ((mode)==SImode)||((mode)==DImode); // ||((mode)==SFmode);
1876
+}
1877
+
1878
+static bool
1879
+zip_libgcc_floating_mode_supported_p(enum machine_mode mode) {
1880
+       return ((mode)==SFmode)||((mode)==DFmode);
1881
+}
1882
+
1883
+static int
1884
+zip_address_cost(rtx addr ATTRIBUTE_UNUSED,
1885
+       enum machine_mode mode ATTRIBUTE_UNUSED,
1886
+       addr_space_t as ATTRIBUTE_UNUSED, bool spd ATTRIBUTE_UNUSED) {
1887
+       return 1;
1888
+}
1889
+
1890
+static bool
1891
+zip_mode_dependent_address_p(const_rtx addr ATTRIBUTE_UNUSED,
1892
+       addr_space_t as ATTRIBUTE_UNUSED) {
1893
+       return false;
1894
+}
1895
+
1896
+/*
1897
+static void
1898
+zip_asm_output_anchor(rtx x) {
1899
+       printf("ANCHOR: OP(%d)\n", GET_CODE(x));
1900
+}
1901
+*/
1902
+
1903
+static void
1904
+zip_debug_print(const char *pfx, int lvl, const char *str) {
1905
+       int     i;
1906
+       i = lvl;
1907
+       if ((true)||(lvl == 0))
1908
+               fprintf(stderr, "%s", pfx);
1909
+       else
1910
+               i += strlen(pfx);
1911
+       while(i-->0)
1912
+               fprintf(stderr, "  ");
1913
+       fprintf(stderr, "%s\n", str);
1914
+}
1915
+
1916
+static void
1917
+zip_debug_print_m(const char *pfx, int lvl, const char *str, enum machine_mode m) {
1918
+       int     i;
1919
+
1920
+       i = lvl;
1921
+       if ((true)||(lvl == 0))
1922
+               fprintf(stderr, "%s", pfx);
1923
+       else
1924
+               i = lvl+strlen(pfx);
1925
+       while(i-->0)
1926
+               fprintf(stderr, "  ");
1927
+       switch(m) {
1928
+               case VOIDmode:
1929
+                       fprintf(stderr, "%s:V\n", str);
1930
+                       break;
1931
+               case BLKmode:
1932
+                       fprintf(stderr, "%s:BLK\n", str);
1933
+                       break;
1934
+               case BImode:
1935
+                       fprintf(stderr, "%s:BI\n", str);
1936
+                       break;
1937
+#ifdef HAVE_QImode
1938
+               case QImode:
1939
+                       fprintf(stderr, "%s:QI\n", str);
1940
+                       break;
1941
+#endif
1942
+#ifdef HAVE_HImode
1943
+               case HImode:
1944
+                       fprintf(stderr, "%s:HI\n", str);
1945
+                       break;
1946
+#endif
1947
+               case SImode:
1948
+                       fprintf(stderr, "%s:SI\n", str);
1949
+                       break;
1950 122 dgisselq
+               case CCmode:
1951
+                       fprintf(stderr, "%s:CC\n", str);
1952
+                       break;
1953 102 dgisselq
+               case DImode:
1954
+                       fprintf(stderr, "%s:DI\n", str);
1955
+                       break;
1956
+               default:
1957
+                       fprintf(stderr, "%s:?\n", str);
1958
+       }
1959
+}
1960
+
1961
+static void
1962
+zip_debug_rtx_1(const char *pfx, const_rtx x, int lvl) {
1963
+       if (x == NULL_RTX) {
1964
+               zip_debug_print(pfx, lvl, "(NULL-RTX)");
1965
+               return;
1966
+       } else if (GET_CODE(x) > NUM_RTX_CODE) {
1967
+               char    buf[64];
1968
+               sprintf(buf, "(BAD-RTX-CODE %d)", GET_CODE(x));
1969
+               zip_debug_print(pfx, lvl, buf);
1970 117 dgisselq
+               gcc_assert(0 && "Bad RTX Code");
1971 102 dgisselq
+               return;
1972
+       } switch(GET_CODE(x)) { // rtl.def
1973 122 dgisselq
+       case PARALLEL:
1974
+               zip_debug_print(pfx, lvl, "(PARALLEL");
1975
+               for(int j=0; j<XVECLEN(x,0);j++)
1976
+                       zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
1977
+               zip_debug_print(pfx, lvl, ")");
1978
+               debug_rtx(x);
1979
+               break;
1980 102 dgisselq
+       case INT_LIST: zip_debug_print(pfx, lvl, "(INT-LIST"); break;
1981 122 dgisselq
+       case SEQUENCE:
1982
+               zip_debug_print(pfx, lvl, "(SEQUENCE");
1983
+               for(int j=0; j<XVECLEN(x,0);j++)
1984
+                       zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
1985
+               zip_debug_print(pfx, lvl, ")");
1986
+               debug_rtx(x);
1987
+               break;
1988 102 dgisselq
+       case ADDRESS: zip_debug_print(pfx, lvl, "(ADDRESS"); break;
1989
+       case DEBUG_INSN: zip_debug_print(pfx, lvl, "(DEBUG-INSN"); break;
1990
+       case INSN:
1991
+               zip_debug_print(pfx, lvl, "(INSN");
1992
+               /*
1993
+               { const rtx_insn *tmp_rtx;
1994
+               for(tmp_rtx = as_a <const rtx_insn *>(x); tmp_rtx != 0; tmp_rtx = NEXT_INSN(tmp_rtx)) {
1995
+                       zip_debug_rtx_1(tmp_rtx, lvl+1);
1996
+               }}
1997
+               */
1998
+               zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
1999
+               zip_debug_print(pfx, lvl, ")");
2000 117 dgisselq
+               debug_rtx(x);
2001 102 dgisselq
+               break;
2002
+       case JUMP_INSN: zip_debug_print(pfx, lvl, "(JUMP-INSN");
2003 111 dgisselq
+               zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
2004
+               zip_debug_print(pfx, lvl, ")");
2005
+               /*
2006 102 dgisselq
+               if (JUMP_LABEL(x)) {
2007 111 dgisselq
+                       if (GET_CODE(JUMP_LABEL(x)) == LABEL_REF) {
2008
+                               char    buf[64];
2009
+                               sprintf(buf, "(LABEL *.L%d))", CODE_LABEL_NUMBER(LABEL_REF_LABEL(JUMP_LABEL(x))));
2010
+                               zip_debug_print(pfx, lvl+1, buf);
2011
+                       } else if (GET_CODE(JUMP_LABEL(x))==CODE_LABEL) {
2012
+                               char    buf[64];
2013
+                               sprintf(buf, "(CODE_LABEL *.L%d))", CODE_LABEL_NUMBER(JUMP_LABEL(x)));
2014
+                               zip_debug_print(pfx, lvl+1, buf);
2015
+                       } else
2016
+                       zip_debug_print(pfx, lvl+1, "(w/Label))");
2017 102 dgisselq
+               } else
2018 111 dgisselq
+                       zip_debug_print(pfx, lvl+1, "(NO label))");
2019
+               debug_rtx(x);
2020
+               */
2021 102 dgisselq
+               break;
2022
+       case CALL:
2023
+               zip_debug_print(pfx, lvl, "(CALL (Adr) (Args)");
2024
+               zip_debug_rtx_1(pfx, XEXP(x,0), lvl+1);
2025
+               zip_debug_rtx_1(pfx, XEXP(x,1), lvl+1);
2026
+               zip_debug_print(pfx, lvl, ")");
2027
+               break;
2028
+       case CALL_INSN: zip_debug_print(pfx, lvl, "(CALL-INSN");
2029
+               debug_rtx(x);
2030
+               break;
2031
+       case BARRIER: zip_debug_print(pfx, lvl, "(BARRIER)"); break;
2032
+       case RETURN: zip_debug_print(pfx, lvl, "(RETURN)"); break;
2033
+       case NOTE:
2034
+               {       char buf[128];
2035
+                       sprintf(buf, "(NOTE %s)", GET_REG_NOTE_NAME(GET_MODE(x)));
2036
+                       zip_debug_print(pfx, lvl, buf);
2037
+               }break;
2038
+       case COND_EXEC: zip_debug_print(pfx, lvl, "(COND_EXEC)");
2039
+               debug_rtx(x);
2040
+               break;
2041
+       case ASM_INPUT: zip_debug_print(pfx, lvl, "(ASM INPUT)"); break;
2042
+       case ASM_OPERANDS: zip_debug_print(pfx, lvl, "(ASM OPERANDS)"); break;
2043
+       case UNSPEC: zip_debug_print(pfx, lvl, "(UNSPEC)"); break;
2044
+       case UNSPEC_VOLATILE: zip_debug_print(pfx, lvl, "(UNSPEC_VOLATILE)"); break;
2045
+       case CODE_LABEL:
2046
+               {
2047 192 dgisselq
+                       char    buf[128];
2048 111 dgisselq
+                       sprintf(buf, "(CODE_LABEL *.L%d)", CODE_LABEL_NUMBER(x));
2049 102 dgisselq
+                       zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
2050
+               } break;
2051
+       case SET:
2052
+               zip_debug_print_m(pfx, lvl, "(SET", GET_MODE(x));
2053 117 dgisselq
+               zip_debug_rtx_1(pfx, SET_DEST(x),lvl+1);
2054
+               zip_debug_rtx_1(pfx, SET_SRC(x),lvl+1);
2055 102 dgisselq
+               zip_debug_print(pfx, lvl, ")");
2056 117 dgisselq
+               debug_rtx(x);
2057 102 dgisselq
+               break;
2058 122 dgisselq
+       case REG: {
2059 127 dgisselq
+               char buf[25], mstr[4];
2060
+               mstr[0] = '\0';
2061
+               if (GET_MODE(x) == SImode)
2062
+                       strcpy(mstr, ":SI");
2063
+               else if (GET_MODE(x) == DImode)
2064
+                       strcpy(mstr, ":DI");
2065
+               else if (GET_MODE(x) == VOIDmode)
2066
+                       strcpy(mstr, ":V");
2067 102 dgisselq
+               if (REGNO(x) == zip_PC)
2068 127 dgisselq
+                       sprintf(buf, "(PC%s)", mstr);
2069 102 dgisselq
+               else if (REGNO(x) == zip_CC)
2070 127 dgisselq
+                       sprintf(buf, "(CC%s)", mstr);
2071 102 dgisselq
+               else if (REGNO(x) == zip_SP)
2072 127 dgisselq
+                       sprintf(buf, "(SP%s)", mstr);
2073 102 dgisselq
+               else if (REGNO(x) == zip_FP)
2074 127 dgisselq
+                       sprintf(buf, "(REG%s FP)", mstr);
2075 102 dgisselq
+               else if (REGNO(x) == zip_GOT)
2076 127 dgisselq
+                       sprintf(buf, "(REG%s GBL)", mstr);
2077 102 dgisselq
+               else if (FUNCTION_VALUE_REGNO_P(REGNO(x)))
2078 127 dgisselq
+                       sprintf(buf, "(REG%s RTN-VL)", mstr);
2079 102 dgisselq
+               else if (REGNO(x) == RETURN_ADDRESS_REGNUM)
2080 127 dgisselq
+                       sprintf(buf, "(REG%s RTN-AD)", mstr);
2081 122 dgisselq
+               else
2082 127 dgisselq
+                       sprintf(buf, "(REG%s %d)", mstr, REGNO(x));
2083
+               if (mstr[0])
2084
+                       zip_debug_print(pfx, lvl, buf);
2085
+               else
2086
+                       zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
2087 102 dgisselq
+               } break;
2088
+       case IF_THEN_ELSE: // 51
2089
+               zip_debug_print(pfx, lvl, "(IF-THEN-ELSE");
2090
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2091
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2092
+               zip_debug_rtx_1(pfx, XEXP(x,2),lvl+1);
2093
+               zip_debug_print(pfx, lvl, ")");
2094
+               break;
2095
+       case PC:
2096
+               zip_debug_print(pfx, lvl, "(PC)");
2097
+               break;
2098
+       case CC0:
2099
+               zip_debug_print(pfx, lvl, "(CC0)");
2100
+               break;
2101
+       case COMPARE:
2102 127 dgisselq
+               zip_debug_print_m(pfx, lvl, "(COMPARE", GET_MODE(x));
2103 102 dgisselq
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2104
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2105
+               zip_debug_print(pfx, lvl, ")");
2106
+               break;
2107 111 dgisselq
+       case CONST:
2108
+               zip_debug_print_m(pfx, lvl, "(CONST", GET_MODE(x));
2109
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2110
+               zip_debug_print(pfx, lvl, ")");
2111
+               break;
2112 102 dgisselq
+       case CONST_INT:
2113 192 dgisselq
+               { char buf[128];
2114 102 dgisselq
+               if (GET_MODE(x)==SImode)
2115 135 dgisselq
+                       sprintf(buf, "(CONST_INT:SI %ld)", (long)INTVAL(x));
2116 102 dgisselq
+               else if (GET_MODE(x)==VOIDmode)
2117 135 dgisselq
+                       sprintf(buf, "(CONST_INT:V %ld)", (long)INTVAL(x));
2118 102 dgisselq
+               else
2119 135 dgisselq
+                       sprintf(buf, "(CONST_INT:? %ld)", (long)INTVAL(x));
2120 102 dgisselq
+               zip_debug_print(pfx, lvl, buf);
2121
+               } break;
2122
+       case LABEL_REF:
2123 122 dgisselq
+               { char buf[256];
2124 111 dgisselq
+               sprintf(buf, "(LABEL *.L%d)", CODE_LABEL_NUMBER(LABEL_REF_LABEL(x)));
2125
+               zip_debug_print(pfx, lvl, buf);
2126
+               }
2127 102 dgisselq
+               break;
2128
+       case SYMBOL_REF:
2129
+               {
2130 192 dgisselq
+                       char buf[128];
2131 102 dgisselq
+                       sprintf(buf, "(SYMBOL: %s)", XSTR(x,0));
2132
+                       // fprintf(file, "%s", XSTR(x,0));
2133
+                       zip_debug_print(pfx, lvl, buf);
2134
+               }
2135
+               break;
2136
+       case MEM:
2137
+               zip_debug_print_m(pfx, lvl, "(MEM", GET_MODE(x));
2138
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2139
+               zip_debug_print(pfx, lvl, ")");
2140
+               break;
2141
+       /*
2142
+       case VALUE:
2143
+               {
2144
+                       char buf[64];
2145
+                       sprintf(buf, "(VALUE: %d)", INTVAL(XEXP,0));
2146
+                       zip_debug_print_m(pfx, lvl, "buf", GET_MODE(x));
2147
+               }
2148
+               break;
2149
+       */
2150
+       case PLUS:
2151
+               zip_debug_print_m(pfx, lvl, "(PLUS", GET_MODE(x));
2152
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2153
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2154
+               zip_debug_print(pfx, lvl, ")");
2155
+               break;
2156
+       case MINUS:
2157
+               zip_debug_print_m(pfx, lvl, "(MINUS", GET_MODE(x));
2158
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2159
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2160
+               zip_debug_print(pfx, lvl, ")");
2161
+               break;
2162
+       case AND:
2163
+               zip_debug_print_m(pfx, lvl, "(AND", GET_MODE(x));
2164
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2165
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2166
+               zip_debug_print(pfx, lvl, ")");
2167
+               break;
2168
+       case IOR:
2169
+               zip_debug_print_m(pfx, lvl, "(OR", GET_MODE(x));
2170
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2171
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2172
+               zip_debug_print(pfx, lvl, ")");
2173
+               break;
2174
+       case XOR:
2175
+               zip_debug_print_m(pfx, lvl, "(XOR", GET_MODE(x));
2176
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2177
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2178
+               zip_debug_print(pfx, lvl, ")");
2179
+               break;
2180
+       case MULT:
2181
+               zip_debug_print_m(pfx, lvl, "(MULT", GET_MODE(x));
2182
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2183
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2184
+               zip_debug_print(pfx, lvl, ")");
2185
+               break;
2186
+       case EQ:        //
2187
+               zip_debug_print_m(pfx, lvl, "(EQ", GET_MODE(x));
2188
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2189
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2190
+               zip_debug_print(pfx, lvl, ")");
2191
+               break;
2192
+       case NE:        //
2193
+               zip_debug_print_m(pfx, lvl, "(NE", GET_MODE(x));
2194
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2195
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2196
+               zip_debug_print(pfx, lvl, ")");
2197
+               break;
2198
+       case GE:        //
2199
+               zip_debug_print_m(pfx, lvl, "(GE", GET_MODE(x));
2200
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2201
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2202
+               zip_debug_print(pfx, lvl, ")");
2203
+               break;
2204
+       case GT:        //
2205
+               zip_debug_print_m(pfx, lvl, "(GT", GET_MODE(x));
2206
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2207
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2208
+               zip_debug_print(pfx, lvl, ")");
2209
+               break;
2210
+       case LE:        //
2211
+               zip_debug_print_m(pfx, lvl, "(LE", GET_MODE(x));
2212
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2213
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2214
+               zip_debug_print(pfx, lvl, ")");
2215
+               break;
2216
+       case LT:        //
2217
+               zip_debug_print_m(pfx, lvl, "(LT", GET_MODE(x));
2218
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2219
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2220
+               zip_debug_print(pfx, lvl, ")");
2221
+               break;
2222
+       case GEU:       //
2223
+               zip_debug_print_m(pfx, lvl, "(GEU", GET_MODE(x));
2224
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2225
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2226
+               zip_debug_print(pfx, lvl, ")");
2227
+               break;
2228
+       case GTU:       //
2229
+               zip_debug_print_m(pfx, lvl, "(GTU", GET_MODE(x));
2230
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2231
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2232
+               zip_debug_print(pfx, lvl, ")");
2233
+               break;
2234
+       case LEU:       //
2235
+               zip_debug_print_m(pfx, lvl, "(LEU", GET_MODE(x));
2236
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2237
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2238
+               zip_debug_print(pfx, lvl, ")");
2239
+               break;
2240
+       case LTU:       //
2241
+               zip_debug_print_m(pfx, lvl, "(LTU", GET_MODE(x));
2242
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2243
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2244
+               zip_debug_print(pfx, lvl, ")");
2245
+               break;
2246
+       case SCRATCH:   //
2247
+               zip_debug_print_m(pfx, lvl, "(SCRATCH)", GET_MODE(x));
2248
+               break;
2249
+       case SUBREG:
2250
+               { char buf[25];
2251 111 dgisselq
+               if (REG_P(XEXP(x,0))) {
2252
+                       sprintf(buf, "(SUBREG %d/%d)", REGNO(XEXP(x,0)),
2253
+                               SUBREG_BYTE(x));
2254
+                       zip_debug_print(pfx, lvl, buf);
2255
+               } else if (MEM_P(XEXP(x,0))) {
2256
+                       sprintf(buf, "(SUBREG /%d", SUBREG_BYTE(x));
2257
+                       zip_debug_print(pfx, lvl, buf);
2258
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2259
+                       zip_debug_print(pfx, lvl, ")");
2260
+               } else {
2261
+                       sprintf(buf, "(SUBREG UNK /%d", SUBREG_BYTE(x));
2262
+                       zip_debug_print(pfx, lvl, buf);
2263
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2264
+                       zip_debug_print(pfx, lvl, ")");
2265
+               }}
2266
+               break;
2267 127 dgisselq
+       case ASHIFT:
2268
+               zip_debug_print_m(pfx, lvl, "(ASHIFT", GET_MODE(x));
2269
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2270
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2271
+               zip_debug_print(pfx, lvl, ")");
2272
+               break;
2273
+       case ASHIFTRT:
2274
+               zip_debug_print_m(pfx, lvl, "(ASHIFTRT", GET_MODE(x));
2275
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2276
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2277
+               zip_debug_print(pfx, lvl, ")");
2278
+               break;
2279
+       case LSHIFTRT:
2280
+               zip_debug_print_m(pfx, lvl, "(LSHIFTRT", GET_MODE(x));
2281
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2282
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2283
+               zip_debug_print(pfx, lvl, ")");
2284
+               break;
2285 102 dgisselq
+       default:
2286 111 dgisselq
+               { char buf[128];
2287 102 dgisselq
+               sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
2288
+               zip_debug_print(pfx, lvl, buf);
2289
+               debug_rtx(x);
2290
+               } break;
2291
+       }
2292
+}
2293
+
2294
+void
2295
+zip_debug_rtx_pfx(const char *pfx, const_rtx x) {
2296
+       zip_debug_rtx_1(pfx, x, 0);
2297
+}
2298
+
2299
+void
2300
+zip_debug_rtx(const_rtx x) {
2301
+       zip_debug_rtx_pfx("", x);
2302
+}
2303
+
2304
+void
2305 142 dgisselq
+zip_debug_ccode(int ccode) {
2306
+       switch(ccode) {
2307
+       case    EQ: fprintf(stderr, "EQ"); break;
2308
+       case    NE: fprintf(stderr, "NE"); break;
2309
+       case    GT: fprintf(stderr, "GT"); break;
2310
+       case    GE: fprintf(stderr, "GE"); break;
2311
+       case    LT: fprintf(stderr, "LT"); break;
2312
+       case    LE: fprintf(stderr, "LE"); break;
2313
+       case    GTU: fprintf(stderr, "GTU"); break;
2314
+       case    GEU: fprintf(stderr, "GEU"); break;
2315
+       case    LTU: fprintf(stderr, "LTU"); break;
2316
+       case    LEU: fprintf(stderr, "LEU"); break;
2317
+       default:
2318
+               fprintf(stderr, "%d", ccode); break;
2319
+       }
2320
+}
2321
+
2322
+void
2323 102 dgisselq
+zip_debug_insn(rtx_insn *insn ATTRIBUTE_UNUSED) {
2324
+}
2325
+
2326
+void
2327
+zip_debug_bb(basic_block bb) {
2328
+       rtx_insn        *insn;
2329
+
2330
+       fprintf(stderr, "************ BASIC-BLOCK ***************\n");
2331
+       FOR_BB_INSNS(bb, insn)
2332
+       {
2333
+               zip_debug_rtx(insn);
2334
+       }
2335
+}
2336
+
2337
+
2338
+static bool
2339 122 dgisselq
+zip_legitimate_opb(rtx x, bool strict)
2340 102 dgisselq
+{
2341 103 dgisselq
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2342 102 dgisselq
+
2343 111 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
2344 102 dgisselq
+       if (dbg) zip_debug_rtx_pfx("Test: ", x);
2345
+
2346
+       if (NULL_RTX == x)
2347
+               return false;
2348 122 dgisselq
+       else if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
2349
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> Mode failure\n");
2350 102 dgisselq
+               return false;
2351 122 dgisselq
+       } else if ((strict)&&(REG_P(x))) {
2352
+               if (REGNO(x)<zip_CC) {
2353
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
2354
+                       return true;
2355
+               } else return false;
2356
+       } else if (register_operand(x, GET_MODE(x))) {
2357
+               // This also handles subregs
2358
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
2359
+               return true;
2360 111 dgisselq
+       } else if ((CONST_INT_P(x))
2361
+               &&(INTVAL(x) >= zip_min_opb_imm)
2362
+               &&(INTVAL(x) <= zip_max_opb_imm)) {
2363 136 dgisselq
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (Const) %ld <= %ld <= %ld\n", (long)zip_min_opb_imm, (long)INTVAL(x), (long)zip_max_opb_imm);
2364 111 dgisselq
+               return true;
2365 122 dgisselq
+       // } else if ((GET_CODE(x) == LABEL_REF)||(GET_CODE(x)==CODE_LABEL)) {
2366
+               // return true;
2367 102 dgisselq
+       } else if (GET_CODE(x) == PLUS) {
2368
+               // Is it a valid register?
2369 122 dgisselq
+               if ((!strict)&&(!register_operand((rtx)XEXP((rtx)x,0), GET_MODE(x)))) {
2370 111 dgisselq
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
2371 102 dgisselq
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
2372
+                       return false;
2373 122 dgisselq
+               } else if ((strict)&&((!REG_P(XEXP(x,0)))||(REGNO(XEXP(x,0))>=zip_CC))) {
2374 102 dgisselq
+                       return false;
2375
+               } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
2376
+                       &&(INTVAL(XEXP(x, 1)) <= zip_max_anchor_offset)
2377
+                       &&(INTVAL(XEXP(x, 1)) >= zip_min_anchor_offset)) {
2378 111 dgisselq
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (reg+int)\n");
2379 103 dgisselq
+                       // if((INTVAL(XEXP(x,1))<0)&&(REGNO(XEXP(x,0))==zip_SP))
2380
+                               // gcc_unreachable();
2381 102 dgisselq
+                       return true;
2382
+               } if ((GET_CODE(XEXP(x, 1)) == LABEL_REF)
2383 122 dgisselq
+                       ||(GET_CODE(XEXP(x, 1)) == CODE_LABEL)
2384 102 dgisselq
+                       ||(GET_CODE(XEXP(x, 1)) == SYMBOL_REF)) {
2385
+                       // While we can technically support this, the problem
2386
+                       // is that the symbol address could be anywhere, and we
2387
+                       // have no way of recovering if it's outside of our
2388
+                       // 14 allowable bits.
2389 111 dgisselq
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No. (reg+lbl)\n");
2390 102 dgisselq
+                       return false;
2391
+               }
2392
+       }
2393
+
2394 111 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No\n");
2395 102 dgisselq
+       if (dbg) zip_debug_rtx(x);
2396
+       return false;
2397
+}
2398
+
2399
+static bool
2400
+zip_legitimate_move_operand_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict) {
2401
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2402
+
2403
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n");
2404
+       if (dbg) zip_debug_rtx_pfx("VMov?: ", x);
2405
+
2406 122 dgisselq
+       if (!zip_legitimate_opb(x, strict))
2407 102 dgisselq
+               return false;
2408 122 dgisselq
+       else if ((GET_CODE(x)==PLUS)&&(CONST_INT_P(XEXP(x,1)))) {
2409
+               if ((INTVAL(XEXP(x, 1)) > zip_max_mov_offset)
2410
+                       ||(INTVAL(XEXP(x, 1)) < zip_min_mov_offset)) {
2411 135 dgisselq
+                       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> NO! (reg+int), int out of bounds: %ld\n", (long)INTVAL(XEXP(x,1)));
2412 102 dgisselq
+                       return false;
2413
+               }
2414
+       }
2415
+
2416 122 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> Yes\n");
2417 102 dgisselq
+       if (dbg) zip_debug_rtx(x);
2418 122 dgisselq
+       return true;
2419 102 dgisselq
+}
2420
+
2421
+int
2422
+zip_pd_mov_operand(rtx op)
2423
+{
2424
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2425
+
2426
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOV(predicate) for OPERAND\n");
2427
+       return zip_legitimate_move_operand_p(VOIDmode, op, !can_create_pseudo_p());
2428
+}
2429
+
2430
+int
2431 111 dgisselq
+zip_pd_mvimm_operand(rtx op)
2432
+{
2433
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2434
+
2435
+       if (dbg) fprintf(stderr, "ZIP-VALID-MVIMM(predicate) for OPERAND\n");
2436
+       if (!CONST_INT_P(op))
2437
+               return false;
2438
+       if (INTVAL(op) > zip_max_mov_offset)
2439
+               return false;
2440
+       if (INTVAL(op) < zip_min_mov_offset)
2441
+               return false;
2442
+       return true;
2443
+}
2444
+
2445
+int
2446
+zip_pd_imm_operand(rtx op)
2447
+{
2448
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2449
+
2450
+       if (dbg) fprintf(stderr, "ZIP-VALID-IMM(predicate) for OPERAND\n");
2451
+       if (!CONST_INT_P(op))
2452
+               return false;
2453
+       if (INTVAL(op) > zip_max_anchor_offset)
2454
+               return false;
2455
+       if (INTVAL(op) < zip_min_anchor_offset)
2456
+               return false;
2457
+       return true;
2458
+}
2459
+
2460
+int
2461 102 dgisselq
+zip_address_operand(rtx op)
2462
+{
2463
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2464
+
2465
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
2466 111 dgisselq
+       if ((REG_P(op))&&(REGNO(op)==zip_CC))
2467
+               return false;
2468
+       else if ((GET_CODE(op) == PLUS)&&(REG_P(XEXP(op,0)))
2469
+                       &&(REGNO(XEXP(op,0))==zip_CC))
2470
+               return false;
2471
+       else
2472
+               return zip_legitimate_opb(op, !can_create_pseudo_p());
2473 102 dgisselq
+}
2474
+
2475
+int
2476 111 dgisselq
+zip_pd_opb_operand(rtx op)
2477 102 dgisselq
+{
2478
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2479
+
2480 111 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
2481 122 dgisselq
+       return zip_legitimate_opb(op, false); //, !can_create_pseudo_p());
2482 102 dgisselq
+}
2483
+
2484
+int
2485
+zip_ct_address_operand(rtx op)
2486
+{
2487
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2488
+
2489
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
2490 111 dgisselq
+       return zip_legitimate_opb(op, !can_create_pseudo_p());
2491 102 dgisselq
+}
2492
+
2493
+int
2494
+zip_const_address_operand(rtx x) {
2495
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2496
+
2497
+       if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n");
2498
+       if (dbg) zip_debug_rtx(x);
2499 127 dgisselq
+       if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
2500
+               fprintf(stderr, "is ZIP-CONST-ADDRESS? -> NO, BAD MODE\n");
2501 102 dgisselq
+               return false;
2502 127 dgisselq
+       }
2503 102 dgisselq
+       if ((GET_CODE(x) == LABEL_REF)
2504
+                       ||(GET_CODE(x) == CODE_LABEL)
2505
+                       ||(GET_CODE(x) == SYMBOL_REF)) {
2506 127 dgisselq
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (LBL)\n");
2507 102 dgisselq
+               return true;
2508
+       } else if (CONST_INT_P(x)) {
2509 127 dgisselq
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (INT)\n");
2510 102 dgisselq
+               return true;
2511
+       } else if (GET_CODE(x) == PLUS) {
2512
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(PLUS)\n");
2513
+               return ((zip_const_address_operand(XEXP(x,0)))
2514
+                       &&(CONST_INT_P(XEXP(x,1))));
2515
+       } else if (GET_CODE(x) == MINUS) {
2516
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(MINUS)\n");
2517
+               return ((zip_const_address_operand(XEXP(x,0)))
2518
+                       &&(zip_const_address_operand(XEXP(x,1))));
2519
+       }
2520
+
2521
+       if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> No\n");
2522
+       if (dbg) zip_debug_rtx(x);
2523
+       return false;
2524
+}
2525
+
2526
+int
2527
+zip_ct_const_address_operand(rtx x) {
2528
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2529
+
2530
+       if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(constraint)\n");
2531
+       return zip_const_address_operand(x);
2532
+}
2533
+
2534
+int
2535
+zip_pd_const_address_operand(rtx x) {
2536
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2537
+
2538
+       if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(predicate)\n");
2539
+       return zip_const_address_operand(x);
2540
+}
2541
+
2542
+
2543
+static bool
2544
+zip_legitimate_address_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict)
2545
+{
2546
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2547
+
2548
+       if (dbg) fprintf(stderr, "Zip-LEGITIMATE-ADDRESS-P\n");
2549
+       if (dbg) zip_debug_rtx(x);
2550
+
2551
+       // Only insist the register be a valid register if strict is true
2552 111 dgisselq
+       if (zip_legitimate_opb(x, strict))
2553 102 dgisselq
+               return true;
2554 111 dgisselq
+       // else if (zip_const_address_operand(x))
2555
+               // return true;
2556 102 dgisselq
+
2557
+       return false;
2558
+}
2559
+
2560 111 dgisselq
+static rtx
2561
+zip_legitimize_address(rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) {
2562
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2563
+
2564
+       if (dbg) zip_debug_rtx_pfx("LEGITIMIZE: ", x);
2565
+       if (zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
2566
+               return x;
2567
+
2568
+       if (GET_CODE(x)==PLUS) {
2569
+               if (!REG_P(XEXP(x,0)))
2570
+                       XEXP(x,0) = force_reg(GET_MODE(x),XEXP(x,0));
2571
+               if ((!zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
2572
+                       &&(!CONST_INT_P(XEXP(x,1))))
2573
+                       x = force_reg(GET_MODE(x),x);
2574
+       } else if (MEM_P(x))
2575
+               x = force_reg(GET_MODE(x),x);
2576
+
2577
+       if (dbg) zip_debug_rtx_pfx("LEGITIMATE: ", x);
2578
+       return x;
2579
+}
2580
+
2581 102 dgisselq
+void
2582
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
2583
+{
2584
+       assemble_name(stream, name);
2585
+       fprintf(stream, "\t.equ ");
2586
+       assemble_name(stream, value);
2587
+       fputc('\n', stream);
2588
+}
2589
+
2590 111 dgisselq
+#define        USE_SUBREG
2591
+#ifdef USE_SUBREG
2592
+#define        SREG_P(RTX) ((SUBREG_P(RTX))&&(REG_P(XEXP(RTX,0))))
2593
+#define        SMEM_P(RTX) ((SUBREG_P(RTX))&&(MEM_P(XEXP(RTX,0))))
2594
+#else
2595
+#define        SREG_P(RTX)     false
2596
+#define        SMEM_P(RTX)     false
2597
+#endif
2598 102 dgisselq
+
2599
+const char *zip_set_zero_or_one(rtx condition, rtx dst) {
2600 103 dgisselq
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2601 102 dgisselq
+       if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n");
2602
+       if (dbg) zip_debug_rtx_pfx("CND", condition);
2603
+       if (dbg) zip_debug_rtx_pfx("REG", dst);
2604
+       switch(GET_CODE(condition)) {
2605
+       case EQ:        return "LDI\t0,%0\n\tLDILO.Z\t1,%0";
2606
+       case NE:        return "LDI\t0,%0\n\tLDILO.NZ\t1,%0";
2607
+       case LT:        return "LDI\t0,%0\n\tLDILO.LT\t1,%0";
2608
+       case GT:        return "LDI\t0,%0\n\tLDILO.GT\t1,%0";
2609
+       case LE:        return "LDI\t1,%0\n\tLDILO.GT\t0,%0";
2610
+       case GE:        return "LDI\t0,%0\n\tLDILO.GE\t1,%0";
2611
+       case LTU:       return "LDI\t0,%0\n\tLDILO.C\t1,%0";
2612
+       case GTU:       return "LDI\t1,%0\n\tLDILO.C\t0,%0\n\tLDILO.Z\t0,%0";
2613
+       case LEU:       return "LDI\t0,%0\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0";
2614
+       case GEU:       return "LDI\t1,%0\n\tLDILO.C\t0,%0";
2615
+       default:
2616
+               zip_debug_rtx(condition);
2617
+               internal_error("CSTORE Unsupported condition");
2618
+               return NULL;
2619
+       }
2620
+}
2621
+
2622 127 dgisselq
+/*
2623 102 dgisselq
+const char *zip_binary_movsicc(rtx_code condition, const char *op, const int opno) {
2624
+       static char     result[64] = "";
2625
+       switch(condition) {
2626
+               //
2627
+               // Result already exists in the iffalse register
2628
+               // Can't change it.  Therefore, on the
2629
+               // condition ... move true register to the
2630
+               // destination
2631
+               //
2632
+               case EQ:        sprintf(result, "%s.Z\t%%%d,%%0", op, opno); break;
2633
+               case NE:        sprintf(result, "%s.NZ\t%%%d,%%0", op, opno); break;
2634
+               case LT:        sprintf(result, "%s.LT\t%%%d,%%0", op, opno); break;
2635
+               case GT:        sprintf(result, "%s.GT\t%%%d,%%0", op, opno); break;
2636
+               // .LE doesn't exist on Zip CPU--turn this into two instructions
2637
+               case LE:        sprintf(result, "%s.LT\t%%%d,%%0\n\t%s.Z\t%%%d,%%0", op, opno, op, opno); break;
2638
+               case GE:        sprintf(result, "%s.GE\t%%%d,%%0", op, opno); break;
2639
+               case LTU:       sprintf(result, "%s.C\t%%%d,%%0", op, opno); break;
2640
+               //
2641
+               // .GTU doesn't exist on the Zip CPU either. We also note that
2642
+               // .C will never be set on an equal condition.  Therefore, we
2643
+               // turn this into a XOR.NZ 2,CC, which will set the .C condition
2644
+               // as long as .Z wasn't true.  We then undo this when we're
2645
+               // done.  This is possible since none of these instructions
2646
+               // (LDI/MOV/Lod conditional, nor Xor conditional) will ever set
2647
+               // the condition codes.
2648
+               //
2649
+               // This is obviously not very optimal.  Avoid this by all means
2650
+               // if you can
2651
+               case GTU:       sprintf(result, "XOR.NZ\t2,CC\n%s.C\t%%%d,%%0\n\tXOR.NZ\t2,CC", op, opno); break;
2652
+               // .LEU doesn't exist on Zip CPU either--turn this into another
2653
+               // two instructions
2654
+               case LEU:       sprintf(result, "%s.C\t%%%d,%%0\n\t%s.Z\t%%%d,%%0", op, opno, op, opno); break;
2655
+               //
2656
+               // .GEU doesn't exist on Zip CPU.  Implementing it her is
2657
+               // painful.  We can change the condition codes to make it so,
2658
+               // but the instruction requires the condition codes not be
2659
+               // changed.  Hence, we must change them back if we do so.
2660
+               //
2661
+               // .C will be set on less than but not equal.  Hence !.C will
2662
+               // be true on greater than or equal.
2663
+               case GEU:       sprintf(result, "XOR\t2,CC\n%s.C\t%%%d,%%0\n\tXOR\t2,CC", op, opno); break;
2664
+               default:
2665
+                       internal_error("MOVSICC(BINARY) Unsupported condition");
2666
+                       return NULL;
2667
+       } return result;
2668
+}
2669 127 dgisselq
+*/
2670 102 dgisselq
+
2671 200 dgisselq
+int
2672 127 dgisselq
+zip_supported_condition(int c) {
2673
+       switch(c) {
2674
+       case NE: case LT: case EQ: case GT: case GE: case LTU:
2675 200 dgisselq
+               return 1;
2676 127 dgisselq
+               break;
2677
+       default:
2678
+               break;
2679 200 dgisselq
+       } return 0;
2680 102 dgisselq
+}
2681
+
2682 127 dgisselq
+bool
2683
+zip_signed_comparison(int c) {
2684
+       switch(c) {
2685
+       case NE: case LT: case EQ: case GT: case GE:
2686
+               return true;
2687
+       default:
2688
+               break;
2689
+       } return false;
2690
+}
2691
+
2692 200 dgisselq
+int
2693 127 dgisselq
+zip_expand_movsicc(rtx dst, rtx condition, rtx iftrue, rtx iffalse) {
2694 142 dgisselq
+       rtx_insn *insn;
2695 103 dgisselq
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2696 102 dgisselq
+       if (dbg) fprintf(stderr, "ZIP::MOVSICC\n");
2697
+       if (dbg) zip_debug_rtx_pfx("DST", dst);
2698
+       if (dbg) zip_debug_rtx_pfx("CND", condition);
2699
+       if (dbg) zip_debug_rtx_pfx("TRU", iftrue);
2700
+       if (dbg) zip_debug_rtx_pfx("FAL", iffalse);
2701 127 dgisselq
+
2702
+       // Start with the condition
2703
+       rtx     cmpa = XEXP(condition,0), cmpb=XEXP(condition,1);
2704
+       enum rtx_code   cmpcode = GET_CODE(condition);
2705
+
2706 142 dgisselq
+       // Want to always do the false expression, and only sometimes the
2707
+       // true expression.  If, however, the false is a constant and the
2708
+       // true and destination are the same thing, this doesn't work.
2709
+       if (rtx_equal_p(dst, iftrue)) {
2710
+               // If the true value is the same as the destination already,
2711
+               // then swap so we only do the condition on true
2712
+               rtx tem = iffalse;
2713
+               iffalse = iftrue;
2714
+               iftrue  = tem;
2715
+               cmpcode = reverse_condition(cmpcode);
2716
+       }
2717
+
2718 127 dgisselq
+       //; Do we need to swap or adjust the condition?
2719
+       if (zip_supported_condition((int)cmpcode)) {
2720
+               // Keep everything as is
2721 142 dgisselq
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- Condition is supported\n");
2722 127 dgisselq
+       } else if ((zip_supported_condition(reverse_condition(cmpcode)))
2723 142 dgisselq
+                       &&(!MEM_P(iffalse))
2724
+                       &&(!rtx_equal_p(dst,iffalse))) {
2725 127 dgisselq
+               rtx tem = iffalse;
2726
+               iffalse = iftrue;
2727
+               iftrue = tem;
2728
+
2729
+               cmpcode = reverse_condition(cmpcode);
2730
+       } else if ((zip_supported_condition((int)swap_condition(cmpcode)))
2731
+               &&((REG_P(cmpb))||(can_create_pseudo_p()))) {
2732
+               rtx tem = cmpa;
2733
+               cmpa = cmpb;
2734
+               cmpa = tem;
2735
+               cmpcode = swap_condition(cmpcode);
2736
+
2737
+               if ((GET_CODE(cmpa)==PLUS)&&(zip_signed_comparison((int)cmpcode))
2738
+                       &&(REG_P(XEXP(cmpa,0)))
2739
+                       &&(CONST_INT_P(XEXP(cmpa,1)))
2740
+                       &&(abs(INTVAL(XEXP(cmpa,1)))<(1<<17))) {
2741
+
2742
+                       // If we were doing CMP x(Rb),Ra
2743
+                       // and we just changed it to CMP Ra,x(Rb)
2744
+                       // adjust it to CMP -x(Ra),Rb
2745
+                       cmpb = plus_constant(SImode, cmpb, -INTVAL(XEXP(cmpa,1)));
2746
+                       cmpa = XEXP(cmpa,0);
2747
+               } else if (!REG_P(cmpa)) {
2748
+                       // Otherwise, if we had anything else in Rb other than
2749
+                       // a register ... such as a constant, then load it into
2750
+                       // a register before comparing it.  So
2751
+                       //      CMP x,Ra
2752
+                       // became
2753
+                       //      CMP Ra,x
2754
+                       // now becomes
2755
+                       //      LDI x,Rt
2756
+                       //      CMP Ra,Rt
2757
+                       // (We already tested for can_create_pseudo_p() above..)
2758
+                       tem = gen_reg_rtx(SImode);
2759
+                       emit_move_insn(tem, cmpa);
2760
+                       cmpa = tem;
2761 102 dgisselq
+               }
2762 127 dgisselq
+       } else {
2763
+               // Here's our last chance.
2764
+               // This will adjust for less than equal types of stuff
2765
+               int     cod = (int)cmpcode;
2766
+               zip_canonicalize_comparison(&cod, &cmpa, &cmpb, false);
2767
+               cmpcode = (enum rtx_code)cod;
2768 102 dgisselq
+       }
2769
+
2770 142 dgisselq
+       if (dbg) fprintf(stderr, "ZIP::MOVSICC -- Post-Modes\n");
2771
+       if (dbg) zip_debug_rtx_pfx("DST-P: ", dst);
2772
+       if (dbg) zip_debug_rtx_pfx("CND-P: ", condition);
2773
+       if (dbg) zip_debug_rtx_pfx("TRU-P: ", iftrue);
2774
+       if (dbg) zip_debug_rtx_pfx("FAL-P: ", iffalse);
2775
+
2776
+       if (!zip_supported_condition((int)cmpcode)) {
2777
+               if (dbg) {
2778
+               fprintf(stderr, "ZIP::MOVSICC -- Unsupported condition: ");
2779
+                       zip_debug_ccode(cmpcode);
2780
+                       fprintf(stderr, "\n");
2781
+               }
2782 200 dgisselq
+               return 0;
2783 142 dgisselq
+       }
2784 127 dgisselq
+       gcc_assert(zip_supported_condition((int)cmpcode));
2785
+
2786
+       //; Always do the default move
2787 142 dgisselq
+       bool    conditionally_do_false = false;
2788
+       conditionally_do_false = (MEM_P(iffalse))
2789
+               &&(!rtx_equal_p(dst,iffalse))
2790
+               &&(zip_supported_condition(reverse_condition(cmpcode)));
2791
+       conditionally_do_false = conditionally_do_false || (rtx_equal_p(dst,iftrue));
2792
+       if ((conditionally_do_false)&&(!zip_supported_condition(reverse_condition(cmpcode)))) {
2793
+               if (dbg) {
2794
+                       fprintf(stderr, "ZIP::MOVSICC -- Cant support the reverse condition: ");
2795
+                       zip_debug_ccode(cmpcode);
2796
+                       fprintf(stderr, "\n");
2797
+               }
2798 200 dgisselq
+               return 0;
2799 142 dgisselq
+       }
2800 127 dgisselq
+
2801 142 dgisselq
+       if ((!rtx_equal_p(dst, iffalse))&&(!conditionally_do_false)) {
2802
+               if (dbg)
2803
+               fprintf(stderr, "ZIP::MOVSICC -- EMITTING MOVE FALSE->DST\n");
2804
+               insn = emit_move_insn(dst, iffalse);
2805
+               if (dbg) zip_debug_rtx_pfx("BARE-U: ", insn);
2806
+       }
2807
+
2808 127 dgisselq
+       rtx     cc_rtx = gen_rtx_REG(CCmode, zip_CC);
2809
+
2810
+       //; Now let's get our comparison right
2811 142 dgisselq
+       if (dbg) fprintf(stderr, "ZIP::MOVSICC -- EMITTING COMPARISON\n");
2812
+       insn = emit_insn(gen_rtx_SET(VOIDmode, cc_rtx,
2813 127 dgisselq
+               gen_rtx_COMPARE(CCmode, cmpa, cmpb)));
2814 142 dgisselq
+       if (dbg) zip_debug_rtx_pfx("BARE-C: ", insn);
2815 127 dgisselq
+
2816
+       //; Finally, let's load the value on true
2817 142 dgisselq
+       if (!rtx_equal_p(dst, iftrue)) {
2818
+               if (dbg) fprintf(stderr, "ZIP::MOVSICC -- EMITTING BARE\n");
2819
+               insn=emit_insn(gen_movsicc_bare(dst,
2820 127 dgisselq
+                       gen_rtx_fmt_ee(cmpcode, SImode, NULL_RTX, NULL_RTX),
2821
+                       iftrue, dst));
2822 142 dgisselq
+               if (dbg) zip_debug_rtx_pfx("BARE-T: ", insn);
2823
+       }
2824
+
2825
+       if (conditionally_do_false) {
2826
+               gcc_assert(zip_supported_condition(reverse_condition(cmpcode)));
2827
+               insn=emit_insn(gen_movsicc_bare(dst,
2828
+                       gen_rtx_fmt_ee(reverse_condition(cmpcode), SImode,
2829
+                       NULL_RTX, NULL_RTX), iffalse, dst));
2830
+               if (dbg) zip_debug_rtx_pfx("BARE-F: ", insn);
2831
+       }
2832
+
2833
+       // Return true on success
2834 200 dgisselq
+       return 1;
2835 102 dgisselq
+}
2836
+
2837
+const char *zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv ATTRIBUTE_UNUSED) {
2838
+       // We know upon entry that REG_P(dst) must be true
2839
+       if (!REG_P(dst))
2840
+               internal_error("%s","ADDSICC into something other than register");
2841
+       if ((REG_P(ifsrc))&&(REGNO(dst)==REGNO(ifsrc))) {
2842
+               switch (GET_CODE(condition)) {
2843
+               case EQ: return "ADD.Z\t%3,%0";
2844
+               case NE: return "ADD.NZ\t%3,%0";
2845
+               case LT: return "ADD.LT\t%3,%0";
2846
+               case GT: return "ADD.GT\t%3,%0";
2847
+               case LE: return "ADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
2848
+               case GE: return "ADD.GE\t%3,%0";
2849
+               case LTU: return "ADD.C\t%3,%0";
2850
+               case LEU: return "ADD.C\t%3,%0\n\tADD.Z\t%3,%0";
2851
+               case GEU: return "XOR\t2,CC\n\tADD.C\t%3,%0\n\tXOR\t2,CC";
2852
+               // Can do a GEU comparison, and then undo on the Zero condition
2853
+               case GTU: return "XOR\t2,CC\n\tADD.C\t%3,%0\n\tSUB.Z\t%3,%0\n\tXOR\t2,CC";
2854
+               default:
2855
+                       internal_error("%s", "Zip/No usable addsi expansion");
2856
+                       break;
2857
+               }
2858
+       } else {
2859
+               // MOV A+REG,REG
2860
+               switch (GET_CODE(condition)) {
2861
+               case EQ: return "MOV.Z\t%3+%2,%0";
2862
+               case NE: return "MOV.NZ\t%3+%2,%0";
2863
+               case LT: return "MOV.LT\t%3+%2,%0";
2864
+               case GT: return "MOV.GT\t%3+%2,%0";
2865
+               case LE: return "MOV.LT\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
2866
+               case GE: return "MOV.GE\t%3+%2,%0";
2867
+               case LTU: return "MOV.C\t%3+%2,%0";
2868
+               case LEU: return "MOV.C\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
2869
+               case GEU: return "XOR\t2,CC\n\tMOV.C\t%3+%2,%0\n\tXOR\t2,CC";
2870
+               // Can do a GEU comparison, and then undo on the Zero condition
2871
+               // EXCEPT: with a move instruction, what's there to undo?  We
2872
+               // just clobbered our register!
2873
+               // case GTU: return "XOR\t2,CC\n\tMOV.C\t%3,%0\n\tSUB.Z\t%3,%0XOR\t2,CC";
2874
+               default:
2875
+                       internal_error("%s", "Zip/No usable addsi(reg,reg) expansion");
2876
+                       break;
2877
+               }
2878
+       }
2879
+
2880
+       return "BREAK";
2881
+}
2882
+
2883 103 dgisselq
+static int     zip_memory_move_cost(machine_mode mode, reg_class_t ATTRIBUTE_UNUSED, bool in ATTRIBUTE_UNUSED) {
2884 102 dgisselq
+       int     rv = 14;
2885
+       if ((mode == DImode)||(mode == DFmode))
2886
+               rv += 2;
2887
+       return rv;
2888
+}
2889
+
2890 103 dgisselq
+// #warning "How do we tell the compiler LDI label is expensive as 2 ops"?
2891 117 dgisselq
+static bool    zip_cannot_modify_jumps_p(void) {
2892
+       // Let's try their suggested approach, keeping us from modifying jumps
2893
+       // after reload.  This should also allow our peephole2 optimizations
2894
+       // to adjust things back to what they need to be if necessary.
2895
+       return (reload_completed || reload_in_progress);
2896
+}
2897 122 dgisselq
+
2898
+rtx_insn       *zip_ifcvt_info;
2899
+
2900
+void
2901
+zip_ifcvt_modify_tests(ce_if_block *ce_info ATTRIBUTE_UNUSED, rtx *true_expr, rtx *false_expr) {
2902
+       const bool      dbg = ((ALL_DEBUG_ON)||(false))&&(!ALL_DEBUG_OFF);
2903
+       if (dbg) fprintf(stderr, "IFCVT-MODIFY-TESTS\n");
2904
+       if (*true_expr) switch(GET_CODE(*true_expr)) {
2905
+               case LE:
2906
+               case GTU:
2907
+               case GEU:
2908
+               case LEU:
2909
+                       if (dbg) fprintf(stderr, "TRUE, missing expr\n");
2910
+                       if (dbg) zip_debug_rtx(*true_expr);
2911
+                       *true_expr = NULL_RTX;
2912
+                       break;
2913
+               default: // LT, GT, GTE, LTU, NE, EQ
2914
+                       break;
2915
+       }
2916
+
2917
+       if (*false_expr) switch(GET_CODE(*false_expr)) {
2918
+               case LE:
2919
+               case GTU:
2920
+               case GEU:
2921
+               case LEU:
2922
+                       if (dbg) fprintf(stderr, "FALSE, missing expr\n");
2923
+                       if (dbg) zip_debug_rtx(*false_expr);
2924
+                       *false_expr = NULL_RTX;
2925
+               default:
2926
+                       break;
2927
+       }
2928
+       if ((dbg)&&((!*true_expr)||(!*false_expr)))
2929
+               fprintf(stderr, "IFCVT-MODIFY-TESTS -- FAIL\n");
2930
+}
2931
+
2932
+void
2933 142 dgisselq
+zip_ifcvt_machdep_init(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
2934 122 dgisselq
+/*
2935 142 dgisselq
+if (!ceinfo->then_bb)
2936
+       return;
2937
+rtx_insn *insn;
2938
+FOR_BB_INSNS(ceinfo->then_bb, insn) {
2939
+       fprintf(stderr, "IFCVT -- INIT\n");
2940
+       zip_debug_rtx_pfx("INIT-BB", insn);
2941 122 dgisselq
+}
2942
+*/
2943
+/*
2944
+       zip_ifcvt_info = NULL;
2945
+       rtx_insn *insn, *ifinsn = NULL;
2946
+       FOR_BB_INSNS(ceinfo->test_bb, insn) {
2947
+               rtx     p;
2948
+               p = single_set(insn);
2949
+               if (!p) continue;
2950
+               if (SET_DEST(p)==pc_rtx) {
2951
+                       ifinsn = insn;
2952
+               }
2953
+               if (!REG_P(SET_DEST(p)))
2954
+                       continue;
2955
+               if (GET_MODE(SET_DEST(p))!=CCmode)
2956
+                       continue;
2957
+               if (REGNO(SET_DEST(p))!=zip_CC)
2958
+                       continue;
2959
+               zip_ifcvt_info = insn;
2960
+       }
2961
+
2962
+       if (zip_ifcvt_info)
2963
+               zip_debug_rtx_pfx("PUTATIVE-CMP",zip_ifcvt_info);
2964
+       if (ifinsn)
2965
+               zip_debug_rtx_pfx("PRIOR-JMP",ifinsn);
2966
+*/
2967
+}
2968
+
2969 142 dgisselq
+void
2970
+zip_ifcvt_modify_insn(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED,
2971
+               rtx pattern ATTRIBUTE_UNUSED,
2972
+               rtx_insn *insn ATTRIBUTE_UNUSED) {
2973
+       // zip_debug_rtx_pfx("MODIFY-INSN: ", insn);
2974
+}
2975
+
2976
+void
2977
+zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
2978
+/*
2979
+       fprintf(stderr, "IFCVT -- CANCEL\n");
2980
+       zip_ifcvt_info = NULL;
2981
+*/
2982
+}
2983
+
2984
+void
2985
+zip_ifcvt_modify_final(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
2986
+/*
2987
+rtx_insn *insn;
2988
+FOR_BB_INSNS(ceinfo->test_bb, insn) {
2989
+       fprintf(stderr, "IFCVT -- FINAL\n");
2990
+       zip_debug_rtx_pfx("FINAL-TEST-BB", insn);
2991
+}
2992
+       zip_ifcvt_info = NULL;
2993
+*/
2994
+}
2995
+
2996
+
2997 127 dgisselq
+int    zip_insn_sets_cc(rtx_insn *insn) {
2998
+       return (get_attr_ccresult(insn)==CCRESULT_SET);
2999
+}
3000
+
3001
+int    zip_is_conditional(rtx_insn *insn) {
3002
+       return (get_attr_conditional(insn)==CONDITIONAL_YES);
3003
+}
3004 200 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-float.md gcc-5.3.0-zip/gcc/config/zip/zip-float.md
3005
--- gcc-5.3.0-original/gcc/config/zip/zip-float.md      1969-12-31 19:00:00.000000000 -0500
3006
+++ gcc-5.3.0-zip/gcc/config/zip/zip-float.md   2016-11-10 10:17:53.248750791 -0500
3007
@@ -0,0 +1,138 @@
3008
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3009
+;;
3010
+;; Filename:   zip-float.md
3011
+;;
3012
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
3013
+;;
3014
+;; Purpose:    This is the machine description of the ZipCPU floating point
3015
+;;             unit (if installed).
3016
+;;
3017
+;;
3018
+;; Creator:    Dan Gisselquist, Ph.D.
3019
+;;             Gisselquist Technology, LLC
3020
+;;
3021
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3022
+;;
3023
+;; Copyright (C) 2015, Gisselquist Technology, LLC
3024
+;;
3025
+;; This program is free software (firmware): you can redistribute it and/or
3026
+;; modify it under the terms of  the GNU General Public License as published
3027
+;; by the Free Software Foundation, either version 3 of the License, or (at
3028
+;; your option) any later version.
3029
+;;
3030
+;; This program is distributed in the hope that it will be useful, but WITHOUT
3031
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
3032
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
3033
+;; for more details.
3034
+;;
3035
+;; License:    GPL, v3, as defined and found on www.gnu.org,
3036
+;;             http://www.gnu.org/licenses/gpl.html
3037
+;;
3038
+;;
3039
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3040
+;;
3041
+;;
3042
+;
3043
+;
3044
+;
3045
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3046
+;;
3047
+;; Floating point Op-codes
3048
+;;
3049
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3050
+;
3051
+;
3052
+;
3053
+(define_insn "addsf3"
3054
+       [(set (match_operand:SF 0 "register_operand" "=r")
3055
+               (plus:SF (match_operand:SF 1 "register_operand" "0")
3056
+                       (match_operand:SF 2 "register_operand" "r")))
3057
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
3058
+       "(ZIP_FPU)"
3059
+       "FPADD  %2,%0"
3060
+       [(set_attr "ccresult" "unknown")])
3061
+(define_insn "subsf3"
3062
+       [(set (match_operand:SF 0 "register_operand" "=r")
3063
+               (minus:SF (match_operand:SF 1 "register_operand" "0")
3064
+                       (match_operand:SF 2 "register_operand" "r")))
3065
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
3066
+       "(ZIP_FPU)"
3067
+       "FPSUB  %2,%0"
3068
+       [(set_attr "ccresult" "unknown")])
3069
+(define_insn "mulsf3"
3070
+       [(set (match_operand:SF 0 "register_operand" "=r")
3071
+               (mult:SF (match_operand:SF 1 "register_operand" "0")
3072
+                       (match_operand:SF 2 "register_operand" "r")))
3073
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
3074
+       "(ZIP_FPU)"
3075
+       "FPMUL  %2,%0"
3076
+       [(set_attr "ccresult" "unknown")])
3077
+(define_insn "divsf3"
3078
+       [(set (match_operand:SF 0 "register_operand" "=r")
3079
+               (div:SF (match_operand:SF 1 "register_operand" "0")
3080
+                       (match_operand:SF 2 "register_operand" "r")))
3081
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
3082
+       "(ZIP_FPU)"
3083
+       "FPDIV  %2,%0"
3084
+       [(set_attr "ccresult" "unknown")])
3085
+; (define_insn "floatsisf2"
3086
+;      [(set (match_operand:SF 0 "register_operand" "=r"
3087
+;              (float:SI (match_operand:SF 1 "register_operand" "r"))))
3088
+;      (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
3089
+;      "(ZIP_FPU)"
3090
+;      "FPI2F  %1,%0")
3091
+; (define_insn "floatunssisf2" ... ?)
3092
+; (define_insn "fix_truncsfsi2"
3093
+;      [(set (match_operand:SI 0 "register_operand" "=r"
3094
+;              (float:SF (match_operand:SF 1 "register_operand" "r"))))
3095
+;      (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
3096
+;      "(ZIP_FPU)"
3097
+;      "FPI2F  %1,%0")
3098
+; (define_insn "nearbyintsf2" ... ?)
3099
+; (define_insn "truncsfsi2" ... ?)
3100
+(define_expand "negsf2"
3101
+       [(set (match_operand:SF 0 "register_operand" "=r")
3102
+               (neg:SF (match_operand:SF 1 "register_operand" "0")))
3103
+       ]
3104
+       ""
3105
+       {
3106
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
3107
+               if (can_create_pseudo_p()) {
3108
+                       rtx tmp = gen_reg_rtx(SImode);
3109
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
3110
+                       emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
3111
+                       DONE;
3112
+               } else {
3113
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
3114
+                       emit_insn(gen_iorsi3(operands[0], operands[0],
3115
+                               gen_int_mode(1,SImode)));
3116
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
3117
+                       DONE;
3118
+               }
3119
+       })
3120
+(define_expand "abssf2"
3121
+       [(set (match_operand:SF 0 "register_operand" "=r")
3122
+               (abs:SF (match_operand:SF 1 "register_operand" "0")))
3123
+       ]
3124
+       ""
3125
+       {
3126
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
3127
+               if (can_create_pseudo_p()) {
3128
+                       rtx tmp = gen_reg_rtx(SImode);
3129
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
3130
+                       emit_insn(gen_andsi3(operands[0], operands[0], tmp));
3131
+                       DONE;
3132
+               } else {
3133
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
3134
+                       emit_insn(gen_andsi3(operands[0], operands[0],
3135
+                               gen_int_mode(-2,SImode)));
3136
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
3137
+                       DONE;
3138
+               }
3139
+       })
3140
+;
3141
+;
3142
+; STILL MISSING:
3143
+;
3144
+;
3145
+;
3146 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.h gcc-5.3.0-zip/gcc/config/zip/zip.h
3147
--- gcc-5.3.0-original/gcc/config/zip/zip.h     1969-12-31 19:00:00.000000000 -0500
3148 200 dgisselq
+++ gcc-5.3.0-zip/gcc/config/zip/zip.h  2016-11-19 08:26:58.092386679 -0500
3149
@@ -0,0 +1,4096 @@
3150 102 dgisselq
+////////////////////////////////////////////////////////////////////////////////
3151
+//
3152
+// Filename:   gcc/config/zip/zip.h
3153
+//
3154
+// Project:    Zip CPU backend for the GNU Compiler Collection
3155
+//
3156
+// Purpose:
3157
+//
3158
+// Creator:    Dan Gisselquist, Ph.D.
3159
+//             Gisselquist Technology, LLC
3160
+//
3161
+////////////////////////////////////////////////////////////////////////////////
3162
+//
3163
+// Copyright (C) 2016, Gisselquist Technology, LLC
3164
+//
3165
+// This program is free software (firmware): you can redistribute it and/or
3166
+// modify it under the terms of  the GNU General Public License as published
3167
+// by the Free Software Foundation, either version 3 of the License, or (at
3168
+// your option) any later version.
3169
+//
3170
+// This program is distributed in the hope that it will be useful, but WITHOUT
3171
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
3172
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
3173
+// for more details.
3174
+//
3175
+// You should have received a copy of the GNU General Public License along
3176
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
3177
+// target there if the PDF file isn't present.)  If not, see
3178
+// <http://www.gnu.org/licenses/> for a copy.
3179
+//
3180
+// License:    GPL, v3, as defined and found on www.gnu.org,
3181
+//             http://www.gnu.org/licenses/gpl.html
3182
+//
3183
+//
3184
+////////////////////////////////////////////////////////////////////////////////
3185
+#ifndef        GCC_ZIP_H
3186
+#define        GCC_ZIP_H
3187
+
3188
+
3189
+//
3190
+//
3191 127 dgisselq
+// Zip CPU configuration defines
3192 102 dgisselq
+//
3193
+//
3194
+#define        ZIP_USER        0        // Assume we are in supervisor mode
3195
+#define        ZIP_MULTIPLY    1       // Assume we have multiply instructions
3196
+#define        ZIP_DIVIDE      1       // Assume we have divide instructions
3197
+#define        ZIP_FPU         0        // Assume we have no floating point instructions
3198
+#define        ZIP_PIPELINED   1       // Assume our instructions are pipelined
3199
+#define        ZIP_VLIW        1       // Assume we have the VLIW feature
3200 200 dgisselq
+#define        ZIP_ATOMIC      (ZIP_PIPELINED)
3201 102 dgisselq
+#define        ZIP_PIC         0        // Attempting to produce PIC code, with GOT
3202
+#define        ZIP_HAS_DI      1
3203 127 dgisselq
+// Should we use the peephole optimizations?
3204
+#define        ZIP_PEEPHOLE    1       // 0 means no peephole optimizations.
3205 138 dgisselq
+// How about the new long multiply instruction set?
3206
+#define        ZIP_LONGMPY     1       // 0 means use the old instruction set
3207 200 dgisselq
+#define        ZIP_NEW_CONDITION_CODE  0        // 0 means use the old condition codes
3208 102 dgisselq
+
3209
+// Zip has 16 registers in each user mode.
3210
+//     Register 15 is the program counter (PC)
3211
+//     Register 14 is the condition codes (CC)
3212
+//     Register 13 is the stack pointer   (SP)
3213
+//     Register 12 (may be) the Global Offset Table pointer (GOT)
3214
+//     Register  0 (may be) the return address pointer
3215
+// Registers 16-31 may only be used in supervisor mode.
3216
+#define        is_ZIP_GENERAL_REG(REGNO)       ((REGNO)<13)
3217 171 dgisselq
+#define        is_ZIP_REG(REGNO)               ((REGNO)<33)
3218 102 dgisselq
+
3219 171 dgisselq
+#define        zip_AP_PSEUDO   32
3220 103 dgisselq
+#define        zip_PC          15
3221
+#define        zip_CC          14
3222
+#define        zip_SP          13
3223
+#define        zip_FP          12
3224
+#define        zip_GOT         11
3225 171 dgisselq
+// #define     zip_AP          10      // We're using a PSEUDO REG instead
3226 103 dgisselq
+#define        zip_R1          1
3227
+#define        zip_R0          0
3228 102 dgisselq
+
3229
+#define        ZIP_FIRST_ARG_REGNO     1
3230
+#define        ZIP_LAST_ARG_REGNO      5
3231 111 dgisselq
+#define        NUM_ARG_REGS            (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
3232
+#define        MAX_PARM_REGS           (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
3233 102 dgisselq
+
3234
+/* The overall framework of an assembler file */
3235
+
3236
+#define        ASM_COMMENT_START       ";"
3237
+#define        ASM_APP_ON              ""
3238
+#define        ASM_APP_OFF             ""
3239
+
3240
+#define        FILE_ASM_OP             "\t.file\n"
3241
+
3242
+/* Output and Generation of Labels */
3243
+#define        GLOBAL_ASM_OP           "\t.global\t"
3244
+
3245
+#undef BITS_PER_UNIT
3246
+#define        BITS_PER_UNIT   (32)
3247
+
3248
+/* Assembler Commands for Alignment */
3249
+#define        ASM_OUTPUT_ALIGN(STREAM,POWER)  \
3250 127 dgisselq
+       { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); }
3251 102 dgisselq
+
3252
+
3253
+/* A C compound statement to output to stdio stream STREAM the assembler syntax
3254
+ * for an instruction operand X. */
3255
+#define        PRINT_OPERAND(STREAM, X, CODE)  zip_print_operand(STREAM, X, CODE)
3256
+#define        PRINT_OPERAND_ADDRESS(STREAM, X) zip_print_operand_address(STREAM, X)
3257
+
3258
+/* Passing arguments in registers */
3259
+#define        FUNCTION_VALUE_REGNO_P(REGNO)   ((REGNO)==zip_R1)
3260
+
3261
+/* Define how to find the value returned by a function.  VALTYPE is the data
3262
+ * type of the value (as a tree).  If the precise function being called is known
3263
+ * FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */
3264
+#define        FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG(TYPE_MODE(VALTYPE), zip_R1)
3265
+
3266
+/* Define how to find the value returned by a library function assuming the
3267
+ * value has mode MODE.
3268
+ */
3269
+#define        LIBCALL_VALUE(MODE)     gen_rtx_REG(MODE, zip_R1)
3270
+
3271
+
3272
+/* STACK AND CALLING */
3273
+
3274
+
3275
+/* Define this macro as a C expression that is nonzero for registers that are
3276
+ * used by the epilogue or the return pattern.  The stack and frame pointer
3277
+ * registers are already assumed to be used as needed.
3278
+ */
3279
+#define        EPILOGUE_USES(R)        (R == RETURN_ADDRESS_REGNUM)
3280
+
3281
+
3282
+/* The best alignment to use in cases where we have a choice. */
3283 127 dgisselq
+#define        FASTEST_ALIGNMENT       BITS_PER_WORD
3284 102 dgisselq
+
3285
+/* MAX_FIXED_MODE_SIZE -- An integer expression for the size in bits of the
3286
+ * largest integer machine mode that should actually be used.  All integer
3287
+ * machine modes of this size and smaller can be used for structures and unions
3288
+ * with the appropriate sizes.  If this macro is undefined,
3289
+ * GET_MODE_BITSIZE(DImode) is assumed.
3290
+ *
3291
+ * ZipCPU -- The default looks good enough for us.
3292
+ */
3293
+
3294
+/* Generate Code for Profiling
3295
+ */
3296
+#define        FUNCTION_PROFILER(FILE,LABELNO)         (abort(), 0)
3297
+
3298
+
3299
+/* A C expression which is nonzero if register number NUM is suitable for use
3300
+ * as an index register in operand addresses.
3301
+ */
3302
+#define        REGNO_OK_FOR_INDEX_P(NUM)       0
3303
+
3304
+
3305
+/* A C compound statement with a conditional 'goto LABEL;' executed if X
3306
+ * (an RTX) is a legitimate memory address on the target machine for a memory
3307
+ * operand of mode MODE.
3308
+ */
3309 111 dgisselq
+/* 17.03 Controlling the Compilation Driver, 'gcc' */
3310
+// DRIVER_SELF_SPECS
3311
+// OPTION_DEFAULT_SPECS
3312
+// CPP_SPEC
3313
+// CPLUSPLUS_CPP_SPEC
3314
+// CC1_SPEC
3315
+// CC1PLUS_SPEC
3316
+/* ASM_SPEC ... A C string constant that tells the GCC driver program options
3317
+ * to pass to the assembler.  It can also specify how to translate options you
3318
+ * give to GCC into options for GCC to pass to the assembler.  See the file
3319
+ * 'sun3.h' for an example of this.
3320
+ *
3321
+ * Do not define thismacro if it does not need to do anything.
3322
+ */
3323
+// #undef      ASM_SPEC
3324
+// ASM_FINAL_SPEC
3325
+// ASM_NEEDS_DASH_FOR_PIPED_INPUT
3326
+
3327
+/* LINK_SPEC ... A C string constant that tells the GCC driver program options
3328
+ * to pass to the linker.  It can also specify how to translate options you give
3329
+ * to GCC into options for GCC to pass to the linker.
3330
+ *
3331
+ * Do not define this macro if it does not need to do anything.
3332
+ */
3333
+
3334
+/* LIB_SPEC ... Another C string constant very much like LINK_SPEC.  The
3335
+ * difference between the two is that LIB_SPEC is used at the end of the
3336
+ * command given to the linker.
3337
+ *
3338
+ * If this macro is not defined, a default is provided that loads the standard
3339
+ * C library from the usual place.  See 'gcc.c'.
3340
+ */
3341
+#undef LIB_SPEC
3342
+// #define     LIB_SPEC        "%{!g:-lc} %{g:-lg} -lzip"
3343
+#define        LIB_SPEC        ""
3344
+
3345
+/* LIBGCC_SPEC ... Another C string constant that tells the GCC driver program
3346
+ * hoow and when to place a reference to 'libgcc.a' into the linker command
3347
+ * line.  This constant is placed both before and after the value of LIB_SPEC.
3348
+ *
3349
+ * If this macro is not defined, the GCC driver provides a default that passes
3350
+ * the string '-lgcc' to the linker.
3351
+ */
3352
+#undef LIBGCC_SPEC
3353
+#define        LIBGCC_SPEC     ""
3354
+
3355
+/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the
3356
+ * LIBGCC_SPEC is not directly used by the driver program but is instead
3357
+ * modified to refer to different versions of 'libgcc.a' depending on the
3358
+ * values of the command line flags '-static', '-shared', '-static-libgcc',
3359
+ * and '-shared-libgcc'.  On targets where these modifications are
3360
+ * inappropriate, define REAL_LIBGCC_SPEC instead.  REAL_LIBGCC_SPEC tells the
3361
+ * driver how to place a reference to 'libgcc' on the link command line, but
3362
+ * unlike LIBGCC_SPEC, it is used unmodified.
3363
+ */
3364
+#define        REAL_LIBGCC_SPEC        ""
3365
+
3366
+// USE_LD_AS_NEEDED
3367
+// LINK_EH_SPEC
3368
+
3369
+/* STARTFILE_SPEC ... Another C string constant used much like LINK_SPEC.  The
3370
+ * difference between the two is that STARTFILE_SPEC is used at the very
3371
+ * beginning of the command given to the linker.
3372
+ *
3373
+ * If this macro is not defined, a default is provided that loads the standard
3374
+ * C startup file from the usual place.  See 'gcc.c'
3375
+ */
3376
+#undef STARTFILE_SPEC
3377
+#define        STARTFILE_SPEC  ""
3378
+
3379
+/* ENDFILE_SPEC ... Another C string constant used much like LINK_SPEC.  The
3380
+ * difference between the two is that ENDFILE_SPEC is used at the very end
3381
+ * of the command given to the linker.
3382
+ *
3383
+ * Do not define this macro if it does not do anything.
3384
+ */
3385
+// #undef      ENDFILE_SPEC
3386
+// #define     ENDFILE_SPEC    ""
3387
+
3388
+// THREAD_MODEL_SPEC
3389
+// SYSROOT_SUFFIX_SPEC
3390
+// SYSROOT_HEADERS_SUFFIX_SPEC
3391
+// EXTRA_SPECS
3392
+// LINK_LIBGCC_SPECIAL_1
3393
+// LINK_GCC_C_SEQUENCE_SPEC
3394
+// LINK_COMMAND_SPEC
3395
+// TARGET_ALWAYS_STRIP_DOTDOT
3396
+// MULTILIB_DEFAULTS
3397
+// RELATIVE_PREFIX_NOT_LINKDIR
3398
+// MD_EXEC_PREFIX
3399
+// STANDARD_STARTFILE_PREFIX
3400
+// STANDARD_STARTFILE_PREFIX_1
3401
+// STANDARD_STARTFILE_PREFIX_2
3402
+// MD_STARTFILE_PREFIX
3403
+// MD_STARTFILE_PREFIX_1
3404
+// INIT_ENVIRONMENT
3405
+// LOCAL_INCLUDE_DIR
3406
+#undef LOCAL_INCLUDE_DIR
3407
+
3408
+// NATIVE_SYSTEM_HEADER_COMPONENT
3409
+// INCLUDE_DEFAULTS
3410
+
3411 102 dgisselq
+/* 17.03 Run-time Target Specification */
3412
+
3413
+/* TARGET_CPU_CPP_BUILTINS() ... This function-like macro expands to a block of
3414
+ * code that defines built-in preprocessor macros and assertions for the target
3415
+ * CPU, using the functions builtin_define, builtin_define_std, and
3416
+ * builtin_assert.  When the front end calls this macro it provides a trailing
3417
+ * semicolon, and since it has finished command line option proccessing your
3418
+ * code can use those results freely.
3419
+ *
3420
+ * ZipCPU --- We should probably capture in this macro what capabilities the
3421
+ * command line parameters we've been given indicate that our CPU has.  That
3422
+ * way, code can be adjusted depending upon the CPU's capabilities.
3423
+ */
3424
+#define        TARGET_CPU_CPP_BUILTINS()                       \
3425
+       { builtin_define("__ZIPCPU__");                 \
3426
+       if (ZIP_FPU) builtin_define("__ZIPFPU__");      \
3427
+       if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__");        \
3428
+       }
3429
+       // If (zip_param_has_fpu)  builtin_define("__ZIPFPU__");
3430
+       // If (zip_param_has_div)  builtin_define("__ZIPDIV__");
3431
+       // If (zip_param_has_mpy)  builtin_define("__ZIPMPY__");
3432
+       // If (zip_param_has_lock) builtin_define("__ZIPLOCK__");
3433
+       // If (zip_param_supervisor) builtin_define("__ZIPUREGS__");
3434
+       // If (we support int64s) builtin_define("___int64_t_defined");
3435
+
3436
+/* TARGET_OS_CPP_BUILTINS() ... Similarly to TARGET_CPU_CPP_BUILTINS but this
3437
+ * macro is optional and is used for the target operating system instead.
3438
+ */
3439
+
3440
+/* Option macros: (we need to define these eventually ... )
3441
+ *
3442
+ *     TARGET_HANDLE_OPTION
3443
+ *     TARGET_HANDLE_C_OPTION
3444
+ *     TARGET_OBJ_CONSTRUCT_STRING_OBJECT
3445
+ *     TARGET_OBJ_DECLARE_UNRESOLVED_CLASS_REFERENCE
3446
+ *     TARGET_OBJ_DECLARE_CLASS_DEFINITION
3447
+ *     TARGET_STRING_OBJECT_REF_TYPE_P
3448
+ *     TARGET_CHECK_STRING_OBJECT_FORMAT_ARG
3449
+ *     TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE(VOID)
3450
+ *     C_COMMON_OVERRIDE_OTPTIONS
3451
+ *     TARGET_OPTION_OPTIMIZATION_TABLE
3452
+ *     TARGET_OPTION_INIT_STRUCT
3453
+ *     TARGET_OPTION_DEFAULT_PARAMS
3454
+ */
3455
+
3456
+/* SWITCHABLE_TARGET
3457
+ *
3458
+ * Zip CPU doesn't need this, so it defaults to zero.  No need to change it
3459
+ * here.
3460
+ */
3461
+
3462
+/* TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(VOID) ... Returns true if the
3463
+ * target supports IEEE 754 floating-point exceptions and rounding modes, false
3464
+ * otherwise.  This is intended to relate to the float and double types, but not
3465
+ * necessarily "long double".  By default, returns true if the adddf3
3466
+ * instruction pattern is available and false otherwise, on the assumption that
3467
+ * hardware floating point supports exceptions and rounding modes but software
3468
+ * floating point does not.
3469
+ *
3470
+ * ZipCPU floating point is barely going to be functional, I doubt it will
3471
+ * support all of these bells and whistles when full functionality is even
3472
+ * achieved.  Therefore, we won't support these modes.  However, we can't just
3473
+ * set this to zero, so let's come back to this.
3474
+ */
3475
+// #warning "Wrong answer encoded to date"
3476 103 dgisselq
+// #undef      TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
3477 102 dgisselq
+// #define     TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(X) 0
3478
+
3479
+/* 17.04 Defining data structures for per-function information */
3480
+
3481
+/* INIT_EXPANDERS ... Macro called to initialize any target specific
3482
+ * information.  This macro is called once per function, before generation of
3483
+ * any RTL has begun.  The intention is to allow the initialization of the
3484
+ * function pointer init_machine_status.
3485
+ */
3486
+// #warning "I may need to define this to handle function return addresses ..."
3487
+
3488
+/* 17.05 Storage Layout */
3489
+
3490
+/* Storage Layout */
3491
+#define        BITS_BIG_ENDIAN         0        // MSB has highest number
3492
+#define        BYTES_BIG_ENDIAN        1       // 1 if MSB is lowest number
3493
+#define        WORDS_BIG_ENDIAN        1       // 1 if MSW is lowest number
3494
+#define        FLOAT_WORDS_BIG_ENDIAN  1
3495
+#define        BITS_PER_WORD           32
3496
+// #define     MAX_BITS_PER_WORD       // defaults to BITS_PER_WORD
3497
+#define        UNITS_PER_WORD          1       // Storage units in a word, pwr of 2:1-8
3498
+#define        MIN_UNITS_PER_WORD      1       // Default is UNITS_PER_WORD
3499
+/* POINTER_SIZE ... Width of a pointer in bits.  You must specify a value no
3500
+ * wider than the width of Pmode.  If it is not equal to the width of Pmode,
3501
+ * you must define POINTERS_EXTEND_UNSIGNED. If you do not specify a value the
3502
+ * default is BITS_PER_WORD.
3503
+ *
3504
+ * ZipCPU --- All of our pointers are 32-bits, the width of our address bus.
3505
+ */
3506
+#define        POINTER_SIZE            32      // Ptr width in bits
3507
+/* POINTERS_EXTEND_UNSIGNED ... A C expression that determines how pointers
3508
+ * should be extended from ptr_mode to either Pmode or word_mode.  It is greater
3509
+ * than zero if pointers should be zero-extended, zero if they should be sign
3510
+ * extended, and negative if some other conversion is needed.  In the last case,
3511
+ * the extension is done by the target's ptr_extend instruction.
3512
+ *
3513
+ * You need not define this macro if the ptr_mode, Pmode, and word_mode are all
3514
+ * the same width.
3515
+ *
3516
+ * ZipCPU --- While we shouldn't need this, QImode and HImode have the same
3517
+ * number of bits as SImode.  Therefore, one might wish to convert between the
3518
+ * two.  Hence, we specify how we would do that here.
3519
+ */
3520 127 dgisselq
+#define        POINTERS_EXTEND_UNSIGNED        1
3521 102 dgisselq
+
3522
+/* PROMOTE_MODE(m,unsignedp,type) ... A macro to update m and unsignedp when an
3523
+ * object whose type is type and which has he specified mode and signedness is
3524
+ * to be stored in a register.  This macro is only called when type is a scalar
3525
+ * type.
3526
+ *
3527
+ * On most RISC machines, which only have operations that operate on a full
3528
+ * register, define this macro to set m to word_mode if m is an integer mode
3529
+ * narrower than BITS_PER_WORD.  In most cases, only integer modes should be
3530
+ * widened because wider precision floating-point operations are usually more
3531
+ * expensive than their narrower counterparts.
3532
+ *
3533
+ * For most machines, the macro definition does not change unsigndep.  However,
3534
+ * some machines, have instructions that preferentially handle either signed or
3535
+ * unsigned quantities of certain modes.  For example, on the DEC Alpha, 32-bit
3536
+ * loads from memory and 32-bit add instructions sign-extend the result to
3537
+ * 64-bits. On such machines, set unsignedp according to which kind of extension
3538
+ * is more efficient.
3539
+ *
3540
+ * Do not define this macro if it would never modify m.
3541
+ *
3542
+ * ZipCPU --- We need to always (if possible) promote everything to SImode where
3543
+ * we can handle things.  HImode and QImode just don't make sense on this CPU.
3544
+ */
3545
+#define        PROMOTE_MODE(M,U,T)     if ((GET_MODE_CLASS(M)==MODE_INT)&&(GET_MODE_SIZE(M)<2)) (M)=SImode;
3546
+
3547
+// TARGET_PROMOTE_FUNCTION_MODE
3548
+/* PARM_BOUNDARY ... Normal alignment required for function parameters on the
3549
+ * stack, in bits.  All stack parameters receive at least this much alignment
3550
+ * regardless of data type.  On most machines, this is the same as the size of
3551
+ * an integer.
3552
+ */
3553
+#define        PARM_BOUNDARY   32
3554
+
3555
+/* STACK_BOUNDARY ... Define this macro to the minimum alignment enforced by
3556
+ * hardware for the stack pointer on this machine.  The definition is a C
3557
+ * expression for the desired alignment (measured in bits).  This value is used
3558
+ * as a default if PREFERRED_STACK_BOUNDARY is not defined.  On most machines,
3559
+ * this should be the same as PARM_BOUNDARY.
3560
+ */
3561
+#define        STACK_BOUNDARY  PARM_BOUNDARY
3562
+
3563
+/* PREFERRED_STACK_BOUNDARY ... Define this ... */
3564 127 dgisselq
+#define        PREFERRED_STACK_BOUNDARY        STACK_BOUNDARY
3565 102 dgisselq
+
3566 127 dgisselq
+/* INCOMING_STACK_BOUNDARY ... Define this macro if the incoming stack boundary
3567
+ * may be different from PREFERRED_STACK_BOUNDARY.  This macro must evaluate
3568
+ * to a value equal to or larger than STACK_BOUNDARY.
3569 102 dgisselq
+ */
3570 127 dgisselq
+#define        INCOMING_STACK_BOUNDARY STACK_BOUNDARY
3571 102 dgisselq
+
3572
+/* FUNCTION_BOUNDARY ... Alignment required for a function entry point, in bits.
3573
+ */
3574
+#define        FUNCTION_BOUNDARY       32
3575
+
3576
+/* BIGGEST_ALIGNMENT ... Biggest alignment that any data type can require on
3577
+ * this machine, in bits.  Note that this is not the biggest alignment that is
3578
+ * supported, just the biggest alignment that, when violated, may cause a fault.
3579
+ */
3580
+#define BIGGEST_ALIGNMENT      32
3581
+
3582 127 dgisselq
+/* MALLOC_ABI_ALIGNMENT
3583
+ */
3584
+
3585
+/* ATTRIBUTE_ALIGNED_VALUE
3586
+ */
3587
+
3588 102 dgisselq
+/* MINIMUM_ATOMIC_ALIGNMENT ... If defined, the smallest alignment, that can be
3589
+ * given to an object that can be referenced in one operation, without
3590
+ * disturbing any nearby object.  Normally, this is BITS_PER_UNIT, but may be
3591
+ * larger on machines that don't have byte or halfword store operations.
3592
+ */
3593
+#define        MINIMUM_ATOMIC_ALIGNMENT        BITS_PER_UNIT
3594
+
3595 127 dgisselq
+/* BIGGEST_FIELD_ALIGNMENT ... Biggest alignment that any structure or union
3596
+ * field can require on this machine, in bits.  If defined, this overrides
3597
+ * BIGGEST_ALIGNMENT for structure and union fields only, unless the field
3598
+ * alignment has been set by the __attribute__((aligned(n))) construct.
3599
+ */
3600
+#define        BIGGEST_FIELD_ALIGNMENT BITS_PER_UNIT
3601
+
3602
+/* ADJUST_FIELD_ALIGN
3603
+ */
3604
+#define        ADJUST_FIELD_ALIGN(A,B) BITS_PER_WORD
3605
+
3606
+/* MAX_STACK_ALIGNMENT
3607
+ */
3608
+#define        MAX_STACK_ALIGNMENT     BITS_PER_WORD
3609
+
3610
+/* MAX_OFILE_ALIGNMENT
3611
+ */
3612
+
3613
+/* DATA_ALIGNMENT(TYPE, BASIC-ALIGN) ... If defined, a C expression to compute
3614
+ * the alignment for a variable in the static store.  TYPE is the data type, and
3615
+ * BASIC-ALIGN is the alignment that the object would ordinarily have.  The
3616
+ * value of this macro is used instead of that alignment to align the object.
3617
+ *
3618
+ * If this macro is not defined, then BASIC-ALIGN is used.
3619
+ *
3620
+ * ZipCPU -- in hindsight, if this macro is not defined then the compiler is
3621
+ * broken.  So we define it to be our fastest alignment, or 32-bits.
3622
+ */
3623
+#define        DATA_ALIGNMENT(TYPE, ALIGN)     BITS_PER_WORD
3624
+
3625
+
3626
+/* DATA_ABI_ALIGNMENT(TYPE,BASIC-ALIGN)
3627
+ */
3628
+
3629
+/* CONSTANT_ALIGNMENT(CONST, BASIC-ALIGN) ... If defined, a C expression to
3630
+ * compute the alignment given to a constant that is being placed in memory.
3631
+ * CONST is the constant and BASIC-ALIGN is the alignment that the object
3632
+ * would ordinarily have.  The value of this macro is used instead of that
3633
+ * alignment to align the object.
3634
+ *
3635
+ * If this macro is not defined, then BASIC-ALIGN is used.
3636
+ *
3637
+ * ZipCPU -- in hindsiht, if this macro is not defined then the compiler is
3638
+ * broken.  We'll define it as above.
3639
+ *
3640
+ */
3641
+#define        CONSTANT_ALIGNMENT(EXP, ALIGN)  BITS_PER_WORD
3642
+
3643
+/* LOCAL_ALIGNMENT(TYPE,BASIC-ALIGN) ... If defined ...
3644
+ */
3645
+#define        LOCAL_ALIGNMENT(TYP,ALIGN)      BITS_PER_WORD
3646
+
3647
+/* TARGET_VECTOR_ALIGNMENT
3648
+ */
3649
+
3650
+/* STACK_SLOT_ALIGNMENT
3651
+ */
3652
+#define        STACK_SLOT_ALIGNMENT(T,M,B)     BITS_PER_WORD
3653
+
3654
+/* LOCAL_DECL_ALIGNMEN(DECL)
3655
+ */
3656
+#define        LOCAL_DECL_ALIGNMENT(DECL)      BITS_PER_WORD
3657
+
3658
+/* MINIMUM_ALIGNMENT
3659
+ */
3660
+#define        MINIMUM_ALIGNMENT(EXP,MOD,ALIGN)        BITS_PER_WORD
3661
+
3662
+/* EMPTY_FIELD_BOUNDARY
3663
+ * Alignment of field after 'int : 0' in a structure.
3664
+ */
3665
+#define        EMPTY_FIELD_BOUNDARY    BITS_PER_WORD
3666
+
3667
+/* STRUCTURE_SIE_BOUNDARY
3668
+ * ZipCPU -- Every structures size must be a multiple of 32-bits.
3669
+ */
3670
+#define        STRUCTURE_SIZE_BOUNDARY BITS_PER_WORD
3671
+
3672 102 dgisselq
+/* STRICT_ALIGNMENT ... Set this nonzero if move instructions will actually
3673
+ * fail to work when given unaligned data.  If instructions will merely go
3674
+ * slower in that case, define this macro as 0.
3675 125 dgisselq
+ *
3676
+ * ZipCPU -- Since we have defined our smallest addressable unit to be a 32-bit
3677
+ * word (one byte, on our machine), and since reading any amount of 32-bit words
3678
+ * is easy, then there really are no instructions that will ever fail.
3679 102 dgisselq
+ */
3680 125 dgisselq
+#define        STRICT_ALIGNMENT        0
3681 102 dgisselq
+
3682 127 dgisselq
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way
3683
+ * other C compilers handle alignment of bit-fields and the structures that
3684
+ * contain them.
3685
+ *
3686
+ * The behavior is that the type written for a named bit-field (int, short, or
3687
+ * other integer type) imposes an alignment for the entire structure, as if the
3688
+ * structure really did contain an ordinary field of that type.  In addition,
3689
+ * the bit-field is placed within the structure so that it would fit within
3690
+ * such a field, not crossing a boundary for it.
3691
+ *
3692
+ * Thus, no most machines, a named bit-field whose type is written as int would
3693
+ * not cross a four-byte boundary, and would force four-byte alignment for the
3694
+ * whole structure.  (The alignment used may not be four bytes; it is controlled
3695
+ * by other alignment parameters.)
3696
+ *
3697
+ * An unnamed bit-field will not affect the alignment of the containing
3698
+ * structure.
3699
+ *
3700
+ * If the macro is defined, its definition should be a C expression, a non
3701
+ * zero value for the expression enables this behavior.
3702
+ * Look at the fundamental type that is used for a bit-field and use that to
3703
+ * impose alignment on the enclosing structure.  struct s{int a:8}; should
3704
+ * have the same alignment as 'int', not 'char'.
3705
+ */
3706
+#undef PCC_BITFIELD_TYPE_MATTERS
3707
+#define        PCC_BITFIELD_TYPE_MATTERS       0
3708
+
3709 102 dgisselq
+/* MAX_FIXED_MODE_SIZE ... An integer expression for the size in bits of the
3710
+ * largest integer machine mode that should actually be used.  All integer
3711
+ * machine modes of this size or smaller can be used for structures and unions
3712
+ * with the appropriate sizes.  If this macro is undefined,
3713
+ * GET_MODE_BITSIZE(DImode) is assumed.
3714
+ *
3715
+ * ZipCPU ... Get_MOD_BITSIZE(DImode) will be 64, and this is really not the
3716
+ * size on bits of the largest integer machine mode.  However, that's the case
3717
+ * with most DI implementations: A long is two words, spliced together.  We'd
3718
+ * like to support that eventually, but we need to get there.  Hence, let's use
3719
+ * compile time flag (ZIP_HAS_DI) that we can enable when we're ready.
3720
+ */
3721
+#if (ZIP_HAS_DI != 0)
3722
+#define        MAX_FIXED_MODE_SIZE     64
3723
+#else
3724
+#define        MAX_FIXED_MODE_SIZE     32
3725
+#endif
3726
+
3727
+
3728
+/* 17.06 Layout of Source Language Data Types */
3729
+
3730
+#undef CHAR_TYPE_SIZE
3731
+#undef SHORT_TYPE_SIZE
3732
+#undef INT_TYPE_SIZE
3733
+#undef LONG_TYPE_SIZE
3734
+#undef LONG_LONG_TYPE_SIZE
3735
+//
3736
+#define        CHAR_TYPE_SIZE  32
3737
+#define        SHORT_TYPE_SIZE 32
3738
+#define        INT_TYPE_SIZE   32
3739 200 dgisselq
+#define        LONG_TYPE_SIZE  64
3740 102 dgisselq
+#define        LONG_LONG_TYPE_SIZE     64
3741
+// BOOL_TYPE_SIZE defaults to CHAR_TYPE_SIZE
3742
+#undef FLOAT_TYPE_SIZE
3743
+#undef DOUBLE_TYPE_SIZE
3744
+#undef LONG_DOUBLE_TYPE_SIZE
3745
+#define        FLOAT_TYPE_SIZE         32
3746 200 dgisselq
+#define        DOUBLE_TYPE_SIZE        64      // This'll need to be done via emulation
3747 102 dgisselq
+#define        LONG_DOUBLE_TYPE_SIZE   64      // This'll need to be done via emulation
3748
+// SHORT_FRAC_TYPE_SIZE
3749
+// LONG_FFRACT_TYPE_SIZE
3750
+// LONG_LONG_FRACT_TIME_SIZE
3751
+#undef SHORT_ACCUM_TYPE_SIZE
3752
+#undef ACCUM_TYPE_SIZE
3753
+#undef LONG_ACCUM_TYPE_SIZE
3754
+#define        SHORT_ACCUM_TYPE_SIZE   SHORT_TYPE_SIZE
3755
+#define        ACCUM_TYPE_SIZE         INT_TYPE_SIZE
3756
+#define        LONG_ACCUM_TYPE_SIZE    LONG_TYPE_SIZE
3757
+
3758
+/* LIBGCC2_GNU_PREFIX ... This macro corresponds to the TARGET_GNU_PREFIX target
3759
+ * hook and should be defined if that hook is overriden to be true.  It causes
3760
+ * function names in libgcc to be changed to use a __gnu_ prefix for their name
3761
+ * rather than the default __.  A port which uses this macro should also arrange
3762
+ * to use t-gnu-prefix in the libgcc config.host.
3763
+ *
3764
+ * ZipCPU -- I see no reason to define and therefore change this behavior.
3765
+ */
3766
+
3767
+/* TARGET_FLT_EVAL_METHOD ... A C expression for the value for FLT_EVAL_METHOD
3768
+ * in float.h,, assuming, if applicable, that the floating-point control word
3769
+ * is in its default state.  If you do not define this macro the value of
3770
+ * FLT_EVAL_METHOD will be zero.
3771
+ *
3772
+ * ZipCPU --- ???
3773
+ */
3774
+
3775
+/* WIDEST_HARDWARE_FP_SIZE ... A C expression for the size in bits of the widest
3776
+ * floating-point format supported by the hardware.  If you define this macro,
3777
+ * you must specify a value less than or equal to the value of LONG_DOUBLE_...
3778
+ * If you do not define this macro, the value of LONG_DOUBLE_TYPE_SIZE is the
3779
+ * default.
3780
+ *
3781
+ * ZipCPU supports 32-bit IEEE floats--IF THE SUPPORT IS COMPILED IN!  This
3782
+ * really needs to be determined, then, based upon a compile time parameter
3783
+ * where the one compiling the code states whether or not the H/W even has
3784
+ * floating point support.
3785
+ *
3786
+ * For now, we'll assume it does--but once we implement GCC parameters, we'll
3787
+ * need to change this.
3788
+ */
3789
+#undef WIDEST_HARDWARE_FP_SIZE
3790
+// #warning "Definition needs to change if no FPU present"
3791
+#define        WIDEST_HARDWARE_FP_SIZE FLOAT_TYPE_SIZE
3792
+
3793
+/* DEFAULT_SIGNED_CHAR ... An expression whose value is 1 or 0, according to
3794
+ * whether the type char should be signed or unsigned by default.  The user
3795
+ * can always override this default with the options -fsigned-char and
3796
+ * -funsigned-char.
3797
+ *
3798
+ * ZipCPU--let's go with the default behavior.
3799
+ */
3800
+#define        DEFAULT_SIGNED_CHAR     1
3801
+
3802
+/* TARGET_DEFAULT_SHORT_ENUMS(VOID) ... This target hook should return true if
3803 103 dgisselq
+ * the compiler should give an enum type only as many bytes as it takes to
3804 102 dgisselq
+ * represent the range of possible values of that type.  It should return
3805
+ * false if all enum types should be allocated like int.
3806
+ *
3807
+ * The default is to return false.  This is what the ZipCPU needs, so we won't
3808
+ * override it.
3809
+ */
3810
+
3811
+/* SIZE_TYPE ... A C expression for a string describing the name of the data
3812
+ * type to use for size values.  The typedef name size_t is defined using the
3813
+ * contents of the string.
3814
+ *
3815
+ * If you don't define this macro, the default is "long unsigned int".  Since
3816
+ * on the ZipCPU this is a 32-bit number, and all ZipCPU values are 32-bits,
3817
+ * the default seems perfect for us.
3818
+ */
3819
+#define        SIZE_TYPE       "unsigned int"
3820
+
3821
+/* SIZETYPE ... GCC defines internal types () for expressions dealing with size.
3822
+ * This macro is a C expression for a string describing the name of the data
3823
+ * type from which the precision of sizetype is extracted.  The string has the
3824
+ * same restrictions as SIZE_TYPE string.  If you don't define this macro, the
3825
+ * default is SIZE_TYPE --- which seems good enough for us.
3826
+ */
3827
+
3828
+/* PTRDIFF_TYPE ... A C expression for a string describing the name of the data
3829 127 dgisselq
+ * type to use for the result of subtracting two pointers.  The typedef name
3830 102 dgisselq
+ * ptrdiff_t is defined using the contents of the string.  See SIZE_TYPE for
3831
+ * more information.
3832
+ *
3833
+ * The default is "long int" which for the ZipCPU is 32-bits---still good enough
3834
+ * for us.
3835
+ */
3836
+#define        PTRDIFF_TYPE    "int"
3837
+
3838
+/* WCHAR_TYPE ... A C expression for a string describing the name of the data
3839
+ * type to use for wide characters.  The typedef name wchar_t is defined using
3840
+ * the contents of  the string.  If you don't define this macro, the default is
3841
+ * 'int'--good enough for ZipCPU.
3842
+ */
3843
+
3844
+/* WCHAR_TYPE_SIZE ... A C expression for the size in bits of the data type for
3845
+ * wide characters.  This is used in cpp, which cannot make use of WCHAR_TYPE.
3846
+ */
3847
+#undef WCHAR_TYPE_SIZE
3848
+#define        WCHAR_TYPE_SIZE 32
3849
+
3850
+/* WINT_TYPE ... A C expression for a string describing the name of the data
3851
+ * type to use for wide characters passed to printf and returned from getwc.
3852
+ * The typedef name wint_t is defined using the contents of the string.  See
3853
+ *
3854 103 dgisselq
+ * ZipCPU -- If you don't define this macro, the default is "unsigned int"--also
3855
+ * best for us again.
3856 102 dgisselq
+ */
3857
+
3858
+/* INTMAX_TYPE ... A C expression for a string describing the name of the
3859
+ * data type that can represent any value of any standard or extended signed
3860
+ * integer type.  The typedef name intmax_t is defined using the contents of
3861
+ * the string.
3862
+ *
3863
+ * If you don't define this macro, the default is the first of "int", "long int"
3864
+ * or "long long int" that has as much precision as "long long int".
3865
+ */
3866
+
3867
+/* UINTMAX_TYPE ... same as INTMAX_TYPE, but for unsigned
3868
+ */
3869
+
3870
+#undef SIG_ATOMIC_TYPE
3871
+#if (ZIP_ATOMIC != 0)
3872
+#define        SIG_ATOMIC_TYPE "int"
3873
+#else
3874
+#define        SIG_ATOMIC_TYPE NULL    // We have no atomic types, but registers
3875
+#endif
3876
+#undef INT8_TYPE
3877
+#define        INT8_TYPE               NULL    // We have no 8-bit integer type
3878
+#undef INT16_TYPE
3879
+#define        INT16_TYPE              NULL
3880
+#undef INT32_TYPE
3881
+#define        INT32_TYPE              "int"
3882
+#undef UINT8_TYPE
3883
+#define        UINT8_TYPE              NULL
3884
+#undef UINT16_TYPE
3885
+#define        UINT16_TYPE             NULL
3886
+#undef UINT32_TYPE
3887
+#define        UINT32_TYPE             "unsigned int"
3888
+#undef INT_LEAST8_TYPE
3889
+#define        INT_LEAST8_TYPE         "int"
3890
+#undef INT_LEAST16_TYPE
3891
+#define        INT_LEAST16_TYPE        "int"
3892
+#undef INT_LEAST32_TYPE
3893
+#define        INT_LEAST32_TYPE        "int"
3894
+#undef UINT_LEAST8_TYPE
3895
+#define        UINT_LEAST8_TYPE        "unsigned int"
3896
+#undef UINT_LEAST16_TYPE
3897
+#define        UINT_LEAST16_TYPE       "unsigned int"
3898
+#undef UINT_LEAST32_TYPE
3899
+#define        UINT_LEAST32_TYPE       "unsigned int"
3900
+#undef INT_FAST8_TYPE
3901
+#define        INT_FAST8_TYPE          "int"
3902
+#undef INT_FAST16_TYPE
3903
+#define        INT_FAST16_TYPE         "int"
3904
+#undef INT_FAST32_TYPE
3905
+#define        INT_FAST32_TYPE         "int"
3906
+#undef UINT_FAST8_TYPE
3907
+#define        UINT_FAST8_TYPE         "unsigned int"
3908
+#undef UINT_FAST16_TYPE
3909
+#define        UINT_FAST16_TYPE        "unsigned int"
3910
+#undef UINT_FAST32_TYPE
3911
+#define        UINT_FAST32_TYPE        "unsigned int"
3912
+#undef INTPTR_TYPE
3913
+#define        INTPTR_TYPE             "unsigned int"
3914
+#undef UINTPTR_TYPE
3915
+#define        UINTPTR_TYPE            "unsigned int"
3916
+
3917
+#undef INT64_TYPE
3918
+#undef UINT64_TYPE
3919
+#undef INT_LEAST64_TYPE
3920
+#undef UINT_LEAST64_TYPE
3921
+#undef INT_FAST64_TYPE
3922
+#undef UINT_FAST64_TYPE
3923
+
3924
+#if (ZIP_HAS_DI != 0)
3925
+#define        INT64_TYPE              "long int"
3926
+#define        UINT64_TYPE             "long unsigned int"
3927
+#define        INT_LEAST64_TYPE        "long int"
3928
+#define        UINT_LEAST64_TYPE       "long unsigned int"
3929
+#define        INT_FAST64_TYPE         "long int"
3930
+#define        UINT_FAST64_TYPE        "long unsigned int"
3931
+#else
3932
+#define        INT64_TYPE              NULL
3933
+#define        UINT64_TYPE             NULL
3934
+#define        INT_LEAST64_TYPE        NULL
3935
+#define        UINT_LEAST64_TYPE       NULL
3936
+#define        INT_FAST64_TYPE         NULL
3937
+#define        UINT_FAST64_TYPE        NULL
3938
+#endif
3939
+
3940
+#define        TARGET_PTRMEMFUNC_VBI_LOCATION  ptrmemfunc_vbit_in_pfn
3941
+
3942
+
3943
+/* 17.07 Register Usage / Register definitions */
3944
+
3945
+/* FIRST_PSEUDO_REGISTER ... Number of hardware registers known to the compiler.
3946
+ * They receive numbers 0 through FIRST_PSEUDO_REGISTER-1; thus the first
3947
+ * pseudo register's numbrer really is assigned the number
3948
+ * FIRST_PSEUDO_REGISTER.
3949
+ *
3950
+ * ZipCPU---There are 16 registers in the ZipCPU, numbered 0-15 with the CC
3951 171 dgisselq
+ * and PC register being numbered 14 and 15 respectively.  The ZipCPU has
3952
+ * another 16 registers, identical to the first, but user mode registers.  These
3953
+ * are number the same as the first (0-15) in user mode, but numbered (16-31)
3954
+ * in supervisor mode.  In addition, we create a pretend argument pointer
3955
+ * register, zip_AP_PSEUDO, to refer to our arguments.  This final register,
3956
+ * although it gets a valid number, will be eliminated in optimization.
3957 102 dgisselq
+ */
3958 171 dgisselq
+#define        FIRST_PSEUDO_REGISTER   (zip_AP_PSEUDO+1)
3959 102 dgisselq
+
3960
+/* FIXED_REGISTERS ... An initializer that says which registers are used for
3961
+ * fixed purposes all throughout the compiled code and are therefore not
3962
+ * available for general allocation.  These would include the stack pointer, the
3963
+ * frame pointer (except on machines where that can be used as a general
3964
+ * register when no frame pointer is needed), the program counter on machines
3965
+ * where that is considered one of the addressable registers, and any other
3966
+ * numbered register with a standard use.
3967
+ *
3968
+ * This information is expressed as a sequence of numbers, separated by commas,
3969
+ * and surrounded by braces.  The nth number is 1 if register n is fixed, 0
3970
+ * otherwise.
3971
+ *
3972
+ * For the Zip CPU, we have three fixed registers that are not available for
3973
+ * general allocation:
3974
+ *
3975
+ *     SP      The stack pointer
3976
+ *     CC      The condition codes and CPU state register
3977
+ *     PC      The program counter
3978
+ *
3979
+ * Other registers, such as FP (the frame pointer) or GBL (the global offset
3980
+ * table pointer) are registers that we hope will not be so fixed.
3981 171 dgisselq
+ *
3982
+ * Okay, just updated this process.  We now have more registers that are not
3983
+ * available for general allocation:
3984
+ *     uR0-uPC         User registers
3985
+ *     PSEUDO-AP       The pseudo arg pointer
3986 102 dgisselq
+ */
3987 171 dgisselq
+#define        FIXED_REGISTERS         { 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, 1 }
3988 102 dgisselq
+
3989
+/* CALL_USED_REGISTERS ... like FIXED_REGISTERS but has 1 for each register
3990
+ * that is clobbered (in general) by function calls as well as for fixed
3991
+ * registers.  This macro therefore identifies the registers that are not
3992
+ * available for general allocation of values that must live across function
3993
+ * calls.
3994
+ *
3995
+ * If a register has 0 in CALL_USED_REGISTERS, the compiler automatically saves
3996
+ * it on function entry and restores it on function exit, if the register is
3997
+ * used within the function.
3998
+ *
3999
+ * On the Zip CPU, we must save R0 (the return address), and (let's pick) any
4000
+ * register above R5.
4001
+ */
4002 171 dgisselq
+#define        CALL_USED_REGISTERS     { 0,1,1,1, 1,0,0,0, 0,0,0,0, 0,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1,  1 }
4003 102 dgisselq
+
4004
+/* CALL_REALLY_USED_REGISTERS ...  optional macro that, if not defined, defaults
4005
+ * to the value of CALL_USED_REGISTERS.
4006
+ */
4007
+
4008
+/* HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) ... A C expression that is nonzero
4009
+ * if it is not permissible to store a value of mode MODE in hard register REGNO
4010
+ * across a call without some part of it being clobbbered.  For most machines,
4011
+ * this macro need not be defined.  It is only required for machines that do
4012 103 dgisselq
+ * not preserve the entire contents of a register across a call.
4013 102 dgisselq
+ *
4014 127 dgisselq
+ * ZipCPU--Always preserves the entire contents of those registers that are
4015
+ * preserved across calls, so this shouldnt need to be defined.
4016 102 dgisselq
+ */
4017 127 dgisselq
+// #define     HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE)      (REGNO==0)
4018 102 dgisselq
+
4019
+/* TARGET_CONDITIONAL_REGISTER_USAGE(VOID) ... This hook may conditionally
4020
+ * modify five variables fixed_regs, call_used_regs, global_regs, reg_names, and
4021
+ * reg_class_contents, to take into account any dependence of these register
4022
+ * sets on target flags.  The first three of these are of type char[]
4023
+ * (interpreted as Boolean vectors).  global_regs is a const char *[] and
4024
+ * reg_class_contents is a HARD_REG_SET.  Before the macro is called,
4025
+ * fixed_regs, call_used_regs, reg_class_contents, and reg_names have been
4026
+ * initialized from FIXED_REGISTERS, CALL_USED_REGISTERS, REG_CLASS_CONTENTS,
4027
+ * and REGISTER_NAMES, respectively.  global_regs has been cleared, and any
4028
+ * -ffixed-reg, -fcall-used-reg, and -fcall-saved-reg command options have been
4029
+ * applied.
4030
+ *
4031 171 dgisselq
+ * ZipCPU -- I may need to return and define this depending upon how the
4032
+ * GBL register allocation goes.  But for now, we'll leave this at its default
4033 102 dgisselq
+ * value.
4034
+ */
4035
+// #warning "Revisit me after FP and GBL allocation"
4036
+
4037
+/* INCOMING_REGNO(out) ... Define this macro if the target machine has register
4038
+ * windows. ...
4039
+ *
4040
+ * Zip CPU has no register windows.
4041
+ */
4042
+
4043
+/* OUTGOING_REGNO ... same thing.
4044 171 dgisselq
+ * LOCAL_REGNO ... same thing.
4045 102 dgisselq
+ */
4046
+
4047
+/* PC_REGNUM ... If the program counter has a register number, define this as
4048
+ * that register number.  Otherwise do not define it.
4049
+ */
4050
+#define        PC_REGNUM       zip_PC
4051
+
4052
+
4053
+/* REG_ALLOC_ORDER ... If defined, an initializer for a vector of integers,
4054
+ * containing the number of hard registers in the order in which GCC should
4055
+ * prefer to use them (from most preferred to least.
4056
+ *
4057 103 dgisselq
+ * If this macro is not defined, registers are used lowest numbered first (all
4058 102 dgisselq
+ * else being equal).
4059
+ *
4060
+ * Since the default is the ZipCPU desired case, we won't define this here.
4061
+ */
4062
+
4063
+/* ADJUST_REG_ALLOC_ORDER ... on most machines it is not necessary to define
4064
+ * this macro, so we won't either.
4065
+ */
4066
+
4067
+/* HONOR_REG_ALLOC_ORDER ...
4068
+ */
4069
+
4070
+/* HONOR_REG_ALLOC_ORDER ... on most machines it is not necessary to define
4071
+ * this macro, so we won't either.
4072
+ */
4073
+
4074
+/* HARD_REGNO_NREGS(REGNO, MODE) ... A C expression for the number of
4075
+ * consecutive hard registers, starting at register number REGNO, required to
4076
+ * hold a value of mode MODE.
4077
+ *
4078
+ * On a machine where all registers are exactly one word, a suitable definition
4079
+ * is given of ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)/UNITS_PER_WORD.
4080
+ *
4081
+ * On ZipCPU, we might do
4082
+ *     ((((MODE)==DImode)||((MODE)==DFmode))?2:1)
4083
+ * but I think the default (above) code should work as well.  Hence, let's stick
4084
+ * with the default, lest someone try to create larger modes (TImode, OImode,
4085
+ * XImode) and expect us to follow them properly some how.
4086
+ *
4087
+ * Okay, now in hind sight, we know that the default doesn't work for our
4088
+ * architecture, since GET_MODE_SIZE(SImode)=4, not 1.  Thus, let's rearrange
4089
+ * this expression to work in bits rather than in bytes and we'll know more
4090
+ * of what we are doing.
4091
+ */
4092
+#undef HARD_REGNO_NREGS
4093
+#define        HARD_REGNO_NREGS(REGNO, MODE)   ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)\
4094
+               / (UNITS_PER_WORD))
4095
+
4096
+/* HARD_REGNO_NREGS_HAS_PADDING(REGNO,MODE) ... A C expression that is nonzero
4097
+ * if a value of mode MODE, stored in memory, ends with padding that causes it
4098
+ * to take up more space than in registers starting at register number REGNO
4099
+ * (as determined by multiplying GCC's notion of the size of the register when
4100
+ * containing this mode by the number of registers returned by HARD_REGNO_NREGS)
4101
+ * By default this is zero.
4102
+ *
4103
+ * Zip CPU --- The default looks good enough to me.
4104
+ */
4105
+
4106
+/* HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE)
4107
+ *
4108
+ * ZipCPU ---
4109
+ */
4110
+
4111
+/* REGMODE_NATURAL_SIZE(MODE) -- Define this macro if the natural size of
4112
+ * registers that hold values of mode mode is not the word size.  It is a C
4113
+ * expression that should give the natural size in bytes for the specified mode.
4114
+ * It is used by the register allocator to try to optimize its results.
4115
+ *
4116
+ * ZipCPU ---
4117
+ */
4118
+// #define     REGMODE_NATURAL_SIZE(MODE)      (((MODE)==DImode)?2:1)
4119
+
4120
+/* HARD_REGNO_MODE_OK ... A C expression that is nonzero if it is permissible
4121 103 dgisselq
+ * to store a value of mode MODE in a hard register number REGNO (or in several
4122 102 dgisselq
+ * registers starting with that one).  For a machine where all registers are
4123
+ * equivalent, a suitable definition is '1'.  You need not include code to check
4124
+ * for the numbers of fixed registers, because the allocation mechanism
4125
+ * considered them to be always occupied.
4126
+ *
4127
+ * ZipCPU --- As long as you are already avoiding the fixed registers, the
4128
+ * suitable default definition mentioned above should be sufficient.
4129
+ */
4130
+#undef HARD_REGNO_MODE_OK
4131 103 dgisselq
+#define        HARD_REGNO_MODE_OK(R,M) (R<zip_CC)
4132 102 dgisselq
+
4133
+/* HARD_REGNO_RENAME_OK(FROM,TO) ... A C expression that is nonzero if it is
4134
+ * okay to rename a hard register FROM to another hard register TO.  One common
4135
+ * use of this macro is to prevernt renaming of a register to another register
4136
+ * that is not saved by a prologue in an interrupt handler.  The default is
4137
+ * always nonzero.
4138
+ *
4139
+ * ZipCPU --- The default looks good enough to us.
4140
+ */
4141
+#undef HARD_REGNO_RENAME_OK
4142
+#define        HARD_REGNO_RENAME_OK(FROM,TO)   ((is_ZIP_GENERAL_REG(FROM))&&(is_ZIP_GENERAL_REG(TO)))
4143
+
4144
+
4145
+/* MODES_TIABLE_P(M1, M2) ... A C expression that is nonzero if a value of mode
4146
+ * M1 is accessible in mode M2 without copying.
4147
+ *
4148
+ * ZipCPU --- well, that's true for us (although we support scant few modes) ...
4149
+ * so lets' set to one.
4150
+ */
4151
+#define        MODES_TIEABLE_P(M1,M2)  1
4152
+
4153
+/* TARGET_HARD_REGNO_SCRATCH_OK(REGNO)
4154
+ * This target hook should return true if it is OK to use a hard register
4155
+ * REGNO has a scratch register in peephole2.  One common use of this macro is
4156
+ * to prevent using of a register that is not saved by a prologue in an
4157
+ * interrupt handler.  The default version of this hook always returns true.
4158
+ *
4159
+ * ZipCPU --- the default works for us as well.  If you are in an interrupt
4160
+ * context, you have an entirely new set of registers (the supervisor set), so
4161
+ * this is a non-issue.
4162
+ */
4163
+
4164
+/* AVOID_CCMODE_COPIES ... define this macro if the compiler should avoid
4165
+ * copies to/from CCmode register(s).  You should only define this macro if
4166
+ * support for copying to/from CCmode is incomplete.
4167
+ *
4168
+ * ZipCPU --- CCmode register copies work like any other, so we'll keep with the
4169
+ * default definition.
4170
+ */
4171
+
4172
+/* STACK_REGS ... Define this if the machine has any stack-like registers.
4173
+ *
4174
+ * Zip CPU has no stack-like registers, as their definition is different from
4175
+ * the ZipCPU stack pointer register.
4176
+ */
4177
+
4178 127 dgisselq
+// #define     ZIP_REG_BYTE_SIZE       1
4179 102 dgisselq
+
4180
+/* 17.08 Register Classes */
4181
+
4182
+/* enum reg_class ... An enumerate type that must be defined with all the
4183
+ * register class names as enumerated values.  NO_REGS must be first.  ALL_REGS
4184
+ * must be the last register class, followed by one more enumerated value,
4185
+ * LIM_REG_CLASSES, which is not a register class but rather tells how many
4186
+ * classes there are.
4187
+ *
4188
+ * ZipCPU --- We'll defined register 0-13 as general registers, 14-15 in
4189
+ * all_regs, and go from there.
4190
+ */
4191
+enum   reg_class {
4192
+       NO_REGS, GENERAL_REGS,
4193
+       USER_REGS,
4194
+       ALL_REGS, LIM_REG_CLASSES
4195
+};
4196
+
4197
+/* N_REG_CLASSES ... the number of distinct register classes, defined as follows
4198
+ */
4199
+#define        N_REG_CLASSES   (int)LIM_REG_CLASSES
4200
+
4201
+/* REG_CLASS_NAMES ... An initializer containing the names of the register
4202
+ * classes as C string constants.  These names are used in writing some of the
4203
+ * debugging dumps.
4204
+ */
4205 171 dgisselq
+#define        REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "USER_REGS", "ALL_REGS" }
4206 102 dgisselq
+
4207
+/* REG_CLASS_CONTENTS ... An initializer containing the contents of the register
4208 127 dgisselq
+ * classes, as integers which are bit masks.  The nth integer specifies the
4209 102 dgisselq
+ * contents of class n.  That way the integer mask is interpreted as that
4210
+ * register r is in the class if (mask&(1<<r)) is 1.
4211
+ *
4212 171 dgisselq
+ * When the machine has more than 32 registers, an integer does not suffice.
4213
+ * Then the integers are replaced by sub-initializers, braced groupings
4214
+ * containing several integers.  Each sub-initializer must be suitable as an
4215
+ * initializer for the type HARD_REG_SET which is defined in 'hard-reg-set.h'.
4216
+ * In this situation, the first integer in each subinitializer corresponds to
4217
+ * registers 0-31, the second integer to registers 32-634, and so on.
4218 102 dgisselq
+ *
4219
+ * ZipCPU --- This is straight forward, three register classes, etc.
4220
+ */
4221 171 dgisselq
+#define        REG_CLASS_CONTENTS { { 0x000000000, 0}, {0x00003fff, 0}, {0x0ffff0000, 0}, {0x0ffffffff, 1} }
4222 102 dgisselq
+
4223
+/* REGNO_REG_CLASS ... A C expression whose value is a register class
4224
+ * containing hard register REGNO.  In general there is more than one such
4225
+ * class;  Choose a class which is minimal, meaning that no smaller class also
4226
+ * contains the register.
4227
+ */
4228 171 dgisselq
+#define        REGNO_REG_CLASS(R)      (is_ZIP_REG(R)?(((R)<=13)?GENERAL_REGS:ALL_REGS):NO_REGS)
4229 102 dgisselq
+
4230
+/* BASE_REG_CLASS ... A macro whose definition is the name of the class to which
4231
+ * a valid base register must belong.  A base register is one used in an address
4232
+ * which is the register value plus a displacement.
4233
+ */
4234
+#undef BASE_REG_CLASS
4235
+#define        BASE_REG_CLASS  GENERAL_REGS
4236
+
4237
+/* MODE_BASE_CLASS(MODE) ... This is a variation of the BASE_REG_CLASS macro
4238
+ * which allows the selection of a bse register in a mode dependent manner.  If
4239
+ * mode is VOIDmode then it should return the same value as BASE_REG_CLASS.
4240
+ */
4241
+#undef MODE_BASE_CLASS
4242
+#define        MODE_BASE_CLASS(MODE)   GENERAL_REGS
4243
+
4244
+/* MODE_BASE_REG_REG_CLASS(MODE) ... A C expression whose value is the register
4245
+ * class to which a valid base register must belong in order to be used in a
4246
+ * base plus index register address.  You should define this macro if base plus
4247
+ * index addresses have different requirements than other base register uses.
4248
+ *
4249
+ * Zip CPU does not support the base plus index addressing mode, thus ...
4250
+ */
4251 111 dgisselq
+// #undef      MODE_BASE_REG_REG_CLASS
4252
+// #define     MODE_BASE_REG_REG_CLASS(MODE)   NO_REGS
4253 102 dgisselq
+
4254
+/* INDEX_REG_CLASS ... A macro whose definition is the name of the class to
4255
+ * which a valid index register must belong.  An index register is one used in
4256
+ * an address where its value is either multiplied by a scale factor or added
4257
+ * to another register (as well as added to a displacement).
4258
+ *
4259
+ * ZipCPU -- Has no index registers.
4260
+ */
4261
+#undef INDEX_REG_CLASS
4262
+#define        INDEX_REG_CLASS NO_REGS
4263
+
4264
+/* REGNO_OK_FOR_BASE_P(NUM) ... A C expression which is nonzero if register
4265
+ * number num is suitable for use as a base register in operand addresses.
4266
+ */
4267
+#undef REGNO_OK_FOR_BASE_P
4268 127 dgisselq
+# define REGNO_OK_FOR_BASE_P(NUM)      ((NUM>=FIRST_PSEUDO_REGISTER)||(NUM != zip_CC))
4269 102 dgisselq
+
4270
+/* REGNO_MODE_OK_FOR_BASE_P ... A C expressison that is just like
4271
+ * REGNO_OK_FOR_BASE_P, except that that expression may examine the mode of the
4272 111 dgisselq
+ * memory reference in MODE.  You should define this macro if the mode of the
4273 102 dgisselq
+ * memory reference affects whether a register may be used as a base register.
4274
+ *
4275
+ * ZipCPU --- the mode doesn't affect anything, so we don't define this.
4276
+ */
4277
+
4278
+/* REGNO_MODE_OK_FOR_REG_BASE_P(NUM, MODE) ... base plus index operand
4279
+ * addresses, accessing memory in mode mode.
4280
+ *
4281
+ * Use of this macro is deprecated.
4282
+ */
4283
+
4284 111 dgisselq
+/* REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) ... A C expression which is
4285 102 dgisselq
+ * nonzero if a register number N is suitable for use as a base register in
4286
+ * operand addresses, accessing memory in mode M in address space AS.  This is
4287
+ * similar to REGNO_MODE_OK_FOR_BASE_P, except that the expression may examine
4288
+ * the context in which the register appears in the memory reference.
4289
+ *
4290
+ * ZipCPU---We aren't specific in how we use our registers.
4291
+ */
4292
+#define        REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) REGNO_OK_FOR_BASE_P(N)
4293
+
4294
+/* REGNO_OK_FOR_INDEX_P(REGNO) ... A C expression which is nonzero if register
4295
+ * num is suitable for use as an index register in opernad addressess.  It may
4296
+ * be either a suitable hard register or a pseudo register that has been
4297 111 dgisselq
+ * allocated such as a hard register.
4298 102 dgisselq
+ *
4299
+ * ZipCPU has no index registers, therefore we declare this to be zero.
4300
+ */
4301
+#undef REGNO_OK_FOR_INDEX_P
4302
+#define        REGNO_OK_FOR_INDEX_P(REGNO)     0
4303
+
4304
+/* TARGET_PREFERRED_RENAME_CLASS(RCLASS) ... A target hook that places
4305
+ * additional preference on the register class to use when it is necessary to
4306
+ * rename a register in class RCLASS to another class, or perhaps NO_REGS, if no
4307
+ * preferred register class is found or hook preferred_rename_class is not
4308
+ * implemented.  SOmething returning a more restrictive class makes better code.
4309
+ * For example, on ARM, thumb-2 instructions using LO_REGS may be smaller than
4310
+ * instructions using GENERIC_REGS.  By returning LO_REGS from
4311
+ * preferred_rename_class, code size can be reduced.
4312
+ */
4313
+// #undef TARGET_PREFERRED_RENAME_CLASS
4314
+// #define     TARGET_PREFERRED_RENAME_CLASS(RCLASS)   RCLASS
4315
+
4316
+/* TARGET_PREFERRED_RELOAD_CLASS(X,RC) ... A target hook that places additional
4317
+ * restri tions on the register class to use when it is necessary to copy value
4318
+ * X into a register in class RC.  The value is a register class; rehaps RC, or
4319
+ * perhaps a smaller class.
4320
+ *
4321
+ * The default fversion of this hook always returns value of RC argument, which
4322
+ * sounds quite appropriate for the ZipCPU.
4323
+ */
4324
+
4325
+/* PREFERRED_RELOAD_CLASS(X,CLASS) ... A C expression that places additional
4326
+ * restrictions on the register class to use when it is necessary to copy
4327
+ * value X into a register in class CLASS.  On many machines, the following
4328
+ * definition is safe: PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
4329
+ * Sometimes returning a more restrictive class makes better code.  For example,
4330
+ * on the 68k, when x is an integer constant that is in range for a moveq
4331
+ * instruction, the value of this macro is always DATA_REGS as long as CLASS
4332 111 dgisselq
+ * includes the data registers.  Requiring a data register guarantees that a
4333 102 dgisselq
+ * 'moveq' will be used.
4334
+ *
4335
+ * ZipCPU --- you can't load certain values into all members of ALL_REGS.  For
4336
+ * example, loading (sleep and !gie) into the CC register could halt the CPU.
4337
+ * Hence, we only allow loads into the GENERAL_REG class.
4338
+ */
4339
+#define        PREFERRED_RELOAD_CLASS(X, CLASS)        GENERAL_REGS
4340
+
4341
+/* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS(RTX,RCLASS) ... Like TARGET_PREFERRED_..
4342
+ * RELOAD_CLASS, but for output instead of input reloads.
4343
+ *
4344
+ * ZipCPU --- there's gotta be a valid default behaviour for this.
4345
+ */
4346
+
4347
+/* LIMIT_RELOAD_CLASS(MODE, CL) ...
4348
+ *
4349
+ * Don't define this macro unless the target machine has limitations which
4350
+ * require the macro to do something nontrivial.  ZipCPU doesn't, so we won't.
4351
+ */
4352
+
4353
+/* TARGET_SECONDARY_RELOAD
4354
+ * SECONDARY_ ...
4355
+ * Don't think we need these ...
4356
+ */
4357
+
4358
+/* CLASS_MAX_NREGS(CLASS,MODE) ... A C expression for the maximum number of
4359
+ * consecutive registers of class CLASS needed to hold a value of mode MODE.
4360
+ *
4361
+ * This is closely related to the macro HARD_REGNO_NREGS.  In fact, the value
4362
+ * of the macro CLASS_MAX_REGS(CL,M) should be the maximum value of
4363
+ * HARD_REGNO_NREGS(REGNO,MODE) for all REGNO values in the class CLASS.
4364
+ *
4365
+ * This macro helps control the handling of multiple word values in the reload
4366
+ * pass.
4367
+ *
4368
+ * ZipCPU --- We'll just use HARDNO_REGNO_NREGS, since CLASS is independent for
4369
+ * us.  We'll also choose register R0, since ... well, since it simply doesn't
4370
+ * matter.  (HARD_REGNO_NREGS ignores this anyway)
4371
+ */
4372
+#define        CLASS_MAX_NREGS(CLASS, MODE)    HARD_REGNO_NREGS(0,MODE)
4373
+
4374
+/* CANNOT_CHANGE_MODE_CLASS
4375
+ * ???
4376
+ */
4377
+
4378
+/* TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
4379
+ */
4380
+
4381
+/* TARRGET_LRA_P
4382
+ * Default looks good.
4383
+ */
4384
+
4385
+/* TARGET_REGISTER_PRIORITY(INT) ... A target hook which returns the register
4386 111 dgisselq
+ * priority number to which the register HARD_REGNO belongs to.  The bigger the
4387 102 dgisselq
+ * number
4388
+ *
4389
+ * The default version of this target hook returns always zero---good enough for
4390
+ * the ZipCPU.
4391
+ */
4392
+
4393
+/* TARGET_REGISTER_USAGE_LEVELING_P(VOID) ... A target hook which returns true
4394
+ * if we need register usage leveling.  That means if a few hard registers are
4395
+ * equally good for the assignment, we choose the least used hard register.  The
4396
+ * register usage leveling may be profitable for some targets.  Don't use usage
4397
+ * leveling for targets with conditional execution or targets with big register
4398
+ * files as it hurts if-conversion and cross-jumping optimizations.  The default
4399
+ * version of this target hook returns always false.
4400
+ *
4401
+ * ZipCPU --- Default is the right answer.
4402
+ */
4403
+
4404
+/* TARGET_DIFFERENT_ADDR_DISPLACEMENT_P ...
4405
+ * Default looks good.
4406
+ */
4407
+
4408
+/* TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P ...
4409
+ * Default looks good.
4410
+ */
4411
+
4412
+/* TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT ....
4413
+ */
4414
+
4415
+/* TARGET_SPILL_CLASS
4416
+ *
4417
+ * ZipCPU --- If we were running in supervisor mode only, this might be the
4418
+ * user set of registers.  However, we're not building for that mode (now),
4419
+ * so we'll leave this at the default of NO_REGS.
4420
+ */
4421
+
4422
+/* TARGET_CSTORE_MODE(ICODE) ... Defines the machine mode to use for the
4423
+ * boolean result of conditional store patterns.  The OCIDE argument is the
4424
+ * instruction code for the cstore being performed.  Not defining this hook is
4425
+ * the same as accepting the mode encoded into operand 0 of the cstore expander
4426
+ * patterns.
4427
+ *
4428
+ * ??? ZipCPU --- I don't follow this documentation.  We'll leave this at the
4429
+ * default therefore.
4430
+ */
4431
+
4432
+/* 17.09 Stack Layout and Calling Conventions */
4433
+
4434
+
4435
+/* STACK_GROWS_DOWNWARD ... Define this macro if pushing a word onto the stack
4436
+ * moves the stack pointer to a smaller address, and false otherwise.
4437
+ *
4438
+ * ZipCPU ... well, our stack does grow downward, but it doesn't do so auto-
4439
+ * magically.  We have to move the stack pointer ourselves.  However, since this
4440
+ * is our convention, we'll define it as such.
4441
+ */
4442
+#undef STACK_GROWS_DOWNWARD
4443
+#define        STACK_GROWS_DOWNWARD    1
4444
+
4445
+/* STACK_PUSH_CODE ... This macro defines the operation used when something is
4446
+ * pushed on the stack.  In RTL, a push operation will be
4447
+ * (set (mem( STACK_PUSH_CODE(reg sp))) ...) The choiecs are PRE_DEC, POST_DEC,
4448
+ * PRE_INC, and POST_INC.  Which of these is correct depends on the stack
4449
+ * direction and on whether the stack pointer points to the last item on the
4450
+ * stack or whether it points to the space for the next item on the stack.
4451
+ * The default is PRE_DECC when STACK_GROWS_DOWNWARD is true, which is almost
4452
+ * always right, and PRE_INC otherwise, which is often wrong.
4453
+ *
4454
+ * ZipCPU --- None of these is right, so let's leave this at the default and
4455
+ * see how badly we get mangled.  In particular, ZipCPU doesn't have any of the
4456
+ * PRE_DEC, POST_DEC, PRE_INC, or POST_INC addressing modes used here.
4457
+ */
4458
+
4459
+/* FRAME_GROWS_DOWNWARD ... Define this macro to nonzero if the addresses of
4460
+ * local variable slots are at negative offsets from the frame pointer.
4461
+ *
4462
+ * ZipCPU --- If the frame pointer is defined as the stack pointer upon the
4463 103 dgisselq
+ * start of function execution, and that stack pointer grows downward, then
4464 102 dgisselq
+ * this should be the case as well.
4465
+ */
4466
+#undef FRAME_GROWS_DOWNWARD
4467
+#define        FRAME_GROWS_DOWNWARD    1
4468
+// #define     FRAME_GROWS_DOWNWARD    0        // This was ECO32's value
4469
+
4470
+
4471
+/* ARGS_GROW_DOWNWARD ... Define this macro if successive arguments to a
4472
+ * function occupy decreasing addresses on the stack.
4473
+ *
4474
+ * ZipCPU -- we can leave this up to the compiler's preferred implementation,
4475
+ * it is of no consequence to the hardware.
4476
+ */
4477
+
4478
+/* STARTING_FRAME_OFFSET ... Offset from the frame pointer to the first local
4479
+ * variable slot to be allocated.  If FRAME_GROWS_DOWNWARD, find the next slot's
4480 171 dgisselq
+ * offset by subtracting the first slot's length from STARTING_FRAME_OFFSET.
4481 102 dgisselq
+ * Otherwise it is found by adding the length of the first slot to the value
4482
+ * START_FRAME_OFFSET.
4483
+ *
4484
+ * ZipCPU --- I'm not certain on this, let's come back after we look at how
4485
+ * the code is getting generated.  However, the ECO32 code I am copying from
4486
+ * suggests that 0 is the right value, so we'll use that here.
4487
+ */
4488 171 dgisselq
+// #warning "Re-evaluate me" --- I did.  This still looks good.
4489 102 dgisselq
+#define        STARTING_FRAME_OFFSET   0
4490
+
4491
+/* STACK_ALIGNMENT_NEEDED ... Define to zero to disable final alignment of the
4492
+ * stack during reload.  The nonzero default for this macro is suitable for most
4493
+ * ports.
4494
+ *
4495
+ * ZipCPU --- we'll leave this at the default, although if any alignment code
4496
+ * shows up on the stack we may need to adjust it.
4497
+ */
4498
+
4499
+/* STACK_POINTER_OFFSET ... Offset from the SP register to the first location at
4500
+ * which outgoing arguments are placed.  If not specified, the default value
4501
+ * of zero is used.  This is the proper value for most machines.
4502
+ */
4503
+#define        STACK_POINTER_OFFSET    0
4504
+
4505
+/* FIRST_PARM_OFFSET ... Offset from the argument pointer register to the first
4506
+ * argument's address.  On some machines it may depend on the data type of the
4507 171 dgisselq
+ * function.
4508 102 dgisselq
+ */
4509
+#define        FIRST_PARM_OFFSET(F)    0
4510
+
4511
+/* STACK_DYNAMIC_OFFSET(F) ... Offset from the stack pointer register to an item
4512
+ * dynamically allocated on the stack, e.g., by alloca.  The default value for
4513
+ * this macro is STACK_POINTER_OFFSET plus the length of the outgoing arguments.
4514
+ * The default is correct for most machines, ...
4515
+ *
4516
+ * ZipCPU --- so we'll use it for the ZipCPU.
4517
+ */
4518
+
4519
+/* INITIAL_FRAME_ADDRESS_RTX ... A C expression whose value is RTL representing
4520
+ * the address of the initial stack frame.  This address is passed to
4521
+ * RETURN_ADDR_RTX and DYNAMIC_CHAIN_ADDRESS.  If you don't define this macro,
4522
+ * a reasonable default value will be used.  Define this macro in order to make
4523
+ * frame pointer elimination work in the presence of __builtin_frame_address(C)
4524
+ * and __builtin_return_address(C) for (C) not equal to zero.
4525
+ *
4526
+ * ZipCPU --- Let's try the reasonable default and see what happens.
4527
+ */
4528
+
4529
+/* SETUP_FRAME_ADDRESSES ... A C expression that produces the machine-specific
4530
+ * code to setup the stack so that arbitrary frames can be accessed.  For
4531
+ * example, on the SPARC, we must flush all of the register windows to the stack
4532
+ * before we can access arbitrary stack frames.  You will seldom need to define
4533
+ * this macro.  The default is to do nothing.
4534
+ *
4535
+ * ZipCPU --- which is what we shall do here.
4536
+ */
4537
+
4538
+/* TARGET_BUILTIN_SETJMP_FRAME_VALUE(VOID) ... This target hook should return
4539
+ * an RTX that is used to store the address of the current frame into the
4540
+ * builtin setjmp buffer.  The default value, virtual_stack_vars_rtx, is correct
4541
+ * for most machines.  One reason you may need to define this target hook is if
4542
+ * hard_frame_pointer_rtx is the appropriate value on your machine.
4543
+ *
4544
+ * ZipCPU --- leave this undefined, since the default value should be correct
4545
+ * for "most" machines.
4546
+ */
4547
+
4548
+/* FRAME_ADDR_RTX ... most machines do not need to define it.
4549
+ */
4550
+
4551
+/* RETURN_ADDR_RTX(COUNT,FRAMEADDR) ... A C expression whose value is RTL
4552
+ * representing the value of the return address for the frame COUNT steps up
4553
+ * from the current frame, after the prologue.  FRAMEADDR is the frame pointer
4554
+ * of the COUNT frame, or the frame pointer of the COUNT-1 frame if
4555
+ * RETURN_ADDR_IN_PREVIOUS_FRAME is nonzero.  The value of the expression must
4556
+ * always be the correct address when COUNT is nonzero, but may be NULL_RTX if
4557
+ * there is no way to determine the return address of other frames.
4558
+ *
4559
+ * ZipCPU --- I have no idea how we'd do this, so let's just return NULL_RTX.
4560
+ */
4561
+#undef RETURN_ADDR_RTX
4562
+#define        RETURN_ADDR_RTX(COUNT,FRAMEADDR)        NULL_RTX
4563
+
4564
+/* RETURN_ADDR_IN_PREVIOUS_FRAME ... Define this macro to nonzero value if the
4565
+ * return address of a particular stack frame is accessed from the frame pointer
4566
+ * of the previous stack frame.  The zero default for this macro is suitable
4567
+ * for most ports.
4568
+ *
4569
+ * ZipCPU---Default works here as well.
4570
+ */
4571
+
4572
+/* INCOMING_RETURN_ADDR_RTX ... A C expression whose value is RTL representing
4573
+ * the location of the incoming return address at the beginning of any function,
4574
+ * before the prologue.  This RTL is either a REG, indicating that the return
4575
+ * value is saved in 'REG', or a MEM representing the location in the stack.
4576
+ * If this RTL is a REG, you should define DWARF_RETURN_COLUMN to
4577
+ * DWARF_FRAME_REGNUM(REGNO).
4578
+ *
4579
+ * ZipCPU --- While our incoming return address could theoretically be in any
4580
+ * register, our machine description file is going to place it into register
4581
+ * R0, so that's what we return here.
4582
+ */
4583
+#undef INCOMING_RETURN_ADDR_RTX
4584
+#define        INCOMING_RETURN_ADDR_RTX        gen_rtx_REG(SImode, zip_R0)
4585
+
4586
+
4587
+/* DWARF_ALT_FRAME_RETURN_COLUMN
4588
+ */
4589
+
4590
+/* DWARF_ZERO_REG ... A C exrpession whose value is an integer giving a DWARF2
4591
+ * register number that is considered to always have the value zero.  This
4592
+ * should only be defined if the target has an architected zero register (ZipCPU
4593
+ * does not), and someone decided it was a good idea to use that register number
4594
+ * to terminate the stack backtrace.  New ports should avoid this (so the
4595
+ * ZipCPU port will avoid it as well).
4596
+ *
4597
+ */
4598
+
4599
+/* TARGET_DWARF_HANDLE_FRAME_UNSPEC
4600
+ */
4601
+
4602 171 dgisselq
+/* INCOMING_FRAME_SP_OFFSET ... A C expression whose value is an integer giving
4603
+ * the offset, in bytes, from the value of the stack pointer register to the
4604
+ * top of the stack frame at the beginning of any function, before the prologue.
4605
+ * The top of the frame is defined to be the value of the stack pointer in the
4606
+ * previous frame, just before the call instruction.
4607
+ *
4608
+ * You only need to define this macro if you want to support call frame
4609
+ * debugging information like that provided by DWARF 2.
4610
+ *
4611
+ * ZipCPU---Our value is zero.
4612 102 dgisselq
+ */
4613
+#define        INCOMING_FRAME_SP_OFFSET        0
4614
+
4615
+/* ARG_POINTER_CFA_OFFSET
4616
+ */
4617
+
4618
+/* FRAME_POINTER_CFA_OFFSET
4619
+ */
4620
+
4621
+/* CFA_FRAME_BASE_OFFSET
4622
+ */
4623
+
4624
+/* 17.09.02 Exception handling support */
4625
+
4626
+/* EH_RETURN_DATA_REGNO(N) ... A C expression whose value is the Nth register
4627
+ * number used for data by exception handlers, or INVALID_REGNUM if fewer than
4628
+ * N registers are usable.  The exception handling library routines communicate
4629
+ * with the exception handlers via a set of agreed upon registers.  Ideally
4630
+ * these registers should be call clobbered; it is possible to use call-saved
4631
+ * registers, but may negatively impact code size.  The target must support at
4632
+ * least 2 data registers, but should define 4 if their are enough free
4633
+ * registers.
4634
+ *
4635
+ * You must define this macro if you want to support call frame exception
4636
+ * handling like that provided by DWARF 2.
4637
+ */
4638
+#define        EH_RETURN_DATA_REGNO(N) (((N<ZIP_FIRST_ARG_REGNO)||(N>ZIP_LAST_ARG_REGNO))?(N-1):INVALID_REGNUM)
4639
+
4640
+/* EH_RETURN_STACKADJ_RTX ... A C expression whose value is RTL representing
4641
+ * a location in which to store a stack adjustment to be applied before function
4642
+ * return.  This is used to unwind the stack to an exception handler's call
4643
+ * frame.  It will be assigned zero on code paths that return normally.
4644
+ *
4645
+ * Do not define this macro if the stack pointer is saved and restored by the
4646
+ * regular prolog and epilog code in the call frame itself (which it is for the
4647
+ * ZipCPU); in this case, the exception handling library routines will update
4648
+ * the stack location to be restored in place.  Otherwise, you must define this
4649
+ * macro if you want to support call frame exception handling like that provided
4650
+ * by DWARF 2.
4651
+ *
4652
+ */
4653
+
4654
+/* EH_RETURN_HANDLER_RTX ... A C expression whose value is RTL representing a
4655
+ * location in which to store the address of an exception handler to which we
4656
+ * should return.  It will not be assigned on code paths that return normally.
4657
+ *
4658
+ * Typcally this is the location in the call frame at which the normal return
4659
+ * address is stored.  For targets that return by popping an address of the
4660
+ * stack, this might be a memory address just below the target callf rame
4661
+ * rather than inside the current call frame.  If defined,
4662
+ * EH_RETURN_STACKADJ_RTX will have already been assigned, so it may be used
4663
+ * to calculate the location of the target call frame.
4664
+ *
4665
+ * If you want to support call frame exception handling, you must define either
4666
+ * this macro or the eh_return instruction pattern.
4667
+ */
4668
+// #warning "I don't know what to do here."
4669
+
4670
+/*
4671
+ *
4672
+ *
4673
+ *
4674
+ *   REST OF SECTION SKIPPED ...
4675
+ *
4676
+ *
4677
+ *
4678
+ */
4679
+
4680
+/* 17.09.03 Specifying how stack checking is done */
4681
+
4682
+/* STACK_CHECK_BUILTIN ... a non-zero value if stack checking is done by the
4683
+ * configuration files in a machine-dependent manner.  You should define this
4684
+ * macro if stack checking is required by the ABI of your machine or if you
4685
+ * would like to do stack checking in some more efficient way than the generic
4686
+ * appraoch.  The default value of this macro is zero.
4687
+ *
4688
+ * ZipCPU --- The default makes sense for us.
4689
+ */
4690
+// #define STACK_CHECK_BUILTIN 0
4691
+
4692
+/* STACK_CHECK_STATIC_BUILTIN ... A nonzero value if static stack checking is
4693
+ * done by the configuration files in a machine-dependent manner.  You should
4694
+ * define this macro if you would like to do static stack checking in some more
4695
+ * efficient way than the generic approach.  The default value of this macro
4696
+ * is zero.
4697
+ *
4698
+ * ZipCPU --- The default makes sense for us.
4699
+ */
4700
+
4701
+/* STACK_CHECK_PROBE_INTERVAL_EXP ...  An integer specifying the interval at
4702
+ * which GCC must generate stack probe instructions, defined as 2 raised to this
4703
+ * interval.  You will normally define this macro so that the interval is no
4704
+ * larger than the size of the "guard pages" at the end of a stack area.  The
4705
+ * default value of 12 (4096-byte interval) is suitable for most systems.
4706
+ *
4707
+ * ZipCPU --- Default.
4708
+ */
4709
+
4710
+/* STACK_CHECK_MOVING_SP ... An integer which is non-zero if GCC should move
4711
+ * the stack pointer page by page when doing probes.  This can be necessary
4712
+ * on systems where the stack pointer contains the bottom address of the memory
4713
+ * area accessible to the executing thread at any point in time.  In this
4714
+ * situation, an alternate signal stack is required in order to be able to
4715
+ * recover from a stack overflow.  The default value of this macro is zero.
4716
+ *
4717
+ * ZipCPU -- Default.
4718
+ */
4719
+
4720
+/* STACK_CHECK_PROTECT
4721
+ */
4722
+/* STACK_CHECK_MAX_FRAME_SIZE
4723
+ * ... you should normally not change the default value of this macro.
4724
+ */
4725
+/* STACK_CHECK_FIXED_FRAME_SIZE
4726
+ * ... you ... will normally use the default of four words.
4727
+ */
4728
+
4729
+/* STACK_CHECK_MAX_VAR_SIZE
4730
+ * ... you will normally not need to override that default.
4731
+ */
4732
+
4733
+/* 17.09.04 Registers that Address the Stack Frame*/
4734
+
4735
+/* STACK_POINTER_REGNUM ... The register number of the stack pointer register,
4736
+ * which must also be a fixed register according to FIXED_REGISTERS.  On most
4737
+ * machines, the hardware determines which register this is.
4738
+ */
4739
+#undef STACK_POINTER_REGNUM
4740
+#define        STACK_POINTER_REGNUM    zip_SP
4741
+
4742
+/* FRAME_POINTER_REGNUM ... The register number of the frame pointer register,
4743
+ * which is used to access certain automatic variables in the stack frame.  On
4744
+ * some machines, the hardware determines which register this is.  On other
4745
+ * machines you can choose any register you wish for this purpose.
4746
+ *
4747
+ * ZipCPU --- While I'd like to dump this pointer, since I don't really see
4748
+ * a need for it, alloca() requires it.  Therefore let's assine a register to
4749
+ * this purpose and watch what the compiler does with it.
4750
+ */
4751
+#define        FRAME_POINTER_REGNUM    zip_FP
4752
+
4753
+/* HARD_FRAME_POINTER_REGNUM ... On some machines the offset between the frame
4754
+ * pointer and starting offset of the automatic variables is not known until
4755
+ * after register allocation has been done (for example, because the saved
4756
+ * registers are between these two locations).  On those machines, define
4757
+ * FRAME_POINTER_REGNUM the number of a special, fixed register to be used
4758
+ * internally until the offset is known, and define HARD_FRAME_POINTER_REGNUM
4759
+ * to be the actual hard register number used for the frame pointer.
4760
+ *
4761
+ * Do not define this macro if it would be the same as FRAME_POINTER_REGNUM
4762
+ *
4763
+ * ZipCPU --- we do not define this macro.
4764
+ */
4765 103 dgisselq
+#define HARD_FRAME_POINTER_REGNUM      zip_FP
4766 102 dgisselq
+
4767
+/* ARG_POINTER_REGNUM ... The register number of the arg pointer register, which
4768
+ * is used to access the function's argument list.  On some machines, this is
4769
+ * the same as the frame pointer register.  On some machines, the hardware
4770
+ * determines which register this is.  On other machines, you can choose any
4771
+ * register you wish for this purpose.  If this is not the same register as the
4772
+ * frame pointer register, then you must mark it as a fixed register according
4773
+ * to FIXED_REGISTERs, or arrange to be able to eliminate it.
4774
+ *
4775
+ * ZipCPU --- We really don't want to lose another register to something
4776
+ * pointless, so let's set this to be the frame pointer register.  Especially
4777
+ * given the ZipCPU's ease of accessing things via offsets of registers, this
4778
+ * should work for a rather large stack frame.
4779 171 dgisselq
+ *
4780
+ * However ... we had problems with passing 6+ variables on the stack, so let's
4781
+ * try creating a pseudo register for this, and appropriately adjusting the
4782
+ * offset between this pseudo register and the stack pointer ...
4783 102 dgisselq
+ */
4784 171 dgisselq
+#define        ARG_POINTER_REGNUM      zip_AP_PSEUDO
4785 102 dgisselq
+
4786
+/* HARD_FRAME_POINTER_IS_FRAME_POINTER ... define this to be a preprocessor
4787
+ * constant that is nonzero if hard_frame_pointer_rtx and frame_pointer_rtx
4788
+ * should be the same.  The default definition is sufficient for us.
4789
+ */
4790
+
4791
+/* HARD_FRAME_POINTER_IS_ARG_POINTER ...
4792
+ * ZipCPU doesn't need this macro
4793
+ */
4794
+
4795
+/* RETURN_ADDRESS_POINTER_REGNUM ... The register number of the return address
4796
+ * pointer register, which is used to access the current function's return
4797
+ * address from the stack.  On some machines, the return address is not at a
4798
+ * fixed offset from the frame pointer or stack pointer or argument pointer.
4799
+ * This register can be defined to point to the return address on the stack, and
4800
+ * then to be converted by ELIMINABLE_REGS into either the frame pointer or the
4801
+ * stack pointer.
4802
+ *
4803
+ * Do not define this macro unless there is no other way to get the return
4804
+ * address from the stack.
4805
+ *
4806
+ * ZipCPU---we need this.
4807
+ */
4808
+#define        RETURN_ADDRESS_REGNUM   zip_R0
4809
+
4810
+
4811
+/* STATIC_CHAIN_REGNUM ... Register numbers used for passing a function's
4812
+ * static chain pointer.  If register windows are used, the register number as
4813
+ * seen by the called function is STATIC_CHAIN_INCOMING_REGNUM, while the
4814
+ * register number as seen by the calling function is STATIC_CHAIN_REGNUM.  If
4815
+ * these register are the same, STATIC_CHAIN_INCOMING_REGNUM need not be
4816
+ * defined.
4817
+ *
4818
+ * ZipCPU doesn't have register windows, so we don't need to define this.
4819
+ */
4820
+// #warning "I have no reason to believe this will even work"
4821
+#define        STATIC_CHAIN_REGNUM     zip_GOT
4822
+
4823
+/* TARGET_STATIC_CHAIN ... This hook replaces the use of STATIC_CHAIN_REGNUM et
4824
+ * al for targets that may use different static chain locations for different
4825
+ * nested functions.  This may be required if the target has function attributes
4826
+ * that affect the calling conventions of the function and those calling
4827
+ * conventions use different static chain locations.
4828
+ *
4829
+ * ZipCPU --- don't need this.
4830
+ */
4831
+// #define     STATIC_CHAIN_REGNUM     zip_R11
4832
+
4833
+
4834
+/* DWARF_FRAME_REGISTERS ... This macro specifies  the maximum number of hard
4835
+ * registers that can be saved in a call frame.  This is used to size data
4836
+ * structures used in DWARF2 exception handling.
4837
+ *
4838
+ * Prior to GCC 3.0, this macro was needed in order to establish a stable
4839
+ * exception handling ABI in the face of adding new hard registers for ISA
4840
+ * extensions.  In GCC 3.0 and later, the EH ABI is insulated from changes in
4841
+ * the number of hard registers.  Nevertheless, this macro can still be used to
4842
+ * reduce the runtime memory requirements of the exception handling routines,
4843
+ * which can be substantial if the ISA contains a lot of registers that are not
4844
+ * call-saved.
4845
+ *
4846
+ * If this macro is not defined, it defaults to FIRST_PSEUDO_REGISTER.
4847
+ *
4848
+ * ZipCPU --- The default is not sufficient.  The CC and PC registers need to
4849
+ * be saved and examined as well in any debug/exception context.  Hence, we
4850
+ * define this to be all of our registers.
4851
+ */
4852
+#undef DWARF_FRAME_REGISTERS
4853
+#define        DWARF_FRAME_REGISTERS   16
4854
+
4855
+/* PRE_GCC3_DWARF_FRAME_REGISTERS ... This macro is similar to DWARF_FRAME_REG..
4856
+ * but is provided for backward compatibility in pre GCC 3.0 compiled code.
4857
+ *
4858
+ * If not defined, it defaults to DWARF_FRAME_REGISTERS---which is perfect for
4859
+ * the ZipCPU.
4860
+ */
4861
+
4862
+/* DWARF_REG_TO_UNWIND_COLUMN(REGNO) ... Define this macro if the target's
4863
+ * representation for dwarf registers is different than the internal
4864
+ * representation for unwind column.  Given a dwarf register, this macro should
4865
+ * return the unwind column number to use instead.
4866
+ *
4867
+ * ... ???
4868
+ */
4869
+
4870
+/* DWARF_FRAME_REGNUM(REGNO) ... Define this macro is the target's
4871
+ * representation for dwarf registers used in .eh_frame or .debug_frame is
4872
+ * different from that used in other debug info sections.  Given a GCC hard
4873
+ * register number, this macro should return the .eh_frame register number.
4874
+ * The default is DBX_REGISTER_NUMBER(REGNO).
4875
+ *
4876
+ * ZipCPU --- provided we define DBX_REGISTER_NUMBER(REGNO) well, this default
4877
+ * should still work for us.
4878
+ */
4879
+
4880
+/* DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) ... Define this macro to map register
4881
+ * numbers held in the call frame info that GCC has collected using
4882
+ * DWARF_FRAME_REGNO to those that should be output in .debug_frame (for_eh is
4883
+ * zero) and .eh_frame (for_eh is non-zero). The default is to return REGNO.
4884
+ *
4885
+ * ZipCPU --- Default is good enough.
4886
+ */
4887
+
4888
+/* REG_VALUE_IN_UNWIND_CONTEXT ... Define this macro if the target stores
4889
+ * register values as _Unwind_Word type in unwind context.  It should be defined
4890
+ * if target register size is larger than the size of void *.  The default
4891
+ * is to store register values as void *type.
4892
+ *
4893
+ * ZipCPU --- Default is what we need.
4894
+ */
4895
+
4896
+/* ASSUME_EXTENDED_UNWIND_CONTEXT ... Define this macro to be 1 if the target
4897
+ * always uses extended unwind context with version, args_size, and by_value
4898
+ * fields.  If it is undefined, it will always be defined to 1 when REG_VALUE_IN_UNWIND_CONTEXT is defined and 0 otherwise.
4899
+ *
4900
+ */
4901
+
4902
+
4903
+/* 17.09.05 Eliminating Frame Pointer and Arg Pointer */
4904
+
4905
+/* TARGET_FRAME_POINTER_REQUIRED(VOID) ... This target hook should return true
4906
+ * if a function must have and use a frame pointer.  This target hook is
4907
+ * called in the reload pass.  If its return value is true, the function will
4908
+ * have a frame pointer.
4909
+ *
4910
+ * This target hook can in principle examine the current function and decide
4911
+ * according to the facts, but on most machines the constant false or the
4912
+ * constant true suffices.  Use false when the machine allows code to be
4913
+ * generated with no frame pointer, and doing so saves some time or space.
4914
+ * Use true when there is no possible advantage to avoiding a frame pointer.
4915
+ *
4916
+ * ZipCPU---if we add in a frame pointer, we become register starved.  Hence,
4917
+ * we'll treat this as a constant false--which is also the default value.
4918
+ */
4919
+#define        target_frame_pointer_required   zip_frame_pointer_required
4920
+
4921
+/* INITIAL_FRAME_POINTER_OFFSET ... A C statement to store in the variable
4922
+ * depth-var the difference between the frame pointer and the stack pointer
4923
+ * values immediately after the function prologue.  The value would be computed
4924
+ * from information such as the result of get_frame_size() and the tables of
4925
+ * registers regs_ever_live and call_used_regs.
4926
+ *
4927
+ * If ELIMINABLE_REGS is defined, this macro will not be used and need not be
4928
+ * defined.  Otherwise, it must be defined even if TARGET_FRAME_POINTER_REQD
4929
+ * always returns true; in that case you may set depth-var to anything.
4930
+ *
4931
+ * ZipCPU --- we intend to set ELIMINABLE_REGS, so this is not necessary.
4932
+ */
4933
+// #define     INITIAL_FRAME_POINTER_OFFSET(DEPTH)     (DEPTH) = 0
4934
+
4935
+
4936
+/* ELIMINABLE_REGS ... If defined, this macro specifies a table of register
4937
+ * pairs used to eliminate unneeded registers that point into the stack frame.
4938
+ * If it is not defined, the only elimination attempted by the compiler is to
4939
+ * replace references to the frame pointer with references to the stack pointer.
4940
+ *
4941
+ * On some machines, the position of the argument pointer is not known until
4942
+ * the compilation is completed.  In such a case, a separate hard register
4943
+ * must be used for the argument pointer.  This register can be eliminated by
4944
+ * replacing it with either the frame pointer or the argument pointer,
4945
+ * depending on whether or not the frame pointer has been eliminated.
4946
+ *
4947
+ * ZipCPU we'll take their suggestion and define this as:
4948
+ */
4949
+#undef ELIMINABLE_REGS
4950
+#define        ELIMINABLE_REGS \
4951
+       {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },  \
4952
+        { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },  \
4953
+        { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
4954
+
4955
+/* bool TARGET_CAN_ELIMINATE(FROM,TO) ... This target function should return
4956
+ * true if the compiler is allowed to try to replace register number FROM with
4957
+ * register number TO.  This target hook need only be defined if ELIMINABLE_REGS
4958
+ * is defined, and will usually return true since most of the cases preventing
4959
+ * register elimination are things that the compiler  already knows about.
4960
+ *
4961
+ * ZipCPU ... does the compiler  know about my decision as to whether or not
4962 117 dgisselq
+ * the frame pointer was needed?  Yes it does, but it's kept separately.  We'll
4963
+ * just say everything can be eliminated.
4964 102 dgisselq
+ */
4965
+#define TARGET_CAN_ELIMINATE   zip_can_eliminate
4966
+
4967
+/* INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) ... This macro is similar to
4968
+ * INITIAL_FRAME_POINTER_OFFSET.  It specifies the initial difference between
4969
+ * the specified pair of registers.  This macro must be defined if
4970
+ * ELIMINABLE_REGS is defined.
4971
+ *
4972 117 dgisselq
+ * ZipCPU---We had at one time set this to a default offset of 0.  This didn't
4973
+ * work.  It turns out that this is not only the *initial* elimination offset,
4974
+ * but also the offset along the way.  Hence, when a variable needs to be
4975
+ * spilled to the stack, this offset must change.  Reload goes and checks for
4976
+ * this, and adjusts registers if the offset has changed.  Hence, without this,
4977
+ * we get negative (i.e. illegal) stack offsets.
4978 102 dgisselq
+ */
4979
+#define        INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)            \
4980
+       do { (OFFSET) = zip_initial_elimination_offset((FROM), (TO)); } \
4981
+       while(0)                                        \
4982
+
4983
+/* 17.09.06 Passing function arguments on the stack */
4984
+
4985
+/* TARGET_PROMOTE_PROTOTYPES ... Returns true if an argument declared in a
4986
+ * prototype as an integral type smaller than int should actually be
4987
+ * passed as an int.  In addition to avoiding errors in certain cases of
4988
+ * mismatch, it also makes for better code on certain machines.  The default is
4989
+ * to not promote prototypes.
4990
+ *
4991
+ * Since everything is an int on the ZipCPU, let's promote anything smaller
4992
+ * (which should still be an int) up to an int anyway.
4993
+ */
4994
+#undef TARGET_PROMOTE_PROTOTYPES
4995
+#define        TARGET_PROMOTE_PROTOTYPES       hook_bool_const_tree_true
4996
+
4997
+/* PUSH_ARGS ... A C expression.  If nonzero, push instructions will be used to
4998
+ * pass outgoing arguments.  If the target machine does not have a push
4999
+ * instruction, set it to zero.  That directs GCC to use an alternate strategy:
5000
+ * to allocate the entire argument block and then store the arguments into it.
5001
+ * When PUSH_ARGS is nonzero, PUSH_ROUNDING must be defined too.
5002
+ *
5003
+ * ZipCPU does not have a push instruction, so we set this to zero.
5004
+ */
5005
+#undef PUSH_ARGS
5006
+#define        PUSH_ARGS       0
5007
+
5008
+/* PUSH_ARGS_REVERSED ... A C expression.  If nonzero, function arguments will
5009
+ * be evaluated last to first, rather than first to last.  If this macro is
5010
+ * not defined, it defaults to PUSH_ARGS on targets where the stack and args
5011
+ * grow in opposite directions, and zero otherwise.
5012
+ *
5013
+ * ZipCPU---Let's evaluate our arguments first to last.
5014
+ */
5015
+#define        PUSH_ARGS_REVERSED      1
5016
+
5017
+/* PUSH_ROUNDING(NPUSHED) ... A C expression that is the number of bytes
5018
+ * actually pushed onto the stack when an instruction attempts to push
5019
+ * (NPUSHED) bytes.
5020
+ *
5021
+ * ZipCPU---We cannot push bytes.  Let's leave this undefined and see what
5022
+ * happens.
5023
+ */
5024
+// #warning "No appropriate definition seemed right."
5025
+
5026
+/* ACCUMULATE_OUTGOING_ARGS ... A C expression.  If non-zero, the maximum amount
5027
+ * of space required for outgoing arguments will be computed and placed into
5028 171 dgisselq
+ * crtl->outgoing_args_size.  No space will be pushed onto the stack for each
5029
+ * call; instead the function prologue should increase the stack frame size by
5030
+ * this amount.
5031 102 dgisselq
+ *
5032
+ * ZipCPU---This is *cool* and so necessary---it saves an extra two instructions
5033
+ * each time we try to call a function/routine.  Yes, we want and *need* this
5034
+ * for good performance.  I mean, think of it, free performance increase?  Who
5035
+ * could argue with that?
5036
+ */
5037
+#undef ACCUMULATE_OUTGOING_ARGS
5038
+#define        ACCUMULATE_OUTGOING_ARGS        1
5039
+
5040
+
5041 191 dgisselq
+/* REG_PARM_STACK_SPACE(FN) ... Define this macro if functions should assume
5042 102 dgisselq
+ * that stack space has been allocated for arguments even when their values
5043
+ * are passed in registers.  The value of this macro is the size, in bytes, of
5044
+ * the area reserved for arguments passed in registers for the function
5045
+ * represented by FN, which can be zero if GCC is calling a library function.
5046
+ * The argument FN can be the FUNCTION_DECL, or the type itself of the function.
5047
+ *
5048
+ * This space can be allocated by the caller, or be part of the machine
5049
+ * dependent stack frame: OUTGOING_REG_PARM_STACK_SPACE says which.
5050
+ *
5051
+ * ZipCPU --- Why allocate space you won't use?  Let's leave this undefined
5052
+ * therefore.
5053
+ */
5054
+// #undef      REG_PARM_STACK_SPACE
5055
+
5056
+
5057
+
5058
+/* INCOMING_REG_PARM_STACK_SPACE(FN) ... Like REG_PARM_STACK_SPACE, but for
5059
+ * incoming register arguments.  Define this macro if space guaranteed when
5060
+ * compiling a function body is different to space required when making a call,
5061
+ * a situation that can arise with K&R style function definitions.
5062
+ *
5063
+ */
5064
+
5065
+/* OUTGOING_REG_PARM_STACK_SPACE(FN) ... Define this to a nonzero value if it
5066
+ * is the responsibility of the caller to allocate the area reserved for
5067
+ * arguments passed in registers when calling a function of FN.  FN may be NULL
5068
+ * if the function called is a library function.
5069
+ *
5070
+ * ZipCPU---Why allocate space you don't need?
5071
+ */
5072
+#define        OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)   0
5073
+
5074
+
5075
+/* STACK_PARMS_IN_REG_PARM_AREA ... Define this macro if REG_PARM_STACK_SPACE
5076
+ * is defined, buyt the stack parameters don't skip the area specified by it.
5077
+ *
5078
+ * ZipCPU---We didn't define REG_PARM_STACK_SPACE, so we won't define this.
5079
+ */
5080
+
5081
+/* TARGET_RETURN_POPS_ARGS(DECL,FNTYPE,SZ) ... This target hook returns the
5082
+ * number of bytes of its own arguments that a function pops on returning, or 0
5083
+ * if the function pops no arguments and the caller must therefore pop them all
5084
+ * after the function returns.
5085
+ *
5086
+ * ZipCPU --- If we define this, we'll lose our gain from
5087
+ * ACCUMULATE_OUTOING_ARGS.  Thus, we leave this undefined.
5088
+ */
5089
+
5090
+/* CALL_POPS_ARGS(CUM) ... A C expression that should indicate the number of
5091
+ * bytes a call sequence pops off of the stack.  It is added to the value of
5092
+ * RETURN_POPS_ARGS when compiling a function call.  CUM is the variable in
5093
+ * which all arguments to the function have been accumulated.
5094
+ *
5095
+ * ZipCPU---The call sequence, by itself, doesn't touch the stack.  Therefore
5096
+ * this is zero.
5097
+ */
5098
+#undef CALL_POPS_ARGS
5099
+#define        CALL_POPS_ARGS(CUM)     0
5100
+
5101
+
5102
+/* 17.09.07 Passing arguments in registers */
5103
+
5104
+/* TARGET_FUNCTION_ARG ... Return an RTX indicating whether a function argument
5105
+ * is passed in a register, and if so, which register.
5106
+ */
5107
+/*
5108
+ * This has been poisoned ... so let's not define it anymore and look for
5109
+ * a better way to do this ...
5110
+ *
5111
+ * #define     FUNCTION_ARG(CUM, MODE, TYPE, NAMED) (((NAMED) == 0) ? NULL_RTX
5112
+ *     : targetm.calls.must_pass_in_stack(MODE, TYPE)  ? NULL_RTX
5113
+ *     : (CUM) > ZIP_LAST_ARG_REGNO                    ? NULL_RTX
5114
+ *     : gen_rtx_REG(MODE, CUM))
5115
+ */
5116
+#define        TARGET_FUNCTION_ARG     zip_function_arg
5117
+
5118
+
5119 171 dgisselq
+/* TARGET_MUST_PASS_IN_STACK(MODE, TYPE) ... This target hook should return
5120
+ * true if we should not pass TYPE solely in registers.  The file 'expr.h'
5121
+ * defines a definition that is usually appropriate, refer to 'expr.h' for
5122
+ * additional documentation.
5123
+ *
5124
+ * ZipCPU ... Ok, so I looked into expr.h and didn't find anything that looked
5125
+ * like this.  So ... I don't know.
5126 102 dgisselq
+ */
5127
+// #undef      TARGET_MUST_PASS_IN_STACK
5128
+// #define     TARGET_MUST_PASS_IN_STACK       zip_must_pass_in_stack
5129
+
5130
+/* TARGET_FUNCTION_INCOMING_ARG ... Define this hook if the target machine
5131
+ * has register windows, ... which ZipCPU does not have.
5132
+ */
5133
+
5134
+/* TARGET_USE_PSEUDO_PIC_REG(void) ... This hook should return 1 in case
5135
+ * pseudo register should be created for pic_offset_table_rtx during function
5136
+ * expand.
5137
+ *
5138
+ * This should be defined by global parameters, isn't it?
5139
+ */
5140
+
5141
+/* TARGET_INIT_PIC_REG(v) ... Perform a target dependent initialization of
5142
+ * pic_offset_table_rtx.  This hook is called at the start of register
5143
+ * allocation.
5144
+ *
5145
+ * ZipCPU---Let's revisit this.
5146
+ */
5147
+// #warning "Come back and relook at relocations"
5148
+
5149
+/* TARGET_ARG_PARTIAL_BYTES ... This target hook returns the number of bytes
5150
+ * at the beginning of an argument that must be put in registers.  The value
5151
+ * must be zero for arguments that are passed entirely in registers or that
5152
+ * are entirely pushed on the stack.
5153
+ */
5154
+// #undef      TARGET_ARG_PARTIAL_BYTES
5155
+// #define     TARGET_ARG_PARTIAL_BYTES        zip_arg_partial_bytes
5156
+
5157
+/* TARGET_PASS_BY_REFERENCE(CUM,MOD,TREE,NAMED) ... This target hook should
5158
+ * return true if an argument at the position indicated by CUM should be passed
5159
+ * by reference.  This predicate is queried after target independent reasons
5160
+ * for being pssed by reference, such as TREE_ADDRESSABLE(TREE).
5161
+ *
5162
+ */
5163
+// #undef      TARGET_PASS_BY_REFERENCE
5164
+// #define     TARGET_PASS_BY_REFERENCE        zip_pass_by_reference
5165
+
5166
+/* CUMULATIVE ARGS ...  A C type for declaring a variable that is used as the
5167
+ * first argument of 'FUNCTION_ARG' and other related values.
5168
+ *
5169
+ * ZipCPU---We're in trouble if an 'int' won't work, so let's just use that.
5170
+ */
5171
+#define        CUMULATIVE_ARGS int
5172
+
5173
+/*
5174
+ * OVERRIDE_ABI_FORMAT
5175
+ */
5176
+
5177
+/* INIT_CUMULATIVE_ARGS ... A C statement (sans semicolon) for initializing the
5178
+ * variable CUM for the state at the beginning of the argument list.
5179
+ *
5180
+ *
5181
+ * ZipCPU---The first argument is passed in register ZIP_FIRST_ARG_REGNO, or
5182
+ * R1 (unless it has been redefined above ...)
5183
+ */
5184
+#define        INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) (CUM = 0)
5185
+
5186
+/* INIT_CUMULATIVE_LIBCALL_ARGS
5187
+ * INIT_CUMULATIVE_INCOMING_ARGS
5188
+ *
5189
+ * These default to the last INIT_CUM_ARGS value above.
5190
+ */
5191
+
5192
+/* TARGET_FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) .. This hook updates
5193
+ * the summarizer variable pointed to by CUM to advance past an argument in
5194
+ * the argument list.  The values MODE, TYPE, and NAMED describe that
5195
+ * argument.  Once this is done, the variable CUM is suitable for analyzing the
5196
+ * following argument with TARGET_FUNCTION_ARG, etc.  This hook need not do
5197
+ * anything if the argument in question was passed on the stack.  The compiler
5198
+ * knows how to track the amount of stack space used for arguments without
5199
+ * any special help.
5200
+ *
5201
+ * ZipCPU---Here we simply copy from ECO32.
5202
+ */
5203
+#define        TARGET_FUNCTION_ARG_ADVANCE     zip_function_arg_advance
5204
+
5205
+/*
5206 171 dgisselq
+ * TARGET_ARG_OFFSET(MODE, TYPE) ... If defined, a C expression that is the
5207
+ * number of bytes to add to the offset of the argument passed in memory.
5208
+ * This is needed for the SPU, which passes char and short arguments in the
5209
+ * preferred slot that is in the middle of the quad word instead of starting
5210
+ * at the top.
5211
+ *
5212
+ * ZipCPU -- sounds like the default would be (more) appropriate.
5213
+ */
5214
+/*
5215 102 dgisselq
+ * FUNCTION_ARG_PADDING        --- not necessary, since we shouldn't be padding
5216
+ * PAD_VARARGS_DOWN    --- not necessary, since we shouldn't be padding
5217
+ * BLOCK_REG_PADDING
5218
+ * TARGET_FUNCTION_ARG_BOUNDARY
5219
+ * TARGET_FUNCTION_ARG_ROUND_BOUNDARY
5220
+ */
5221
+
5222
+/* FUNCTION_ARG_REGNO_P(REGNO) ... A C expression that is nonzero if REGNO is
5223
+ * the number of a hard register in which function arguments are sometimes
5224
+ * passed.  This does not include implicit arguments such as the static chain
5225
+ * and the structure-value address.  On many machines, no registers can be used
5226
+ * for this purpose since all function arguments are pushed on the stack.
5227
+ */
5228
+#define        FUNCTION_ARG_REGNO_P(r) ((r >= ZIP_FIRST_ARG_REGNO)&&(r<=ZIP_LAST_ARG_REGNO))
5229
+
5230
+/* TARGET_SPLIT_COMPLEX_ARG(TYPE) ... This hook should return true if parameter
5231
+ * of type TYPE are passed as two scalar parameters.  By default, GCC will
5232
+ * attempt to pack complex arguments into the target's word size.  Some ABI's
5233
+ * require complex arguments to be split and treated as their individual
5234
+ * components.
5235
+ *
5236
+ * The default value of this hook is NULL, which is treated as always false,
5237
+ * and which should be good enough for ZipCPU--which can go either way.
5238
+ */
5239
+
5240
+/* TARGET_BUILD_BUILTIN_VA_LIST ... This hook returns a type node for va_list
5241
+ * for the target.  The default version of the hook returns void*.
5242
+ *
5243
+ */
5244
+
5245
+/* TARGET_ENUM_VA_LIST_P
5246
+ */
5247
+
5248
+/* TARGET_FN_ABI_VA_LIST ... This hook returns the va_list type of the calling
5249
+ * convention specified by FN.  The default version of this returns va_list_type_node.
5250
+ */
5251
+
5252
+/* TARGET_FN_ABI_VA_LIST
5253
+ */
5254
+
5255
+/* TARGET_CANONICAL_VA_LIST_TYPE
5256
+ */
5257
+
5258
+/* TARGET_GIMPLIFY_VA_ARG_EXPR
5259
+ */
5260
+
5261
+/* TARGET_VALID_POINTER_MODE(MODE) ... Define this to return nonzero if the
5262
+ * port can handle pointers with machine mode MODE.  The default version of this
5263
+ * hook returns true for both ptr_mode and Pmode.
5264
+ *
5265
+ * ZipCPU---if Pmode is properly defined (above, and I think it is), then the
5266
+ * default behavior is quite appropriate.
5267
+ */
5268
+
5269
+/* TARGET_REF_MAY_ALIAS_ERRNO(REFP) ... Define this to return nonzero if the
5270
+ * memory reference REF may alias with the system C library errno location.
5271
+ * The default version of this hook assumes the system C library errno location
5272
+ * is either a declaration of type int or accessed by dereferencing a pointer
5273
+ * to int.
5274
+ *
5275
+ * ZipCPU --- Default sounds good to me.
5276
+ */
5277
+
5278
+
5279
+/* TARGET_SCALAR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if
5280
+ * the port is prepared to handl instructions involving scalar mode MODE.  For
5281
+ * a scalar mode to be considered supported, all the basic arithmetic and
5282
+ * comparisons must work.
5283
+ *
5284
+ * The default version of this hook returns true for any mode required to
5285
+ * handle the basic C types (as defined by the port).  Included here are the
5286
+ * double-word arithmetic supported by the code in optabs.c.
5287
+ */
5288
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
5289
+#define        TARGET_SCALAR_MODE_SUPPORTED_P  zip_scalar_mode_supported_p
5290
+
5291
+/* TARGET_VECTOR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if the
5292
+ * port is prepared to handle instructions involving vector mode MODE.  At the
5293
+ * very least, it must have move patterns for this mode.
5294
+ *
5295
+ * ZipCPU---does not support any vector modes.
5296
+ */
5297
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
5298
+#define        TARGET_VECTOR_MODE_SUPPORTED_P  hook_bool_mode_false
5299
+
5300
+/* TARGET_ARRAY_MODE_SUPPORTED_P(MODE, NELEMS) ... Return true if GCC should
5301
+ * try to use a scalar mode to store an array of NELEMS elements, given that
5302
+ * each element has mode MODE.  Returning true here overrides the usual MAX_FIXED_MODE limit and allows GCC to use any defined integer mode.
5303
+ *
5304
+ * ZipCPU---Sounds good.
5305
+ */
5306
+// #undef      TARGET_ARRAY_MODE_SUPPORTED_P
5307
+// #define     TARGET_ARRAY_MODE_SUPPORTED_P   zip_array_mode_supported_p
5308
+
5309
+/* TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P(MODE) ... Define this to return
5310
+ * nonzero if libgcc provides support for the floating-point mode MODE, which is
5311
+ * known to pass TARGET_SCALAR_MODE_SUPPORTED_P.  The default version of this
5312
+ * hook returns true for all of SFmode, DFmode, XFmode, and TFmode, if such
5313
+ * modes exist.
5314
+ *
5315
+ * ZipCPU---We only support SFmode and DFmode, but for now only in emulation
5316
+ * (if we can).  Let's allow both of those and see how far we get.
5317
+ */
5318
+#undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
5319
+#define        TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P zip_libgcc_floating_mode_supported_p
5320
+
5321
+/* TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P(MODE) ... Define this to return
5322
+ * nonzero for machine modes for which the port has small register classes.  If
5323
+ * target hook returns nonzero for a given MODE, the compiler will try to
5324
+ * minimize the lifetime of registers in MODE.  The hook may be called with
5325
+ * VOIDmode as an argument.  In this case, the hook is expected to return
5326
+ * nonzero if it returns nonzero for any mode.
5327
+ *
5328
+ * The default version of this hook returns false for any mode.
5329
+ *
5330
+ * ZipCPU---Default sounds good.
5331
+ */
5332
+
5333
+/* 17.09.08 How scalar function values are returned */
5334
+
5335
+/* TARGET_FUNCTION_VALUE
5336
+ */
5337
+
5338
+/* LIBCALL_VALUE
5339
+ */
5340
+
5341
+
5342
+/* 17.09.09 How large values are returned */
5343
+
5344
+/* TARGET_RETURN_IN_MEMORY(TYP,FNTYP) ... This target hook should return a
5345
+ * nonzero value to say to return the function value in memory, just as large
5346
+ * structures are always returned.  Here type will be the data type of the value
5347
+ * and FNTYP will be the type of the function doing the returning, or NULL
5348
+ * for libcalls.
5349
+ *
5350
+ */
5351
+#undef TARGET_RETURN_IN_MEMORY
5352
+#define        TARGET_RETURN_IN_MEMORY zip_return_in_memory
5353
+
5354
+/* DEFAULT_PCC_STRUCT_RETURN
5355
+ * TARGET_STRUCT_VALUE_RTX
5356
+ * PCC_STATIC_STRUCT_RETURN
5357
+ * TARGET_GET_RAW_RESULT_MODE
5358
+ * TARGET_GET_RAW_ARG_MODE
5359
+ */
5360
+
5361
+
5362
+/* 17.09.10 Caller-Saves Register Allocation */
5363
+/* 17.09.11 Function Entry and Exit */
5364 111 dgisselq
+// TARGET_ASM_FUNCTION_PROLOGUE
5365
+// TARGET_ASM_FUNCTION_END_PROLOGUE
5366
+// TARGET_ASM_FUNCCTION_BEGIN_EPILOGUE
5367
+// TARGET_ASM_FUNCTION_EPILOGUE
5368
+/* EXIT_IGNORE_STACK ... Define this macro as a C expression that is nonzero
5369
+ * if the return instruction or the function epilogue ignores the value of the
5370
+ * stack pointer; in other words, if it is safe to delete an instruction to
5371
+ * adjust the stack pointer before a return from the function.
5372
+ *
5373
+ * The default is 0.
5374
+ *
5375
+ * Note that this macro's value is relevant only for functions for which frame
5376
+ * pointers are maintained.  It is never safe to delete a final stack adjustment
5377
+ * in a function that has no frame pointer, and the compiler knows this
5378
+ * regardless of EXIT_IGNORE_STACK.
5379
+ *
5380
+ * ZipCPU -- Thanks to the example of the m68k, and a careful selection of what
5381
+ * our options otherwise could have been, our epilogue code does not use the
5382
+ * stack register at all, but rather starts by moving the frame register into
5383
+ * the stack register.
5384
+ */
5385
+#define EXIT_IGNORE_STACK      1
5386
+// EPILOGUE_USES(regno)
5387
+// EH_USES(regno)
5388
+// TARGET_ASM_OUTPUT_MI_THUNK
5389
+// TARGET_ASM_CAN_OUTPUT_MI_THUNK
5390
+
5391 102 dgisselq
+/* 17.09.12 Generating code for profiling */
5392 111 dgisselq
+// FUNCTION_PROFILER
5393
+// PROFILE_HOOK
5394
+// NO_PROFILE_COUNTERS
5395
+// PROFILE_BEFORE_PROLOGUE
5396
+// TARGET_KEEP_LEAF_WHEN_PROFILED
5397
+
5398 102 dgisselq
+/* 17.09.13 Permitting tail calls*/
5399 111 dgisselq
+
5400
+/* TARGET_FUNCTION_OK_FOR_SIBCALL(DECL,EXP) ... True if it is OK to do sibling
5401
+ * call optimizations for the specified call expression EXP.  DECL will be the
5402
+ * called function, or NULL if this is an indirect call.
5403
+ *
5404
+ * It is not uncommon for limitations of calling conventions to prevent tail
5405
+ * calls to functions outside the current unit of translation, or during PIC
5406
+ * compilation.  The hook is used to enforce these restrictions, as the sibcall
5407
+ * md pattern can not fail, or fall over to a 'normal' call.  The criteria for
5408
+ * successful sibling call optimization may vary greatly between different
5409
+ * architectures.
5410
+ *
5411 191 dgisselq
+ * What's a sibling call?  "Sibling calls or tail calls terminate the function
5412
+ * in a nonn-standard way and thus an edge to the exit must be present.
5413
+ * EDGE_SIBCALL and EDGE_ABNORMAL are set in such case(s).  These edges only
5414
+ * exist in the RTL representation.
5415
+ *
5416
+ * So, basically, a sibling call is a function call at the end of one function.
5417
+ * Rather than setting up a new stack frame, return address, etc, it is
5418
+ * possible to just jump to this new function, leaving the return address for
5419
+ * the prior function as the (now) return address for this one.
5420
+ *
5421
+ * ZipCPU --- These are good things.  We wish to support them.  We will require,
5422
+ * though, that the sibling require no more stack space than the original.
5423
+ * We might go even stricter, requiring that the sibling require no stack space
5424
+ * at all--and only register variables.
5425 111 dgisselq
+ */
5426 191 dgisselq
+#define        TARGET_FUNCTION_OK_FOR_SIBCALL  zip_function_ok_for_sibcall
5427 111 dgisselq
+
5428 191 dgisselq
+/* TARGET_EXTRA_LIVE_ON_ENTRY(REGS) ... Add any hard registers to regs that are
5429
+ * live on entry to the function.  This hook only needs to be defined to provide
5430
+ * registers that cannot be found by examination of FUNTION_ARG_REGNO_P, the
5431
+ * ... and the ...
5432
+ *
5433
+ * ZipCPU -- the default should be good enough for us.
5434
+ */
5435
+/* TARGET_SET_UP_BY_PROLOGUE(CONTAINER) ... This hook should add additional
5436
+ * registers that are computed by the prologue to the hard register set for
5437
+ * shrink-wrapping optimization purposes.
5438
+ *
5439
+ * ??
5440
+ */
5441 111 dgisselq
+
5442 191 dgisselq
+/* TARGET_WARN_FUNC_RETURN(TREE) ... True if a function's return statements
5443
+ * should be checked for matching the function's return type.  This includes
5444
+ * checking for falling off the end of a non-void function.  Return false if
5445
+ * no such check should be made.
5446
+ *
5447
+ * ZipCPU--the default should be good enough for us.
5448
+ */
5449
+
5450 102 dgisselq
+/* 17.09.14 Stack smashing protection */
5451 111 dgisselq
+// TARGET_STACK_PROTECT_GUARD
5452
+// TARGET_STACK_PROTECT_FAIL
5453
+// TARGET_SUPPORTS_SPLIT_STACK
5454
+
5455 102 dgisselq
+/* 17.09.15 Miscellaneous register hooks */
5456
+
5457 111 dgisselq
+// TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
5458
+
5459 102 dgisselq
+/* TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
5460
+ * ZipCPU --- default is good enough for us.
5461
+ */
5462
+
5463
+/* 17.10 Implementing VARARGS MACROS */
5464
+
5465
+/* ...
5466
+ */
5467
+
5468
+/* void TARGET_SETUP_INCOMING_VARARGS(A,M,T,I,S) ... This target hook offers an
5469
+ * alternative to using __builtin_saveregs and defining the hook TARGET_EXPAND..
5470
+ * _BUILTIN_SAVEREGS.  Use it to store the anonymous register arguments into the
5471
+ * stack so that all the arguments appear to have been passed consecutively
5472
+ * on the stack.  Once this is done, you can use the standard implementation
5473
+ * of varargs that works for machines that pass all their arguments on the
5474
+ * stack.
5475
+ */
5476
+// #undef      TARGET_SETUP_INCOMING_VARARGS
5477
+// #define     TARGET_SETUP_INCOMING_VARARGS   zip_setup_incoming_varargs
5478
+
5479
+/* ...
5480
+ */
5481
+
5482
+/* 17.11 Trampolines for Nested Functions */
5483
+
5484
+/* TARGET_ASM_TRAMPOLINE_TEMPLATE ... This hook is called by
5485
+ * assemble_trampoline_template to output, on the stream f, assembler code for
5486
+ * a block of data that contains the constant parts of a trampoline.  This code
5487
+ * should not include a label--the label is taken care of automatically.
5488
+ *
5489
+ * ZipCPU -- looks like we need to do this.
5490
+ */
5491
+#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
5492
+#define        TARGET_ASM_TRAMPOLINE_TEMPLATE  zip_asm_trampoline_template
5493
+
5494
+/* TRAMPOLINE_SECTION ... Return the section into which the trampoline template
5495
+ * is to be placed.  The default value is readonly_data_section.
5496
+ *
5497
+ * ZipCPU--default should be good enough.
5498
+ */
5499
+
5500
+/* TRAMPOLINE_SIZE ... A C expression for the size (in bytes) of the trampoline
5501
+ * as an integer.
5502
+ *
5503
+ * ZipCPU--it's three instructions, or 96 bits.  However, 32-bits is our minimal
5504
+ * addressible unit, so what size do we offer here?  We'll stick with the number
5505
+ * of bytes, but we may need to change this later.
5506
+ *
5507
+ */
5508
+// #warning "May need to redefine trampoline_size in words, not bytes"
5509
+#undef TRAMPOLINE_SIZE
5510
+#define        TRAMPOLINE_SIZE 3
5511
+
5512
+/* TRAMPOLINE_ALIGNMENT ... alignment required for trampolines, in bits.
5513
+ *
5514
+ * Well that's well known in ZipCPU --- 32-bits.
5515
+ */
5516
+#undef TRAMPOLINE_ALIGNMENT
5517
+#define        TRAMPOLINE_ALIGNMENT    32
5518
+
5519
+/* void TARGET_TRAMPOLINE_INIT(RTX,TREE,RTX CH) ... This hook is called to
5520
+ * initialize a trampoline.  m_tramp is an RTX for the memory block for the
5521
+ * trampoline; TREE is the FUNCTION_DECL for the nested fucntion;  CH is an
5522
+ * rtx for the static chain value that should be passed to the function when
5523
+ * it is called.
5524
+ *
5525
+ * ZipCPU ... Can we get by without this?
5526
+ */
5527
+#undef TARGET_TRAMPOLINE_INIT
5528
+#define        TARGET_TRAMPOLINE_INIT  zip_trampoline_init
5529
+
5530
+/* TARGET_TRAMPOLINE_ADJUST_ADDRESS(RTX) ... This hook should perform any
5531
+ * machine-specific adjustment in the address of the trampoline.  Its argument
5532
+ * contains the address of the memory block that was passed to
5533
+ * TARGET_TRAMPOLINE_INIT.  In case the address to be used for a function call
5534
+ * should be different from the address at which the template was stored, the
5535
+ * different address should be returned; otherwise addr should be returned
5536
+ * unchanged.  If the hook is not defined, RTX (addr) will be used for function
5537
+ * calls.
5538
+ *
5539
+ * ZipCPU--works for us!
5540
+ */
5541
+
5542
+/* CLEAR_INSN_CACHE(BEG,END) ... If defined, expands to a C expression clearing
5543
+ * the instruction cache in the specified interval.  The definition of this
5544
+ * macro would typically be a series of asm statements.   Both BEG and END are
5545
+ * pointer expressions.
5546
+ *
5547
+ * ZipCPU --- Ouch!  We have no way to do this (yet)!
5548
+ */
5549
+
5550
+/* TRANSFER_FROM_TRAMPOLINE ... Define this macro is trampolines need a special
5551 111 dgisselq
+ * subroutine to do their work.  The macro should expand to a series of asm
5552 102 dgisselq
+ * statements which will be compiled with GCC.  They go in a library function
5553
+ * named __transfer_from_trampoline.
5554
+ *
5555
+ * We may need to rethink trampolines on ZipCPU.
5556
+ */
5557
+
5558
+
5559
+/* 17.12 Implicit Calls to Library Routines */
5560
+
5561
+/* DECLARE_LIBRARY_RENAMES
5562
+ *
5563
+ * ZipCPU: Don't need it.
5564
+ */
5565
+
5566
+/* TARGET_INIT_LIBFUNCS(VOID) ... This hook should declare additional library
5567
+ * routines or rename existing ones, using the functions set_optab_libfunc and
5568
+ * init_one_libfunc defined in optabs.c.  init_optabs calls this macro after
5569
+ * initializing all the normal library routines.
5570
+ *
5571
+ * Most ports don't need to define this hook, so we won't either.
5572
+ */
5573
+
5574
+/* TARGET_LIBFUNC_GNU_PREFIX ... If false (the default), internal library
5575
+ * routines start with two underscores.  If set to true, these routines start
5576
+ * with __gnu_ instead.
5577
+ *
5578
+ * ZipCPU: No change necessary.
5579
+ */
5580
+
5581
+/* FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE,COMPARISON) ... This macro should return
5582
+ * true if the library routine that implements the floating point comparison
5583
+ * operator comparison in mode mode will return a boolean and false if it will
5584
+ * return a tristate.
5585
+ *
5586
+ * Most ports don't need to define this macro, so Zip CPU won't either.
5587
+ */
5588
+
5589
+/* TARGET_HAS_NO_HW_DIVIDE ... This macro should be defined if the target has no
5590
+ * hardware divide instructions.  If this macro is defined, GCC will use an
5591
+ * algorithm which makes use of simple logical and arithmetic operations for
5592
+ * 64-bit division.  If the macro is not defined, GCC will use an algorithm
5593
+ * which makes use of a 64-bit by 32-bit divide primitive.
5594
+ *
5595
+ * Zip CPU, though, doesn't have the 64-bit by 32-bit divide primitive, thus
5596
+ * we have no HW DIVIDE (for now).
5597
+ */
5598
+#define        TARGET_HAS_NO_HW_DIVIDE
5599
+
5600
+/* TARGET_EDOM ... The value of EDOM on the target machine, as a C integer
5601
+ * expression.  If you don't define this macro, GCC does not attempt to deposit
5602
+ * the value of EDOM into errno directly.  Look in /usr/include/errno.h to find
5603
+ * the value of EDOM on your system.
5604
+ *
5605
+ * EDOM is the error created when a math argument is out of the domain of the
5606
+ * function.
5607
+ *
5608
+ * ZipCPU: Don't need it---I don't think.
5609
+ */
5610
+
5611
+/* GEN_ERRNO_RTX ... Define this macro as a C exrpession to create an rtl
5612
+ * expression that refers to the global "variable" errno.  (On certain
5613
+ * systems, errno may not actually be a variable.)  If you don't define this
5614
+ * macro, a reasonable default is used.
5615
+ *
5616
+ * ZipCPU --- if a reasonable default is used, we'll use that--especially since
5617
+ * I doubt we'll be using errno for a while.
5618
+ */
5619
+
5620
+/* NEXT_OBJC_RUNTIME ... Set this macro to 1 to use the "NeXT" Objective-C
5621
+ * message sending conventions by default.  This calling convention involves
5622
+ * passing the object, the selector and the method arguments all at once to the
5623
+ * method-lookup library function.  This is the usual setting when targetting
5624
+ * Darwin/Mac OS X systems, which have the NeXT runtime installed.
5625
+ *
5626
+ * If the macro is set to 0, ...
5627
+ *
5628
+ * Doesn't look relevant (yet) for the Zip CPU--especially since we don't have
5629
+ * an O/S yet.
5630
+ */
5631
+
5632
+
5633
+
5634
+/* 17.13 Addressing Modes */
5635
+
5636
+/* C expressions that are nonzero if the machine supports pre-increment,
5637
+ * pre-decrement, post-increment, or post-decrement addressing respectively.
5638
+ */
5639
+#define        HAVE_PRE_INCREMENT      (0)
5640
+#define        HAVE_PRE_DECREMENT      (0)
5641
+#define        HAVE_POST_INCREMENT     (0)
5642
+#define        HAVE_POST_DECREMENT     (0)
5643
+
5644
+/* C expression that is nonzero if the machine supports pre- or post- address
5645
+ * side-effect generation involving constants other than the size of the memory
5646
+ * operand.
5647
+ */
5648
+#define        HAVE_PRE_MODIFY_DISP    (0)
5649
+#define        HAVE_POST_MODIFY_DISP   (0)
5650
+
5651
+/* C expression that is non-zero if the machine supports pre- or post-address
5652
+ * side-effect generation involving a register displacement.
5653
+ */
5654
+#define        HAVE_PRE_MODIFY_REG     (0)
5655
+#define        HAVE_POST_MODIFY_REG    (0)
5656
+
5657
+/* CONSTANT_ADDRESS_P(X) ... A C expression that is 1 if the RTX X is a constant
5658
+ * which is a valid address.  On most machines the default definition ... is
5659
+ * acceptable, but a few machines are more restrictive as to which constant
5660
+ * addresses are supported.
5661
+ *
5662
+ * Zip CPU is designed for offset addresses, not constant addresses.  Although
5663
+ * the CPU will support 18-bit signed constant addresses, the assembler and
5664
+ * general programming model do not.  Further, without knowing where the final
5665
+ * address will be located, this is an unusable model.  Therefore we will
5666
+ * define this as not supported.
5667
+ *
5668
+ * In hindsight, this isn't true--labels and symbols are valid addresses, and
5669
+ * they are also constant addresses.  Hence, we leave this at its default.
5670
+ */
5671
+// #undef      CONSTANT_ADDRESS_P
5672
+// #define     CONSTANT_ADDRESS_P(X)   (0)
5673
+
5674 111 dgisselq
+/* CONSTANT_P(X) ... CONSTANT_P, which is defined by target-independent code,
5675
+ * accepts integer values expressions whose values are not explicitly known,
5676
+ * such as symbol_ref, label_ref, and high expressions and const arithmetic
5677
+ * expressions, in addition to const_int and const_double expressions.
5678 102 dgisselq
+ *
5679
+ * Huh???
5680
+ */
5681
+// #define CONSTANT_P(X) ???
5682
+
5683 111 dgisselq
+/* MAX_REGS_PER_ADDRESS ... A number, the maximum number of registers that can
5684
+ * appear in a valid memory address.  Note that it is up to you to specify a
5685
+ * value equal to the maximum number that TARGET_LEGITIMATE_ADDRESS_P would
5686
+ * ever accept.
5687 102 dgisselq
+ */
5688
+#define        MAX_REGS_PER_ADDRESS    1
5689
+
5690
+/* TARGET_LEGITIMATE_ADDRESS_P(MODE,RTX,STRICT) ... A function that returns
5691
+ * whether RTX is a legitimate memory address on the target machine for a
5692
+ * memory operation of mode MODE.
5693
+ */
5694
+#undef TARGET_LEGITIMATE_ADDRESS_P
5695
+#define TARGET_LEGITIMATE_ADDRESS_P    zip_legitimate_address_p
5696
+
5697
+/* TARGET_MEM_CONSTRAINT ... A single character to be used instead of the
5698
+ * default 'm' character for general memory addresses.  This defines the
5699
+ * constraint letter which matches the memory addresses accepted by
5700
+ * TARGET_LEGITIMATE_ADDRESS_P.  Define this macro if you want to support new
5701
+ * address format in your back end without changing the semantics of the 'm'
5702
+ * constraint.  This is necessary in order to preserve functionality of inline
5703
+ * assembly constructs using the 'm' constraint.
5704
+ *
5705
+ * ZipCPU--doesn't look like we need to define this at all.
5706
+ */
5707
+
5708
+/* FIND_BASE_TERM(X) ... A C expression to determine the base term of address
5709
+ * X or to provide a simplified version of X from which alias.c can easily find
5710
+ * the base term.  This macro is used in only two places: find_base_value and
5711
+ * find_base_term in alias.c.
5712
+ *
5713
+ * It is always safe for this macro  to not be defined.  It exists so that
5714
+ * alias analysis can understand machine-dependent addresses.
5715
+ *
5716
+ * ZipCPU: We'll skip this then.
5717
+ */
5718
+
5719
+/* TARGET_LEGITIMIZE_ADDRESS(RTX,OLD,MODE) ... This hook is given an invalid
5720
+ * memory address RTX for an operand of mode MODE and should try to return a
5721
+ * valid memory address.  RTX will always be the result of a call to
5722
+ * break_out_memory_refs, and OLD will be the operand that was given to that
5723
+ * function to produce RTX.
5724
+ *
5725 111 dgisselq
+ * ZipCPU --
5726 102 dgisselq
+ */
5727 111 dgisselq
+#undef TARGET_LEGITIMIZE_ADDRESS
5728
+#define        TARGET_LEGITIMIZE_ADDRESS       zip_legitimize_address
5729 102 dgisselq
+
5730
+/* LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OP,TYPE,IND,WIN) ... A C compound statement
5731
+ * that attempts to replace X, which is an address that needs reloading, with
5732
+ * a valid memory address for an operand of mode MODE.  WIN will be a C
5733
+ * statement label elsewhere in the code.  It is not necessary to define this
5734
+ * macro, but it might be useful for performance reasons.
5735
+ *
5736
+ * ZipCPU: This is worth coming back to, according to the notes page, but it
5737
+ * may also be a difficult macro to use.  Look at other implementations before
5738
+ * we dive into this.
5739
+ */
5740
+// #undef LEGITIMIZE_RELOAD_ADDRESS
5741
+// #define LEGITIMIZE_RELOAD_ADDRESS
5742
+
5743
+/* TARGET_MODE_DEPENDENT_ADDRESS_P(ADDR,SPACE) ... This hook returns true
5744
+ * if memory address addr in address space addrspace can have different meanings
5745
+ * depending on the machine mode of the memory reference it is used for or if
5746
+ * the address is valid for some modes but not others.
5747
+ */
5748
+#undef TARGET_MODE_DEPENDENT_ADDRESS_P
5749
+#define        TARGET_MODE_DEPENDENT_ADDRESS_P         zip_mode_dependent_address_p
5750
+
5751 111 dgisselq
+/* TARGET_LEGITIMATE_CONSTANT_P(MODE,RTX) ... This hook returns true if x is a
5752
+ * legitimate constant for a MODE-mode immediate operand on the target machine.
5753
+ * You can assume the RTX satisfies CONSTANT_P, so you need not check this.
5754
+ *
5755
+ * The default definition returns true.
5756 102 dgisselq
+ */
5757
+
5758
+/* TARGET_DELIGITIMIZE_ADDRESS(RTX)
5759
+ */
5760
+
5761
+/* TARGET_CONST_NOT_OK_FOR_DEBUG_P(RTX) ... This hook should return true if RTX
5762
+ * should not be emitted into debug sections.
5763
+ */
5764
+
5765
+/* TARGET_CANNOT_FORCE_CONST_MEM(MODE,RTX) ... This hook should return true if
5766
+ * RTX is a form that cannot (or should not) be spilled to the constant pool.
5767
+ * MODE is the mode of X.  The default version returns false.
5768
+ */
5769 111 dgisselq
+// #define     TARGET_CANNOT_FORCE_CONST_MEM   hook_bool_mode_rtx_false
5770 102 dgisselq
+
5771
+/* TARGET_USE_BLOCKS_FOR_CONSTANT_P(MODE,RTX) ... This hook should return true
5772
+ * if pool entries for constant RTX can be placed in an object_block structure.
5773
+ * MODE is the mode of X.  The default version returns false for all constants.
5774
+ *
5775
+ *????
5776
+ */
5777
+// #warning "Huh?"
5778
+
5779
+/* TARGET_USE_BLOCKS_FOR_DECL_P(DECL) ... This hook should return true if pool
5780
+ * entries for DECL should be placed in an object_block structure.  The default
5781
+ * version returns true for all DECL's.
5782
+ *
5783
+ * Sounds good.
5784
+ */
5785
+
5786
+/* TARGET_BUILTIN_RECIPROCAL(TREE) ... This hook should return the DECL of a
5787
+ * function that implements the reciprocal of the machine specific builtin
5788
+ * function fndecl, or NULL_TREE if such a function is not available.
5789
+ */
5790
+
5791
+/* TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD(VOID) ... This hook should return the
5792
+ * DECL of a function f that given an address addr as an argument returns a mask
5793
+ * m that can be used to extrract from two vectors the relevant data that
5794
+ * resides in addr in case addr is not properly aligned.
5795
+ *
5796
+ * Zip CPU does not support vectorization.
5797
+ */
5798
+
5799
+/* Other vector, SIMD, and GOACC macros skipped as Zip CPU doesn't support
5800
+ * such data accesses and manipulation.
5801
+ */
5802
+
5803
+/* 17.14 Anchored Addresses */
5804
+
5805
+/* TARGET_MIN_ANCHOR_OFFSET ... The minimum offset that should be applied to
5806
+ * a section anchor.  On most targets, it should be the smallest offset that
5807
+ * can be applied to a base register while still giving a legitimate address for
5808
+ * every mode.  The default value is 0.
5809
+ *
5810
+ * On the Zip CPU, this is the minimum operand B offset to a LOD or STO
5811
+ * operation, which would be a signed 14 bit number.
5812
+ */
5813
+#undef TARGET_MIN_ANCHOR_OFFSET
5814
+#define TARGET_MIN_ANCHOR_OFFSET       zip_min_anchor_offset
5815
+
5816
+/* TARGET_MAX_ANCHOR_OFFSET ... Like TARGET_MIN_ANCHOR_OFFSET, but the maximum
5817
+ * (inclusive) offset that should be applied to section anchors.  The default
5818
+ * value is 0.
5819
+ */
5820
+#undef TARGET_MAX_ANCHOR_OFFSET
5821
+#define TARGET_MAX_ANCHOR_OFFSET       zip_max_anchor_offset
5822
+
5823
+/* TARGET_ASM_OUTPUT_ANCHOR(RTX) ... Write the assembly code to define section
5824
+ * anchor RTX, which is a SYMBOL_REF for which 'SYMBOL_REF_ANCHOR_P(RTL) is
5825
+ * true.  The hook is called with the assembly output position set to the
5826
+ * beginning of SYMBOL_REF_BLOCK(X).
5827
+ *
5828
+ * If ASM_OUTPUT_DEF is available, the hook's default definition uses it to
5829
+ * define the symbol as '. + SYMBOL_REF_BLOCK_OFFSET(RTL)'.  If ASM_OUTPUT_DEF
5830
+ * is not available, the hook's default definition is NULL, which disables the
5831
+ * use of section anchors altogether.
5832
+ *
5833
+ * Section anchors will be very valuable in Zip CPU assembly, therefore we
5834
+ * must define this hook.
5835
+ */
5836
+// #undef      TARGET_ASM_OUTPUT_ANCHOR
5837
+// #define     TARGET_ASM_OUTPUT_ANCHOR        zip_asm_output_anchor
5838
+
5839
+/* TARGET_USE_ANCHORS_FOR_SYMBOL_P(RTX) ... Return true if GCC should attempt
5840
+ * to use anchors to access SYMBOL_REF X.  You can assume SYMBOL_REF_HAS_BLOCK_INFO_P(X) and !SYMBOL_REF_ANCHOR_P(X).
5841
+ *
5842
+ * The default version is correct for most targets, but you might need to intercept this hook to handle things like target specific attributes or target-specific sections.
5843
+ *
5844
+ * Not knowing anything more, we'll leave the default as is for the Zip CPU.
5845
+ */
5846
+// #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
5847
+// #define TARGET_USE_ANCHORS_FOR_SYMBOL_P     zip_use_anchors_for_symbol_p
5848
+
5849
+/* 17.15 Condition Code Status */
5850
+
5851
+/* 17.15.1 Representation of condition codes using (cc0) --- that's us */
5852
+
5853
+/* CC_STATUS_MDEP ... C code for a data type which is used for declaring
5854
+ * the mdep component of cc_status.  It defaults to int.
5855
+ *
5856
+ * ZipCPU---Int is good for us.
5857
+ */
5858
+
5859
+/* CC_STATUS_MDEP_INIT ... A C expression to initialize the mdep field to
5860
+ * "empty".  The default definition does nothing, since most machines don't
5861
+ * use the field anyway.  If you want to use the field, you should probably
5862
+ * define  this macro to initialize it.
5863
+ */
5864
+
5865
+/* NOTICE_UPDATE_CC(EXP, INSN) ... A C compound statement to set the components
5866
+ * of cc_status appropriately for an insn insn whose body is exp.  It is this
5867
+ * macro's responsibility to recognize insns that set the condition code as
5868
+ * a byproduct of other activity as well as those that explicitly set (cc0).
5869
+ *
5870
+ * ZipCPU --- We need this, as not all expressions set (cc0).
5871
+ *
5872 191 dgisselq
+ * In hind sight, this is the *old* and unsupported way of doing business within
5873
+ * GCC.  To switch to the new way, all instruction definitions within our .md
5874
+ * file have been adjusted to either change or clobber the CC register.
5875
+ *
5876 102 dgisselq
+ */
5877 122 dgisselq
+#ifdef HAVE_cc0
5878 191 dgisselq
+// #define     NOTICE_UPDATE_CC(EXP, INSN)     zip_update_cc_notice(EXP, INSN)
5879
+#error "ZipCPU no longer has CC0"
5880 122 dgisselq
+#endif
5881 102 dgisselq
+
5882
+
5883
+/* 17.15.2 Representation of condition codes using registers */
5884
+/* ... which the ZipCPU doesn't have.  The ZipCPU has a CC0 register, and hence
5885
+ * this section isn't supposed to apply.
5886
+ */
5887
+
5888 122 dgisselq
+/* SELECT_CC_MODE(op, x, y) ... On many machines, the condition code may be
5889
+ * produced by other instructions than compares, for example the branch can use
5890
+ * directyl the condition code set by a subtract instruction.  However, on some
5891
+ * machines when the condition code is set this way some bits (such as the
5892
+ * overflow bit) are not set in the same way as a test instruction, so that a
5893
+ * different branch instruction must be used for some conditional branches.
5894
+ * When this happens, use the machinemode of the condition code register to
5895
+ * record different formats of the condition code register.  Modes can also be
5896
+ * used to reccord which compare instruction (e.g. a signed or an unsigned
5897
+ * comparison) produced the condition codes.
5898
+ *
5899
+ * If other modes than CCmode are required, add them to 'machine-modes.def' and
5900
+ * define SELECT_CC_MODE to choose a mode given an operand of a compare.  This
5901
+ * is needed because the modes have to be chosen not only during RTL generation
5902
+ * but also, for example, by instruction combination.  The result of
5903
+ * SELECT_CC_MODE should be consistent with the mode used in the patterns; ...
5904
+ *
5905
+ * ZipCPU ... We have only one CC Mode, so we'll use the CCmode defined in
5906
+ * machine-modes.def and should be fine with it.  Hence, this doesn't need
5907
+ * to be defined.
5908 102 dgisselq
+ */
5909
+
5910
+/* TARGET_CANONICALIZE_COMPARISON(int,rtx *, rtx *, bool) ... On some machines
5911
+ * (such as the ZipCPU) not all possible comparisons are defined, but you can
5912
+ * convert an invalid comparison into a valid one.  For example, the Alpha
5913
+ * does not have a GT comparison, but you can use an LT comparison instead and
5914
+ * swap the order of the operands.
5915
+ *
5916
+ * On such machines, implement this hook to do any required conversions:  code
5917
+ * is the initial comparison code and op0 and op1 are the left and right
5918
+ * operands of the comparison, respectively.  If op0_preserve_value is true the
5919
+ * implementation is not allowed to change the value of op0 since the value
5920
+ * might be used in RTXs which aren't comparisons.  E.g. the implementation is
5921
+ * not allowed to swap operands in that case.
5922
+ *
5923
+ * GCC will not assume that the comparison resulting from this macro is valid
5924
+ * but will see if the resulting insn matches a pattern in the 'md' file.
5925
+ *
5926
+ * You need not implement this hook if it would never change the comparison
5927
+ * code or operands.
5928
+ *
5929
+ * In the case of the ZipCPU, the ZipCPU only keeps track of 8 possible
5930
+ * comparisons, and bastardizing other comparisons into those 8 is extremely
5931
+ * painful.  Therefore, we *need* this capability to make certain we can use
5932
+ * our comparisons successfully.
5933
+ *
5934
+ * The only problem is ... this hook appears to only be called on non-CC0
5935
+ * machines.  Hence, defining it hasn't done anything for us.
5936
+ */
5937 122 dgisselq
+#define        TARGET_CANONICALIZE_COMPARISON  zip_canonicalize_comparison
5938 102 dgisselq
+
5939 122 dgisselq
+/* REVERSIBLE_CC_MODE(MODE) ... A C expression whose value is one if it is
5940
+ * always safe to reverse a comparison whose mode is MODE.  If SELECT_CC_MODE
5941
+ * can ever return MODE for a floating-point inequality comparison, than
5942
+ * REVERSIBLE_CC_MODE(MODE) must be zero.
5943
+ *
5944
+ * You need not define this macro if it would always return zero or if the
5945
+ * floating-point format is anything other than IEEE_FLOAT_FORMAT.  For example,
5946
+ * here ...
5947
+ *
5948
+ * ZipCPU -- We'll always return zero, so this need not be defined.
5949
+ */
5950
+
5951
+/* REVERSE_CONDITION(CODE,MODE) ... A C expression whose value is reversed
5952
+ * condition code of thecode for comparison done in CC_MODE MODE.  This macro
5953
+ * is used only in case REVERSIBLE_CC_MODE(MODE) is nonzero. ...
5954
+ *
5955
+ * ZipCPU ... Since REVERSIBLE_CC_MODE(MODE) will always be zero, we'll leave
5956
+ * this undefined.
5957
+ */
5958
+
5959
+/* bool TARGET_FIXED_CONDITION_CODE_REGS(int *, int *) ... On targets which do
5960
+ * not use (cc0), and which use a hard register rather than a pseudo-register
5961
+ * to hold condition codes, the regular CSE passes are often not able to
5962
+ * identify cases in which the hard register is set to a common value.  Use this
5963
+ * hook to enable a small pass which optimizes such cases.  This hook should
5964
+ * return true to enable this pass, and it should set the integers to which its
5965
+ * arguments point to the hard register numbers used for condition codes.  When
5966
+ * there is only one such register, as is true on most systems, the integer
5967
+ * pointed to by p2 should  be set to INVALID_REGNUM.
5968
+ *
5969
+ * The default version of this hook returns false.
5970
+ *
5971
+ * ZipCPU --- I like the idea of enabling optimizations.  Let's return
5972
+ * something other than false.
5973
+ */
5974
+#define        TARGET_FIXED_CONDITION_CODE_REGS        zip_fixed_condition_code_regs
5975
+
5976
+/* machine_mode TARGET_CC_MODES_COMPATIBLE(M1,M2) .. On targets which use
5977
+ * multiple condition code modes in class MODE_CC, it is sometimes the case
5978
+ * that a comparison can be validly done in more than one mode.  On such a
5979
+ * system, define this target hook to take two mode arguments and to return a
5980
+ * mode in which both comparisons may be validly done.  If there is no such
5981
+ * mode, return VOIDmode.
5982
+ *
5983
+ * The default version of this hook checks whether the modes are the same.  If
5984
+ * they are, it returns that mode.  If they are different, it returns VOIDmode.
5985
+ *
5986
+ * ZipCPU--Given that we only have the one CCmode, the default definition works
5987
+ * well enough for us.
5988
+ */
5989
+
5990
+/* unsigned int TARGET_FLAGS_REGNUM ... If the target has a dedicated flags
5991
+ * register, and it needs to use the post-reload comparison elimination pass,
5992
+ * then this value should be set appropriately.
5993
+ *
5994
+ * ZipCPU---Looks like we can set this easily enough without any problems.
5995
+ */
5996
+#undef TARGET_FLAGS_REGNUM
5997
+#define        TARGET_FLAGS_REGNUM     zip_CC
5998
+
5999 102 dgisselq
+/* 17.16 Relative costs of operations */
6000
+
6001
+
6002
+// #define     REGISTER_MOVE_COST(MODE,FROM,TO)        ((MODE==DImode)||(MODE==DFmode))?4:2
6003
+// #define     TARGET_REGISTER_MOVE_COST
6004
+// #define     MEMORY_MOVE_COST(MODE, CLASS, IN)       ((MODE==DImode)||(MODE==DFmode))?8:7
6005
+/* TARGET_REGISTER_MOVE_COST(M,FRM,TO) ... This target hook should return the
6006
+ * cost of moving data of mode M from a register in class FRM to one in class
6007
+ * TO.  The classes are expressed using the enumeration values such as
6008
+ * GENERAL_REGS.  A value of 2 is the default; other values are interpreted
6009
+ * relative to that.
6010
+ *
6011
+ * It is not required that the cost always equal 2 when FROM is the same as TO;
6012
+ * on some machines it is expensive to move between registers if they are not
6013
+ * general registers.
6014
+ *
6015
+ * If reload sees ...
6016
+ *
6017
+ * ZipCPU ... We can leave this at its default value of 2.
6018
+ */
6019
+
6020
+/* TARGET_MEMORY_MOVE_COST(MOD,CL,IN) ... This target hook should return the
6021
+ * cost of moving data of mode MOD between a register of class CL and memory.
6022
+ * IN is false if the value is to be written to memory, true if it is to be
6023
+ * read in.  This cost is relative to those in TARGET_REGISTER_MOVE_COST.
6024
+ * If moving between registers and memory is more expensive that between two
6025
+ * registers, you should add this target hook to express the relative cost.
6026
+ *
6027
+ * If you do not add this target hook, GCC uses a default cost of 4 plus the
6028
+ * cost of copying via a secondary reload register, if one is needed.  If your
6029
+ * machine requires a secondary reload register to copy between memory and a
6030
+ * register of CL but the reload mechanism is more complex than copying via
6031
+ * an intermediate, use this target hook to reflect the actual cost of the
6032
+ * move.
6033
+ *
6034
+ * ZipCPU --- Memory moves are more expensive than twice the cost of register
6035
+ * moves, so let's make certain this is defined.
6036
+ */
6037
+#define        TARGET_MEMORY_MOVE_COST zip_memory_move_cost
6038
+
6039
+// #warning "This needs to be double checked, and annotated"
6040 111 dgisselq
+#define        BRANCH_COST(SPEED,PREDICTABLE)          ((PREDICTABLE)?2:5)
6041 102 dgisselq
+
6042
+/* Define this macro as a C expression which is nonzero if accessing less than
6043
+ * a word of memory (i.e. a 'char' or a 'short') is no faster than accessing
6044
+ * a word of memory.
6045
+ */
6046
+#define        SLOW_BYTE_ACCESS        1
6047
+
6048
+/* MOVE_RATIO(SPD) ... The threshold of number of scalar memory-to-memory move
6049
+ * instructions, below which a sequence of instructions should be generated
6050
+ * instead of a string move instruction or a library call.  Increasing the
6051
+ * value will always make code faster, but eventually incurs high cost in
6052
+ * increased code size.
6053
+ */
6054
+#define        MOVE_RATIO(SPD) 5
6055
+
6056
+/* TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(SZ,ALGN,OP,SPD) ...
6057
+ */
6058
+// #undef      TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(S,A,OP,SPD)
6059
+// #define     TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(S,A,OP,SPD)// needs hook
6060
+
6061
+/* CLEAR_RATIO(SPD) ... The threshold number of scalar move instructions, below
6062
+ * which a sequence of instructions should be generated to clear memory instead
6063
+ * of a string clear instruction or a library call.  Increasing the value will
6064
+ * always make the code faster, but eventually incurs high cost in increased
6065
+ * code size.
6066
+ */
6067
+#define        CLEAR_RATIO(SPD)        MOVE_RATIO(SPD)
6068
+
6069
+/* NO_FUNCTION_CSE ... Define this macro to be true if it is as good or better
6070
+ * to call a constant function address than to call an address kept in a
6071
+ * register.
6072
+ *
6073
+ * On the Zip CPU, constant function addresses--especially relative ones,
6074
+ * can be optimized into a single cycle delay.  Register jumps will always
6075
+ * stall the whole (5-stage) pipeline.
6076
+ */
6077
+#define        NO_FUNCTION_CSE
6078
+
6079 111 dgisselq
+/* TARGET_RTX_COSTS(X,CODE,OUTER,OPNO,TOTAL,SPD) ... This target hook describes
6080
+ * the relative costs of RTL expressions.
6081
+ *
6082
+ * The cost may depend on the precise form of the expression, which is avaialble
6083
+ * for examination in X, and the fact that X appears as operand OPNO of an
6084
+ * expression with rtx code OUTER.  That is, the hook can assume that there is
6085
+ * some RTX Y such that GET_CODE(Y)==OUTER and such that either (a) XEXP(Y,OPNO)
6086
+ * == X or (b) XVEC(Y,OPNO) contains X.
6087
+ *
6088
+ * ...
6089
+ * The hook returns true when all subexpressions of x have been processed and
6090
+ * false when rtx_cost should recurse.
6091 102 dgisselq
+ */
6092 111 dgisselq
+
6093 102 dgisselq
+/* TARGET_ADDRESS_COST(ADDR,MODE,AS, SPD) ... This hook computes the cost of an
6094
+ * addressing mode that contains ADDR.  If not defined, the cost is computed
6095
+ * from the ADDR expression and the TARGET_RTX_COST hook.  In cases where more
6096
+ * than one form of an address is known, the form with the lowest cost will be
6097
+ * used.  If multiple forms have the same, lowest, cost, the one that is the
6098
+ * most complex will be used.
6099
+ *
6100
+ * ZipCPU really has only one address cost, the only type of address it
6101
+ * supports.  Sure, index addressing would cost us more, but we don't support
6102
+ * that so ... I think we're okay defining this as a constant.  Indeed, the
6103
+ * docs state that, "On RISC amchines, all instructions normally have the same
6104
+ * length and execution time.  Hence all addresses will have equal costs."
6105
+ */
6106
+#undef TARGET_ADDRESS_COST
6107
+#define        TARGET_ADDRESS_COST     zip_address_cost
6108
+
6109
+
6110
+/* TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P ... This predicate controls the use
6111
+ * of the eager delay slot filler to disallow speculatively executed
6112
+ * instructions being placed in delay slots.  Targets such as certain MIPS
6113
+ * architectures posess both branches with and without delay slots.  As the
6114
+ * eager delay slot filler can decrease performance, disabling it is beneficial
6115
+ * when ordinary branches are available.  Use of delay slot branches filled
6116
+ * using basic filler is often still desirable as the delay slot can hide a
6117
+ * pipeline bubble.
6118
+ */
6119
+// How should Zip CPU define this--we have no delay slots.
6120
+
6121
+
6122
+/* 17.17 Instruction Scheduler */
6123
+
6124
+#define        TARGET_SCHED_ISSUE_RATE zip_sched_issue_rate
6125
+
6126
+/* 17.18 Dividing the Output into Sections */
6127
+
6128
+/* Switch to the text or data segment. */
6129
+#define        TEXT_SECTION_ASM_OP     "\t.text"
6130
+#define        DATA_SECTION_ASM_OP     "\t.data"
6131
+
6132
+// #undef      TARGET_LIBGCC_SDATA_SECTION
6133
+// #define     TARGET_LIBGCC_SDATA_SECTION     ".sdata"
6134
+
6135
+
6136
+/* 17.19 Position Independent Code */
6137
+
6138
+#define        PIC_OFFSET_TABLE_REGNUM                 zip_GOT
6139
+#define        PIC_OFFSET_TABLE_REG_CALL_CLOBBERED     0
6140
+// #define LEGITIMATE_PIC_OPERAND_P(X) should evaluate to X(GOT) only
6141
+
6142
+/* 17.20 Defining the Output Assembler Language */
6143
+
6144 146 dgisselq
+/* 17.20.4 Output of Data */
6145
+
6146
+#undef TARGET_ASM_ALIGNED_HI_OP
6147
+#undef TARGET_ASM_ALIGNED_SI_OP
6148
+#define        TARGET_ASM_UNALIGNED_HI_OP      "\t.byte\t"
6149
+#define        TARGET_ASM_UNALIGNED_SI_OP      "\t.byte\t"
6150
+/* These hooks (above) specify assembly directives for creating certain kinds
6151
+ * of integer objects.  The TARGET_ASM_BYTE_OP directive creates a byte-sized
6152
+ * object.  The TARGET_ASMALIGNED_HI_OP one creates an aligned two-byte object
6153
+ * and so on.  Any of the hookd may be NULL, indicating that no suitable
6154
+ * directive is available.
6155
+ *
6156
+ * The compiler will print these strings at the start of a new line, followed
6157
+ * immediately by the object's initial value.  In most cases, the string should
6158
+ * contain a tab, a pseudo op, and then another tab.
6159
+ */
6160
+
6161 102 dgisselq
+/* 17.20.4 Output and Generation of Labels */
6162
+
6163
+/* ASM_OUTPUT_LABEL
6164
+ * ... A default definition of this macro is provided which is correct for
6165
+ * most systems.
6166
+ */
6167
+
6168
+/* ASM_OUTPUT_FUNCTION_LABEL
6169
+ * ... if not defined, then the function name is defined in the usual manner
6170
+ * as a label.
6171
+ */
6172
+
6173
+/* ASM_OUTPUT_INTERNAL_LABEL ... Identical to ASM_OUTPUT_LABEL, except that name
6174
+ * is known to refer to a compiler-generated label.  The default definition
6175
+ * uses assemble_name_raw, which is like assemble_name except that it is more
6176
+ * efficient.
6177
+ */
6178
+
6179
+/* SIZE_ASM_OP ... A C string containing the appropriate assembler directive
6180
+ * to specify the size of a symbol, without any arguments.  ON systems that
6181
+ * use ELF, the dfault is "\t.size\t"; on other systems, the default is not to
6182
+ * define this macro.
6183
+ *
6184
+ * Define this amcro only if it is correct to use the default definitions of
6185
+ * ASM_OUTPUT_SIZE_DERECTIVE and ASM_OUTPUT_MEASURED_SIZE for your system.
6186
+ * If you need your own custom definitions of those macros, or if you do not
6187
+ * need explicit symbol sizes at all, do not define this macro.
6188
+ */
6189
+
6190
+/* ASM_OUTPUT_SIZE_DIRECTIVE
6191
+ * ASM_OUTPUT_MEASURED_SIZE
6192
+ */
6193
+
6194
+/* NO_DOLLAR_IN_LABEL ... Define this macro if the assembler does not accept
6195
+ * the character '$' in label names.  By default constructors and destructors
6196
+ * in G++ have "$" in the identifiers.  If this label is defined, '.' is
6197
+ * used instead.
6198
+ */
6199
+
6200
+/* NO_DOT_IN_LABEL ... Define this macro if the assembler does not accept the
6201
+ * character '.' in label names.  By default constructors and destructors in
6202
+ * G++ have names that use '.'.  If this macro is defined, these names are
6203
+ * rewritten to avoid '.'.
6204
+ */
6205
+
6206
+/* TYPE_ASM_OP ... A C string containing the appropriate assembler directive to
6207
+ * specify the type of a symbol, without any arguments.  On systems that use
6208
+ * ELF the default in config/elfos.h is "\t.type\t"; on other systems, the default is not to define this macro.
6209
+ *
6210
+ * Define this macro only if it is correct to use the default definition of
6211
+ * ASM_OUTPUT_TYPE_DIRECTIVE forr your system.  If you need your own custom
6212
+ * definition of this macr, or if you do not need explicit symbol types at all,
6213
+ * do not define this macro.
6214
+ */
6215
+
6216
+/* TYPE OPERAND_FMD ... A
6217
+ */
6218
+
6219
+/* ASM_OUTPUT_TYPE_DIRECTIVE
6220
+ */
6221
+
6222
+/* ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) ...
6223
+ * if this macro is not defined, then the function name is defined in the usual
6224
+ * manner as a label (by means of ASM_OUTPUT_FUNCTION_LABEL).
6225
+ */
6226
+
6227
+/* ASM_DECLARE_FUNCTION_SIZE
6228
+ * ASM_DECLARE_COLD_FUNCTION_NAME
6229
+ * ASM_DECLARE_COLD_FUNCTION_SIZE
6230
+ * ASM_DECLARE_OBJECT_NAME
6231
+ * TARGET_ASM_DECLARE_CONSTANT_NAME
6232
+ */
6233
+/* ASM_DECLARE_REGISTER_GLOBAL(STREAM, DECL, REGNO, NAME) ... A C statement
6234
+ * (sans semicolon) to output to the stdio stream STREAM any text necessary for
6235
+ * claiming a register REGNO for a global variable DECL with name NAME.
6236
+ *
6237
+ * If you don't defin this macro, that is equivalent to dfining it to do
6238
+ * nothing.
6239
+ */
6240
+
6241
+/* ASM_FINISH_DECLARE_OBJECT
6242
+ * TARGET_ASM_GLOBALIZE_LABEL
6243
+ * TARGET_ASM_GLOBALIZE_DECL_NAME
6244
+ * TARGET_ASM_ASSEMBLE_UNDEFINED_DECL
6245
+ * ASM_WEAKEN_LABEL
6246
+ * ASM_WEAKEN_DECL
6247
+ * ASM_OUTPUT_WEAKREF
6248
+ * SUPPORTS_WEAK
6249
+ * TARGET_SUPPORTS_WEAK
6250
+ * MAKE_DECL_ONE_ONLY
6251
+ * SUPPORTS_ONE_ONLY
6252
+ * TARGTE_ASM_ASSEMBLE_VISIBILITY
6253
+ * TARGET_WEAK_NOT_IN_ARCHIVE_TOC
6254
+ * ASM_OUTPUT_EXTERNAL
6255
+ * TARGET_ASM_EXTERNAL_LIBCALL
6256
+ * TARGET_ASM_MARK_DECLPRESERVED
6257
+ * ASM_OUTPUT_LABELREF
6258
+ * TARGET_MANGLE_ASSEMBLER_NAME
6259
+ * ASM_OUTPUT_SYMBOL_REF
6260
+ * ASM_OUTPUT_LABEL_REF
6261
+ * TARGET_ASM_INTERNAL_LABEL
6262
+ * ASM_OUTPUT_DEBUG_LABEL
6263
+ * ASM_GENERATE_INTERNAL_LABEL
6264
+ * ASM_FORMAT_PRIVATE_NAME
6265
+ */
6266
+
6267
+/* ASM_OUTPUT_DEF ... A C statement to output to the stdio stream STREAM
6268
+ * assembler code which defines (equates) the symbol NAME to have the value
6269
+ * VALUE.
6270
+ *
6271
+ * ZipCPU---So many other things that we need depend upon this, that we need
6272
+ * to implement a non-default version.
6273
+ */
6274
+#define        ASM_OUTPUT_DEF  zip_asm_output_def
6275
+
6276
+/* ASM_OUTPUT_DEF_FROM_DECLS
6277
+ * TARGET_DEFERRED_OUTPUT_DEFS
6278
+ * ASM_OUTPUT_WEAK_ALIAS
6279
+ * OBJ_GEN_METHOD_LABEL
6280
+ */
6281
+
6282
+
6283
+/* 17.20.7 Output of Assembler Instructions */
6284
+
6285 171 dgisselq
+#define        REGISTER_NAMES {                                        \
6286
+       "R0", "R1", "R2",  "R3",  "R4",  "R5", "R6", "R7",      \
6287
+       "R8", "R9", "R10", "R11", "R12", "SP", "CC", "PC",      \
6288
+       "uR0","uR1","uR2", "uR3", "uR4", "uR5","uR6","uR7",     \
6289
+       "uR8","uR9","uR10","uR11","uR12","uSP","uCC","uPC",     \
6290
+       "PSEUDO-AP" }
6291 102 dgisselq
+
6292
+/* REGISTER_PREFIX     (Undefined by default)
6293
+ * LOCAL_LABEL_PREFIX  (Undefined by default)
6294
+ * USER_LABEL_PREFIX   defaults to "*"
6295
+ * IMMEDIATE_PREFIX    (Undefined by default)
6296
+ *
6297
+ * If defined, C string expressions to be used for the '%R', '%L', '%U', and
6298
+ * '%I' options of asm_fprintf (see 'final.c').  These are useful when a single
6299
+ * 'md' file must support multiple assembler formats.  In that case, the various
6300
+ * 'tm.h' files can define these macros differently.
6301
+ */
6302
+// #define     USER_LABEL_PREFIX       "*"
6303
+
6304
+/* Defining memory operand address formats is in this section. */
6305
+
6306
+/* 17.20.10 Assembler Commands for Alignment */
6307
+
6308
+/* JUMP_ALIGN(label) ... The alignment (log base 2) to put in front of label,
6309
+ * which is a common destination of jumps and has no fallthru incoming
6310
+ * edge.  This macro need not be defined if you don't want any special alignment
6311
+ * to be done at such a time.  Most machine descriptions do not currently define
6312
+ * this macro.
6313
+ *
6314
+ * ZipCPU---The assembler should automatically deal with label alignment, so
6315
+ * let's not do anything about it here.
6316
+ */
6317
+
6318
+/* TARGET_ASM_JUMP_ALIGN_MAX_SKIP
6319
+ */
6320
+
6321
+/* LABEL_ALIGN_AFTER_BARRIER
6322
+ * TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
6323
+ */
6324
+
6325
+/* LOOP_ALIGN(label)
6326
+ * TARGET_ASM_LOOP_ALIGN_MAX_SKIP
6327
+ * LABEL_ALIGN
6328
+ * TARGET_ASM_LABEL_ALIGN_MAX_SKIP
6329
+ */
6330
+
6331
+/* ASM_OUTPUT_SKIP(STREAM, NBYTES) A C statement to output to the stdio
6332
+ * stream an assembler instruction to advance the location counter by nbytes
6333
+ * bytes.
6334
+ */
6335
+
6336
+/* TARGET_ASM_LABEL_ALIGN */
6337
+/* Assembler Commands for Alignment */
6338
+#define        ASM_OUTPUT_ALIGN(STREAM,POWER)  \
6339 127 dgisselq
+       { int pwr = POWER; fprintf(STREAM, "\t.p2align %d\n", (pwr<2)?2:pwr); }
6340 102 dgisselq
+
6341
+
6342
+
6343
+/* 17.21 Controlling Debugging Information Format */
6344
+/* 17.22 Cross Compilation and Floating Point */
6345 111 dgisselq
+
6346
+// REAL_VALUE_TYPE
6347
+// REAL_VALUES_EQUAL
6348
+// REAL_VALUES_LESS ... Tess whether x is less than y
6349
+/* REAL_VALUE_FIX ... Truncates x to an unsigned integer, rouding toward zero.
6350
+ * If x is negative, returns zero.
6351
+ */
6352
+// REAL_VALUE_ATOF
6353
+// REAL_VALUE_NEGATIVE
6354
+// REAL_VALUE_ISINF
6355
+// REAL_VALUE_ISNAN
6356
+/* REAL_ARITHMETIC(OUT,CODE,X,Y) ... (Macro) Calculates an arithmetic operation
6357
+ * on two floating point values X and Y, storing the result in OUT (which must
6358
+ * be a variable).
6359
+ *
6360
+ * The operation to be performed is specified by CODE.  Only the following
6361
+ * codes are supported: PLUS_EXPR, MINUS_EXPR, MULT_EXPR, RDIV_EXPR, MAX_EXPR,
6362
+ * MIN_EXPR.
6363
+ *
6364
+ * If REAL_ARITHMETIC is asked to evaluate division by zero and the target's
6365
+ * floating point format cannot represent infinity, it will call abort().
6366
+ * Callers shoudl check for this situation first, using MODE_HAS_INFINITIES.
6367
+ */
6368
+/* REAL_VALUE_NEGATE(X) ... [Macro] Returns the negative of the floating point
6369
+ * value X.
6370
+ */
6371
+/* REAL_VALUE_ABS(X) ... [Macro] Returns the absolute value of X.
6372
+ */
6373 102 dgisselq
+/* 17.23 Mode switching instructions */
6374
+/* 17.24 Defining target-specific uses of __attribute__ */
6375
+#undef TARGET_OPTION_OVERRIDE
6376
+#define        TARGET_OPTION_OVERRIDE  zip_override_options
6377
+
6378
+/* 17.25 Emulating TLS */
6379
+/* 17.26 Defining coprocessor specifics for MIPS targets*/
6380
+
6381
+ // ZipCPU isn't MIPS.
6382
+
6383
+/* 17.27 Parameters for Precompiled Header Validity Checking */
6384
+/* 17.28 C++ ABI parameters */
6385
+/* 17.29 Adding support for named address spaces */
6386
+/* 17.30 Miscellaneous Parameters */
6387
+
6388
+/* HAS_LONG_COND_BRANCH ... Define this boolean macro to indicate whether or
6389
+ * not your architecture has conditional branches that can span all of memory.
6390
+ * It is used in conjunction with an optimization that partitions hot and
6391
+ * cold basic blocks into separate sections of the executable.  If this macro
6392
+ * is set to false, gcc will convert any conditional branches that attempt to
6393
+ * cross between sections into unconditional branches or indirect jumps.
6394
+ *
6395
+ * ZipCPU --- The assembler renders long unconditional branch code without
6396
+ * problems, so we can pretend that such long branches exist.
6397
+ */
6398
+#define        HAS_LONG_COND_BRANCH true
6399
+
6400
+/* HAS_LONG_UNCOND_BRANCH ... Define this boolean macro to indicate whether
6401
+ * or not your architecture has unconditional branches that can span all of
6402
+ * memory.  (ZipCPU does ... via the LOD (PC),PC instruction.)  It is used in
6403
+ * conjunction with an optimization that partitions hot and cold basic blocks
6404
+ * into separate sections of the executable.  If this macro is set to false,
6405
+ * gcc will convert any unconditional branches that attempt to cross between
6406
+ * sections into indirect jumps.
6407
+ *
6408
+ * ZipCPU has the LOD (PC),PC instruction which can be used to implement a long
6409
+ * jump.
6410
+ */
6411
+#define        HAS_LONG_UNCOND_BRANCH  true
6412
+
6413
+/* CASE_VECTOR_MODE ... An alias for a machine mode name.  This is the machine
6414
+ * mode that eleemnts of a jump-table should have.
6415
+ *
6416
+ */
6417
+#define        CASE_VECTOR_MODE        SImode
6418
+
6419
+/* CASE_VECTOR_SHORTEN_MODE(MIN,MAX,BODY) ... Optional: return the preferred
6420
+ * mode for an addr_diff_vec when the minimum and maximum offset are known.
6421
+ * If you define this, it enables extra code in branch shortening to deal with
6422
+ * addr_diff_vec.  To make this work, you also have to define INSN_ALIGN and
6423
+ * make the alignment for addr_diff_vec explicit.  The body argument is provided so that the offset_unsigned and scale flags can be updated.
6424
+ *
6425
+ * ZipCPU---No advantage here.
6426
+ */
6427
+
6428
+/* CASE_VECTOR_PC_RELATIVE ... Define this exrpession to indicate when
6429
+ * jump-tables should contain relative addresses.  You need not define this
6430
+ * macro if jump-tables never contain relative addresses, or jump-tables
6431
+ * should contain relative addresses only when -fPIC or -FPIC is in effect.
6432
+ *
6433
+ * ZipCPU---No advantage in PC-Relative jump tables--except in PIC relative
6434
+ * code.
6435
+ */
6436
+
6437
+/* TARGET_CASE_VALUES_THRESHOLD(VOID) ... This function returns the smallest
6438
+ * number of different values for which it is best to use a jump-table instead
6439
+ * of a tree of conditional branches.  The default is four for machines with a
6440
+ * casesi instruction and five otherwise.  This is best for most machines.
6441
+ *
6442
+ * ZipCPU---Leave at the default.
6443
+ */
6444
+
6445
+/* WORD_REGISTER_OPERATIONS ... Define this macro to 1 if operations between
6446
+ * registers with integral mode smaller than a word are always performed on the
6447
+ * entire register.  Most RISC machines have this property and most CISC
6448
+ * machines do not.
6449
+ *
6450
+ * ZipCPU---We have the property, 'cause we're fairly risk.
6451
+ */
6452
+#undef WORD_REGISTER_OPERATIONS
6453
+#define        WORD_REGISTER_OPERATIONS        1
6454
+
6455
+/* LOAD_EXTEND_OP(MEMODE) ... Define this macro to be a C expression indicating
6456
+ * when insns that read memory in MEMMODE, an integral mode narrower than a
6457
+ * word, set the bits outside of MEMMODE to be either the sign extension or
6458
+ * zero-extension of the data read.  Return SIGN_EXTEND for values of MEMMODE
6459
+ * for which the insn sign-extends, ZERO_EXTEND for which it zero-extends, and
6460
+ * UNKNOWN for other modes.
6461
+ *
6462
+ * Do not define this macro if it would always return UNKNOWN.
6463
+ *
6464
+ * ZipCPU---This should be irrelevant, so we leave it undefined.
6465
+ */
6466
+#undef LOAD_EXTEND_OP
6467
+#define        LOAD_EXTEND_OP(MEM)     SIGN_EXTEND
6468
+
6469
+/* SHORT_IMMEDIATES_SIGN_EXTEND ... Define this macro to 1 if loading short immediate values into registers sign extends.
6470
+ *
6471
+ * ZipCPU---All immediates are sign extended, so yes.
6472
+ */
6473
+#undef SHORT_IMMEDIATES_SIGN_EXTEND
6474
+#define        SHORT_IMMEDIATES_SIGN_EXTEND    1
6475
+
6476
+/* TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
6477
+ */
6478
+
6479
+/* MOVE_MAX ... The maximum number of bytes that a single instruction can move
6480
+ * quickly between memory and registers or between two memory locations.
6481
+ *
6482
+ * ZipCPU --- Although we can move 32-bits at a time, and most people would call
6483
+ * this 4-bytes, the compiler defines a byte as the minimum addressable unit.
6484
+ * Therefore, this is defined to be one.
6485
+ */
6486
+#define        MOVE_MAX        1
6487
+
6488
+/* MAX_MOVE_MAX ... The maximum number of bytes that a single instruction can
6489
+ * move quickly between memory and registers or between two memory ...
6490
+ *
6491
+ * ZipCPU --- this sounds just the same as MOVE_MAX, which is the default
6492
+ * definition of this.
6493
+ */
6494
+
6495
+/* SHIFT_COUNT_TRUNCATED ... A C expression that is nonzero if on this machine
6496
+ * the number of bits actually used for the count of a shift operation is equal
6497
+ * to the number of bits needed to represent the size of the object being
6498
+ * shifted.
6499
+ *
6500
+ * You need not define this macro if it would have the value of zero.
6501
+ *
6502
+ * ZipCPU---A shift of 33 (or more) in either direction will wipe out the
6503
+ * value in the register, therefore this value should be zero, the default.
6504
+ */
6505
+
6506
+/* TARGET_SHIFT_TRUNCATION_MASK(MODE) ... This function describes how the
6507
+ * standard shift patterns for MODE deal with shifts by negative amounts or by
6508
+ * more than the width of the mode.
6509
+ *
6510
+ * ZipCPU---The default is zero, since we didn't define SHIFT_COUNT_TRUNCATED.
6511
+ * This is the case for the ZipCPU as well.
6512
+ */
6513
+
6514
+/* TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) ... A C expression which is nonzero
6515
+ * if on this machine it is safe to "convert" an integer of INPREC bits to one
6516
+ * of OUTPREC bits (where OUTPREC is smaller than INPREC) by merely operating on
6517
+ * it as if it had OUTPREC bist.  On many machines, this expression can be 1.
6518
+ *
6519
+ * ZiPCPU ... If both values are 32-bit, what conversion takes place?  If one is
6520
+ * 64-bit and the other 32-bit ... I suppose it would then be safe.
6521
+ */
6522
+#undef TRULY_NOOP_TRUNCATION
6523
+#define TRULY_NOOP_TRUNCATION(O,I)     1
6524
+
6525
+/* TARGET_MODE_REP_EXTENDED(MODE,REPMODE) ... The representation of an integral
6526
+ * mode can be such that the values are always extended to a wider integral
6527
+ * mode.  Return SIGN_EXTEND if values of MODE are represented in sign-extended
6528
+ * form to REPMODE.  Return UNKNOWN otherwise.  (Currently none of the targets
6529
+ * use zero-extended.
6530
+ *
6531
+ */
6532
+// #undef      TARGET_MODE_REP_EXTENDED
6533
+// #define     TARGET_MODE_REP_EXTENDED(R,M)   SIGN_EXTEND
6534
+
6535
+/* STORE_FLAG_VALUE ... A C expression describing the value returned by a
6536
+ * comparison operator with an integral mode and stored by a store-flag
6537
+ * instruction (cstoremode4) when the condition is true.  This description
6538
+ * must apply to all the cstoremode4 patterns and all the comparison operators
6539
+ * whose results have MODE_INT mode.
6540
+ *
6541
+ * ZipCPU---Doesn't really have a STORE_FLAG_VALUE instruction ...
6542
+ */
6543
+
6544
+/* FLOAT_STORE_FLAG_VALUE
6545
+ *
6546
+ * ZipCPU
6547
+ */
6548
+
6549
+/* VECTOR_STORE_FLAG_VALUE ... define this macro on machines that have vector
6550
+ * comparison operations that return a vector result ...
6551
+ *
6552
+ * ZipCPU---Doesn't support vector operations.
6553
+ */
6554
+
6555
+/* CLZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
6556
+ * CTZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
6557
+ *
6558
+ * A C expression that indicates whetther the architecture defines a value for
6559
+ * clz or ctz with a zero operand.  A result of 0 indicates the value is
6560
+ * undefined.  If the value is defined for only the RTL expression, the macro should evaluate to 1.  If the value also applies to the corresponding optab
6561
+ * entry, then the macro should evaluate to 2.  In cases where the value is
6562
+ * defined, value should be set to this value.
6563
+ * If this macro is not defined, the value of clz or ctz at zero is assumed to
6564
+ * be undefined.
6565
+ *
6566
+ * ZipCPU---Has neither clz nor ctz instructions, so we don't need this.
6567
+ */
6568
+
6569
+/* Pmode ... An alias for the machine mode for pointers.  On most machines,
6570
+ * define this to be the integer mode corresponding to the width of a
6571
+ * hardware pointer.  SImode on 32-bits machines, or DImode on 64-bit machines.
6572
+ * On some machines you must define this to be one of the partial
6573
+ * integer modes, such as PSImode.
6574
+ */
6575
+#undef Pmode
6576
+#define        Pmode   SImode
6577
+
6578
+/* FUNCTION_MODE ... An alais for the machine mode used for memory references to
6579
+ * function being called, in call RTL expressions.  On most CISC machines, where
6580
+ * an instruction can begin at any byte address, this should be QImode.  On most
6581
+ * RISC machines, where all instructions have fixed size and alignment, this
6582
+ * should be a mode with the same size and alignment as the machine instruction
6583
+ * words--typically SImode or HImode.
6584
+ *
6585
+ * ZipCPU---Definitely SImode, as with Pmode.  (All words are 32-bits, including
6586
+ * addresses on the ZipCPU.
6587
+ */
6588
+#undef FUNCTION_MODE
6589
+#define        FUNCTION_MODE   SImode
6590
+
6591
+/* STDC_0_IN_SYSTEM_HEADERS
6592
+ */
6593
+
6594
+/* TARGET_C_PREINCLUDE(V) ... Define this hook to return the name of  a header
6595
+ * file to be included at the start of all compilations, as if it had been
6596
+ * included with #include <file>.  If this hook returns NULL, or is not defined,
6597
+ * or if the header is not found, or if the user specifies -ffreestanding or
6598
+ * -nostdinc, no header is included.
6599
+ *
6600
+ * ZipCPU --- We don't have a standard library defined yet, so we'll leave this
6601
+ * as NULL.
6602
+ */
6603
+#undef TARGET_C_PREINCLUDE
6604
+#define        TARGET_C_PREINCLUDE     NULL
6605
+
6606
+/* TARGET_CXX_IMPLICIT_EXTERN_C(CONST CHAR *) ... Define this hook to add target
6607
+ * specific C++ implicit extern C functions.  If this function returns true
6608
+ * for the name of a file-scope function, that function implicitly gets extern
6609
+ * "C" linkage rather than whatever linkage the declaration would normally have.
6610
+ * An example of such function is WinMain on Win32 targets.
6611
+ *
6612
+ * ZipCPU---Not ready to deal with this yet.
6613
+ */
6614
+
6615
+/* NO_IMPLICIT_EXTERN_C ... Define this macro if the system header files
6616
+ * support C++ as well as C.  This macro inhibits the usual method of using
6617
+ * system header files in C++, which is to pretend that the file's contents
6618
+ * are enclosed in 'extern "C" {...}'.
6619
+ *
6620
+ *
6621
+ * ZipCPU --- Don't have either C or C++ headers, so let's skip this for now.
6622
+ * Eventually, though, I think ZipCPU and C++ would go very well together.
6623
+ */
6624
+
6625
+/* REGISTER_TARGET_PRAGMAS ... Define this macro if you want to implement any
6626
+ * target specific pragmas.
6627
+ *
6628
+ * ZipCPU --- let's not.
6629
+ */
6630
+
6631
+/* HANDLE_PRAGMA_PACK_WITH_EXPANSION ... Define this macro if macros should be
6632
+ * expanded in the arguments of #pragma pack().
6633
+ *
6634
+ * ZipCPU ... why?
6635
+ */
6636
+
6637
+/* TARGET_DEFAULT_PACK_STRUCT ... If your target requires a struct packing
6638
+ * default other than 0 (meaning the machine default), define this macro to
6639
+ * the necessary value (in bytes).  This must be a value that would also be
6640
+ * valid to use with #pragma pack() (that is a small power of two.
6641
+ */
6642
+
6643
+/* DOLLARS_IN_IDENTIFIERS
6644
+ * ZipCPU --- Default (not changing C)
6645
+ */
6646
+
6647
+/* INSN_SETS_ARE_DELAYED(INSN) ... Define this macro as a C expression that
6648
+ * is nonzero if it is safe for the delay slot schedule to place instructions
6649
+ * in the delay slot of INSN, even if they appear to use a resource set or
6650
+ * clobbered in INSN.  INSN is always a ...
6651
+ *
6652
+ * ZipCPU --- You need not define this macro if it would always return zero.
6653
+ */
6654
+
6655
+/* INSN_REFERENCES_ARE_DELAYED(INSN) ... Define this macro as a C expression
6656
+ * that is nonzero if it is safe for the delay slot schedule to place
6657
+ * instructions in the delay slot of INSN, even if they appear to set or clobber
6658
+ * a resource referenced in INSN.  INSN is always a jump_insn or an insn.  On
6659
+ * machines where some insn or jump_insn is really a function call and ...
6660
+ *
6661
+ * ZipCPU --- You need not define this macro if it would always return zero.
6662
+ */
6663
+
6664
+/* MULTIPLE_SYMBOL_SPACES ... Define this macro as a C expression that is
6665
+ * nonzero if, in some cases, global symbols from one translation unit may not
6666
+ * be bound to undefined symbols in another translation unit without user
6667
+ * intervention.  For instance, under Microsoft Windows symbols must be
6668
+ * explicitly imported from shared libraries (DLLs).
6669
+ *
6670
+ * ZipCPU---You need not define this macro if it would always evaluate to zero,
6671
+ * so we won't.
6672
+ */
6673
+
6674
+/* TARGET_MD_ASM_ADJUST
6675
+ */
6676
+/* MATH_LIBRARY ... Define this macro as a C constant ... you only need to
6677
+ * define this macro if the default of "m" is wrong.
6678
+ *
6679
+ * ZipCPU --- as we don't have a math library yet, building one such that "m"
6680
+ * works doesn't sound like a problem.  Let's not define this.
6681
+ */
6682
+
6683
+/* LIBRARY_PATH_ENV ... Define this as a C string constant for the environment
6684
+ * variable that specifies where the linker should look for libraries.
6685
+ *
6686
+ * Just in case we want to add libraries for ZipCPU, let's place them in
6687
+ * /usr/local/zip/lib, so as not to confuse them with our local systems
6688
+ * libraries.
6689
+ */
6690
+#define        LIBRARY_PATH_ENV        "/usr/local/zip/lib"
6691
+
6692
+/* TARGET_POSIX_IO ... Define this macro if the target supports the following
6693
+ * POSIX file fucntions: access, mkdir, and file locking with fcntl/F_SETLKW.
6694
+ *
6695
+ * ZipCPU does not.
6696
+ */
6697
+
6698
+/* MAX_CONDITIONAL_EXECUTE ... A C expression for the maximum number of
6699
+ * instructions to execute via conditional execution instructions instead of a
6700
+ * branch.  A value of BRANCH_COST+1 is the default if the machine does not use
6701
+ * cc0 and 1 if it does use cc0.
6702
+ *
6703
+ * ZipCPU---This sounds good enough for the ZipCPU as well--as long as we have
6704
+ * BRANCH_COST defined.  However, BRANCH_COST is defined as conditionally to
6705
+ * something else, so let's keep looking into this.
6706
+ */
6707
+
6708
+/* IFCVT_MODIFY_TESTS(CEINFO,TRUE,FALSE) ... Used if the target needs to
6709 103 dgisselq
+ * perform machine-dependent modifications on the conditionals used for turning
6710 102 dgisselq
+ * basic blocks into conditionally executed code.  CEINFO points to a data
6711
+ * structure, struct ce_if_block, which contains information about the currently
6712
+ * processed blocks.  TRUE and FALSE are the tests that are used for
6713
+ * converting the then-block and the else-block, respectively.  Set either TRUE
6714
+ * or FALSE to a null pointer if the tests cannot be converted.
6715
+ *
6716
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6717
+ * execution and conditional testing capabilities.
6718
+ */
6719 122 dgisselq
+#define        IFCVT_MODIFY_TESTS(CI,TR,FL)    zip_ifcvt_modify_tests(CI,&TR,&FL)
6720 102 dgisselq
+
6721
+/* IFCVT_MODIFY_MULTIPLE_TESTS(CEINFO, BB, TRUE, FALSE) ... Like
6722
+ * IFCVT_MODIFY_TESTS, but used when converting more complicated if-statements
6723
+ * into conditions combined by and and or operations.  BB contains the basic
6724
+ * block that contains the test that is currently being processed and about to
6725
+ * be turned into a condition.
6726
+ *
6727
+ *
6728
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6729
+ * execution and conditional testing capabilities.
6730
+ */
6731
+// #warning "Need to come back to this."
6732 122 dgisselq
+#define        IFCVT_MODIFY_MULTIPLE_TESTS(CI,BB,TR,FL) TR=NULL_RTX
6733 102 dgisselq
+
6734
+
6735
+/* IFCVT_MODIFY_INSN(CEINFO, PATTERN, INSN) ... A C expression to modify the
6736
+ * PATTERN of an INSN that is to be converted to conditional execution format.
6737
+ * CEINFO points to a data structure, struct ce_if_block, which contains
6738
+ * information about the currently processed blocks.
6739
+ *
6740
+ *
6741
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6742
+ * execution and conditional testing capabilities.
6743
+ */
6744 142 dgisselq
+#define        IFCVT_MODIFY_INSN(CE,PATRN,INSN) zip_ifcvt_modify_insn(CE,PATRN,INSN)
6745 102 dgisselq
+
6746
+
6747
+/* IFCVT_MODIFY_FINAL(CEINFO) ... A C expression to perform any final
6748
+ * machine dependent modifications in converting code to conditional
6749
+ * execution.  The involved basic blocks can be found in struct ce_if_block
6750
+ * structure pointed to be CEINFO.
6751
+ *
6752
+ *
6753
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6754
+ * execution and conditional testing capabilities.
6755
+ */
6756
+// #warning "Need to come back to this."
6757 122 dgisselq
+#define        IFCVT_MODIFY_FINAL(CEINFO)      zip_ifcvt_modify_final(CEINFO)
6758 102 dgisselq
+
6759
+
6760
+/* IFCVT_MODIFY_CANCEL(CEINFO) ... A C expression to cancel any machine
6761
+ * dependent modifications in converting code to conditional execution.  The
6762
+ * involved basic blocks can be found in the struct ce_if_block structure that
6763
+ * is pointed to by CEINFO.
6764
+ *
6765
+ *
6766
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6767
+ * execution and conditional testing capabilities.
6768
+ */
6769
+// #warning "Need to come back to this."
6770 122 dgisselq
+#define        IFCVT_MODIFY_CANCEL(CEINFO)     zip_ifcvt_modify_cancel(CEINFO)
6771 102 dgisselq
+
6772
+
6773
+/* IFCVT_MACHDEP_INIT(CEINFO) ... A C expression to initialize any machine
6774
+ * specific data for if-conversion of the if-block in the CEINFO block structure
6775
+ * that is pointed by CEINFO.
6776
+ *
6777
+ *
6778
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
6779
+ * execution and conditional testing capabilities.
6780
+ */
6781
+// #warning "Need to come back to this."
6782 122 dgisselq
+#define        IFCVT_MACHDEP_INIT(CEINFO)      zip_ifcvt_machdep_init(CEINFO)
6783 102 dgisselq
+
6784
+
6785
+/* TARGET_MACHINE_DEPENDENT_REORG(VOID) ... If non-null, this hook performs a
6786
+ * target specific pass over the instruction stream.  The compiler will run it
6787
+ * at all optimization levels, just before the point at which it normally does
6788
+ * delayed branch scheduling.
6789
+ *
6790
+ * You need not implement the hook if it has nothing to do.
6791
+ *
6792
+ * ZipCPU---This may be part of a later upgrade, but shouldn't be needed to
6793
+ * just get us started.
6794
+ */
6795
+
6796
+
6797
+/* TARGET_INIT_BUILTINS(VOID) ... Define this hook if you ahve any machine
6798
+ * specific builtin functions that need to be defined.  It should be a function
6799
+ * that performs the necessary setup.  Machine specific builtin functions can be
6800
+ * useful to expand special machine instructions that would otherwise not
6801
+ * normally be generated because they have no equivalent in the source language.
6802
+ *
6803
+ * To create a built in function, call the function lang_hooks.builtin_function
6804
+ * which is defined by the language front end.  You can use any type nodes
6805
+ * set up by build_common_tree_nodes; only language front ends that use those
6806
+ * two functions will call "TARGET_INIT_BUILTINS".
6807
+ *
6808
+ * ZipCPU---We need to come back to this.  We should have several built-ins
6809
+ * defined: rtu(), wait(), halt(), save_context(cstackregno), and
6810
+ * restore_context(cstackregno).
6811
+ *
6812
+ */
6813
+#undef TARGET_INIT_BUILTINS
6814
+#define        TARGET_INIT_BUILTINS    zip_init_builtins
6815
+
6816
+/* TARGET_BUILTIN_DECL(CODE,INITP) ... Define this hook if you have any
6817
+ * machine specific builtin functions that need to be defined.  It should be a
6818
+ * function that returns the builtin function declaration for the builtin
6819
+ * function code code.  If there is no such builtin and it cannot be initialized
6820
+ * at this time if INITP is true the function should return NULL_TREE.  If
6821
+ * CODE is out of range the fucntion should return error-mark_node.
6822
+ *
6823
+ * ZipCPU ... needs to be done, don't know how to do it yet.
6824
+ */
6825
+#undef TARGET_BUILTIN_DECL
6826
+#define        TARGET_BUILTIN_DECL     zip_builtin_decl
6827
+
6828
+
6829
+/* TARGET_EXPAND_BUILTIN(TREE,TGT,SUB,MODE,IGNORE) ... Expand a call to a
6830
+ * machine specific built-in function that was set up by TARGET_INIT_BUILTINS.
6831
+ * TREE is the expression for the function call; the result should go to
6832
+ * TGT if that is convenient, and have mode MODE if that is convenient.  SUB
6833
+ * may be used as the target for computing one of EXP's operands.  IGNORE is
6834
+ * non-zero if the value is to be ignored.  This function should return the
6835
+ * result of the call to the built-in function.
6836
+ *
6837
+ * ZipCPU ... needs to do it, just to get our special intrinsic functions
6838
+ */
6839
+#define        TARGET_EXPAND_BUILTIN   zip_expand_builtin
6840
+
6841
+
6842
+/* TARGET_BUILTIN_CHKP_FUNCTION(FCODE) ... Allows the target to redefine
6843
+ * builtin functions used by Pointer Bounds Checker for code instrumentation.
6844
+ *
6845
+ * ZipCPU --- not interested.
6846
+ */
6847
+/* TARGET_CHKP_BOUND_TYPE
6848
+ * TARGET_CHKP_MAKE_BOUNDS_CONSTANT
6849
+ * TARGET_CHKP_INITIALIZE_BOUNDS
6850
+ *
6851
+ * ZipCPU --- Same as last one.
6852
+ */
6853
+
6854
+
6855
+/* TARGET_RESOLVE_OVERLOADED_BUILTIN(LOC, FN, ARGS) ... Select a replacement
6856
+ * for a machine specific built-in function that was set up by
6857
+ * TARGET_INIT_BUILTINS.
6858
+ *
6859
+ * ZipCPU --- If I go to the trouble to create a builtin, why would I want
6860
+ * to then overload it?
6861
+ */
6862
+
6863
+/* TARGET_FOLD_BUILTIN(FN,NARGS,ARGP,IGNORE) ... Fold a call to a machine
6864
+ * specific built-in function that was set up by 'TARGET_INIT_BUILTINS'  FN
6865
+ * is the declaration of the built-in function.  NARGS is the number of
6866
+ * arguments passed to the function; the arguments themselves are pointed to by
6867
+ * ARGP.  The result is another tree, valid for both GIMPLE and GENERIC,
6868
+ * containing as simplified expression for the call's result.  If IGNORE is
6869
+ * true the value will be ignored.
6870
+ *
6871
+ * ZipCPU --- You know, this and the previous couple sound like something
6872
+ * whereby I might be able replace bit-reversal code with my bit reverse
6873
+ * instruction.  That would be very useful, but not necessary to get me
6874
+ * started.
6875
+ */
6876
+
6877
+/* TARGET_GIMPLE_FOLD_BUILTIN
6878
+ * TARGET_COMPARE_VERSION_PRIORITY
6879
+ * TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
6880
+ * TARGET_GENERATE_VERSION_DISPATCHER_BODY
6881
+ * TARGET_CAN_USE_DOLOOP_P
6882
+ * TARGET_INVALID_WITHIN_DOOLOOP
6883
+ * TARGET_LEGITIMATE_COMBINED_INSN
6884
+ * TARGET_CAN_FOLLOW_JUMP
6885
+ * TARGET_COMMUTATIVE_P
6886
+ */
6887
+
6888
+/* TARGET_ALLOCATE_INITIAL_VALUE(REGNO)  ... When the initial value of a hard
6889
+ * register has been copied in a pseudo register, it is often not necessary
6890
+ * ...
6891
+ */
6892
+/* TARGET_UNSPEC_MAY_TRAP_P(RTX,FLAGS)  ... This target hook returns nonzero in
6893
+ * RTX, un unspec or unspec_volatile operation, might cause a trap.  Targets
6894
+ * can use this hook to enhance precision of analysis for unspec and
6895
+ * unspec_volatile operations.  You may call may_trap_p_1 to analyze inner
6896
+ * elements of RTX in which case flags should be passed along.
6897
+ */
6898
+
6899
+/* TARGET_SET_CURRENT_FUNCTION(TREE)  The compiler invokes this hook whenever
6900
+ * it changes its current function context (CFUN).  You can define this
6901
+ * function if the back end needs to perform any initialization or reset
6902
+ * actions on a per-function basis.  For example, it may be used to implement
6903
+ * function attributes that affect register usage or code generation patterns.
6904
+ */
6905
+
6906
+/* TARGET_OBJECT_SUFFIX ... Define this macro to be a C string representing the
6907
+ * suffix for object files on your target machine.  If you do not define this
6908
+ * macro, GCC will use ".o" as the suffix for object files.
6909
+ */
6910
+#define        TARGET_OBJECT_SUFFIX    ".o"
6911
+
6912
+/* TARGET_EXECUTABLE_SUFFIX
6913
+ */
6914
+#define        TARGET_EXECUTABLE_SUFFIX        ""
6915
+
6916
+/* COLLECT_EXPORT_LIST ... If defined, collect2 will scan the individual object
6917
+ * files specified on its command line and create an export list for the linker.
6918
+ * Define this macro for systems like AIX, where the linker discards object
6919
+ * files that are not referenced from main and uses export lists.
6920
+ *
6921
+ * ZipCPU --- shoudln't need this.
6922
+ */
6923
+
6924
+/* MODIFY_JNI_METHOD_CALL(MDECL)  ... Define this macro to a C expression
6925
+ * representing a variant of the method call mdecl, if Java Native Interface
6926
+ * (JNI) methods must be invoked differently from other methods on your
6927
+ * target.  For example, on 32-bit MSWindows, JNI methods must be invoked
6928
+ * using the stdcall calling convention and this macro is then ...
6929
+ *
6930
+ * ZipCPU----Don't need this.  (yet)
6931
+ */
6932
+
6933
+
6934
+/* TARGET_CANNOT_MODIFY_JUMPS_P ... This target hook returns true past the
6935
+ * point in which a new jump instructions could be created.  On machines that
6936
+ * require a register for every jump such as the SHmedia ISA of SH5, this point
6937
+ * would typically be reload, so thiss target hook should be defined to a
6938
+ * function such as:
6939
+ *
6940 117 dgisselq
+ * ZipCPU --- I don't get what this is for.
6941
+ *     Actually, in hind sight, ZipCPU needs this.  Without this, the
6942
+ * compiler will try to reorder basic blocks, shuffling logic around and so
6943
+ * fortch, preventing our comparison optimizations from being used.  By setting
6944
+ * this function appropriately, we can prevent it from reversing conditions into
6945
+ * conditions we don't support.
6946 102 dgisselq
+ */
6947 117 dgisselq
+#define        TARGET_CANNOT_MODIFY_JUMPS_P    zip_cannot_modify_jumps_p
6948 102 dgisselq
+
6949
+/* TARGET_BRANCH_TARGET_REGISTER_CLASS ... This target hook returns a register
6950
+ * class for which branch target register optimizations should be applied.  All
6951
+ * registers in this class should be usable interchangably.  After reload,
6952
+ * registers in this class will be re-allocated and loads will be hoisted out of
6953
+ * loops and be subjected to inter-block scheduling.
6954
+ *
6955
+ * ZipCPU---GENERAL_REGS, but this should be a default already ...
6956
+ */
6957
+
6958
+
6959
+/* TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED ...  Branch target register
6960
+ * optimization will by default exclude callee-saved registers that are not
6961
+ * already live during the current function.  If this target hook returns true,
6962
+ * they will be included.  The target code must then make sure that all target
6963
+ * registers in the class returned by TARGET_BRANCH_REGISTER_CLASS that might
6964
+ * be saved are saaved.
6965
+ *
6966
+ * ZipCPU---
6967
+ */
6968
+
6969
+
6970
+/* TARGET_HAVE_CONDITIONAL_EXECUTION(VOID) ... This target hook returns true
6971
+ * if the target supports conditional execution.  This target hook is required
6972
+ * only when the target has several different modes and they have different
6973
+ * conditional execution capability, such as ARM.
6974
+ *
6975
+ * ZipCPU---Yes!  All instructions may be conditionally executed (except the
6976
+ * long version load immediate ...)
6977
+ */
6978
+#define        TARGET_HAVE_CONDITIONAL_EXECUTION       hook_bool_void_true
6979
+
6980
+/* TARGET_GEN_CCMP_FIRST(PREP,GEN,CODE,OP0,OP1) .. This function prepares to
6981
+ * emit a comparison instruction for the first compare in a sequence of
6982
+ * conditional comparisons.  It returns an appropriate comparison with CC for
6983
+ * passing to gen_ccmp_next or cbranch_optab.  The instructions to prepare the
6984
+ * compare are saved in prep_seq and the compare instructions are saved in
6985
+ * gen_seq.  They will be emitted when all the compares in the conditional
6986
+ * comparison are generated without error.  CODE is the rtx_code of the compare
6987
+ * for op0 and op1.
6988
+ *
6989
+ *
6990
+ * ZipCPU---???
6991
+ */
6992
+
6993
+/* TARGET_GEN_CCMP_NEXT(PREP,GEN,PREV,CMP,OP0,OP1,BITCODE) ... This function
6994
+ * prepares to emit a conditional comparison within a sequence of conditional
6995
+ * comparisons.  It returns an appropriate comparison with CC for passing to
6996
+ * gen_ccmp_next or cbranch_optab.  The insn to prepare the compare are saved
6997
+ * in prep_seq and the compare instructions are saved in gen_seq.  They will be
6998
+ * emitted when all the compares in the conditional comparison are generated
6999
+ * without error.  The pPREV expression is the result of a prior call to either
7000
+ * gen_ccmp_first or gen_ccmp_next.  It may return NULL if the combination of
7001
+ * PREV and this comparison is not supported, otherwise the result must be the
7002
+ * appropriate for passing to gen_ccmp_next or cbranch_optab.  CODE is the RTX
7003
+ * code of the compare for op0 and op1.  BITCODE is AND or IOR, which is the op
7004
+ * on the compares.
7005
+ *
7006
+ *
7007
+ * ZipCPU --- ???
7008
+ */
7009
+
7010
+/* TARGET_LOOP_UNROLL_ADJUST(NUNROLL, LOOP) ... This target hook returns a new
7011
+ * value for the number of times loop should be unrolled.  The parameter NUNROLL
7012
+ * is the number of times the loop is to be unrolled.  The parameter loop is a
7013
+ * pointer to the loop, which is going to be checked for unrolling.  The target
7014
+ * hook is required only when the target has special constraints like maximum number of memory accesses.
7015
+ *
7016
+ *
7017
+ * ZipCPU -- ???
7018
+ */
7019
+
7020
+
7021
+/* POWI_MAX_MULTS ... If defined, this macro is interpreted as a signed integer
7022
+ * C expression that specifies the maximum number of floating point
7023
+ * multiplications that should be emitted when expanding exponentiation by an
7024
+ * integer constant inline.  When this value is defined, exponentiation
7025
+ * requiring more than this number of multiplications is implemented by calling
7026
+ * the system library's pow, powf, or powl routines.  The default value
7027
+ places no upper bound on the multiplication count.
7028
+ *
7029
+ * ZipCPU---As we have no system library pow() routine (yet) ... we're not
7030
+ * ready for this macro.
7031
+ */
7032
+
7033
+
7034
+/* TARGET_EXTRA_INCLUDES(SYSROOT, PFX, STDINC) ... This target hook should
7035
+ * register any extra include files for the target.  The parameter stdinc
7036
+ * indicates if normal include files are present.  The parameter SYSROOT is the
7037
+ * system root directory.  The parameter PFX is the prefix for the GCC
7038
+ * directoiry.
7039
+ *
7040
+ *
7041
+ * ZipCPU---None yet.
7042
+ */
7043
+
7044
+/* TARGET_EXTRA_PRE_INCLUDES(SYSROOT, PFX, STDINC) ... This target hook should
7045
+ * register any extrra include files for the target before any standard headers.
7046
+ * The parameter stdinc indicates if normal include files are present.
7047
+ *
7048
+ * ZipCPU --- None.
7049
+ */
7050
+
7051
+/* TARGET_OPTF(PATH) ... This target hook should register special include paths
7052
+ * for the target.  The parameter path is the integer to register.  On Darwin
7053
+ * systems, this is used for Framework includes, which have semantics that are
7054
+ * different from -I.
7055
+ *
7056
+ *
7057
+ * ZipCPU --- None.
7058
+ */
7059
+
7060
+/* TARGET_USE_LOCAL_THUNK_ALIAS_P(FN) ... This target macro returns if it is
7061
+ * safe to use a local alias for a virtual function FN when constructing
7062
+ * thunks, false otherwise.  By default, the macro returns true for all
7063
+ * functions, if a target supports aliases (i.e. defines ASM_OUTPUT_DEF),
7064
+ * false otherwise.
7065
+ *
7066
+ *
7067
+ * ZipCPU --- ???
7068
+ */
7069
+// #warning "ASM_OUTPUT_DEF's definition has not been considered"
7070
+
7071
+
7072
+/* TARGET_FORMAT_TYPES ... If defined, this macro is the name of a global
7073
+ * variable containing target-specific format checking information for the
7074
+ * -Wformat option.  The default is to have no target-specific format checks.
7075
+ *
7076
+ * ZipCPU --- Default
7077
+ */
7078
+
7079
+/* TARGET_N_FORMAT_TYPES
7080
+ *
7081
+ * ZipCPU --- Default
7082
+ */
7083
+
7084
+/* TARGET_OVERRIDES_FORMAT_ATTRIBUTES ... If defined, this macro is the name of
7085
+ * a global variable containing target-specific format overrides for the
7086
+ * -Wformat option.  The default is to have no target specific format overrides.
7087
+ *
7088
+ * ZipCPU --- Default
7089
+ */
7090
+
7091
+/* TARGET_OVERRIDEES_FORMAT_ATTRIBUTES
7092
+ * TARGET_OVERRIDEES_FORMAT_ATTRIBUTES_COUNT
7093
+ *
7094
+ * If defined, the (first) macro is the name of a global variable containing
7095
+ * target-specific format overrides for the -Wformat option.
7096
+ */
7097
+/* TARGET_OVERRIDES_FORMAT_INIT ... If defined, this macro specifies the
7098
+ * optional initialization routine for target specific customizations of the
7099
+* system printf and scanf formatter settings.
7100
+ */
7101
+
7102
+/* TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN(TLIST,FN,VAL) ... If defined, this
7103
+ * macro returns the diagnostic message when it is illegal to pass an argument
7104
+ * VAL to function FN with prototype TLIST.
7105
+ *
7106
+ * ZipCPU---Default.
7107
+ */
7108
+
7109
+/* TARGET_INVALID_CONVERSION
7110
+ * TARGET_INVALID_UNARY_OP
7111
+ * TARGET_INVALID_BINARY_OP
7112
+ * TARGET_INVALID_PARAMETER_TYPE
7113
+ * TARGET_INVALID_RETURN_TYPE
7114
+ * TARGET_PROMOTED_TYPE
7115
+ * TARGET_CONVERT_TO_TYPE
7116
+ * TARGET_USE_JCR_SECTION_TYPE
7117
+ * OBJC_JBLEN
7118
+ * LIBGCC2_UNWIND_ATTRIBUTE
7119
+ * TARGET_UPDATE_STACK_BOUNDARY
7120
+ * TARGET_GET_DRAP_RTX
7121
+ * TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
7122
+ */
7123
+/* TARGET_CONST_ANCHOR ... On some architectures it can take multiple
7124
+ * instructions to synthesize a constant. If there is another constant already
7125
+ * in a register that is close enough in value then it is preferable that the
7126
+ * new constant is computed from the register using immediate addition or
7127
+ * subtraction.  We accomplish this through CSE.  Besides the value of the
7128
+ * constant we also add a lower and an upper constant anchor to the available
7129
+ * expressions.  These are then queried when encountering new constants.  The
7130
+ * anchors are computed by rounding the constant up and down to a multiple of
7131
+ * the value of TARGET_CONST_ANCHOR.  TARGET_CONST_ANCHOR should be the maximum
7132
+ * positive value accepted by immediate-add plus one.  We currently assume that
7133
+ * the value of TARGET_CONST_ANCHOR is a poewr of 2.  For example, on MIPS,
7134
+ * where add-immediate takes a 16-bit signed value, TARGET_CONST_ANCHOR is set
7135
+ * to 0x8000.  The default value is zero, which disables this optimization.
7136
+ *
7137
+ * ZipCPU---One of the great strengths of the ZipCPU ISA is its ability to
7138
+ * access registers plus immediates.  To use this, we *need* this capability.
7139
+ * So, we define it here. (to 0x20000, or 2^17 because we can handle 18-bits of
7140
+ * signed immediate offsets)
7141
+ *
7142
+ * On ZipCPU---2^17
7143
+ */
7144
+#define        TARGET_CONST_ANCHOR     zip_const_anchor
7145
+
7146
+/* TARGET_ASAN_SHADOW_OFFSET ... Return the offset bitwise ored into shifted
7147
+ * address to get corresponding Address Sanitizer shadow memory address.  NULL
7148
+ * if address Sanitizer is not supported by the target.
7149
+ */
7150
+#define        TARGET_ASAN_SHADOW_OFFSET       NULL
7151
+
7152
+/* TARGET_MEMMODEL_CHECK
7153
+ */
7154
+/* TARGET_ATOMIC_TEST_AND_SET_TRUEVAL ... This value should be set if the result
7155
+ * written by atomic test and set is not exactly 1, i.e. the bool true.
7156
+ */
7157
+/* TARGET_HAS_IFUNC_P ... It returns true if the target supports GNU indirect
7158
+ * functions.  The support includes the assembler, linker, and dynamic linker.
7159
+ * The default value of this hook is based on target's libc.
7160
+ */
7161
+#define        TARGET_HAS_IFUNC_P      hook_bool_void_true
7162
+
7163
+/* TARGET_ATOMIC_ALIGN_FOR_MODE(MODE) ... If defined, this function returns
7164
+ * an appropriate alignment in bits for an atomic object of machine mode
7165
+ * MODE.  If 0 is returned then the default alignment for the specified mode
7166
+ * is used.
7167
+ *
7168
+ * ZipCPU---Both default and 2 would be valid.  We'll stick to the default.
7169
+ */
7170
+
7171
+/* TARGET_ATOMIC_ASSIGN_EXPAND_FENV --- ISO C11 requires atomic compound
7172
+ * assignments that may raise floating-point exceptions to raise exceptions
7173
+ * corresponding to the arithmetic operation whose result was successfully
7174
+ * stored in a compare-and-exchange sequence.  This requires code equivalent to
7175
+ * calls to feholdexcept, feclearexcept and feupdateenv to be generated at
7176
+ * appropriate points in the compare-and-exchange sequence.  This hook should
7177
+ * set *hold to an expression equivalent
7178
+ *
7179
+ * ZipCPU --- ???
7180
+ */
7181
+
7182
+/* TARGET_RECORD_OFFLOAD_SYMBOL ... Used when offloaded functions are seen in
7183
+ * the compilation unit and no named sections are available.  It is called once
7184
+ * for each symbol that must be recorded in the offload function and variable
7185
+ * table.
7186
+ *
7187
+ * ZipCPU --- Offloaded functions?
7188
+ */
7189
+
7190
+/* TARGET_OFFLOAD_OPTIONS
7191
+ *
7192
+ * ZipCPU---none defined
7193
+ */
7194
+
7195
+/* TARGET_SUPPORTS_WIDE_INT ... On older ports, large integers are stored
7196
+ * in CONST_DOUBLE rtl objects.  Newer ports define TARGET_SUPPORTS_WIDE_INT
7197
+ * to be nonzero to indicate that large integers are stored in CONST_WIDE_INT
7198
+ * rtl objects.  The CONST_WIDE_INT allows very large integer constants to be
7199
+ * represented.  CONST_DOUBLE is limited to twice the size of the hosts
7200
+ * HOST_WIDE_INT representation.
7201
+ *
7202
+ * ZipCPU---We don't need these yet, so this isn't yet relevant.  (These ints
7203
+ * are wider than DImode ...)
7204
+ */
7205
+#define        TARGET_SUPPORTS_WIDE_INT        0
7206
+
7207
+
7208
+/* Now, for the prototype functions ...*/
7209
+// These have been moved to zip-protos.h
7210
+
7211
+// extern void zip_init_builtins(void);
7212
+// extern void zip_asm_output_anchor(rtx x);
7213
+// extern bool zip_legitimate_address_p(enum machine_mode mode, rtx x, bool string);
7214
+// extern void zip_asm_trampoline_template(FILE *);
7215
+// extern void zip_initial_elimination_offset(int from, int to);
7216
+// extern void zip_print_operand(FILE *stream, rtx *x, int code);
7217
+// extern void zip_print_operand_address(FILE *stream, rtx *x);
7218
+// extern void zip_asm_output_def(FILE *s, const char *n, const char *v);
7219
+// extern void zip_update_cc_notice(rtx exp, rtx_insn *insn);
7220
+// extern      int zip_address_operand(rtx op);
7221
+// extern      int zip_const_address_operand(rtx op);
7222
+// extern void zip_expand_prologue(void);
7223
+// extern void zip_expand_epilogue(void);
7224
+// extern bool zip_gen_move_rtl(rtx, rtx);
7225
+// extern bool zip_load_address_lod(rtx, rtx);
7226
+// extern bool zip_load_address_sto(rtx, rtx);
7227
+// extern void zip_print_operand(FILE *fp, rtx x, int code);
7228
+// extern void zip_print_operand_address(FILE *fp, rtx x);
7229
+// extern bool zip_use_return_insn(void);
7230
+
7231 111 dgisselq
+#define        UQQmode USQmode
7232
+#define        UHQmode USQmode
7233
+#define        UHAmode USAmode
7234
+#define        QQmode  SQmode
7235
+#define        HQmode  SQmode
7236 102 dgisselq
+#define        QImode  SImode
7237
+#define        HImode  SImode
7238 111 dgisselq
+#define        QAmode  SAmode
7239
+#define        HAmode  SAmode
7240 102 dgisselq
+
7241
+#include "insn-modes.h"
7242 200 dgisselq
+// #include "zip-protos.h"     // Cant include this here!
7243 102 dgisselq
+
7244
+#endif /* GCC_ZIP_H */
7245
+
7246
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip.md gcc-5.3.0-zip/gcc/config/zip/zip.md
7247
--- gcc-5.3.0-original/gcc/config/zip/zip.md    1969-12-31 19:00:00.000000000 -0500
7248 200 dgisselq
+++ gcc-5.3.0-zip/gcc/config/zip/zip.md 2016-11-28 18:12:19.339493020 -0500
7249
@@ -0,0 +1,3058 @@
7250 102 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7251
+;;
7252
+;; Filename:   zip.md
7253
+;;
7254
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
7255
+;;
7256
+;; Purpose:    This is the machine description of the Zip CPU as needed by the
7257
+;;             GNU compiler collection (GCC).
7258
+;;
7259
+;;
7260
+;; Creator:    Dan Gisselquist, Ph.D.
7261
+;;             Gisselquist Technology, LLC
7262
+;;
7263
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7264
+;;
7265
+;; Copyright (C) 2015, Gisselquist Technology, LLC
7266
+;;
7267
+;; This program is free software (firmware): you can redistribute it and/or
7268
+;; modify it under the terms of  the GNU General Public License as published
7269
+;; by the Free Software Foundation, either version 3 of the License, or (at
7270
+;; your option) any later version.
7271
+;;
7272
+;; This program is distributed in the hope that it will be useful, but WITHOUT
7273
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
7274
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
7275
+;; for more details.
7276
+;;
7277
+;; License:    GPL, v3, as defined and found on www.gnu.org,
7278
+;;             http://www.gnu.org/licenses/gpl.html
7279
+;;
7280
+;;
7281
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7282
+;;
7283
+;;
7284
+;; - Immediate integer operand constraints
7285
+;;     'I'     -2^22 ... 2^22-1, or -4194304 .. 4194303        (LDI insn)
7286
+;;     'M'     -2^12 ... 2^12-1, or -4096 ... 4095             (MOV offset)
7287
+;;     'N'     -2^14 ... 2^14-1, or -16384 ... 16383           (OpB offset)
7288
+;;     'O'     -2^17 ... 2^17-1, or -131072 ... 131071         (OpB Immediate)
7289
+;;     'R'     0...31                                          (Shift value)
7290
+;; - Memory constraints
7291 111 dgisselq
+;;     "Q"     Op-B capable references to memory
7292
+;;     "S"     References to constant memory
7293 102 dgisselq
+;; - Address constraints
7294 111 dgisselq
+;;     "U"     Op-B capable address that references to memory
7295
+;;     "T"     Constant memory addresses
7296 102 dgisselq
+(define_constraint "M"
7297
+  "An 13-bit signed immediate such as a MOV instruction can handle"
7298
+  (and (match_code "const_int")
7299
+       (match_test "(ival < 0x1000) && (ival >= -0x1000)")))
7300
+(define_constraint "N"
7301
+  "An 14-bit signed immediate offset such as an Op-B register offset"
7302
+  (and (match_code "const_int")
7303
+       (match_test "(ival < 0x2000) && (ival >= -0x2000)")))
7304
+(define_constraint "O"
7305
+  "An 18-bit signed immediate such as an Op-B Immediate can handle"
7306
+  (and (match_code "const_int")
7307
+       (match_test "(ival < 0x20000) && (ival >= -0x20000)")))
7308
+(define_constraint "R"
7309
+  "Bits that a value may be shifted"
7310
+  (and (match_code "const_int")
7311
+       (match_test "(ival < 32) && (ival >= 0)")))
7312
+;;
7313
+;
7314
+;
7315
+; Our builtin functions, by identifier
7316
+;
7317
+(define_constants
7318 117 dgisselq
+       [(UNSPEC_RTU             1)
7319
+       (UNSPEC_HALT             2)
7320
+       (UNSPEC_IDLE             3)
7321
+       (UNSPEC_SYSCALL          4)
7322
+       (UNSPEC_SAVE_CONTEXT     5)
7323
+       (UNSPEC_RESTORE_CONTEXT  6)
7324
+       (UNSPEC_BITREV           7)
7325
+       (UNSPEC_GETUCC           8)
7326
+       (UNSPEC_GETCC            9)
7327
+       (UNSPEC_LDILO           10)
7328 127 dgisselq
+       ; (UNSPEC_RAW_CALL      11)
7329 102 dgisselq
+       ])
7330
+;
7331
+;
7332
+; Registers by name
7333
+(define_constants
7334
+  [(RTN_REG            0)      ; Return address register
7335
+   (RTNV_REG           1)      ; Subroutine return value register
7336
+   (AP_REG             10)     ; Hopefully never used
7337
+   (GBL_REG            11)     ; Hopefully never used, but just in case ...
7338
+   (FP_REG             12)
7339
+   (SP_REG             13)
7340
+   (CC_REG             14)
7341
+   (PC_REG             15)
7342
+  ])
7343
+;
7344
+;
7345
+;
7346 200 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7347
+;;
7348 102 dgisselq
+;; Predicates
7349 200 dgisselq
+;;
7350
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7351
+;
7352
+;
7353
+;
7354 102 dgisselq
+(define_predicate "zip_const_address_operand_p"
7355
+       (match_code "symbol_ref,const,label_ref,code_label")
7356
+{
7357
+       return zip_const_address_operand(op);
7358
+})
7359
+
7360
+(define_predicate "zip_address_operand_p"
7361
+       (match_code "reg,plus")
7362
+{
7363 111 dgisselq
+       return zip_pd_opb_operand(op);
7364 102 dgisselq
+})
7365
+
7366 111 dgisselq
+(define_predicate "zip_opb_operand_p"
7367 122 dgisselq
+       (match_code "reg,plus,const_int,subreg")
7368 111 dgisselq
+{
7369
+       return zip_pd_opb_operand(op);
7370
+})
7371
+
7372 122 dgisselq
+(define_predicate "zip_opb_immv_p"
7373
+       (match_code "const_int")
7374
+{
7375
+       return (INTVAL(op)<((1<<13)-1))&&(INTVAL(op)>=-((1<<13)));
7376
+})
7377
+
7378 111 dgisselq
+(define_predicate "zip_opb_single_operand_p"
7379 122 dgisselq
+       (match_code "reg,subreg,const_int")
7380 111 dgisselq
+{
7381
+       return zip_pd_opb_operand(op);
7382
+})
7383
+
7384 102 dgisselq
+(define_predicate "zip_mov_operand_p"
7385
+       (match_code "reg,plus")
7386
+{
7387
+       return zip_pd_mov_operand(op);
7388
+})
7389
+
7390
+(define_predicate "zip_memory_operand_p"
7391
+       (match_code "mem")
7392
+{
7393 111 dgisselq
+       return zip_pd_opb_operand(XEXP(op,0));
7394 102 dgisselq
+})
7395
+
7396 111 dgisselq
+(define_predicate "zip_imm_operand_p"
7397
+       (match_code "const_int")
7398
+{
7399
+       return zip_pd_imm_operand(op);
7400
+})
7401
+
7402
+(define_predicate "zip_mvimm_operand_p"
7403
+       (match_code "const_int")
7404
+{
7405
+       return zip_pd_mvimm_operand(op);
7406
+})
7407
+
7408
+(define_predicate "zip_movdst_operand_p"
7409
+       (match_code "mem,reg,subreg")
7410
+{
7411
+       if (MEM_P(op)) // Check for valid store address
7412
+               return zip_pd_opb_operand(XEXP(op,0));
7413 122 dgisselq
+       else if (SUBREG_P(op))
7414
+               return 1;
7415
+       else if ((REG_P(op))||(SUBREG_P(op)))
7416
+               return register_operand(op, GET_MODE(op));
7417 111 dgisselq
+       return 1;
7418
+})
7419
+
7420
+(define_predicate "zip_movsrc_operand_p"
7421
+       (match_code "mem,reg,subreg,const_int,const,symbol_ref,label_ref,code_label")
7422
+{
7423
+       if (MEM_P(op))
7424
+               return zip_pd_opb_operand(XEXP(op,0));
7425
+       else if (GET_CODE(op)==PLUS)
7426
+               return zip_pd_opb_operand(op);
7427 122 dgisselq
+       else if (SUBREG_P(op)) {
7428
+               //; As far as predicates are concerned, subregs must be valid.
7429
+               //; The details of them are settled within the constraints.
7430
+               return 1;
7431
+       } else if ((REG_P(op))||(SUBREG_P(op)))
7432
+               return register_operand(op,SImode);
7433
+       else if (CONST_INT_P(op))
7434
+               return 1;
7435 111 dgisselq
+       return 1;
7436
+})
7437
+
7438 200 dgisselq
+;
7439
+;
7440
+;
7441
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7442
+;;
7443 102 dgisselq
+;; Constraints
7444 200 dgisselq
+;;
7445
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7446 102 dgisselq
+;
7447 200 dgisselq
+;
7448
+;
7449 102 dgisselq
+(define_memory_constraint "S"
7450
+       "Any memory referenced by a constant address, possibly unknown at compile time"
7451
+       (and (match_code "mem")
7452
+               (match_test "zip_ct_const_address_operand(XEXP(op,0))")))
7453
+(define_memory_constraint "Q"
7454
+       "Any memory addressed suitably for a load or store instruction"
7455
+       (and (match_code "mem")
7456
+               (match_test "zip_ct_address_operand(XEXP(op,0))")))
7457
+(define_address_constraint "U"
7458
+       "An address suitable for a load or store instruction"
7459
+       (and (match_code "reg,plus")
7460
+               (match_test "zip_ct_address_operand(op)")))
7461
+(define_address_constraint "T"
7462
+       "Any constant address, to include those made by symbols unknown at compile time"
7463
+       (and (match_code "label_ref,code_label,symbol_ref,const")
7464
+               (match_test "zip_ct_const_address_operand(op)")))
7465
+;
7466
+;
7467 200 dgisselq
+;
7468
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7469
+;;
7470 102 dgisselq
+;; Attributes
7471 200 dgisselq
+;;
7472
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7473 102 dgisselq
+;
7474 200 dgisselq
+;
7475
+;
7476
+;
7477
+;
7478 102 dgisselq
+(define_attr "predicable"  "no,yes" (const_string "yes"))
7479
+(define_attr "conditional" "no,yes" (const_string "no"))
7480
+(define_attr "ccresult" "set,unknown,unchanged,validzn" (const_string "set"))
7481
+;
7482
+; Mode attributes
7483
+; (define_mode_iterator ZI [QI HI SI])
7484
+; (define_mode_attr zipa [(QI "") (HI "") (SI "")])
7485
+(define_mode_iterator ZI [SI])
7486
+(define_mode_attr zipa [(SI "")])
7487
+;
7488
+;
7489
+;
7490 200 dgisselq
+;
7491
+;
7492
+;
7493
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7494
+;;
7495 102 dgisselq
+;; Instructions
7496 200 dgisselq
+;;
7497
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7498 102 dgisselq
+;
7499 200 dgisselq
+;
7500
+;
7501
+;; Instructions
7502
+;
7503 102 dgisselq
+; (define_insn
7504
+;      optional name
7505
+;      RTL template -- a vector of incomplete RTL expressions describing the
7506
+;              semantics of the instruction.  It is incomplete because it may
7507
+;              contain match_operand, match_operator, and match_dup expressions
7508
+;      The condition --- contains a C expression, may be an empty string
7509
+;      output template or output statement--fragment of C code returning a str
7510
+;      Attributes --
7511
+;      )
7512
+;
7513
+; (match_operand:m n predicate constraint)
7514
+;      Placeholder for operand #n of the instruction
7515
+;      Predicate       string that is the name of a fucntion w/ 2 arguments:
7516
+;                              (expression, machine mode)
7517
+;              we can build functions:
7518
+;                      "isregister"    to describe a register
7519
+;                      "isimmediate"   to describe an immediate
7520
+;                      "offsetreg"     to describe a register plus offset
7521
+;                      "anyregister"   to describe *ANY* register (uRx or Rx)
7522
+;              But ... functions "address_operand", "immediate_operand",
7523
+;                      "register_operand", "indirect_operand"
7524
+;              "comparison_operatot" and "ordered_comparison_operator"
7525
+;              are also available--be aware, they include more comparisons
7526
+;              than Zip CPU can do.
7527
+;
7528
+;
7529
+;
7530
+;
7531
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7532
+;;
7533
+;; Move instructions: both
7534 200 dgisselq
+;;     (arbitrary) from variables to variables, but this gets
7535
+;;             expanded into:
7536
+;;     from registers to registers
7537
+;;     from immediates to registers
7538 102 dgisselq
+;;
7539
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7540
+;
7541
+;
7542
+;
7543
+(define_expand "mov<mode>"
7544 111 dgisselq
+       [(set (match_operand:ZI 0 "nonimmediate_operand" "")
7545
+               (match_operand:ZI 1 "general_operand" ""))]
7546 102 dgisselq
+       ""
7547 111 dgisselq
+       {//; Everything except mem=const or mem=mem can be done easily
7548
+       //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
7549
+       //; fprintf(stderr, "ZIP-GEN-MOVE\n");
7550
+       //; zip_debug_rtx_pfx("FROM: ", operands[1]);
7551
+       //; zip_debug_rtx_pfx("TO  : ", operands[0]);
7552
+
7553
+       //; Need to load into a register between memory slots
7554
+       if ((MEM_P(operands[0]))&&(MEM_P(operands[1]))) {
7555
+               //; fprintf(stderr, "GEN-MOVSI: MEM -> MEM\n");
7556
+               if (can_create_pseudo_p()) {
7557
+                       rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
7558
+                       emit_insn(gen_movsi(tmp,operands[1]));
7559
+                       operands[1] = tmp;
7560
+               }
7561 102 dgisselq
+       }
7562 111 dgisselq
+
7563
+       //; Op[0] has a bad address, need to legitimize it
7564
+       if ((MEM_P(operands[0]))&&
7565
+               ((zip_const_address_operand(XEXP(operands[0],0)))
7566
+               ||(!zip_pd_opb_operand(XEXP(operands[0],0))))
7567
+               )
7568
+               {
7569
+               //; fprintf(stderr, "GEN-MOVSI: Not to a MEM(REG)\n");
7570
+               if (can_create_pseudo_p()) {
7571
+                       rtx tmp = gen_reg_rtx(Pmode);
7572
+                       //; Load the address into a register
7573
+                       emit_insn(gen_movsi(tmp,XEXP(operands[0],0)));
7574
+                       XEXP(operands[0],0) = tmp;
7575
+                       mark_reg_pointer(tmp,1);
7576
+               }
7577
+       }
7578
+       //; Op[1] is a constant.  Need to load into a register before we can
7579
+       //; place it into memory.
7580
+       if ((MEM_P(operands[0]))&&
7581
+               ((CONSTANT_P(operands[1]))
7582
+               ||(CONST_INT_P(operands[1])))) {
7583
+               //; fprintf(stderr, "GEN-MOVSI: CONST -> MEM\n");
7584
+               //; zip_debug_rtx_pfx("MEM  : ", operands[0]);
7585
+               //; zip_debug_rtx_pfx("CONST: ", operands[1]);
7586
+               if (can_create_pseudo_p()) {
7587
+                       rtx tmp = gen_reg_rtx(GET_MODE(operands[0]));
7588
+                       emit_insn(gen_movsi(tmp,operands[1]));
7589
+                       operands[1] = tmp;
7590
+               }
7591
+       }
7592
+       //; Op[1] has a bad address, need to legitimize it
7593
+       if ((MEM_P(operands[1]))&&
7594
+               //; (!REG_P(XEXP(operands[1],0)))
7595
+               ((zip_const_address_operand(XEXP(operands[1],0)))
7596 122 dgisselq
+               ||(!zip_pd_opb_operand(XEXP(operands[1],0))))) {
7597 111 dgisselq
+               //; fprintf(stderr, "GEN-MOVSI: Not from a MEM(REG)\n");
7598
+               if (can_create_pseudo_p()) {
7599
+                       rtx tmp = gen_reg_rtx(Pmode);
7600
+                       emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
7601
+                       XEXP(operands[1],0) = tmp;
7602
+               } else if (REG_P(operands[0])) { //; Can we steal Op[0]'s reg?
7603
+                       rtx tmp = operands[0];
7604
+                       emit_insn(gen_movsi(tmp,XEXP(operands[1],0)));
7605
+                       XEXP(operands[1],0) = tmp;
7606
+               }
7607
+       }
7608
+       }
7609 102 dgisselq
+       [(set_attr "ccresult" "unchanged")])
7610 111 dgisselq
+(define_insn "movsi_raw"
7611
+       [(set (match_operand:SI 0 "zip_movdst_operand_p" "=r,Q,r,r")
7612
+               (match_operand:SI 1 "zip_movsrc_operand_p" "r,r,Q,i"))]
7613 122 dgisselq
+       "(register_operand(operands[0],SImode))||(register_operand(operands[1],SImode))"
7614 111 dgisselq
+       "@
7615
+       MOV\t%1,%0
7616
+       STO\t%1,%0
7617
+       LOD\t%1,%0
7618
+       LDI\t%1,%0"
7619
+       [(set_attr "ccresult" "unchanged")])
7620 102 dgisselq
+(define_insn "mov<mode>_reg"   ; Register to register move
7621
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7622
+               (match_operand:ZI 1 "register_operand" "r"))]
7623
+       ""
7624
+       "MOV    %1,%0"
7625
+       [(set_attr "ccresult" "unchanged")])
7626 124 dgisselq
+(define_insn "mov<mode>_reg_off" ; Register to register move, used by prologue
7627 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7628
+               (plus:ZI (match_operand:ZI 1 "register_operand" "r")
7629 111 dgisselq
+                       (match_operand:ZI 2 "zip_mvimm_operand_p" "M")))
7630
+               ]
7631 102 dgisselq
+       ""
7632
+       "MOV    %2(%1),%0"
7633
+       [(set_attr "ccresult" "unchanged")])
7634 103 dgisselq
+;(define_insn "mov<mode>_lod"  ; Load from memory
7635
+;      [(set (match_operand:ZI 0 "register_operand" "=r")
7636
+;              (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
7637
+;      ""
7638
+;      "LOD    %1,%0"
7639
+;      [(set_attr "ccresult" "unchanged")])
7640
+;(define_insn "mov<mode>_sto"  ; Store into memory
7641
+;      [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
7642
+;              (match_operand:ZI 1 "register_operand" "r"))]
7643
+;      ""
7644
+;      "STO    %1,%0"
7645
+;      [(set_attr "ccresult" "unchanged")])
7646
+(define_expand "mov<mode>_lod" ; Load from memory
7647 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7648
+               (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
7649 103 dgisselq
+       "")
7650
+(define_insn "*movsi_lod"
7651
+       [(set (match_operand:SI 0 "register_operand" "=r")
7652 111 dgisselq
+               (match_operand:SI 1 "zip_memory_operand_p" ""))]
7653 102 dgisselq
+       ""
7654 103 dgisselq
+       "LOD\t%1,%0"
7655
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
7656 124 dgisselq
+(define_insn "movsi_lod_off" ; used by epilogue code
7657
+       [(set (match_operand:SI 0 "register_operand" "=r")
7658
+               (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
7659
+                       (match_operand:SI 2 "const_int_operand" "N"))))]
7660
+       ""
7661
+       "LOD\t%2(%1),%0"
7662
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
7663 103 dgisselq
+(define_expand "mov<mode>_sto" ; Store into memory
7664 102 dgisselq
+       [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
7665
+               (match_operand:ZI 1 "register_operand" "r"))]
7666 103 dgisselq
+       "")
7667
+(define_insn "*movsi_sto"
7668 111 dgisselq
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
7669 103 dgisselq
+               (match_operand:SI 1 "register_operand" "r"))]
7670 102 dgisselq
+       ""
7671 111 dgisselq
+       "STO\t%1,%0"
7672 103 dgisselq
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
7673 124 dgisselq
+(define_insn "movsi_sto_off" ; used by prologue code
7674
+       [(set (mem:SI (plus:SI
7675
+                       (match_operand:SI 0 "register_operand" "r")
7676
+                       (match_operand:SI 1 "const_int_operand" "N")))
7677
+               (match_operand:SI 2 "register_operand" "r"))]
7678
+       ""
7679
+       "STO\t%2,%1(%0)"
7680
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
7681 102 dgisselq
+(define_insn "mov<mode>_ldi"   ; Load immediate
7682
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7683
+               (match_operand:ZI 1 "immediate_operand" "ipU"))]
7684
+       ""
7685
+       "LDI    %1,%0"
7686
+       [(set_attr "ccresult" "unchanged")])
7687
+;
7688
+;
7689
+;
7690
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7691
+;;
7692
+;; Load and store multiple values
7693
+;;
7694
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7695
+;
7696
+; So far, from the code I've seen from GCC's output,
7697
+; these instructions do not appear to be necessary.
7698
+;
7699
+;(define_insn "load_multiple"
7700
+;      for(a=0; a<%2; a++)
7701
+;              LOD a(%1),%0+a
7702
+;(define_insn "store_multiple"
7703
+;      for(a=0; a<%2; a++)
7704
+;              STO %0+a,a(%1)
7705
+; pushsi -- Do not define, compiler will work around it nicely w/o our help
7706
+;
7707
+;
7708
+;
7709
+;
7710
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7711
+;;
7712 127 dgisselq
+;; Substitution Pattern
7713
+;;
7714
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7715
+;
7716
+;
7717
+(define_subst "cc_substitution"
7718
+       ; The pattern may not have any match_dup expressions.
7719
+       [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
7720
+               (clobber (reg:CC CC_REG))]
7721
+       ""
7722
+       [(set (match_dup 0) (match_dup 1))
7723
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))
7724
+       ])
7725
+;
7726
+(define_subst_attr "cc_subst" "cc_substitution" "_raw" "_clobber")
7727
+;
7728
+;
7729
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7730
+;;
7731 102 dgisselq
+;; General arithmetic instructions
7732
+;;
7733
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7734
+;
7735
+;
7736
+;
7737
+;
7738 111 dgisselq
+(define_expand "add<mode>3" ; Fastest/best instruction always goes first
7739 127 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7740 103 dgisselq
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
7741 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
7742 127 dgisselq
+       ])
7743
+(define_insn_and_split "add<mode>3_split_reg"
7744
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7745
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
7746
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
7747
+       ""
7748
+       "#"     ; This code means the instruction *must* be split
7749
+       "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))"
7750
+       [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1) (match_dup 2)))
7751
+               (clobber (reg:CC CC_REG))])]
7752
+       ""
7753
+       [(set_attr "predicable" "yes")])
7754
+(define_insn_and_split "add<mode>3_split_off"
7755
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7756
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
7757
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7758
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
7759
+       ""
7760
+       "#"     ; This code means the instruction *must* be split
7761
+       "(reload_completed)&&(REG_P(operands[0]))&&(REG_P(operands[1]))&&(REGNO(operands[0])==REGNO(operands[1]))"
7762
+       [(parallel [(set (match_dup 0) (plus:ZI (match_dup 1)
7763
+                       (plus:ZI (match_dup 2) (match_dup 3))))
7764
+               (clobber (reg:CC CC_REG))])]
7765
+       ""
7766
+       [(set_attr "predicable" "yes")])
7767
+(define_insn "addsi3_reg_clobber"
7768 122 dgisselq
+       [(set (match_operand:SI 0 "register_operand" "=r")
7769
+               (plus:SI (match_operand:SI 1 "register_operand" "0")
7770
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
7771 127 dgisselq
+       (clobber (reg:CC CC_REG))]
7772
+       ""
7773
+       "ADD    %2,%0"
7774
+       [(set_attr "ccresult" "set")])
7775
+(define_insn "addsi3_reg_raw"
7776
+       [(set (match_operand:SI 0 "register_operand" "=r")
7777
+               (plus:SI (match_operand:SI 1 "register_operand" "0")
7778
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
7779 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7780 102 dgisselq
+       ""
7781
+       "ADD    %2,%0"
7782
+       [(set_attr "ccresult" "set")])
7783 127 dgisselq
+(define_insn "add<mode>3_off_raw"
7784 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7785 103 dgisselq
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
7786
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7787 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7788
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7789 102 dgisselq
+       ""
7790
+       "ADD    %3+%2,%0"
7791
+       [(set_attr "ccresult" "set")])
7792 127 dgisselq
+(define_insn "add<mode>3_off_clobber"
7793
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7794
+               (plus:ZI (match_operand:ZI 1 "register_operand" "0")
7795
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7796
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7797
+       (clobber (reg:CC CC_REG))]
7798
+       ""
7799
+       "ADD    %3+%2,%0"
7800
+       [(set_attr "ccresult" "set")])
7801 102 dgisselq
+;
7802
+;
7803
+;
7804 103 dgisselq
+(define_expand "sub<mode>3"
7805 138 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7806 103 dgisselq
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7807 138 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
7808 127 dgisselq
+(define_insn_and_split "sub<mode>3_split_reg"
7809 103 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7810
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7811 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
7812
+       ""
7813
+       "#"
7814
+       "(reload_completed)"
7815
+       [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1) (match_dup 2)))
7816
+       (clobber (reg:CC CC_REG))])]
7817
+       ""
7818 138 dgisselq
+       [(set_attr "ccresult" "set") (set_attr "predicable" "yes")])
7819 127 dgisselq
+(define_insn "sub<mode>3_reg_raw"
7820
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7821
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7822 111 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7823 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7824 102 dgisselq
+       ""
7825
+       "SUB    %2,%0"
7826
+       [(set_attr "ccresult" "set")])
7827 127 dgisselq
+(define_insn "sub<mode>3_reg_clobber"
7828 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7829 103 dgisselq
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7830 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7831
+       (clobber (reg:CC CC_REG))]
7832
+       ""
7833
+       "SUB    %2,%0"
7834
+       [(set_attr "ccresult" "set")])
7835
+(define_insn_and_split "sub<mode>3_off_split"
7836
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7837
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7838 103 dgisselq
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
7839 127 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
7840
+       ""
7841
+       "#"
7842
+       "(reload_completed)"
7843
+       [(parallel [(set (match_dup 0) (minus:ZI (match_dup 1)
7844
+                       (plus:ZI (match_dup 2) (match_dup 3))))
7845
+       (clobber (reg:CC CC_REG))])]
7846
+       ""
7847
+       [(set_attr "ccresult" "set")])
7848
+(define_insn "sub<mode>3_off_raw"
7849
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7850
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7851
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
7852 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7853
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7854 102 dgisselq
+       ""
7855
+       "SUB    %3+%2,%0"
7856
+       [(set_attr "ccresult" "set")])
7857 127 dgisselq
+(define_insn "sub<mode>3_off_clobber"
7858
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7859
+               (minus:ZI (match_operand:ZI 1 "register_operand" "0")
7860
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "%r")
7861
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7862
+       (clobber (reg:CC CC_REG))]
7863
+       ""
7864
+       "SUB    %3+%2,%0"
7865
+       [(set_attr "ccresult" "set")])
7866 138 dgisselq
+;
7867
+;
7868
+(define_expand "mul<mode>3"
7869
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7870
+               (mult:ZI (match_operand:ZI 1 "register_operand" "0")
7871
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))]
7872
+       "(ZIP_LONGMPY)")
7873
+(define_insn_and_split "mul<mode>3_split_reg"
7874
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7875
+               (mult:ZI (match_operand:ZI 1 "register_operand" "0")
7876
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
7877
+       "(ZIP_LONGMPY)"
7878
+       "#"
7879
+       "(reload_completed)"
7880
+       [(parallel [(set (match_dup 0) (mult:ZI (match_dup 1) (match_dup 2)))
7881
+       (clobber (reg:CC CC_REG))])]
7882
+       ""
7883
+       [(set_attr "ccresult" "set")])
7884
+(define_insn_and_split "mul<mode>3_split_off"
7885
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7886
+               (mult:ZI (match_operand:ZI 1 "register_operand" "0")
7887
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7888
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
7889
+       "(ZIP_LONGMPY)"
7890
+       "#"
7891
+       "(reload_completed)"
7892
+       [(parallel [(set (match_dup 0) (mult:ZI (match_dup 1)
7893
+                       (plus:ZI (match_dup 2) (match_dup 3))))
7894
+       (clobber (reg:CC CC_REG))])]
7895
+       ""
7896
+       [(set_attr "ccresult" "set")])
7897
+(define_insn "mul<mode>3_reg_clobber"
7898
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7899
+               (mult:ZI (match_operand:ZI 1 "register_operand" "0")
7900
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7901
+       (clobber (reg:CC CC_REG))]
7902
+       "(ZIP_LONGMPY)"
7903
+       "MPY\t%2,%0"
7904
+       [(set_attr "ccresult" "set")])
7905
+(define_insn "mul<mode>3_reg_raw"
7906
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7907
+               (mult:ZI (match_operand:ZI 1 "register_operand" "0")
7908
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
7909
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7910
+       "(ZIP_LONGMPY)"
7911
+       "MPY\t%2,%0"
7912
+       [(set_attr "ccresult" "set")])
7913
+(define_insn "mul<mode>3_off_raw"
7914
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7915
+               (mult:ZI (match_operand:ZI 1 "register_operand" "0")
7916
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7917
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7918
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7919
+       "(ZIP_LONGMPY)"
7920
+       "MPY\t%3+%2,%0"
7921
+       [(set_attr "ccresult" "set")])
7922
+(define_insn "mul<mode>3_off_clobber"
7923
+       [(set (match_operand:ZI 0 "register_operand" "=r")
7924
+               (mult:ZI (match_operand:ZI 1 "register_operand" "0")
7925
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
7926
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
7927
+       (clobber (reg:CC CC_REG))]
7928
+       "(ZIP_LONGMPY)"
7929
+       "MPY\t%3+%2,%0"
7930
+       [(set_attr "ccresult" "set")])
7931
+;
7932
+;
7933
+(define_expand "smulsi3_highpart"
7934
+       [(set (match_operand:SI 0 "register_operand" "=r")
7935
+           (truncate:SI (ashiftrt:DI (mult:DI
7936
+               (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
7937
+               (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "")))
7938
+               (const_int 32))))]
7939 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))")
7940 138 dgisselq
+(define_insn_and_split "smulsi3_highpart_split_reg"
7941
+       [(set (match_operand:SI 0 "register_operand" "=r")
7942
+           (truncate:SI (ashiftrt:DI (mult:DI
7943
+               (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
7944
+               (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
7945
+               (const_int 32))))]
7946 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
7947 138 dgisselq
+       "#"
7948
+       "(reload_completed)"
7949
+       [(parallel [(set (match_dup 0)
7950
+               (truncate:SI (ashiftrt:DI
7951
+                       (mult:DI
7952
+                               (sign_extend:DI (match_dup 1))
7953
+                               (sign_extend:DI (match_dup 2)))
7954
+                       (const_int 32))))
7955
+       (clobber (reg:CC CC_REG))])]
7956
+       ""
7957
+       [(set_attr "ccresult" "set")])
7958
+(define_insn_and_split "smulsi3_highpart_split_off"
7959
+       [(set (match_operand:SI 0 "register_operand" "=r")
7960
+          (truncate:SI (ashift:DI (mult:DI
7961
+               (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
7962
+               (sign_extend:DI
7963
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
7964
+                               (match_operand:SI 3 "zip_opb_immv_p" "N"))))
7965
+                       (const_int 32))))]
7966 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
7967 138 dgisselq
+       "#"
7968
+       "(reload_completed)"
7969
+       [(parallel [(set (match_dup 0)
7970
+               (truncate:SI (ashiftrt:DI
7971
+                       (mult:SI
7972
+                               (sign_extend:DI (match_dup 1))
7973
+                               (sign_extend:DI
7974
+                                       (plus:SI (match_dup 2) (match_dup 3))))
7975
+                       (const_int 32))))
7976
+       (clobber (reg:CC CC_REG))])]
7977
+       ""
7978
+       [(set_attr "ccresult" "set")])
7979
+(define_insn "smulsi3_highpart_reg_clobber"
7980
+       [(set (match_operand:SI 0 "register_operand" "=r")
7981
+            (truncate:SI (ashiftrt:DI
7982
+               (mult:SI
7983
+                 (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
7984
+                 (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
7985
+               (const_int 32))))
7986
+       (clobber (reg:CC CC_REG))]
7987 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
7988 138 dgisselq
+       "MPYSHI\t%2,%0"
7989
+       [(set_attr "ccresult" "set")])
7990
+(define_insn "smulsi3_highpart_reg_raw"
7991
+       [(set (match_operand:SI 0 "register_operand" "=r")
7992
+           (truncate:SI (ashiftrt:DI
7993
+               (mult:SI
7994
+                 (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
7995
+                 (sign_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
7996
+               (const_int 32))))
7997
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
7998 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
7999 138 dgisselq
+       "MPYSHI\t%2,%0"
8000
+       [(set_attr "ccresult" "set")])
8001
+(define_insn "smulsi3_highpart_off_raw"
8002
+       [(set (match_operand:SI 0 "register_operand" "=r")
8003
+           (truncate:SI (ashiftrt:DI
8004
+               (mult:SI
8005
+                 (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
8006
+                 (sign_extend:DI (plus:SI
8007
+                               (match_operand:SI 2 "register_operand" "r")
8008
+                               (match_operand:SI 3 "zip_opb_immv_p" "N"))))
8009
+               (const_int 32))))
8010
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8011 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
8012 138 dgisselq
+       "MPYSHI\t%3+%2,%0"
8013
+       [(set_attr "ccresult" "set")])
8014
+(define_insn "smulsi3_highpart_off_clobber"
8015
+       [(set (match_operand:SI 0 "register_operand" "=r")
8016
+           (truncate:SI (ashiftrt:DI
8017
+               (mult:SI
8018
+                 (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
8019
+                 (sign_extend:DI (plus:SI
8020
+                       (match_operand:SI 2 "register_operand" "r")
8021
+                       (match_operand:SI 3 "zip_opb_immv_p" "N"))))
8022
+               (const_int 32))))
8023
+       (clobber (reg:CC CC_REG))]
8024 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
8025 138 dgisselq
+       "MPYSHI\t%3+%2,%0"
8026
+       [(set_attr "ccresult" "set")])
8027
+;
8028
+;
8029
+(define_expand "umulsi3_highpart"
8030
+       [(set (match_operand:SI 0 "register_operand" "=r")
8031
+           (truncate:SI (ashiftrt:DI (mult:DI
8032
+               (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
8033
+               (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "")))
8034
+               (const_int 32))))]
8035 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))")
8036 138 dgisselq
+(define_insn_and_split "umulsi3_highpart_split_reg"
8037
+       [(set (match_operand:SI 0 "register_operand" "=r")
8038
+           (truncate:SI (ashiftrt:DI (mult:DI
8039
+               (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
8040
+               (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
8041
+               (const_int 32))))]
8042 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
8043 138 dgisselq
+       "#"
8044
+       "(reload_completed)"
8045
+       [(parallel [(set (match_dup 0)
8046
+               (truncate:SI (ashiftrt:DI
8047
+                       (mult:SI
8048
+                               (zero_extend:DI (match_dup 1))
8049
+                               (zero_extend:DI (match_dup 2)))
8050
+                       (const_int 32))))
8051
+       (clobber (reg:CC CC_REG))])]
8052
+       ""
8053
+       [(set_attr "ccresult" "set")])
8054
+(define_insn_and_split "umulsi3_highpart_split_off"
8055
+       [(set (match_operand:SI 0 "register_operand" "=r")
8056
+               (truncate:SI (ashiftrt:DI
8057
+               (mult:DI
8058
+                 (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
8059
+                 (zero_extend:DI
8060
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
8061
+                               (match_operand:SI 3 "zip_opb_immv_p" "N"))))
8062
+               (const_int 32))))]
8063 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
8064 138 dgisselq
+       "#"
8065
+       "(reload_completed)"
8066
+       [(parallel [(set (match_dup 0)
8067
+               (truncate:SI (ashiftrt:DI
8068
+                       (mult:DI
8069
+                               (zero_extend:DI (match_dup 1))
8070
+                               (zero_extend:DI
8071
+                                       (plus:SI (match_dup 2) (match_dup 3))))
8072
+                       (const_int 32))))
8073
+       (clobber (reg:CC CC_REG))])]
8074
+       ""
8075
+       [(set_attr "ccresult" "set")])
8076
+(define_insn "umulsi3_highpart_reg_clobber"
8077
+       [(set (match_operand:SI 0 "register_operand" "=r")
8078
+           (truncate:SI (ashiftrt:DI
8079
+               (mult:DI
8080
+                   (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
8081
+                   (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
8082
+               (const_int 32))))
8083
+       (clobber (reg:CC CC_REG))]
8084 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
8085 138 dgisselq
+       "MPYSHI\t%2,%0"
8086
+       [(set_attr "ccresult" "set")])
8087
+(define_insn "umulsi3_highpart_reg_raw"
8088
+       [(set (match_operand:SI 0 "register_operand" "=r")
8089
+           (truncate:SI (ashiftrt:DI
8090
+               (mult:DI
8091
+                  (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
8092
+                  (zero_extend:DI (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
8093
+               (const_int 32))))
8094
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8095 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
8096 138 dgisselq
+       "MPYSHI\t%2,%0"
8097
+       [(set_attr "ccresult" "set")])
8098
+(define_insn "umulsi3_highpart_off_raw"
8099
+       [(set (match_operand:SI 0 "register_operand" "=r")
8100
+           (truncate:SI (ashiftrt:DI
8101
+               (mult:DI
8102
+                   (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
8103
+                   (zero_extend:DI (plus:SI
8104
+                               (match_operand:SI 2 "register_operand" "r")
8105
+                               (match_operand:DI 3 "zip_opb_immv_p" "N"))))
8106
+               (const_int 32))))
8107
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8108 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
8109 138 dgisselq
+       "MPYSHI\t%3+%2,%0"
8110
+       [(set_attr "ccresult" "set")])
8111
+(define_insn "umulsi3_highpart_off_clobber"
8112
+       [(set (match_operand:SI 0 "register_operand" "=r")
8113
+           (truncate:SI (ashiftrt:DI
8114
+               (mult:DI
8115
+                   (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
8116
+                   (zero_extend:DI (plus:SI
8117
+                       (match_operand:SI 2 "register_operand" "r")
8118
+                       (match_operand:DI 3 "zip_opb_immv_p" "N"))))
8119
+               (const_int 32))))
8120
+       (clobber (reg:CC CC_REG))]
8121 200 dgisselq
+       "((ZIP_LONGMPY)&&(ZIP_HAS_DI))"
8122 138 dgisselq
+       "MPYSHI\t%3+%2,%0"
8123
+       [(set_attr "ccresult" "set")])
8124
+;
8125
+;
8126 111 dgisselq
+(define_expand "div<mode>3"
8127 122 dgisselq
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
8128 103 dgisselq
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
8129 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
8130
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
8131 111 dgisselq
+       "(ZIP_DIVIDE)")
8132
+(define_insn "div<mode>3_reg"
8133
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8134
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
8135 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
8136
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8137 111 dgisselq
+       "(ZIP_DIVIDE)"
8138 102 dgisselq
+       "DIVS   %2,%0"
8139
+       [(set_attr "ccresult" "set")])
8140
+(define_insn "div<mode>3_off"
8141
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8142 103 dgisselq
+               (div:ZI (match_operand:ZI 1 "register_operand" "0")
8143
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
8144 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
8145
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8146 111 dgisselq
+       "(ZIP_DIVIDE)"
8147 102 dgisselq
+       "DIVS   %3+%2,%0"
8148
+       [(set_attr "ccresult" "set")])
8149 111 dgisselq
+(define_expand "udiv<mode>3"
8150 122 dgisselq
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
8151 103 dgisselq
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
8152 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
8153
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
8154 111 dgisselq
+       "(ZIP_DIVIDE)")
8155
+(define_insn "udiv<mode>3_reg"
8156
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8157
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
8158 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
8159
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8160 111 dgisselq
+       "(ZIP_DIVIDE)"
8161 102 dgisselq
+       "DIVU   %2,%0"
8162
+       [(set_attr "ccresult" "set")])
8163
+(define_insn "udiv<mode>3_off"
8164
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8165 103 dgisselq
+               (udiv:ZI (match_operand:ZI 1 "register_operand" "0")
8166
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
8167 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
8168
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8169 111 dgisselq
+       "(ZIP_DIVIDE)"
8170 102 dgisselq
+       "DIVU   %3+%2,%0"
8171
+       [(set_attr "ccresult" "set")])
8172
+;;
8173
+;; modsi3
8174
+;; umodsi3
8175
+;;
8176
+(define_insn "umin<mode>3"
8177
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8178
+               (umin:ZI (match_operand:ZI 1 "register_operand" "%0")
8179
+                       (match_operand:ZI 2 "register_operand" "r")))
8180 122 dgisselq
+       (clobber (reg:CC CC_REG))
8181 102 dgisselq
+       ]
8182
+       ""
8183
+       "CMP    %0,%2
8184
+       MOV.C   %2,%0"
8185
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8186
+(define_insn "umax<mode>3"
8187
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8188
+               (umax:ZI (match_operand:ZI 1 "register_operand" "%0")
8189
+                       (match_operand:ZI 2 "register_operand" "r")))
8190 122 dgisselq
+       (clobber (reg:CC CC_REG))
8191 102 dgisselq
+       ]
8192
+       ""
8193
+       "CMP    %2,%0
8194
+       MOV.C   %2,%0"
8195
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8196
+(define_insn "smin<mode>3"
8197
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8198
+               (smin:ZI (match_operand:ZI 1 "register_operand" "%0")
8199
+                       (match_operand:ZI 2 "register_operand" "r")))
8200 122 dgisselq
+       (clobber (reg:CC CC_REG))
8201 102 dgisselq
+       ]
8202
+       ""
8203
+       "CMP    %2,%0
8204
+       MOV.GT  %2,%0"
8205
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8206
+(define_insn "smax<mode>3"
8207
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8208
+               (smax:ZI (match_operand:ZI 1 "register_operand" "%0")
8209
+                       (match_operand:ZI 2 "register_operand" "r")))
8210 122 dgisselq
+       (clobber (reg:CC CC_REG))
8211 102 dgisselq
+       ]
8212
+       ""
8213
+       "CMP    %0,%2
8214
+       MOV.LT  %2,%0"
8215
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8216 127 dgisselq
+;
8217
+;
8218 200 dgisselq
+; AND
8219
+;
8220
+;
8221 111 dgisselq
+(define_expand "and<mode>3"
8222 127 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8223 102 dgisselq
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
8224 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
8225
+(define_insn_and_split "and<mode>3_reg_split"
8226 111 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8227
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
8228 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
8229
+       ""
8230
+       "#"
8231
+       "(reload_completed)"
8232
+       [(parallel [(set (match_dup 0) (and:ZI (match_dup 1) (match_dup 2)))
8233
+       (clobber (reg:CC CC_REG))])]
8234
+       ""
8235
+       [(set_attr "ccresult" "set")])
8236
+(define_insn "and<mode>3_reg_raw"
8237
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8238
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
8239 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
8240
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8241 102 dgisselq
+       ""
8242
+       "AND    %2,%0"
8243
+       [(set_attr "ccresult" "set")])
8244 127 dgisselq
+(define_insn "and<mode>3_reg_clobber"
8245 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8246 127 dgisselq
+               (and:ZI (match_operand:ZI 1 "register_operand" "%0")
8247
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
8248
+       (clobber (reg:CC CC_REG))]
8249
+       ""
8250
+       "AND    %2,%0"
8251
+       [(set_attr "ccresult" "set")])
8252
+(define_insn_and_split "and<mode>3_off_split"
8253
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8254 102 dgisselq
+               (and:ZI (match_operand:ZI 1 "register_operand" "0")
8255
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
8256 127 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
8257
+       ""
8258
+       "#"
8259
+       "(reload_completed)"
8260
+       [(parallel [(set (match_dup 0) (and:ZI (match_dup 1)
8261
+                       (plus:ZI (match_dup 2) (match_dup 3))))
8262
+       (clobber (reg:CC CC_REG))])]
8263
+       ""
8264
+       [(set_attr "ccresult" "set")])
8265
+(define_insn "and<mode>3_off_raw"
8266
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8267
+               (and:ZI (match_operand:ZI 1 "register_operand" "0")
8268
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
8269 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
8270
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8271 102 dgisselq
+       ""
8272
+       "AND    %3+%2,%0"
8273
+       [(set_attr "ccresult" "set")])
8274 127 dgisselq
+(define_insn "and<mode>3_off_clobber"
8275
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8276
+               (and:ZI (match_operand:ZI 1 "register_operand" "0")
8277
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
8278
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
8279
+       (clobber (reg:CC CC_REG))]
8280
+       ""
8281
+       "AND    %3+%2,%0"
8282
+       [(set_attr "ccresult" "set")])
8283
+;
8284
+;
8285 200 dgisselq
+;
8286
+;
8287
+; iOR
8288
+;
8289
+;
8290 111 dgisselq
+(define_expand "ior<mode>3"
8291 127 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8292 102 dgisselq
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
8293 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))])
8294
+(define_insn_and_split "ior<mode>3_reg_split"
8295 111 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8296
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
8297 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
8298
+       ""
8299
+       "#"
8300
+       "(reload_completed)"
8301
+       [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1) (match_dup 2)))
8302
+       (clobber (reg:CC CC_REG))])]
8303
+       ""
8304
+       [(set_attr "ccresult" "set")])
8305
+(define_insn "ior<mode>3_reg_raw"
8306
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8307
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
8308 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
8309
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8310 102 dgisselq
+       ""
8311
+       "OR     %2,%0"
8312
+       [(set_attr "ccresult" "set")])
8313 127 dgisselq
+(define_insn "ior<mode>3_reg_clobber"
8314 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8315 127 dgisselq
+               (ior:ZI (match_operand:ZI 1 "register_operand" "%0")
8316
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
8317
+       (clobber (reg:CC CC_REG))]
8318
+       ""
8319
+       "OR     %2,%0"
8320
+       [(set_attr "ccresult" "set")])
8321
+(define_insn_and_split "ior<mode>3_off_split"
8322
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8323 102 dgisselq
+               (ior:ZI (match_operand:ZI 1 "register_operand" "0")
8324
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
8325 127 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
8326
+       ""
8327
+       "#"
8328
+       "(reload_completed)"
8329
+       [(parallel [(set (match_dup 0) (ior:ZI (match_dup 1)
8330
+                       (plus:ZI (match_dup 2) (match_dup 3))))
8331
+       (clobber (reg:CC CC_REG))])]
8332
+       ""
8333
+       [(set_attr "ccresult" "set")])
8334
+(define_insn "ior<mode>3_off_raw"
8335
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8336
+               (ior:ZI (match_operand:ZI 1 "register_operand" "0")
8337
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
8338 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
8339
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8340 102 dgisselq
+       ""
8341
+       "OR     %3+%2,%0"
8342
+       [(set_attr "ccresult" "set")])
8343 127 dgisselq
+(define_insn "ior<mode>3_off_clobber"
8344
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8345
+               (ior:ZI (match_operand:ZI 1 "register_operand" "0")
8346
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
8347
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
8348
+       (clobber (reg:CC CC_REG))]
8349
+       ""
8350
+       "OR     %3+%2,%0"
8351
+       [(set_attr "ccresult" "set")])
8352
+;
8353
+;
8354
+;
8355 200 dgisselq
+;
8356
+; XOR
8357
+;
8358
+;
8359
+;
8360 111 dgisselq
+(define_expand "xor<mode>3"
8361 122 dgisselq
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
8362 102 dgisselq
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
8363 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_operand_p" "")))
8364
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])]
8365
+       "")
8366 127 dgisselq
+(define_insn_and_split "xor<mode>3_reg_split"
8367 111 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8368
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
8369 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))]
8370
+       ""
8371
+       "#"
8372
+       "(reload_completed)"
8373
+       [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1) (match_dup 2)))
8374
+       (clobber (reg:CC CC_REG))])]
8375
+       ""
8376
+       [(set_attr "ccresult" "set")])
8377
+(define_insn "xor<mode>3_reg_raw"
8378
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8379
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
8380 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
8381
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8382 102 dgisselq
+       ""
8383
+       "XOR    %2,%0"
8384
+       [(set_attr "ccresult" "set")])
8385 127 dgisselq
+(define_insn "xor<mode>3_reg_clobber"
8386 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8387 127 dgisselq
+               (xor:ZI (match_operand:ZI 1 "register_operand" "%0")
8388
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
8389
+       (clobber (reg:CC CC_REG))]
8390
+       ""
8391
+       "XOR    %2,%0"
8392
+       [(set_attr "ccresult" "set")])
8393
+(define_insn_and_split "xor<mode>3_off_split"
8394
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8395 102 dgisselq
+               (xor:ZI (match_operand:ZI 1 "register_operand" "0")
8396
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
8397 127 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))]
8398
+       ""
8399
+       "#"
8400
+       "(reload_completed)"
8401
+       [(parallel [(set (match_dup 0) (xor:ZI (match_dup 1)
8402
+                       (plus:ZI (match_dup 2) (match_dup 3))))
8403
+       (clobber (reg:CC CC_REG))])]
8404
+       ""
8405
+       [(set_attr "ccresult" "set")])
8406
+(define_insn "xor<mode>3_off_raw"
8407
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8408
+               (xor:ZI (match_operand:ZI 1 "register_operand" "0")
8409
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
8410 122 dgisselq
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
8411
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8412 102 dgisselq
+       ""
8413
+       "XOR    %3+%2,%0"
8414
+       [(set_attr "ccresult" "set")])
8415 127 dgisselq
+(define_insn "xor<mode>3_off_clobber"
8416
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8417
+               (xor:ZI (match_operand:ZI 1 "register_operand" "0")
8418
+                       (plus:ZI (match_operand:ZI 2 "register_operand" "r")
8419
+                               (match_operand:ZI 3 "zip_opb_immv_p" "N"))))
8420
+       (clobber (reg:CC CC_REG))]
8421
+       ""
8422
+       "XOR    %3+%2,%0"
8423
+       [(set_attr "ccresult" "set")])
8424 102 dgisselq
+;(define_insn "addv<mode>4"
8425
+       ;[(set (match_operand:ZI 0 "register_operand" "=r")
8426
+               ;(plus:ZI (match_operand:ZI 1 "register_operand" "%r")
8427
+                       ;(match_operand:ZI 2 "general_operand" "rO")))
8428 122 dgisselq
+       ;(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
8429 102 dgisselq
+                       ;(label_ref (match_operand 3))
8430
+                       ;(pc)))]
8431
+       ;""
8432
+       ;"MOV   %1,%0
8433
+       ;ADD    %2,%0
8434
+       ;BV     %3"
8435
+       ;[(set_attr "predicable" "no") (set_attr "ccresult" "set")])
8436
+;;(define_insn "subvsi4"
8437
+;;     MOV     %1,%0
8438
+;;     SUB     %2,%0
8439
+;;     BV      %3
8440
+;;(mulvsi4)
8441
+;;(define_insn "uaddvsi4"
8442
+;;     ADD     %2,%0
8443
+;;     BC      %3
8444
+;;(define_insn "usubvsi4"
8445
+;;     MOV     %1,%0
8446
+;;     SUB     %2,%0
8447
+;;     BC      %3
8448
+;;
8449
+;; (define_insn "umulvsi4"
8450
+;;     ... ???)
8451
+;;
8452 200 dgisselq
+;
8453
+;
8454
+; ASR
8455
+;
8456
+;
8457 127 dgisselq
+(define_expand "ashr<mode>3"
8458 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8459
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
8460 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
8461
+(define_insn_and_split "ashr<mode>3_split"
8462
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8463
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
8464
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
8465
+       ""
8466
+       "#"
8467
+       "(reload_completed)"
8468
+       [(parallel [(set (match_dup 0) (ashiftrt:ZI (match_dup 1) (match_dup 2)))
8469
+       (clobber (reg:CC CC_REG))])]
8470
+       ""
8471
+       [(set_attr "ccresult" "set")])
8472
+(define_insn "ashr<mode>3_raw"
8473
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8474
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
8475 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
8476
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8477 102 dgisselq
+       ""
8478
+       "ASR    %2,%0"
8479
+       [(set_attr "ccresult" "set")])
8480 127 dgisselq
+(define_insn "ashr<mode>3_clobber"
8481 111 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8482 127 dgisselq
+               (ashiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
8483
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
8484
+       (clobber (reg:CC CC_REG))]
8485
+       ""
8486
+       "ASR    %2,%0"
8487
+       [(set_attr "ccresult" "set")])
8488
+;
8489
+;
8490 200 dgisselq
+;
8491
+; LSL
8492
+;
8493
+;
8494
+;
8495 127 dgisselq
+(define_expand "ashl<mode>3"
8496
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8497 111 dgisselq
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
8498 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
8499
+(define_insn_and_split "ashl<mode>3_split"
8500
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8501
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
8502
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
8503
+       ""
8504
+       "#"
8505
+       "(reload_completed)"
8506
+       [(parallel [(set (match_dup 0) (ashift:ZI (match_dup 1) (match_dup 2)))
8507
+       (clobber (reg:CC CC_REG))])]
8508
+       ""
8509
+       [(set_attr "ccresult" "set")])
8510
+(define_insn "ashl<mode>3_raw"
8511
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8512
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
8513 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
8514
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8515 111 dgisselq
+       ""
8516 122 dgisselq
+       "LSL    %2,%0"
8517 111 dgisselq
+       [(set_attr "ccresult" "set")])
8518 127 dgisselq
+(define_insn "ashl<mode>3_clobber"
8519 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8520 127 dgisselq
+               (ashift:ZI (match_operand:ZI 1 "register_operand" "0")
8521
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
8522
+       (clobber (reg:CC CC_REG))]
8523
+       ""
8524
+       "LSL    %2,%0"
8525
+       [(set_attr "ccresult" "set")])
8526
+;
8527
+;
8528 200 dgisselq
+;
8529
+; LSR
8530
+;
8531
+;
8532
+;
8533 127 dgisselq
+(define_expand "lshr<mode>3"
8534
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8535 102 dgisselq
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
8536 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
8537
+(define_insn_and_split "lshr<mode>3_split"
8538
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8539
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
8540
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
8541
+       ""
8542
+       "#"
8543
+       "(reload_completed)"
8544
+       [(parallel [(set (match_dup 0) (lshiftrt:ZI (match_dup 1) (match_dup 2)))
8545
+       (clobber (reg:CC CC_REG))])]
8546
+       ""
8547
+       [(set_attr "ccresult" "set")])
8548
+(define_insn "lshr<mode>3_raw"
8549
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8550
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
8551
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
8552 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8553 102 dgisselq
+       ""
8554
+       "LSR    %2,%0"
8555
+       [(set_attr "ccresult" "set")])
8556 127 dgisselq
+(define_insn "lshr<mode>3_clobber"
8557 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8558 127 dgisselq
+               (lshiftrt:ZI (match_operand:ZI 1 "register_operand" "0")
8559
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
8560
+       (clobber (reg:CC CC_REG))]
8561
+       ""
8562
+       "LSR    %2,%0"
8563
+       [(set_attr "ccresult" "set")])
8564
+;
8565
+;
8566
+(define_expand "rotl<mode>3"
8567
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8568 102 dgisselq
+               (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
8569 127 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))])
8570
+(define_insn_and_split "rotl<mode>3_split"
8571
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8572
+               (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
8573
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))]
8574
+       ""
8575
+       "#"
8576
+       "(reload_completed)"
8577
+       [(parallel [(set (match_dup 0) (rotate:ZI (match_dup 1) (match_dup 2)))
8578
+       (clobber (reg:CC CC_REG))])]
8579
+       ""
8580
+       [(set_attr "ccresult" "set")])
8581
+(define_insn "rotl<mode>3_raw"
8582
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8583
+               (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
8584 122 dgisselq
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
8585
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8586 102 dgisselq
+       ""
8587
+       "ROL    %2,%0"
8588
+       [(set_attr "ccresult" "set")])
8589 127 dgisselq
+(define_insn "rotl<mode>3_clobber"
8590
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8591
+               (rotate:ZI (match_operand:ZI 1 "register_operand" "0")
8592
+                       (match_operand:ZI 2 "zip_opb_single_operand_p" "rR")))
8593
+       (clobber (reg:CC CC_REG))]
8594
+       ""
8595
+       "ROL    %2,%0"
8596
+       [(set_attr "ccresult" "set")])
8597 102 dgisselq
+;
8598 127 dgisselq
+;
8599
+;
8600 200 dgisselq
+;
8601
+;
8602
+; Others:  NEG, TEST, POPC, NOT
8603
+;
8604
+;
8605 102 dgisselq
+(define_insn "neg<mode>2"
8606
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8607
+               (neg:ZI (match_operand:ZI 1 "register_operand" "r")))
8608 122 dgisselq
+       (clobber (reg:CC CC_REG))]
8609 102 dgisselq
+       ""
8610
+       "NEG    %1,%0"
8611
+       [(set_attr "ccresult" "validzn")])
8612
+(define_insn "abs<mode>2"
8613
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8614
+               (abs:ZI (match_operand:ZI 1 "register_operand" "0")))
8615 122 dgisselq
+       (clobber (reg:CC CC_REG))]
8616 102 dgisselq
+       ""
8617
+       "TEST   %0
8618
+       NEG.LT  %0"
8619
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8620
+(define_insn "popcount<mode>2"
8621
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8622
+               (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
8623 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8624 102 dgisselq
+       ""
8625
+       "POPC   %1,%0"
8626
+       [(set_attr "ccresult" "set")])
8627
+(define_expand "parity<mode>2"
8628 122 dgisselq
+       [(parallel [(set (match_operand:ZI 0 "register_operand" "=r")
8629 102 dgisselq
+               (popcount:ZI (match_operand:ZI 1 "register_operand" "r")))
8630 127 dgisselq
+               (clobber (reg:CC CC_REG))])
8631 122 dgisselq
+       (parallel [
8632
+               (set (match_dup 0) (and:ZI (match_dup 0) (const_int -2)))
8633
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
8634 102 dgisselq
+       ])
8635
+(define_insn "one_cmpl<mode>2"
8636
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8637
+               (not:ZI (match_operand:ZI 1 "register_operand" "0")))
8638 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8639 102 dgisselq
+       ""
8640
+       "XOR    -1,%0"
8641
+       [(set_attr "ccresult" "set")])
8642
+;
8643
+;
8644
+;
8645
+;
8646 117 dgisselq
+;
8647 102 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8648
+;;
8649
+;; General arithmetic instructions -- double words
8650
+;;
8651
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8652
+;
8653
+;
8654
+;
8655 111 dgisselq
+(define_expand "movdi3"
8656
+       [(set (match_operand:DI 0 "nonimmediate_operand" "")
8657 200 dgisselq
+               (match_operand:DI 1 "general_operand" ""))]
8658
+       "(ZIP_HAS_DI)")
8659 111 dgisselq
+(define_insn "movdi_lod"
8660
+       [(set (match_operand:DI 0 "register_operand" "=r")
8661 122 dgisselq
+               (mem:DI (match_operand:SI 1 "zip_opb_operand_p" "")))]
8662 200 dgisselq
+       "(ZIP_HAS_DI)"
8663 111 dgisselq
+       {
8664 122 dgisselq
+               if (REG_P(operands[1]))
8665 111 dgisselq
+                       return "LOD\t(%1),%H0\n\tLOD\t1(%1),%L0";
8666 122 dgisselq
+               else if (GET_CODE(operands[1])==PLUS) {
8667
+                       if ((REG_P(XEXP(operands[1],0)))
8668
+                               &&(CONST_INT_P(XEXP(operands[1],1)))) {
8669 111 dgisselq
+                               static  char    buf[64];
8670
+                               sprintf(buf,
8671
+                                       "LOD\t%ld(%%1),%%H0\n\tLOD\t%ld(%%1),%%L0",
8672 138 dgisselq
+                                       (long)INTVAL(XEXP(operands[1],1)),
8673
+                                       (long)INTVAL(XEXP(operands[1],1)+1));
8674 111 dgisselq
+                               return buf;
8675
+                       }
8676 122 dgisselq
+               } return "BREAK";
8677 111 dgisselq
+       }
8678
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
8679
+(define_insn "movdi_sto"
8680
+       [(set (mem:DI (match_operand:SI 0 "zip_opb_operand_p" ""))
8681
+               (match_operand:DI 1 "register_operand" "r"))]
8682 200 dgisselq
+       "(ZIP_HAS_DI)"
8683 111 dgisselq
+       {
8684
+               if (REG_P(operands[0]))
8685
+                       return "STO\t%H0,(%1)\n\tSTO\t%L0,1(%1)";
8686
+               else if (GET_CODE(operands[0])==PLUS) {
8687
+                       if ((REG_P(XEXP(operands[0],0)))
8688
+                               &&(CONST_INT_P(XEXP(operands[0],1)))) {
8689
+                               static  char    buf[64];
8690
+                               sprintf(buf,
8691
+                                       "STO\t%%H0,%ld(%%1)\n\tSTO\t%%L0,%ld(%%1)",
8692 138 dgisselq
+                                       (long)INTVAL(XEXP(operands[0],1)),
8693
+                                       (long)INTVAL(XEXP(operands[0],1)+1));
8694 111 dgisselq
+                               return buf;
8695
+                       }
8696 127 dgisselq
+               } return "BREAK";
8697 111 dgisselq
+       }
8698
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
8699
+(define_insn "movdi_ldi"
8700
+       [(set (match_operand:DI 0 "register_operand" "=r")
8701
+               (match_operand:DI 1 "immediate_operand" "i"))]
8702 200 dgisselq
+       "(ZIP_HAS_DI)"
8703 111 dgisselq
+       "LDI\t%H1,%H0\n\tLDI\t%L1,%L0"
8704
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
8705 200 dgisselq
+;
8706
+;
8707
+; ADD
8708
+;
8709
+;
8710 102 dgisselq
+(define_insn "adddi3" ; Fastest/best instruction always goes first
8711
+       [(set (match_operand:DI 0 "register_operand" "=r")
8712 103 dgisselq
+               (plus:DI (match_operand:DI 1 "register_operand" "0")
8713 102 dgisselq
+                       (match_operand:DI 2 "register_operand" "r")))
8714 122 dgisselq
+       (clobber (reg:CC CC_REG))
8715 102 dgisselq
+       ]
8716 200 dgisselq
+       "(ZIP_HAS_DI)"
8717 102 dgisselq
+       "ADD    %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
8718
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8719
+;
8720 200 dgisselq
+;
8721
+;
8722
+; SUB
8723
+;
8724
+;
8725 102 dgisselq
+(define_insn "subdi3"
8726
+       [(set (match_operand:DI 0 "register_operand" "=r")
8727 103 dgisselq
+               (minus:DI (match_operand:DI 1 "register_operand" "0")
8728 102 dgisselq
+                       (match_operand:DI 2 "register_operand" "r")))
8729 122 dgisselq
+       (clobber (reg:CC CC_REG))
8730 102 dgisselq
+       ]
8731 200 dgisselq
+       "(ZIP_HAS_DI)"
8732 102 dgisselq
+       "SUB    %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
8733
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8734
+;
8735 200 dgisselq
+;
8736
+;
8737
+; AND
8738
+;
8739
+;
8740 102 dgisselq
+(define_insn "anddi3"
8741
+       [(set (match_operand:DI 0 "register_operand" "=r")
8742
+               (and:DI (match_operand:DI 1 "register_operand" "%0")
8743
+                       (match_operand:DI 2 "register_operand" "r")))
8744 122 dgisselq
+       (clobber (reg:CC CC_REG))
8745 102 dgisselq
+       ]
8746 200 dgisselq
+       "(ZIP_HAS_DI)"
8747 102 dgisselq
+       "AND    %L2,%L0\n\tAND\t%H2,%H0"
8748
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8749
+;
8750 200 dgisselq
+;
8751
+;
8752
+; iOR
8753
+;
8754
+;
8755 102 dgisselq
+(define_insn "iordi3"
8756
+       [(set (match_operand:DI 0 "register_operand" "=r")
8757
+               (ior:DI (match_operand:DI 1 "register_operand" "%0")
8758
+                       (match_operand:DI 2 "register_operand" "r")))
8759 122 dgisselq
+       (clobber (reg:CC CC_REG))
8760 102 dgisselq
+       ]
8761 200 dgisselq
+       "(ZIP_HAS_DI)"
8762
+       "OR     %L2,%L0\n\tOR\t%H2,%H0"
8763 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8764
+;
8765 200 dgisselq
+;
8766
+;
8767
+; XOR
8768
+;
8769
+;
8770 102 dgisselq
+(define_insn "xordi3"
8771
+       [(set (match_operand:DI 0 "register_operand" "=r")
8772
+               (xor:DI (match_operand:DI 1 "register_operand" "%0")
8773
+                       (match_operand:DI 2 "register_operand" "r")))
8774 122 dgisselq
+       (clobber (reg:CC CC_REG))
8775 102 dgisselq
+       ]
8776 200 dgisselq
+       "(ZIP_HAS_DI)"
8777
+       "XOR    %L2,%L0\n\tXOR\t%H2,%H0"
8778 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8779
+;
8780 200 dgisselq
+;
8781
+;
8782
+; NEG
8783
+;
8784
+;
8785 102 dgisselq
+(define_insn "negdi2"
8786
+       [(set (match_operand:DI 0 "register_operand" "=r")
8787 122 dgisselq
+               (neg:DI (match_operand:DI 1 "register_operand" "0")))
8788
+       (clobber (reg:CC CC_REG))
8789
+       ]
8790 200 dgisselq
+       "(ZIP_HAS_DI)"
8791 102 dgisselq
+       "XOR    -1,%L0\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
8792
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8793
+;
8794 200 dgisselq
+;
8795
+;
8796
+; ABS
8797
+;
8798
+;
8799 102 dgisselq
+(define_insn "absdi2"
8800 122 dgisselq
+       [(set (match_operand:DI 0 "register_operand" "=r")
8801
+               (abs:DI (match_operand:DI 1 "register_operand" "0")))
8802
+       (clobber (match_scratch:SI 2 "=r"))
8803
+       (clobber (reg:CC CC_REG))
8804
+       ]
8805 200 dgisselq
+       "(ZIP_HAS_DI)"
8806 102 dgisselq
+       "CLR    %2
8807
+       TEST    %H0             ; Problem, we can't tell conditions
8808
+       LDILO.LT        1,%2
8809
+       XOR.LT  -1,%L0
8810
+       XOR.LT  -1,%H0
8811
+       ADD     %2,%L0
8812 122 dgisselq
+       ADD.C   1,%H0"
8813 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8814 200 dgisselq
+;
8815
+;
8816
+; NOT
8817
+;
8818
+;
8819 102 dgisselq
+(define_insn "one_cmpldi2"
8820
+       [(set (match_operand:DI 0 "register_operand" "=r")
8821
+               (not:DI (match_operand:DI 1 "register_operand" "0")))
8822 122 dgisselq
+       (clobber (reg:CC CC_REG))
8823 102 dgisselq
+       ]
8824 200 dgisselq
+       "(ZIP_HAS_DI)"
8825 102 dgisselq
+       "XOR    -1,%L0\n\tXOR\t-1,%H0"
8826
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8827 200 dgisselq
+;
8828
+;
8829
+; Unsigned min/max
8830
+;
8831
+;
8832 102 dgisselq
+(define_insn "umindi3"
8833
+       [(set (match_operand:DI 0 "register_operand" "=r")
8834
+               (umin:DI (match_operand:DI 1 "register_operand" "%0")
8835
+                       (match_operand:DI 2 "register_operand" "r")))
8836 122 dgisselq
+       (clobber (reg:CC CC_REG))
8837 102 dgisselq
+       ]
8838 200 dgisselq
+       "(ZIP_HAS_DI)"
8839 102 dgisselq
+       "CMP    %H0,%H2
8840
+       CMP.Z   %L0,%L2
8841
+       MOV.C   %H2,%H0
8842
+       MOV.C   %L2,%L0"
8843
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8844
+(define_insn "umaxdi3"
8845
+       [(set (match_operand:DI 0 "register_operand" "=r")
8846
+               (umax:DI (match_operand:DI 1 "register_operand" "%0")
8847
+                       (match_operand:DI 2 "register_operand" "r")))
8848 122 dgisselq
+       (clobber (reg:CC CC_REG))
8849 102 dgisselq
+       ]
8850 200 dgisselq
+       "(ZIP_HAS_DI)"
8851 102 dgisselq
+       "CMP    %H2,%H0
8852
+       CMP.Z   %L2,%L0
8853
+       MOV.C   %H2,%H0
8854
+       MOV.C   %L2,%L0"
8855
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8856 200 dgisselq
+;
8857
+;
8858
+; POP
8859
+;
8860
+;
8861 102 dgisselq
+(define_insn "popcountdi2"
8862
+       [(set (match_operand:SI 0 "register_operand" "=r")
8863 122 dgisselq
+               (popcount:SI (match_operand:DI 1 "register_operand" "r")))
8864 102 dgisselq
+       (clobber (match_scratch:SI 2 "=r"))
8865 122 dgisselq
+       (clobber (reg:CC CC_REG))
8866 102 dgisselq
+       ]
8867 200 dgisselq
+       "(ZIP_HAS_DI)"
8868 102 dgisselq
+       "POPC   %L1,%0
8869
+       POPC    %H1,%2
8870
+       ADD     %2,%0"
8871
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
8872 200 dgisselq
+;
8873
+;
8874
+; PARITY
8875
+;
8876
+;
8877 102 dgisselq
+(define_expand "paritydi2"
8878
+       [(set (match_operand:SI 0 "register_operand" "=r")
8879
+               (popcount (match_operand:DI 1 "register_operand" "r")))
8880
+       (set (match_dup 0) (and:SI (match_dup 0) (const_int -2)))
8881
+       ])
8882 117 dgisselq
+;(define_insn "extendsidi2"
8883
+;      [(set (match_operand:DI 0 "register_operand" "=r")
8884
+;              (sign_extend:DI (match_operand:SI 0 "register_operand" "r")))]
8885 200 dgisselq
+;      "(ZIP_HAS_DI)"
8886 117 dgisselq
+;      "TEST\t%1\nMOV\t%1,%L0\nCLR\t%L1\nLDI.LT\t-1,%L1"
8887
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8888
+;(define_insn "mulsidi3"
8889
+;      [(set (match_operand:DI 0 "register_operand" "=r")
8890
+;              (mult:SI (match_operand:SI 1 "register_operand" "%r")
8891
+;                      (match_operand:SI 2 "register_operand" "r")))
8892
+;      (clobber (match_scratch:SI 3 "=r"))]
8893
+;      ; "(R0 != R1)&&(R0 != R2)&&(R0!=R3)&&(R1!=R2)&&(R1=R3)&&(R2!=R3)"
8894 200 dgisselq
+;      "(ZIP_HAS_DI)"
8895 117 dgisselq
+;      "MOV    %1,%L0
8896
+;      MPYS    %2,%L0                  ; L0 = R2 * R1
8897
+;      MOV     %1,%3                   ; R3 = R1
8898
+;      ROL     16,%3                   ; R3 = (R1 <<< 16)
8899
+;      MPYS    %2,%3                   ; R3 = (R1 <<< 16) * R2
8900
+;      ROL     16,%3                   ; R3 = upper bits of (R1<<<16)*R2
8901
+;      AND     0x0ffff,%3
8902
+;      ADD     %3,%L0                  ; L0 = L0 + R3 = L0  + (R1>>16)*R2
8903
+;      MOV     %2,%3
8904
+;      ROL     16,%3
8905
+;      MPYS    %1,%3
8906
+;      ROL     16,%3
8907
+;      AND     0x0ffff,%3
8908
+;      ADD     %3,%0"
8909
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8910
+
8911 102 dgisselq
+;
8912
+; Still missing DI instructions for smin:DI, smax:DI, movdicc, adddicc,
8913
+;      mult:di, div:di, divu:di
8914
+;
8915
+;
8916
+;
8917
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8918
+;;
8919
+;; Conditional arithmetic instructions
8920
+;;
8921
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8922
+;
8923
+;
8924
+;
8925
+;
8926
+(define_expand "cstore<mode>4" ; Store 0 or 1 in %0 based on cmp between %2&%3
8927 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 2 "register_operand" "r")
8928
+               (match_operand:ZI 3 "zip_opb_operand_p" "rO")))
8929 102 dgisselq
+       (set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
8930
+                       (match_operator 1 "ordered_comparison_operator"
8931 122 dgisselq
+                                       [(reg:CC CC_REG) (const_int 0)])
8932 102 dgisselq
+                       (const_int 1) (const_int 0)))]
8933
+       ""
8934
+       )
8935
+(define_insn "cstoredi4" ; Store 0 or 1 in %0 based on cmp between %2&%3
8936
+       [(set (match_operand:SI 0 "register_operand" "=r")
8937
+               (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
8938 122 dgisselq
+                       [(match_operand:DI 2 "register_operand" "r")
8939
+                               (match_operand:DI 3 "register_operand" "r")])
8940
+                       (const_int 1) (const_int 0)))
8941
+       (clobber (reg:CC CC_REG))]
8942 200 dgisselq
+       "(ZIP_HAS_DI)"
8943 102 dgisselq
+       {
8944
+               switch(GET_CODE(operands[1])) {
8945
+               case EQ:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
8946
+               case NE:        return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.NZ\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
8947
+               case LTU:       return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n";
8948 200 dgisselq
+               case LEU:
8949
+                       if (ZIP_NEW_CONDITION_CODE)
8950
+                       return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.NC\t1,%0\n";
8951
+                       else
8952
+                       return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
8953 102 dgisselq
+               case GTU:       return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n";
8954 200 dgisselq
+               case GEU:
8955
+                       if (ZIP_NEW_CONDITION_CODE)
8956
+                       return "CLR\t%0\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.NC\t1,%0\n";
8957
+                       else
8958
+                       return "CLR\t%0\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\n";
8959 102 dgisselq
+               default:
8960
+                       gcc_unreachable();
8961
+               }
8962
+       }
8963
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8964
+;
8965
+;
8966
+;
8967
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8968
+;;
8969
+;; Comparison instructions, both compare and test
8970
+;;
8971
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8972
+;
8973
+;
8974
+;
8975
+;; This will only work so well, since the direction of the compare is
8976
+;; important in unsigned compares.
8977
+;;
8978 122 dgisselq
+(define_expand "cmp<mode>"
8979
+       [(set (reg:CC CC_REG) (compare:CC
8980
+               (match_operand:ZI 0 "register_operand" "r")
8981
+               (match_operand:ZI 1 "nonmemory_operand" "")))]
8982 102 dgisselq
+       ""
8983 122 dgisselq
+       {
8984
+               if (!zip_opb_operand_p(operands[1],SImode)) {
8985
+                       if (can_create_pseudo_p()) {
8986
+                               //; fprintf(stderr, "Generating pseudo register for compare\n");
8987
+                               rtx tmp = gen_reg_rtx(SImode);
8988
+                               emit_insn(gen_movsi(tmp,operands[1]));
8989
+                               operands[1] = tmp;
8990
+                       } else FAIL;
8991
+               }
8992
+       })
8993
+(define_insn "cmp<mode>_reg"
8994
+       [(set (reg:CC CC_REG) (compare:CC
8995
+               (match_operand:ZI 0 "register_operand" "r")
8996
+               (match_operand:ZI 1 "zip_opb_single_operand_p" "rO")))]
8997
+       ""
8998 102 dgisselq
+       "CMP\t%1,%0"
8999
+       [(set_attr "ccresult" "set")])
9000
+(define_insn "cmp<mode>_off"
9001 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
9002
+               (match_operand:ZI 0 "register_operand" "r")
9003 146 dgisselq
+               (plus:ZI (match_operand:ZI 1 "register_operand" "r")
9004 122 dgisselq
+                       (match_operand 2 "zip_opb_immv_p" "N"))))]
9005 102 dgisselq
+       ""
9006
+       "CMP\t%2+%1,%0"
9007
+       [(set_attr "ccresult" "set")])
9008
+(define_insn "test<mode>"
9009 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_operand:ZI 0 "register_operand" "r")
9010
+                               (match_operand:ZI 1 "zip_opb_single_operand_p" "rO"))
9011 102 dgisselq
+                       (const_int 0)))]
9012
+       ""
9013
+       "TEST   %1,%0"
9014
+       [(set_attr "ccresult" "set")])
9015
+(define_insn "test<mode>_off"
9016 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
9017
+               (and:ZI (match_operand:ZI 0 "register_operand" "r")
9018
+                       (plus:ZI
9019
+                               (match_operand:ZI 1 "register_operand" "r")
9020
+                               (match_operand:ZI 2 "zip_opb_immv_p" "N")))
9021
+               (const_int 0)))]
9022 102 dgisselq
+       ""
9023
+       "TEST   %2+%1,%0"
9024
+       [(set_attr "ccresult" "set")])
9025
+(define_insn "nop"
9026
+       [(const_int 0)]
9027
+       ""
9028
+       "NOOP"
9029
+       [(set_attr "ccresult" "unchanged")])
9030
+;
9031
+;
9032
+;
9033
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9034
+;;
9035
+;; Conditional execution predicates
9036
+;;
9037
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9038
+;
9039
+; Sadly, these aren't complete like they should be.  Although these are all of
9040
+; the conditional execution prefixes that the Zip CPU supports, GCC looks for
9041
+; other conditions then these.  That is, (cond_exec ...) is not as well
9042
+; recognized as (if_then_else ...).  So we have to duplicate things to support
9043
+; both methods.
9044
+;
9045
+(define_cond_exec
9046 122 dgisselq
+       [(ne (reg:CC CC_REG) (const_int 0))]
9047 102 dgisselq
+       ""
9048
+       "(NZ)"
9049
+       [(set_attr "conditional" "yes")])
9050
+(define_cond_exec
9051 122 dgisselq
+       [(lt (reg:CC CC_REG) (const_int 0))]
9052 102 dgisselq
+       ""
9053
+       "(LT)"
9054
+       [(set_attr "conditional" "yes")])
9055
+(define_cond_exec
9056 122 dgisselq
+       [(eq (reg:CC CC_REG) (const_int 0))]
9057 102 dgisselq
+       ""
9058
+       "(Z)"
9059
+       [(set_attr "conditional" "yes")])
9060
+(define_cond_exec
9061 122 dgisselq
+       [(gt (reg:CC CC_REG) (const_int 0))]
9062 102 dgisselq
+       ""
9063
+       "(GT)"
9064
+       [(set_attr "conditional" "yes")])
9065
+(define_cond_exec
9066 200 dgisselq
+       [(geu (reg:CC CC_REG) (const_int 0))]
9067
+       "(ZIP_NEW_CONDITION_CODE)"
9068
+       "(NC)"
9069
+       [(set_attr "conditional" "yes")])
9070
+(define_cond_exec
9071 122 dgisselq
+       [(ge (reg:CC CC_REG) (const_int 0))]
9072 200 dgisselq
+       "(!ZIP_NEW_CONDITION_CODE)"
9073 102 dgisselq
+       "(GE)"
9074
+       [(set_attr "conditional" "yes")])
9075
+(define_cond_exec
9076 122 dgisselq
+       [(ltu (reg:CC CC_REG) (const_int 0))]
9077 102 dgisselq
+       ""
9078
+       "(C)"
9079
+       [(set_attr "conditional" "yes")])
9080
+;
9081
+;
9082
+;
9083
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9084
+;;
9085
+;; Conditional move instructions, since these won't accept conditional
9086
+;;     execution RTL
9087
+;;
9088
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9089
+;
9090
+; // Look for #define HAVE_conditional_move to understand how these might be
9091
+; // used.
9092
+;
9093
+(define_insn "set_zero_or_one<mode>"
9094
+       [(set (match_operand:ZI 0 "register_operand" "=r") (if_then_else:ZI
9095
+                       (match_operator 1 "ordered_comparison_operator"
9096 122 dgisselq
+                                       [(reg:CC CC_REG) (const_int 0)])
9097 102 dgisselq
+                       (const_int 1) (const_int 0)))]
9098
+       ""
9099
+       { return (zip_set_zero_or_one(operands[1], operands[0]));
9100
+       }
9101
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9102 127 dgisselq
+(define_expand "mov<mode>cc"
9103 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
9104 127 dgisselq
+               (if_then_else:ZI (match_operand 1 "comparison_operator")
9105 102 dgisselq
+                       (match_operand:ZI 2 "general_operand" "rio")
9106
+                       (match_operand:ZI 3 "nonmemory_operand" "rio")))]
9107
+       ""
9108
+       {
9109 142 dgisselq
+       if (zip_expand_movsicc(operands[0], operands[1], operands[2], operands[3]))
9110
+               DONE;
9111
+       else
9112
+               FAIL;
9113 127 dgisselq
+       })
9114
+(define_insn_and_split "movsicc_bare"
9115
+       [(set (match_operand:SI 0 "register_operand" "=r")
9116 191 dgisselq
+               (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
9117 127 dgisselq
+                               [(reg:CC CC_REG) (const_int 0)])
9118
+                       (match_operand:SI 2 "general_operand" "rio")
9119
+                       (match_operand:SI 3 "register_operand" "0")))]
9120
+       "(zip_supported_condition(GET_CODE(operands[1])))"
9121
+       "#"
9122
+       "(reload_completed)"
9123
+       [(cond_exec (match_operator 1 "ordered_comparison_operator"
9124
+                               [(reg:CC CC_REG) (const_int 0)])
9125
+                       (set (match_dup 0) (match_dup 2)))]
9126
+       "" [(set_attr "predicable" "no")])
9127 102 dgisselq
+;
9128
+;
9129 192 dgisselq
+; Dies when trying to do reloads for "ADD.NZ R6,R7,R9"
9130 102 dgisselq
+;
9131 192 dgisselq
+;(define_insn "add<mode>cc"
9132
+;      [(set (match_operand:ZI 0 "register_operand" "=r,r")
9133
+;              (if_then_else:ZI (match_operator 1 "ordered_comparison_operator"
9134
+;                      [(reg:CC CC_REG) (const_int 0)])
9135
+;                      (plus:ZI (match_operand:ZI 2 "register_operand" "0,r")
9136
+;                              (match_operand:ZI 3 "nonmemory_operand" "rO,M"))
9137
+;                      (match_operand:ZI 4 "register_operand" "0,0")))]
9138
+;      ""
9139
+;      {
9140
+;      return zip_addsicc(operands[0], operands[1], operands[2], operands[3]);
9141
+;      }
9142
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9143
+;
9144
+
9145
+;
9146
+;
9147 102 dgisselq
+; While an interesting approach, the following suffers from problems when the
9148
+; move amount is constant.  At anything less than four, moves should not require
9149
+; the movmemSI instruction.  At anything greater, if constant, the initial tests
9150
+; are not required and should result in a hardcoded result.  Practically,
9151
+; though, this should really be a define_expand instruction, calling on the
9152 127 dgisselq
+; RTX's of all the respective subinstructions found below.  Or, perhaps, it is
9153
+; better as a subroutine?
9154 102 dgisselq
+;
9155
+;(define_insn "movmemSI"
9156
+;      [(parallel [(set (mem:BLK (match_operand 0 "register_operand" "+r"));Dst
9157
+;                      (mem:BLK (match_operand 1 "register_operand" "+r")));Src
9158
+;              (use (match_operand:SI 2 "register_operand" "+r"))]); Length
9159
+;              (match_operand 3 "" "")                 ;Alignment
9160
+;              (clobber (match_scratch:SI 4 "=r"))
9161
+;              (clobber (match_scratch:SI 5 "=r"))
9162
+;              (clobber (match_scratch:SI 6 "=r"))
9163
+;              (clobber (match_scratch:SI 7 "=r"))]
9164
+;      ""
9165
+;      "TEST\t1,%2
9166
+;      LOD.NZ\t%1,%4
9167
+;      STO.NZ\t%4,%0
9168
+;      ADD.NZ\t1,%0
9169
+;      ADD.NZ\t1,%1
9170
+;      TEST\t2,%2
9171
+;      LOD.NZ\t%1,%4
9172
+;      LOD.NZ\t1(%1),%5
9173
+;      STO.NZ\t%4,(%0)
9174
+;      STO.NZ\t%4,1(%0)
9175
+;      ADD.NZ\t2,%0
9176
+;      ADD.NZ\t2,%1
9177
+;      AND\t-4,%2
9178
+;      BZ\t.Lskp%=\n.Ltop%=:
9179
+;      LOD\t(%1),%4
9180
+;      LOD\t1(%1),%5
9181
+;      LOD\t2(%1,%6
9182
+;      LOD\t3(%1),%7
9183
+;      STO\t%4,(%1)
9184
+;      STO\t%5,1(%1)
9185
+;      STO\t%6,2(%1)
9186
+;      STO\t%7,3(%1)
9187
+;      SUB\t4,%2
9188
+;      BZ\t%.Lskp%=
9189
+;      BRA\t.Ltop%=\n.Lskp%=:"
9190
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9191
+;(define_insn "setmemsi"
9192
+;      [(parallel
9193
+;              [(set (mem:BLK
9194
+;                      (match_operand 0 "register_operand" "+r")); Destination
9195
+;                      (match_operand:SI 2 "register_operand" "r")) ; Source
9196
+;              (use (match_operand:SI 1 "register_operand" "+r"))])  ; Length
9197
+;              (match_operand 3 "" "")]
9198
+;      ""
9199
+;      "TEST\t1,%1
9200
+;      STO.NZ\t%2,(%0)
9201
+;      ADD.NZ\t1,%0
9202
+;      TEST\t2,%1
9203
+;      STO.NZ\t%2,(%0)
9204
+;      STO.NZ\t%2,1(%0)
9205
+;      ADD.NZ\t2,%0
9206
+;      AND\t-4,%1
9207
+;      BZ\t.Lskp%=\n.Ltop%=:\n
9208
+;      STO\t%2,(%0)
9209
+;      STO\t%2,1(%0)
9210
+;      STO\t%2,2(%0)
9211
+;      STO\t%2,3(%0)
9212
+;      SUB\t%4,%0
9213
+;      BZ\t.Lskp%=
9214
+;      BRA\t.Ltop%=\n.Lskp%=:"
9215
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9216
+;;
9217
+;
9218
+;
9219
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9220
+;;
9221
+;; Control flow instructions
9222
+;;
9223
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9224
+;
9225
+;
9226
+;
9227
+(define_expand "jump"
9228
+       [(set (pc)
9229
+               (label_ref (match_operand 0 "" "")))]); // Was general-op, "mro"
9230 127 dgisselq
+(define_insn "jump_const"
9231
+       [(set (pc)
9232 102 dgisselq
+               (match_operand:SI 0 "zip_const_address_operand_p" ""))]
9233
+       ""
9234
+       "BRA    %0"
9235
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9236
+(define_insn "jump_label"      ; Must be modeless, VOIDmode, not SI or any othr
9237
+       [(set (pc)      ; Otherwise it won't accept jumps to labels
9238
+               (label_ref (match_operand 0 "" "")))]
9239
+       ""
9240
+       "BRA    %0"
9241
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9242
+;
9243
+; This is really the same thing as an indirect jump ... the big difference
9244
+; is that the zip_address_operand_p checks for an "N" type condition, not an
9245
+; "M" type condition ... a bug, but one that works for now.  (The assembler
9246
+; should be able to catch and except on it ...)
9247
+;
9248
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
9249
+(define_insn "jump_variable"
9250
+       [(set (pc)
9251
+               (match_operand:SI 0 "zip_address_operand_p" ""))]
9252
+       ""
9253
+       "JMP    %0"
9254
+       [(set_attr "ccresult" "unchanged")])
9255
+;
9256
+; Indirect jumps ... both to registers, and registers plus offsets
9257
+;
9258
+(define_insn "indirect_jump"
9259
+       [(set (pc)
9260
+               (match_operand:SI 0 "register_operand" "r"))]
9261
+       ""
9262
+       "JMP    %0"
9263
+       [(set_attr "ccresult" "unchanged")])
9264
+(define_insn "indirect_jump_mem"
9265
+       [(set (pc) (match_operand:SI 0 "zip_memory_operand_p" "o"))]
9266
+       ""
9267
+       "LOD    %0,PC"
9268
+       [(set_attr "ccresult" "unchanged")])
9269
+(define_insn "indirect_jump_off"
9270
+       [(set (pc)
9271
+               (plus:SI (match_operand:SI 0 "register_operand" "r")
9272
+                       (match_operand:SI 1 "const_int_operand" "M")))]
9273
+       ""
9274
+       "JMP    %1(%0)"
9275
+       [(set_attr "ccresult" "unchanged")])
9276
+;;
9277
+; cbranchsi4
9278
+;;     Op 0 = the comparison operator (le,lt,eq,ne,gt,ge,and usgn ltu,geu,etc.)
9279
+;;     Op 1&2 the operands of the compare instruction
9280
+;;     Op 3 is the jump label
9281
+;;
9282
+;;
9283
+;;
9284
+(define_expand "cbranch<mode>4"
9285 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (match_operand:ZI 1 "register_operand" "r")
9286
+               (match_operand:ZI 2 "zip_opb_operand_p" "rO")))
9287 102 dgisselq
+       (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator"
9288 122 dgisselq
+                       [(reg:CC CC_REG) (const_int 0)])
9289 102 dgisselq
+                       (label_ref (match_operand 3 "" ""))
9290
+                       (pc)))]
9291
+       ""
9292
+       {
9293 125 dgisselq
+               if (true) {
9294 117 dgisselq
+               extern void zip_debug_rtx_pfx(const char *, const_rtx);
9295 102 dgisselq
+               //; Two branches give us no end of difficulty when implementing.
9296
+               //; Let's check for these two branch codes, and swap the
9297
+               //; comparison to simplify them.
9298 122 dgisselq
+               //; fprintf(stderr, "CBRANCH\n");
9299
+               //; zip_debug_rtx_pfx("- CMP: ", operands[0]);
9300
+               //; zip_debug_rtx_pfx("- A  : ", operands[1]);
9301
+               //; zip_debug_rtx_pfx("- B  : ", operands[2]);
9302
+               //; zip_debug_rtx_pfx("- JMP: ", operands[3]);
9303 117 dgisselq
+               //; Can we do better if we reverse some compares?
9304 102 dgisselq
+               if ((GET_CODE(operands[0])==GTU)&&(REG_P(operands[2]))) {
9305 122 dgisselq
+                       //; fprintf(stderr, "CBRANCH:(GTU,?,REG,?)\n");
9306
+                       emit_insn(gen_cmpsi(operands[2], operands[1]));
9307 102 dgisselq
+                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
9308
+                       DONE;
9309
+               } else if((GET_CODE(operands[0])==GEU)&&(REG_P(operands[2]))) {
9310 122 dgisselq
+                       //; fprintf(stderr, "CBRANCH:(GEU,?,REG,?)\n");
9311 200 dgisselq
+                       if (ZIP_NEW_CONDITION_CODE) {
9312
+                               emit_insn(gen_cmpsi(operands[1], operands[2]));
9313
+                               emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
9314
+                       } else {
9315
+                               emit_insn(gen_cmpsi_off(operands[2], operands[1],
9316 122 dgisselq
+                                       GEN_INT(1)));
9317 200 dgisselq
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
9318
+                       }
9319 102 dgisselq
+                       DONE;
9320 117 dgisselq
+               } else if ((GET_CODE(operands[0])==LE)&&(REG_P(operands[2]))) {
9321 122 dgisselq
+                       //; fprintf(stderr, "CBRANCH:(LE,?,REG,?)\n");
9322 117 dgisselq
+                       //; Swap operands, turn into a GTE compare
9323 200 dgisselq
+                       if (ZIP_NEW_CONDITION_CODE) {
9324
+                               emit_insn(gen_cmpsi_off(operands[1], operands[2],
9325
+                                       GEN_INT(1)));
9326
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
9327
+                       } else {
9328
+                               emit_insn(gen_cmpsi(operands[2], operands[1]));
9329
+                               emit_jump_insn(gen_cbranch_jmp_ge(operands[3]));
9330
+                       }
9331 117 dgisselq
+                       DONE;
9332 102 dgisselq
+               } // ; Otherwise ... just handle the branch normally
9333
+
9334
+               //; Except ... we can do better for some instructions, such as
9335
+               //; LE.  While we could exchange CMP Rx,Ry into -1(Rx),Ry, it
9336
+               //; would be difficult to explain to users why MIN_INT didn't
9337
+               //; compare properly.  Hence we only adjust constant integers.
9338
+               //;
9339 122 dgisselq
+               if (GET_CODE(operands[0])==LE) {
9340
+                       if ((CONST_INT_P(operands[2]))
9341 117 dgisselq
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
9342 122 dgisselq
+                               //; fprintf(stderr, "CBRANCH:(LE,?,#,?)\n");
9343
+                               emit_insn(gen_cmpsi(operands[1],
9344
+                                               GEN_INT(INTVAL(operands[2])+1)));
9345
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
9346
+                               DONE;
9347
+                       //; Now for the controversial ones--where we add one
9348
+                       //; when it may or may not be permissable.  For now, we
9349
+                       //; just do it anyway and postpone the philosophical
9350
+                       //; discussion for later.
9351
+                       } else if (REG_P(operands[2])) {
9352
+                               emit_insn(gen_cmpsi_off(operands[1],
9353
+                                               operands[2],GEN_INT(1)));
9354
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
9355
+                               DONE;
9356
+                       } else if ((GET_CODE(operands[2])==PLUS)
9357
+                               &&(REG_P(XEXP(operands[2],0)))
9358
+                               &&(CONST_INT_P(XEXP(operands[2],1)))
9359
+                               &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
9360
+                               emit_insn(gen_cmpsi_off(operands[1],
9361
+                                               XEXP(operands[2],0),
9362
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
9363
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
9364
+                               DONE;
9365
+                       }
9366 200 dgisselq
+#if (ZIP_NEW_CONDITION_CODE != 0)
9367
+               } else if (GET_CODE(operands[0])==GE) {
9368
+                       if ((CONST_INT_P(operands[2]))
9369
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
9370
+                               //; fprintf(stderr, "CBRANCH:(LE,?,#,?)\n");
9371
+                               emit_insn(gen_cmpsi(operands[1],
9372
+                                               GEN_INT(INTVAL(operands[2])+1)));
9373
+                               emit_jump_insn(gen_cbranch_jmp_gt(operands[3]));
9374
+                               DONE;
9375
+                       //; Now for the controversial ones--where we add one
9376
+                       //; when it may or may not be permissable.  For now, we
9377
+                       //; just do it anyway and postpone the philosophical
9378
+                       //; discussion for later.
9379
+                       } else if (REG_P(operands[2])) {
9380
+                               emit_insn(gen_cmpsi_off(operands[1],
9381
+                                               operands[2],GEN_INT(1)));
9382
+                               emit_jump_insn(gen_cbranch_jmp_gt(operands[3]));
9383
+                               DONE;
9384
+                       } else if ((GET_CODE(operands[2])==PLUS)
9385
+                               &&(REG_P(XEXP(operands[2],0)))
9386
+                               &&(CONST_INT_P(XEXP(operands[2],1)))
9387
+                               &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
9388
+                               emit_insn(gen_cmpsi_off(operands[1],
9389
+                                               XEXP(operands[2],0),
9390
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
9391
+                               emit_jump_insn(gen_cbranch_jmp_gt(operands[3]));
9392
+                               DONE;
9393
+                       }
9394
+#endif
9395 122 dgisselq
+               } else if (GET_CODE(operands[0])==LEU) {
9396 200 dgisselq
+#if (ZIP_NEW_CONDITION_CODE != 0)
9397
+                       emit_insn(gen_cmpsi(operands[1], operands[2]));
9398
+                       emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
9399
+#else
9400 122 dgisselq
+                       if ((CONST_INT_P(operands[2]))
9401 102 dgisselq
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
9402 122 dgisselq
+                               //; fprintf(stderr, "CBRANCH:(LEU,?,#,?)\n");
9403
+                               emit_insn(gen_cmpsi(operands[1],
9404
+                                               GEN_INT(INTVAL(operands[2])+1)));
9405
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
9406
+                               DONE;
9407
+                       //; Now for the controversial ones--this time having
9408
+                       //; to do with unsigned compares.
9409
+                       } else if (REG_P(operands[2])) {
9410
+                               emit_insn(gen_cmpsi_off(operands[1],
9411
+                                                       operands[2],GEN_INT(1)));
9412
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
9413
+                               DONE;
9414
+                       } else if ((GET_CODE(operands[2])==PLUS)
9415
+                               &&(REG_P(XEXP(operands[2],0)))
9416
+                               &&(CONST_INT_P(XEXP(operands[2],1)))
9417
+                               &&(INTVAL(XEXP(operands[2],1))<((1<<13)-2))) {
9418
+                               emit_insn(gen_cmpsi_off(operands[1],
9419
+                                       XEXP(operands[2],0),
9420
+                                       GEN_INT(INTVAL(XEXP(operands[2],1))+1)));
9421
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
9422
+                               DONE;
9423
+                       }
9424 200 dgisselq
+#endif
9425 124 dgisselq
+               }}
9426 102 dgisselq
+       })
9427
+(define_insn "cbranch_jmp_eq"
9428 122 dgisselq
+       [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
9429 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9430
+                (pc)))]
9431
+       ""
9432
+       "BZ\t%0"
9433
+       [(set_attr "predicable" "no")
9434
+               (set_attr "conditional" "yes")
9435
+               (set_attr "ccresult" "unchanged")])
9436
+(define_insn "cbranch_jmp_neq"
9437 122 dgisselq
+       [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0))
9438 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9439
+                (pc)))]
9440
+       ""
9441
+       "BNZ\t%0"
9442
+       [(set_attr "predicable" "no")
9443
+               (set_attr "conditional" "yes")
9444
+               (set_attr "ccresult" "unchanged")])
9445
+(define_insn "cbranch_jmp_lt"
9446 122 dgisselq
+       [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
9447 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9448
+                (pc)))]
9449
+       ""
9450
+       "BLT\t%0"
9451
+       [(set_attr "predicable" "no")
9452
+               (set_attr "conditional" "yes")
9453
+               (set_attr "ccresult" "unchanged")])
9454
+(define_insn "cbranch_jmp_le"
9455 122 dgisselq
+       [(set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
9456 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9457
+                (pc)))]
9458
+       ""
9459
+       "BLT\t%0
9460
+       BZ\t%0"
9461
+       [(set_attr "predicable" "no")
9462
+               (set_attr "conditional" "yes")
9463
+               (set_attr "ccresult" "unchanged")])
9464
+(define_insn "cbranch_jmp_gt"
9465 122 dgisselq
+       [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0))
9466 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9467
+                (pc)))]
9468
+       ""
9469
+       "BGT\t%0"
9470
+       [(set_attr "predicable" "no")
9471
+               (set_attr "conditional" "yes")
9472
+               (set_attr "ccresult" "unchanged")])
9473 200 dgisselq
+(define_expand "cbranch_jmp_ge"
9474 122 dgisselq
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
9475 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9476 200 dgisselq
+                (pc)))])
9477
+(define_insn "cbranch_jmp_ge_newcc"
9478
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
9479
+                (label_ref (match_operand 0 "" ""))
9480 102 dgisselq
+                (pc)))]
9481 200 dgisselq
+       "(ZIP_NEW_CONDITION_CODE)"
9482
+       "BGT\t%0\n\tBZ\t%0"
9483
+       [(set_attr "predicable" "no")
9484
+               (set_attr "conditional" "yes")
9485
+               (set_attr "ccresult" "unchanged")])
9486
+(define_insn "cbranch_jmp_ge_oldcc"
9487
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
9488
+                (label_ref (match_operand 0 "" ""))
9489
+                (pc)))]
9490
+       "(!ZIP_NEW_CONDITION_CODE)"
9491 102 dgisselq
+       "BGE\t%0"
9492
+       [(set_attr "predicable" "no")
9493
+               (set_attr "conditional" "yes")
9494
+               (set_attr "ccresult" "unchanged")])
9495
+(define_insn "cbranch_jmp_ltu"
9496 122 dgisselq
+       [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
9497 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9498
+                (pc)))]
9499
+       ""
9500
+       "BC\t%0"
9501
+       [(set_attr "predicable" "no")
9502
+               (set_attr "conditional" "yes")
9503
+               (set_attr "ccresult" "unchanged")])
9504 200 dgisselq
+(define_expand "cbranch_jmp_gtu"
9505 122 dgisselq
+       [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
9506 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9507 200 dgisselq
+                (pc)))])
9508
+(define_insn "cbranch_jmp_gtu_newcc"
9509
+       [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
9510
+                (label_ref (match_operand 0 "" ""))
9511
+                (pc)))]
9512
+       "(ZIP_NEW_CONDITION_CODE)"
9513
+       ;// We could flip the condition code, and then be able to jump.
9514
+       ;// The problem is that doing this adjusts the condition code, and
9515
+       ;// we aren't allowed to do that here.
9516
+       ;//
9517
+       ;// The problem here is the equals.  What do you do if A=B?  Our new
9518
+       ;// condition tests for A>=B, not A>B.  So ... how do you get rid of
9519
+       ;// the equals?  We do so here by branching around. (sigh)
9520
+       "BZ\t.Lgtu%=\n\tBNC\t%0\n.Lgtu%=:"
9521
+       [(set_attr "predicable" "no")
9522
+               (set_attr "conditional" "yes")
9523
+               (set_attr "ccresult" "unknown")])
9524
+(define_insn "cbranch_jmp_gtu_oldcc"
9525
+       [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
9526
+                (label_ref (match_operand 0 "" ""))
9527
+                (pc)))]
9528
+       "(!ZIP_NEW_CONDITION_CODE)"
9529
+       ;// We could flip the condition code, and then be able to jump.
9530
+       ;// The problem is that doing this adjusts the condition code, and
9531
+       ;// we aren't allowed to do that here.
9532
+       ;//
9533
+       ;// With the old condition code, things are worse.  Sure, we still need
9534
+       ;// to branch around, but it's worse 'cause we are always branching
9535
+       ;// around the conditional branch.  With the new condition code, we
9536
+       ;// only branch around on part of the unsupported condition.
9537 127 dgisselq
+       "BC\t.Lgtu%=\n\tBZ\t.Lgtu%=\n\tBRA\t%0\n.Lgtu%=:"
9538 102 dgisselq
+       [(set_attr "predicable" "no")
9539
+               (set_attr "conditional" "yes")
9540
+               (set_attr "ccresult" "unknown")])
9541
+(define_insn "cbranch_jmp_leu"
9542 122 dgisselq
+       [(set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
9543 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9544
+                (pc)))]
9545
+       ""      ; Need to check for both LTU (i.e. C) and Z
9546
+       "BC\t%0
9547
+       BZ\t%0"
9548
+       [(set_attr "predicable" "no")
9549
+               (set_attr "conditional" "yes")
9550
+               (set_attr "ccresult" "unchanged")])
9551 200 dgisselq
+(define_expand "cbranch_jmp_geu"
9552 122 dgisselq
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
9553 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9554 200 dgisselq
+                (pc)))])
9555
+(define_insn "cbranch_jmp_geu_newcc"
9556
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
9557
+                (label_ref (match_operand 0 "" ""))
9558
+                (pc)))]
9559
+       "(ZIP_NEW_CONDITION_CODE)"
9560
+       "BNC\t%0"
9561
+       [(set_attr "predicable" "no")
9562
+               (set_attr "conditional" "yes")
9563
+               (set_attr "ccresult" "unchanged")])
9564
+(define_insn "cbranch_jmp_geu_oldcc"
9565
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
9566
+                (label_ref (match_operand 0 "" ""))
9567
+                (pc)))]
9568
+       "(!ZIP_NEW_CONDITION_CODE)"
9569 127 dgisselq
+       "BC\t.Lgeu%=\n\tBRA\t%0\n.Lgeu%=:"
9570 102 dgisselq
+       [(set_attr "predicable" "no")
9571
+               (set_attr "conditional" "yes")
9572 200 dgisselq
+               (set_attr "ccresult" "unchanged")])
9573 102 dgisselq
+(define_insn "cbranchdi4"
9574
+       [(set (pc) (if_then_else
9575
+               (match_operator 0 "ordered_comparison_operator"
9576
+                       [(match_operand:DI 1 "register_operand" "r")
9577 122 dgisselq
+                               (match_operand:DI 2 "register_operand" "r")])
9578 102 dgisselq
+                       (label_ref (match_operand 3 "" ""))
9579
+                       (pc)))
9580 122 dgisselq
+       (clobber (reg:CC CC_REG))]
9581 200 dgisselq
+       "(ZIP_HAS_DI)"
9582 102 dgisselq
+       {
9583
+               switch(GET_CODE(operands[0])) {
9584
+               case EQ:
9585
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
9586
+               case NE:
9587
+                       return "CMP\t%H2,%H1\n\tCMP.NZ\t%L2,%L1\n\tBNZ\t%3";
9588
+               case LE:
9589 200 dgisselq
+                       if (ZIP_NEW_CONDITION_CODE)
9590
+                       return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBNC\t%3\n.Ldi%=:";
9591
+                       else
9592
+                       return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3\n.Ldi%=";
9593 102 dgisselq
+               case GT:
9594
+                       return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\n.Ldi%=:";
9595
+               case LT:
9596
+                       return "CMP\t%H2,%H1\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBC\t%3\n.Ldi%=:";
9597
+               case GE:
9598 200 dgisselq
+                       if (ZIP_NEW_CONDITION_CODE)
9599
+                       return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L2,%L1\n\tBNC\t%3\n.Ldi%=:";
9600
+                       else
9601 102 dgisselq
+                       return "CMP\t%H1,%H2\n\tBLT\t%3\n\tBNZ\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBC\t%3\nBZ\t%3\n.Ldi%=:";
9602
+               case LTU:
9603
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n";
9604
+               case LEU:
9605 200 dgisselq
+                       if (ZIP_NEW_CONDITION_CODE)
9606
+                       return "CMP\t%H1,%H2\n\tBC\t.Ldi%=\n\tCMP\t%L1,%L2\n\tBNC\t%3\n.Ldi%=:";
9607
+                       else
9608 102 dgisselq
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBC\t%3\n\tBZ\t%3";
9609
+               case GTU:
9610 200 dgisselq
+                       return "CMP\t%H1,%H2\n\tBC\t%3\nBNZ\t%.Ldi%=\nCMP\t%L1,%L2\n\tBC\t%3\n.Ldi%=:";
9611 102 dgisselq
+               case GEU:
9612 200 dgisselq
+                       if (ZIP_NEW_CONDITION_CODE)
9613
+                       return "CMP\t%H2,%H1\n\tCMP.Z\t%L2,%L1\n\tBNC\t%3";
9614
+                       else
9615 102 dgisselq
+                       return "CMP\t%H1,%H2\n\tCMP.Z\t%L1,%L2\n\tBC\t%3\nBZ\t%3";
9616
+               default:
9617
+                       gcc_unreachable();
9618
+               }
9619
+       }
9620
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9621
+;
9622
+;
9623
+;
9624
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9625
+;;
9626 191 dgisselq
+;; Looping constructs
9627
+;;
9628
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9629
+;
9630
+;
9631
+;
9632
+(define_insn "decrement_and_branch_until_zero"
9633
+       [(set (pc)
9634
+               (if_then_else
9635
+                       (ge (plus:SI (match_operand:SI 0 "register_operand" "+r")
9636
+                               (const_int -1)) (const_int 0))
9637
+                       (label_ref (match_operand 1 "" ""))
9638
+                       (pc)))
9639
+       (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
9640
+       ;(set (reg:CC CC_REG)
9641
+               ;(compare:CC (minus:SI (match_dup 0) (const_int 1))
9642
+                       ;(const_int 0)))
9643
+       (clobber (reg:CC CC_REG))]
9644
+       ""
9645
+       "ADD\t-1,%0\n\tBLT\t.Ldec%=\n\tBRA\t%1\n.Ldec%=:"
9646
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9647
+;
9648
+;
9649
+(define_insn "doloop_end"
9650
+       [(set (pc)
9651
+               (if_then_else
9652
+                       (ne (plus:SI (match_operand:SI 0 "register_operand" "+r")
9653
+                               (const_int -1)) (const_int 0))
9654
+                       (label_ref (match_operand 1 "" ""))
9655
+                       (pc)))
9656
+       (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
9657
+       ; (set (reg:CC CC_REG)
9658
+               ; (compare:CC (minus:SI (match_dup 0) (const_int 1))
9659
+                       ; (const_int 0)))
9660
+       (clobber (reg:CC CC_REG))]
9661
+       "(reload_completed)"
9662
+       "ADD\t-1,%0\n\tBZ\t.Lloop%=\n\tBRA\t%1\n.Lloop%=:"
9663
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9664
+;
9665
+; Since we have a doloop_end, we must also have a doloop_begin.  Since the
9666
+; ZipCPU has no special begin looping instruction, we'll simply define this
9667
+; as a null instruction.
9668
+(define_expand "doloop_begin" [(const_int 0)] "(0)")
9669
+;
9670
+;
9671
+;
9672
+;
9673
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9674
+;;
9675 102 dgisselq
+;; Subroutine call
9676
+;;
9677
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9678
+;
9679
+;
9680
+; There are two types of calls: "call" and "call_value".
9681
+;
9682
+; Each of these types of calls are then expanded into one of:
9683
+;
9684
+;      _const          - A call to a constant address, such as a symbol
9685
+;                      reference or a fixed location
9686
+;
9687
+;      _label          - This should be the same as _const, except that for
9688
+;                      some reason the RTL and matching rules are separate.
9689
+;                      Hence we have a separate rule for this.
9690
+;
9691
+;      _mem            - The memory address we wish to jump to is stored in
9692
+;                      memory somewhere, and we have only a pointer.  In this
9693
+;                      case, we load that pointer straight to the PC and go.
9694
+;
9695
+;      _var            - The address to jump to is given as an offset to a
9696
+;                      register, such as X+R3.  This is an indirect jump.
9697
+;                      Although we support it, it does require different RTL
9698
+;                      code.
9699
+;
9700
+(define_expand "call"
9701
+       [(call (match_operand 0 "" "")
9702
+               (match_operand 1 "" ""))]
9703
+       ""
9704
+       {
9705
+               if (MEM_P(operands[0])) {
9706
+                       // This should always be the case
9707
+                       rtx addr = XEXP(operands[0],0);
9708
+                       if (zip_const_address_operand_p(addr, SImode)) {
9709 122 dgisselq
+                               //; fprintf(stderr, "Generating gen_void_call_const()\n");
9710 102 dgisselq
+                               emit_call_insn(gen_void_call_const(addr,
9711
+                                               operands[1]));
9712
+                       } else if ((MEM_P(addr))&&(zip_address_operand(
9713
+                                                       XEXP(addr,0)))) {
9714
+                               emit_call_insn(gen_void_call_mem(XEXP(addr,0),
9715
+                                                                operands[1]));
9716
+                       } else {
9717
+                               emit_call_insn(gen_void_call_var(addr,
9718
+                                                                operands[1]));
9719
+                       }
9720
+                       DONE;
9721
+               }
9722
+       })
9723
+;
9724 191 dgisselq
+(define_expand "sibcall"
9725
+       [(call (mem:SI (match_operand 0 "zip_const_address_operand_p" ""))
9726
+               (match_operand 1 "" ""))
9727
+       (use (match_operand 2 "" ""))
9728
+       (use (reg:SI RTN_REG))
9729
+       (simple_return)]
9730
+       ""
9731
+       {
9732
+               if (MEM_P(operands[0])) {
9733
+                       // This should always be the case
9734
+                       rtx addr = XEXP(operands[0],0);
9735
+                       if (zip_const_address_operand_p(addr, SImode)) {
9736
+                               //; fprintf(stderr, "Generating gen_void_call_const()\n");
9737
+                               emit_call_insn(gen_void_sibcall_const(addr,
9738
+                                               operands[1]));
9739
+                       } else if ((MEM_P(addr))&&(zip_address_operand(
9740
+                                                       XEXP(addr,0)))) {
9741
+                               emit_call_insn(gen_void_sibcall_mem(XEXP(addr,0),
9742
+                                                                operands[1]));
9743
+                       } else {
9744
+                               emit_call_insn(gen_void_sibcall_var(addr,
9745
+                                                                operands[1]));
9746
+                       }
9747
+                       DONE;
9748
+               }
9749
+       }) ; "BAR\t%0\n"
9750 102 dgisselq
+;
9751 191 dgisselq
+(define_insn "void_sibcall_const"
9752
+       [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
9753
+                       (match_operand 1 "const_int_operand" "n"))
9754
+               (use (reg:SI RTN_REG))
9755
+               (clobber (reg:CC CC_REG))
9756
+               (simple_return)]
9757
+       ""
9758
+       "BRA\t%0"
9759
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9760
+(define_insn "void_sibcall_mem"
9761
+       [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
9762
+                       (match_operand 1 "const_int_operand" "n"))
9763
+               (use (reg:SI RTN_REG))
9764
+               (clobber (reg:CC CC_REG))
9765
+               (simple_return)]
9766
+       ""
9767
+       "LOD\t%0,PC"
9768
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9769 102 dgisselq
+;
9770 191 dgisselq
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
9771
+(define_insn "void_sibcall_var"
9772
+       [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
9773
+                       (match_operand 1 "const_int_operand" "n"))
9774
+               (use (reg:SI RTN_REG))
9775
+               (clobber (reg:CC CC_REG))
9776
+               (simple_return)]
9777
+       ""
9778
+       "JMP\t%0"
9779
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9780
+;
9781
+(define_expand "sibcall_value"
9782
+       [(set (match_operand 0 "register_operand" "")
9783
+               (call (mem:SI
9784
+                       (match_operand 1 "zip_const_address_operand_p" ""))
9785
+               (match_operand 2 "" "")))
9786
+       (use (match_operand 3 "" ""))
9787
+       (use (reg:SI RTN_REG))
9788
+       (clobber (reg:CC CC_REG))
9789
+       (simple_return)]
9790
+       ""
9791
+       {
9792
+               if (MEM_P(operands[1])) {
9793
+                       rtx addr = XEXP(operands[1],0);
9794
+                       if (zip_const_address_operand_p(addr, SImode)) {
9795
+                               emit_call_insn(gen_reg_sibcall_const(addr, operands[2]));
9796
+                       } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
9797
+                               emit_call_insn(gen_reg_sibcall_mem(XEXP(addr,0), operands[2]));
9798
+                       } else {
9799
+                               //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
9800
+                               emit_call_insn(gen_reg_sibcall_var(addr, operands[2]));
9801
+                       }
9802
+                       DONE;
9803
+               }
9804
+       })
9805
+;
9806
+;
9807
+;
9808
+;
9809 102 dgisselq
+; How do we want to do this better?
9810
+;      Replace the RTL w/
9811
+;              return_label= gen_label_rtx();
9812
+;              emit_movsi(gen_rtx_REG(zip_R0),plus_constant(
9813
+;                      gen_rtx_REG(zip_PC),return_label));
9814
+;              emit_jump(label_rtx(
9815
+;
9816
+;              emit_label(return_label);
9817
+;
9818
+; The problem is: we can't!  GCC distinguishes between jumps and calls when
9819
+; optimizing, and it doesn't see the need to keep the label around.  Thus, the
9820
+; label gets removed and the call gets lost.  Hence we do it this way (below).
9821
+; I'll probably bastardize a means of getting a new codelabel that GCC doesn't
9822
+; recognize as such, but for now we'll use .Lcall# as our label.
9823
+;
9824
+(define_insn "void_call_const"
9825 122 dgisselq
+       [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
9826 111 dgisselq
+                       (match_operand 1 "const_int_operand" "n"))
9827 122 dgisselq
+               (clobber (reg:SI RTN_REG))
9828
+               (clobber (reg:CC CC_REG))]
9829 102 dgisselq
+       ""
9830
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
9831
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9832
+(define_insn "void_call_mem"
9833 122 dgisselq
+       [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
9834 111 dgisselq
+                       (match_operand 1 "const_int_operand" "n"))
9835 122 dgisselq
+               (clobber (reg:SI RTN_REG))
9836
+               (clobber (reg:CC CC_REG))]
9837 102 dgisselq
+       ""
9838
+       "MOV    .Lcall%=(PC),R0\;LOD\t%0,PC\n.Lcall%=:"
9839
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9840
+;
9841
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
9842
+(define_insn "void_call_var"
9843 122 dgisselq
+       [(call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
9844 111 dgisselq
+                       (match_operand 1 "const_int_operand" "n"))
9845 122 dgisselq
+               (clobber (reg:SI RTN_REG))
9846
+               (clobber (reg:CC CC_REG))]
9847 102 dgisselq
+       ""
9848
+       "MOV    .Lcall%=(PC),R0\;JMP\t%0\n.Lcall%=:"
9849
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9850 191 dgisselq
+;
9851
+;
9852 102 dgisselq
+(define_expand "call_value"
9853 122 dgisselq
+       [(parallel [(set (reg:SI RTNV_REG)
9854 102 dgisselq
+               (call (match_operand:SI 1 "" "")
9855 111 dgisselq
+                       (match_operand 2 "const_int_operand" "n")))
9856 122 dgisselq
+       (set (match_operand:SI 0 "register_operand" "=r") (reg:SI RTNV_REG))
9857
+       (clobber (reg:CC CC_REG))])]
9858 102 dgisselq
+       ""
9859
+       {
9860 122 dgisselq
+               //; extern void zip_debug_rtx(const_rtx);
9861
+               //; fprintf(stderr, "ZIP.MD::CALL-VALUE()\n");
9862
+               //; zip_debug_rtx(operands[1]);
9863 102 dgisselq
+               if (MEM_P(operands[1])) {
9864 122 dgisselq
+                       //; fprintf(stderr, "ZIP.MD::CALL-VALUE() MEM_P\n");
9865
+                       //; zip_debug_rtx(operands[1]);
9866
+                       //; This should always be the case
9867 102 dgisselq
+                       rtx addr = XEXP(operands[1],0);
9868
+                       if (zip_const_address_operand_p(addr, SImode)) {
9869 122 dgisselq
+                               //; fprintf(stderr, "Generating gen_reg_call_const()\n");
9870 102 dgisselq
+                               emit_call_insn(gen_reg_call_const(addr, operands[2]));
9871
+                       } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
9872 122 dgisselq
+                               //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
9873 102 dgisselq
+                               emit_call_insn(gen_reg_call_mem(XEXP(addr,0), operands[2]));
9874
+                       } else {
9875 122 dgisselq
+                               //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
9876 102 dgisselq
+                               emit_call_insn(gen_reg_call_var(addr, operands[2]));
9877
+                       }
9878
+                       DONE;
9879
+               }
9880
+       })
9881
+(define_insn "reg_call_const"
9882 122 dgisselq
+       [(set (reg:SI RTNV_REG)
9883 102 dgisselq
+               (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
9884 111 dgisselq
+                       (match_operand 1 "const_int_operand" "n")))
9885 122 dgisselq
+               (clobber (reg:SI RTN_REG))
9886
+               (clobber (reg:CC CC_REG))]
9887 102 dgisselq
+       ""
9888
+       "MOV    .Lcall%=(PC),R0\;BRA\t%0\n.Lcall%=:"
9889
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9890
+(define_insn "reg_call_mem"
9891
+       [(set (reg:SI RTNV_REG)
9892 111 dgisselq
+               (call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
9893
+                       (match_operand 1 "const_int_operand" "n")))
9894 122 dgisselq
+               (clobber (reg:SI RTN_REG))
9895
+               (clobber (reg:CC CC_REG))]
9896 102 dgisselq
+       ""
9897 111 dgisselq
+       "MOV    .Lcall%=(PC),R0\n\tLOD\t%0,PC\n.Lcall%=:"
9898 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9899 111 dgisselq
+;
9900 102 dgisselq
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
9901
+(define_insn "reg_call_var"
9902 122 dgisselq
+       [(set (reg:SI RTNV_REG)
9903 102 dgisselq
+               (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
9904 111 dgisselq
+                       (match_operand 1 "const_int_operand" "n")))
9905 122 dgisselq
+               (clobber (reg:SI RTN_REG))
9906
+               (clobber (reg:CC CC_REG))]
9907 102 dgisselq
+       ""
9908 111 dgisselq
+       "MOV    .Lcall%=(PC),R0\n\tJMP\t%0\n.Lcall%=:"
9909 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9910
+;
9911
+;
9912
+;
9913 191 dgisselq
+(define_insn "reg_sibcall_const"
9914
+       [(set (reg:SI RTNV_REG)
9915
+               (call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
9916
+                       (match_operand 1 "const_int_operand" "n")))
9917
+               (use (reg:SI RTN_REG))
9918
+               (clobber (reg:CC CC_REG))
9919
+               (simple_return)]
9920
+       ""
9921
+       "BRA\t%0"
9922
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9923
+(define_insn "reg_sibcall_mem"
9924
+       [(set (reg:SI RTNV_REG)
9925
+               (call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
9926
+                       (match_operand 1 "const_int_operand" "n")))
9927
+               (use (reg:SI RTN_REG))
9928
+               (clobber (reg:CC CC_REG))
9929
+               (simple_return)]
9930
+       ""
9931
+       "LOD\t%0,PC"
9932
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9933
+;
9934
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
9935
+(define_insn "reg_sibcall_var"
9936
+       [(set (reg:SI RTNV_REG)
9937
+               (call (mem:SI (match_operand:SI 0 "zip_address_operand_p" ""))
9938
+                       (match_operand 1 "const_int_operand" "n")))
9939
+               (use (reg:SI RTN_REG))
9940
+               (clobber (reg:CC CC_REG))
9941
+               (simple_return)]
9942
+       ""
9943
+       "JMP\t%0"
9944
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9945
+;
9946
+;
9947
+;
9948 102 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9949
+;;
9950
+;; Frame manipulation RTX
9951
+;;
9952
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9953
+;
9954
+;
9955
+;
9956
+(define_expand "prologue"
9957
+       [(const_int 0)]
9958
+       ""
9959
+       "{ zip_expand_prologue(); DONE; }")
9960 191 dgisselq
+(define_expand "sibcall_epilogue"
9961
+       [(return)]
9962
+       ""
9963
+       "{ zip_sibcall_epilogue(); DONE; }")
9964 102 dgisselq
+(define_expand "epilogue"
9965
+       [(return)]
9966
+       ""
9967
+       "{ zip_expand_epilogue(); DONE; }")
9968
+(define_expand "return" ; In order to use the function predicate, this *must*
9969
+       [(return)]      ; be a define_expand
9970
+       "zip_use_return_insn()")
9971
+       ; "JMP  R0"
9972
+       ; [(set_attr "ccresult" "unchanged")])
9973
+(define_insn "*return" ; A "*" -- means it cannot be called from C
9974
+       [(return)]
9975
+       ""
9976 200 dgisselq
+       "RETN"
9977 102 dgisselq
+       [(set_attr "ccresult" "unchanged")])
9978
+(define_insn "simple_return"   ; A "*" -- means it cannot be called from C
9979
+       [(simple_return)]
9980
+       ""
9981 200 dgisselq
+       "RETN"
9982 102 dgisselq
+       [(set_attr "ccresult" "unchanged")])
9983 191 dgisselq
+(define_insn "return_if_eq"
9984
+       [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
9985
+                       (return) (pc)))]
9986
+       "zip_use_return_insn()"
9987 200 dgisselq
+       "RETN.Z"
9988 191 dgisselq
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
9989
+(define_insn "return_if_ne"
9990
+       [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0))
9991
+                       (return) (pc)))]
9992
+       "zip_use_return_insn()"
9993 200 dgisselq
+       "RETN.NZ"
9994 191 dgisselq
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
9995
+(define_insn "return_if_lt"
9996
+       [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
9997
+                       (return) (pc)))]
9998
+       "zip_use_return_insn()"
9999 200 dgisselq
+       "RETN.LT"
10000 191 dgisselq
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10001
+(define_insn "return_if_gt"
10002
+       [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0))
10003
+                       (return) (pc)))]
10004
+       "zip_use_return_insn()"
10005 200 dgisselq
+       "RETN.GT"
10006 191 dgisselq
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10007 200 dgisselq
+;(define_insn "return_if_gte"
10008
+       ;[(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
10009
+                       ;(return) (pc)))]
10010
+       ;"((ZIP_NEW_CONDITION_CODE)&&(zip_use_return_insn()))"
10011
+       ;"RETN.GT\n\tRETN.Z"
10012
+       ;[(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10013 191 dgisselq
+(define_insn "return_if_gte"
10014
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
10015
+                       (return) (pc)))]
10016 200 dgisselq
+       "((!ZIP_NEW_CONDITION_CODE)&&(zip_use_return_insn()))"
10017
+       "RETN.GTE"
10018 191 dgisselq
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10019
+(define_insn "return_if_ltu"
10020
+       [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
10021
+                       (return) (pc)))]
10022
+       "zip_use_return_insn()"
10023 200 dgisselq
+       "RETN.C"
10024 191 dgisselq
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10025 200 dgisselq
+(define_insn "return_if_geu"
10026
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
10027
+                       (return) (pc)))]
10028
+       "((ZIP_NEW_CONDITION_CODE)&&(zip_use_return_insn()))"
10029
+       "RETN.NC"
10030
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10031 102 dgisselq
+;
10032
+;
10033
+;
10034
+;;;;;;;;;;;;;;;;;;;;;;;;;;
10035
+;;
10036
+;; Zip Builtin Functions
10037
+;;
10038
+;;;;;;;;;;;;;;;;;;;;;;;;;;
10039
+;
10040
+;
10041
+;
10042
+(define_insn "zip_rtu"
10043
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_RTU)
10044 122 dgisselq
+       (clobber (reg:CC CC_REG))]
10045 102 dgisselq
+       "(!ZIP_USER)"
10046
+       "RTU"
10047
+       [(set_attr "ccresult" "unknown")])
10048 171 dgisselq
+(define_insn "zip_busy"
10049
+       [(set (pc) (minus:SI (pc) (const_int 1)))]
10050
+       ""
10051
+       "BUSY"
10052
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
10053 102 dgisselq
+(define_insn "zip_halt" ; Needs to be unspec_volatile, or optimizer will opt out
10054
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_HALT)
10055 122 dgisselq
+       (clobber (reg:CC CC_REG))]
10056 102 dgisselq
+       "(!ZIP_USER)"
10057
+       "HALT"
10058
+       [(set_attr "ccresult" "unknown")])
10059
+(define_insn "zip_idle"
10060
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_IDLE)
10061 122 dgisselq
+       (clobber (reg:CC CC_REG))]
10062 102 dgisselq
+       ""
10063
+       "WAIT"
10064
+       [(set_attr "ccresult" "unknown")])
10065
+(define_insn "zip_syscall"
10066
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_SYSCALL)]
10067
+       ""
10068
+       "CLR\tCC"
10069
+       [(set_attr "ccresult" "unknown")])
10070
+;
10071
+;
10072
+; Operator "save_context"
10073
+;
10074 117 dgisselq
+;      Okay, so we're not really reading and writing operand 0, %0, however
10075
+;      if we don't list it as a "+r" register, the compiler may allocate it
10076
+;      among the other registers, thus we clobber it in the middle of the
10077
+;      operation before the task is complete.
10078 102 dgisselq
+;
10079
+(define_insn "zip_save_context"
10080 117 dgisselq
+       [(unspec_volatile
10081
+                       [ (match_operand:SI 0 "register_operand" "+r") ]
10082 102 dgisselq
+                       UNSPEC_SAVE_CONTEXT)
10083
+               (clobber (match_scratch:SI 1 "=r"))
10084
+               (clobber (match_scratch:SI 2 "=r"))
10085
+               (clobber (match_scratch:SI 3 "=r"))
10086 117 dgisselq
+               (clobber (match_scratch:SI 4 "=r"))]
10087 102 dgisselq
+       "(!ZIP_USER)"
10088
+       "MOV\tuR0,%1
10089
+       MOV\tuR1,%2
10090
+       MOV\tuR2,%3
10091
+       MOV\tuR3,%4
10092
+       STO\t%1,%0
10093
+       STO\t%2,1(%0)
10094
+       STO\t%3,2(%0)
10095
+       STO\t%4,3(%0)
10096
+       MOV\tuR4,%1
10097
+       MOV\tuR5,%2
10098
+       MOV\tuR6,%3
10099
+       MOV\tuR7,%4
10100
+       STO\t%1,4(%0)
10101
+       STO\t%2,5(%0)
10102
+       STO\t%3,6(%0)
10103
+       STO\t%4,7(%0)
10104
+       MOV\tuR8,%1
10105
+       MOV\tuR9,%2
10106
+       MOV\tuR10,%3
10107
+       MOV\tuR11,%4
10108
+       STO\t%1,8(%0)
10109
+       STO\t%2,9(%0)
10110
+       STO\t%3,10(%0)
10111
+       STO\t%4,11(%0)
10112
+       MOV\tuR12,%1
10113
+       MOV\tuSP,%2
10114
+       MOV\tuCC,%3
10115
+       MOV\tuPC,%4
10116
+       STO\t%1,12(%0)
10117
+       STO\t%2,13(%0)
10118
+       STO\t%3,14(%0)
10119
+       STO\t%4,15(%0)"
10120 122 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10121 117 dgisselq
+;
10122
+; See the comment above about why operand 0, %0, *must* be a "+r" operand,
10123
+; even though we don't really read (or change) its value throughout this
10124
+; operation.
10125
+;
10126 102 dgisselq
+(define_insn "zip_restore_context"
10127
+       [(unspec_volatile [
10128 117 dgisselq
+               (match_operand:SI 0 "register_operand" "+r")] UNSPEC_RESTORE_CONTEXT)
10129 102 dgisselq
+       (clobber (match_scratch:SI 1 "=r"))
10130
+       (clobber (match_scratch:SI 2 "=r"))
10131
+       (clobber (match_scratch:SI 3 "=r"))
10132 117 dgisselq
+       (clobber (match_scratch:SI 4 "=r"))]
10133 102 dgisselq
+       "(!ZIP_USER)"
10134
+       "LOD\t0(%0),%1
10135
+       LOD\t1(%0),%2
10136
+       LOD\t2(%0),%3
10137
+       LOD\t3(%0),%4
10138
+       MOV\t%1,uR0
10139
+       MOV\t%2,uR1
10140
+       MOV\t%3,uR2
10141
+       MOV\t%4,uR3
10142
+       LOD\t4(%0),%1
10143
+       LOD\t5(%0),%2
10144
+       LOD\t6(%0),%3
10145
+       LOD\t7(%0),%4
10146
+       MOV\t%1,uR4
10147
+       MOV\t%2,uR5
10148
+       MOV\t%3,uR6
10149
+       MOV\t%4,uR7
10150
+       LOD\t8(%0),%1
10151
+       LOD\t9(%0),%2
10152
+       LOD\t10(%0),%3
10153
+       LOD\t11(%0),%4
10154
+       MOV\t%1,uR8
10155
+       MOV\t%2,uR9
10156
+       MOV\t%3,uR10
10157
+       MOV\t%4,uR11
10158
+       LOD\t12(%0),%1
10159
+       LOD\t13(%0),%2
10160
+       LOD\t14(%0),%3
10161
+       LOD\t15(%0),%4
10162
+       MOV\t%1,uR12
10163
+       MOV\t%2,uSP
10164
+       MOV\t%3,uCC
10165
+       MOV\t%4,uPC"
10166 122 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10167 102 dgisselq
+(define_insn "zip_bitrev"
10168
+       [(set (match_operand:SI 0 "register_operand" "=r")
10169
+               (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_BITREV))
10170
+       ]
10171
+       ""
10172
+       "BREV\t%1,%0"
10173 122 dgisselq
+       [(set_attr "ccresult" "unchanged")])
10174 102 dgisselq
+(define_insn "zip_cc"
10175
+       [(set (match_operand:SI 0 "register_operand" "=r")
10176
+               (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
10177
+       ""
10178
+       "MOV\tCC,%0"
10179
+       [(set_attr "ccresult" "unchanged")])
10180 117 dgisselq
+(define_insn "zip_ucc"
10181
+       [(set (match_operand:SI 0 "register_operand" "=r")
10182
+               (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETUCC))]
10183
+       ""
10184
+       "MOV\tuCC,%0"
10185
+       [(set_attr "ccresult" "unchanged")])
10186 111 dgisselq
+(define_insn "zip_cc_sto"
10187
+       [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
10188 117 dgisselq
+               (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
10189 111 dgisselq
+       ""
10190
+       "STO\tCC,(%0)"
10191
+       [(set_attr "ccresult" "unchanged")])
10192
+(define_insn "zip_cc_sto_off"
10193
+       [(set (mem:SI (plus:SI
10194
+                       (match_operand:SI 0 "register_operand" "r")
10195
+                       (match_operand:SI 1 "const_int_operand" "N")))
10196 117 dgisselq
+               (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
10197 111 dgisselq
+       ""
10198
+       "STO\tCC,%1(%0)"
10199
+       [(set_attr "ccresult" "unchanged")])
10200 102 dgisselq
+(define_insn "ldilo"
10201
+       [(set (match_operand:SI 0 "register_operand" "=r")
10202
+               (unspec:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_LDILO))]
10203
+       ""
10204
+       "LDILO  %1,%0"
10205
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
10206
+
10207
+;
10208
+;
10209 171 dgisselq
+; Missing still: zip_break(idno)
10210
+; Would also be nice to have a zip_reg builtin, allowing us to read or write
10211
+; a register, as in zip_reg(5)=40;.  Not sure what this means, though, when the
10212
+; number placed into this is not constant, or how to specify that it must *only*
10213
+; be constant.  Thats actually the problem with both proposals, zip_break(id)
10214
+; and zip_reg(regno)--both depend upon a compile time constant to work.
10215 102 dgisselq
+;
10216 171 dgisselq
+;
10217
+;
10218
+;
10219
+;
10220 102 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10221
+;;
10222
+;; Trap Instruction
10223
+;;
10224
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10225
+;
10226
+;
10227
+; The ZipCPU doesn't really have a "trap" instruction per se.  The goal is that
10228
+; *nothing* should ever trap, and so we should never get here.  However, the
10229
+; compiler seems to want a trap instruction for some reason.  (It keeps us
10230
+; from calling the abort() function, if we don't define these ...)  So let's
10231
+; just grab onto the break instruction and declare it to be a trap instruction
10232
+; for our purposes.  Alternatively, we might've used a syscall, but ... this
10233
+; will work for both user and system instructions.
10234
+;
10235
+(define_insn "trap"
10236
+       [(trap_if (const_int 1) (const_int 0))]
10237
+       ""
10238
+       "BREAK"
10239
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
10240
+;
10241
+(define_expand "ctrap<mode>4"
10242 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
10243
+               (match_operand:ZI 1 "register_operand" "r")
10244
+               (match_operand:ZI 2 "zip_opb_single_operand_p" "rO")))
10245 102 dgisselq
+       (trap_if (match_operator 0 "ordered_comparison_operator"
10246 122 dgisselq
+                       [(reg:CC CC_REG) (const_int 0)])
10247 102 dgisselq
+                       (match_operand 3 "const_int_operand" "O"))]
10248
+       ""
10249
+       )
10250
+(define_insn "trapif"
10251
+       [(trap_if (match_operator 0 "ordered_comparison_operator"
10252 122 dgisselq
+                       [(reg:CC CC_REG) (const_int 0)])
10253 102 dgisselq
+                       (match_operand 1 "const_int_operand" "O"))]
10254
+       ""
10255
+       "BREAK\t%1"
10256
+       [(set_attr "predicable" "no")])
10257
+;
10258
+;
10259
+;
10260 200 dgisselq
+;
10261
+(include "zip-float.md")
10262
+(include "zip-sync.md")
10263
+(include "zip-peephole.md")
10264
+;
10265
+;
10266 102 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10267
+;;
10268
+;; Unimplemented (or not yet implemented) RTL Codes
10269
+;;
10270
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10271
+;
10272
+;
10273
+;
10274
+;
10275 200 dgisselq
+;(define_insn "addvsi4"
10276
+;      )
10277
+;(define_insn "subvsi4"
10278
+;      )
10279
+;(define_insn "mulvsi4"
10280
+;      )
10281
+;(define_insn "umulvsi4"
10282
+;      )
10283
+;(define_insn "umulvsi4"
10284
+;      )
10285 102 dgisselq
+;(define_insn "negvsi3"
10286
+;      "MOV    %1,%0
10287
+;      XOR     -1,%0
10288
+;      ADD     1,%0
10289
+;      BV      %2"
10290 200 dgisselq
+;      )
10291 124 dgisselq
+;
10292 200 dgisselq
+;(define_insn "ssum_widen
10293
+;(define_insn "usum_widen
10294
+;(define_insn "udot_prod"
10295
+;(define_insn "maddsidi4"
10296
+;(define_insn "umaddsidi4"
10297
+;(define_insn "msubsidi4"
10298
+;(define_insn "umsubsidi4"
10299
+;
10300
+;
10301
+; STILL MISSING:
10302
+;      SYSCALL(ID)
10303
+;              MOV %ID,R0
10304
+;              CLR     CC
10305
+;      cmove   ... the conditional move, created from a
10306
+;      (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))
10307
+;      pattern
10308
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-modes.def gcc-5.3.0-zip/gcc/config/zip/zip-modes.def
10309
--- gcc-5.3.0-original/gcc/config/zip/zip-modes.def     1969-12-31 19:00:00.000000000 -0500
10310
+++ gcc-5.3.0-zip/gcc/config/zip/zip-modes.def  2016-03-08 12:10:21.982586940 -0500
10311
@@ -0,0 +1,23 @@
10312
+/*
10313
+ * Commends in C-long comment form
10314
+ * class
10315
+ *     Mode = "SI"
10316
+ *     PRECISION, BYTESIZE, COUNT ??
10317
+ *     FORMAT
10318
+ *     EXPR
10319
+ *
10320
+ * The manual says I need to define BITS_PER_UNIT here.
10321
+ */
10322
+// INT_MODE(QI, 1);
10323
+// INT_MODE(HI, 1);
10324
+// INT_MODE(SI, 1);
10325
+// INT_MODE(DI, 2);
10326
+
10327
+// FLOAT_MODE(SF, 1, ieee_single_format);
10328
+// FLOAT_MODE(DF, 2, ieee_single_format);
10329
+
10330
+// We cannot override machmodes.def from here.  Thus, even though our QI,
10331
+// HI, and SI modes are all 1-byte, we cant set them that way here.  The
10332
+// change needed to be made in machmodes.def.  Hence, here is a target
10333
+// configuration change--in machmodes.def--that properly belonged in the
10334
+// config directory.
10335
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-peephole.md gcc-5.3.0-zip/gcc/config/zip/zip-peephole.md
10336
--- gcc-5.3.0-original/gcc/config/zip/zip-peephole.md   1969-12-31 19:00:00.000000000 -0500
10337
+++ gcc-5.3.0-zip/gcc/config/zip/zip-peephole.md        2016-11-09 12:12:15.750820248 -0500
10338
@@ -0,0 +1,617 @@
10339
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10340
+;;
10341
+;; Filename:   zip-peephole.md
10342
+;;
10343
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
10344
+;;
10345
+;; Purpose:    This is a machine description of a variety of peephole
10346
+;;             optimizations which can be applied to the ZipCPU RTL
10347
+;;     representation.
10348
+;;
10349
+;;
10350
+;; Creator:    Dan Gisselquist, Ph.D.
10351
+;;             Gisselquist Technology, LLC
10352
+;;
10353
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10354
+;;
10355
+;; Copyright (C) 2015, Gisselquist Technology, LLC
10356
+;;
10357
+;; This program is free software (firmware): you can redistribute it and/or
10358
+;; modify it under the terms of  the GNU General Public License as published
10359
+;; by the Free Software Foundation, either version 3 of the License, or (at
10360
+;; your option) any later version.
10361
+;;
10362
+;; This program is distributed in the hope that it will be useful, but WITHOUT
10363
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
10364
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
10365
+;; for more details.
10366
+;;
10367
+;; License:    GPL, v3, as defined and found on www.gnu.org,
10368
+;;             http://www.gnu.org/licenses/gpl.html
10369
+;;
10370
+;;
10371
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10372
+;;
10373
+;
10374
+;
10375
+;
10376
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10377
+;;
10378
+;; Peephole optimizations
10379
+;;
10380
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10381
+;
10382
+;
10383
+;
10384
+;
10385
+;
10386 124 dgisselq
+; Match:
10387
+;      CMP     R1,R0
10388
+;      BGTU    lbl
10389
+; Transform to:
10390
+;      CMP     R0,R1
10391
+;      BC      lbl
10392
+;
10393 117 dgisselq
+(define_peephole2
10394 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
10395
+               (match_operand:SI 0 "register_operand")
10396
+               (match_operand:SI 1 "register_operand")))
10397
+       (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
10398
+                       (label_ref (match_operand 2 ""))
10399 117 dgisselq
+                       (pc)))]
10400 127 dgisselq
+       "(ZIP_PEEPHOLE)"
10401 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 0)))
10402
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
10403 117 dgisselq
+                       (label_ref (match_dup 2))
10404
+                       (pc)))]
10405
+       "")
10406 127 dgisselq
+(define_peephole2
10407
+       [(match_scratch:SI 3 "=r")
10408
+       (set (reg:CC CC_REG) (compare:CC
10409
+               (match_operand:SI 0 "register_operand")
10410
+               (match_operand 1 "const_int_operand")))
10411
+       (match_dup 3)
10412
+       (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
10413
+                       (label_ref (match_operand 2 ""))
10414
+                       (pc)))]
10415
+       "(ZIP_PEEPHOLE)"
10416
+       [(set (match_dup 3) (match_dup 1))
10417
+       (set (reg:CC CC_REG) (compare:CC (match_dup 3) (match_dup 0)))
10418
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
10419
+                       (label_ref (match_dup 2))
10420
+                       (pc)))]
10421
+       "")
10422
+;(define_peephole2
10423
+;      [(set (reg:CC CC_REG) (compare:CC
10424
+;              (match_operand:SI 0 "register_operand")
10425
+;              (match_operand 1 "const_int_operand")))
10426
+;      (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
10427
+;                      (label_ref (match_operand 2 ""))
10428
+;                      (pc)))]
10429
+;      ""
10430
+;      [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
10431
+;      (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
10432
+;                      (label_ref (match_dup 2))
10433
+;                      (pc)))]
10434
+;      "operands[1] = GEN_INT(INTVAL(operands[1])-1);")
10435 124 dgisselq
+;
10436
+;
10437
+; Match:
10438
+;      CMP     R1,R0
10439
+;      BGEU    lbl
10440
+; Transform to:
10441
+;      CMP     1(R0),R1
10442
+;      BC      lbl
10443
+;
10444 117 dgisselq
+(define_peephole2
10445 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
10446
+               (match_operand:SI 0 "register_operand")
10447
+               (match_operand:SI 1 "register_operand")))
10448
+       (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
10449
+                       (label_ref (match_operand 2 ""))
10450 117 dgisselq
+                       (pc)))]
10451 127 dgisselq
+       "(ZIP_PEEPHOLE)"
10452 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
10453 146 dgisselq
+               (match_dup 1) (plus:SI (match_dup 0) (const_int 1))))
10454 122 dgisselq
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
10455 117 dgisselq
+                       (label_ref (match_dup 2))
10456
+                       (pc)))]
10457
+       "")
10458 124 dgisselq
+;
10459
+;
10460
+; Match:
10461
+;      CMP     R1,R0
10462
+;      BGE     lbl
10463
+; Transform to:
10464
+;      CMP     1(R0),R1
10465
+;      BLT     lbl
10466 142 dgisselq
+; ... why?  when we support a BGE instruction?
10467
+;(define_peephole2
10468
+       ;[(set (reg:CC CC_REG) (compare:CC
10469
+               ;(match_operand:SI 0 "register_operand")
10470
+               ;(match_operand:SI 1 "register_operand")))
10471
+       ;(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
10472
+                       ;(label_ref (match_operand 2 ""))
10473
+                       ;(pc)))]
10474
+       ;"(ZIP_PEEPHOLE)"
10475
+       ;[(set (reg:CC CC_REG) (compare:CC (match_dup 1)
10476
+                       ;(plus:SI (match_dup 0) (const_int 1))))
10477
+       ;(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
10478
+                       ;(label_ref (match_dup 2))
10479
+                       ;(pc)))]
10480
+       ;"")
10481 124 dgisselq
+;
10482
+;
10483
+; Match:
10484
+;      CMP     R1,R0
10485
+;      BLEU    lbl
10486
+; Transform to:
10487
+;      CMP     1(R1),R0
10488 142 dgisselq
+;      BC      lbl
10489 124 dgisselq
+;
10490 117 dgisselq
+(define_peephole2
10491 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC
10492
+               (match_operand:SI 0 "register_operand" "")
10493 117 dgisselq
+               (match_operand:SI 1 "register_operand" "")))
10494 122 dgisselq
+       (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
10495 117 dgisselq
+                       (label_ref (match_operand 2 "" ""))
10496
+                       (pc)))]
10497 127 dgisselq
+       "(ZIP_PEEPHOLE)"
10498 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
10499 146 dgisselq
+                       (plus:SI (match_dup 1) (const_int 1))))
10500 122 dgisselq
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
10501 117 dgisselq
+                       (label_ref (match_dup 2))
10502
+                       (pc)))]
10503
+       "")
10504
+;
10505 142 dgisselq
+;
10506
+;
10507
+; Match:
10508
+;      CMP     R1,R0
10509
+;      BLE     lbl
10510
+; Transform to:
10511
+;      CMP     1(R1),R0
10512
+;      BLT     lbl
10513
+;
10514 127 dgisselq
+(define_peephole2
10515
+       [(set (reg:CC CC_REG)
10516
+               (compare:CC (match_operand:SI 0 "register_operand" "")
10517
+                       (match_operand:SI 1 "const_int_operand" "")))
10518
+       (set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
10519
+                       (label_ref (match_operand 2 "" ""))
10520
+                       (pc)))]
10521
+       "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))"
10522
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
10523
+       (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
10524
+                       (label_ref (match_dup 2))
10525
+                       (pc)))]
10526
+       "operands[1] = GEN_INT(INTVAL(operands[1])+1);")
10527 142 dgisselq
+;
10528
+; Match:
10529
+;      CMP     R1,R0
10530
+;      BLEU    lbl
10531
+; Transform to:
10532
+;      CMP     1(R1),R0
10533
+;      BC(LTU) lbl
10534
+;
10535 127 dgisselq
+(define_peephole2
10536
+       [(set (reg:CC CC_REG)
10537
+               (compare:CC (match_operand:SI 0 "register_operand" "")
10538
+                       (match_operand:SI 1 "const_int_operand" "")))
10539
+       (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
10540
+                       (label_ref (match_operand 2 "" ""))
10541
+                       (pc)))]
10542
+       "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))"
10543
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
10544 142 dgisselq
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
10545 127 dgisselq
+                       (label_ref (match_dup 2))
10546
+                       (pc)))]
10547
+       "operands[1] = GEN_INT(INTVAL(operands[1])+1);")
10548 102 dgisselq
+;
10549 117 dgisselq
+;
10550
+;
10551
+;
10552 127 dgisselq
+; Match:
10553
+;      (parallel [(set () ()) (clobber (CC))])
10554
+;      (compare () ())
10555
+; Transform to:
10556
+;      (parallel [(set () ()) (set (CC) (0))]
10557
+;      (compare () ())
10558 117 dgisselq
+;
10559 127 dgisselq
+(define_peephole2
10560
+       [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 ""))
10561
+               (clobber (reg:CC CC_REG))])
10562
+       (set (reg:CC CC_REG) (compare:CC (match_operand:SI 2 "")
10563
+                       (match_operand:SI 3 "")))]
10564
+       "(ZIP_PEEPHOLE)&&zip_insn_sets_cc(insn)"
10565
+       [(parallel [(set (match_dup 0) (match_dup 1))
10566
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10567
+       (set (reg:CC CC_REG) (compare:CC (match_dup 2) (match_dup 3)))]
10568
+       "")
10569
+;
10570
+;
10571
+;
10572 122 dgisselq
+; Match:
10573 127 dgisselq
+;      (parallel [(set () ()) (clobber (CC))])
10574
+;      (set () ())
10575
+;      (compare () ())
10576
+; Transform to:
10577
+;      (parallel [(set () ()) (set (CC) (0))]
10578
+;      (set () ())
10579
+;      (compare () ())
10580
+;
10581
+(define_peephole2
10582
+       [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 ""))
10583
+               (clobber (reg:CC CC_REG))])
10584
+       (set (match_operand 2 "") (match_operand 3 ""))
10585
+       (set (reg:CC CC_REG) (compare:CC (match_operand:SI 4 "")
10586
+                       (match_operand:SI 5 "")))]
10587
+       "(ZIP_PEEPHOLE)&&(zip_insn_sets_cc(insn))&&((!REG_P(operands[2]))||(REGNO(operands[2])!=CC_REG))"
10588
+       [(parallel [(set (match_dup 0) (match_dup 1))
10589
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10590
+       (set (match_dup 2) (match_dup 3))
10591
+       (set (reg:CC CC_REG) (compare:CC (match_dup 4) (match_dup 5)))]
10592
+       "")
10593
+;
10594
+;
10595
+;
10596
+; Match:
10597 122 dgisselq
+;      MOV A(R1),R3
10598
+;      CMP R3,R0
10599
+;      (R3 is dead)
10600
+; Transform to:
10601
+;      CMP A(R1),R0
10602
+;
10603
+(define_peephole2
10604
+       [(set (match_operand:SI 3 "register_operand")
10605
+               (plus:SI (match_operand:SI 1 "register_operand")
10606
+                       (match_operand:SI 2 "zip_mvimm_operand_p")))
10607
+       (set (reg:CC CC_REG)
10608
+               (compare:CC (match_operand:SI 0 "register_operand")
10609
+                       (match_dup 3)))]
10610 127 dgisselq
+       "(ZIP_PEEPHOLE)&&peep2_regno_dead_p(2, REGNO(operands[3]))"
10611 122 dgisselq
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
10612
+               (plus:SI (match_dup 1) (match_dup 2))))]
10613
+       "")
10614
+;
10615
+;
10616
+; Match:
10617
+;      ALU OpB,R0
10618
+;      CMP 0,R0
10619
+; Transform to:
10620
+;      ALU OpB,R0
10621
+;
10622
+(define_peephole2
10623 124 dgisselq
+       [(parallel [(set (match_operand:SI 0 "register_operand")
10624
+                       (match_operand:SI 1 ""))
10625 122 dgisselq
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10626
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
10627 127 dgisselq
+       "(ZIP_PEEPHOLE)"
10628 122 dgisselq
+       [(parallel [(set (match_dup 0) (match_dup 1))
10629
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10630
+       ])
10631
+;
10632
+;
10633
+; Match:
10634
+;      ALU OpB,R0
10635
+;      MOV R1,R2       // Can be LDI, LOD, STO, etc.
10636 127 dgisselq
+;      CMP 0,R0
10637 122 dgisselq
+; Transform to:
10638
+;      ALU OpB,R0
10639
+;      MOV R0,R1
10640
+;
10641
+(define_peephole2
10642 124 dgisselq
+       [(parallel [(set (match_operand:SI 0 "register_operand")
10643
+                       (match_operand:SI 1 ""))
10644 122 dgisselq
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10645 124 dgisselq
+       (set (match_operand:SI 2 "nonimmediate_operand") (match_operand:SI 3 ""))
10646 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
10647 127 dgisselq
+       "(ZIP_PEEPHOLE)&&((!REG_P(operands[2]))||((REGNO(operands[2])!=REGNO(operands[0]))&&((REGNO(operands[2])>=FIRST_PSEUDO_REGISTER)||(REGNO(operands[2])<CC_REG))))"
10648 122 dgisselq
+       [(parallel [(set (match_dup 0) (match_dup 1))
10649
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10650
+       (set (match_dup 2) (match_dup 3))
10651
+       ])
10652
+;
10653
+;
10654
+; Match:
10655
+;      ALU OpB,R0
10656
+;      MOV R0,R1
10657
+;      CMP 0,R1
10658
+; Transform to:
10659
+;      ALU OpB,R0
10660
+;      MOV R0,R1
10661
+;
10662
+(define_peephole2
10663 124 dgisselq
+       [(parallel [(set (match_operand:SI 0 "register_operand")
10664
+                       (match_operand:SI 1 ""))
10665 122 dgisselq
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10666 124 dgisselq
+       (set (match_operand:SI 2 "register_operand") (match_dup 0))
10667 122 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))]
10668 127 dgisselq
+       "(ZIP_PEEPHOLE)"
10669 122 dgisselq
+       [(parallel [(set (match_dup 0) (match_dup 1))
10670
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10671
+       (set (match_dup 2) (match_dup 3))
10672
+       ])
10673
+;
10674 124 dgisselq
+;
10675
+; Match:
10676
+;      MOV R1,R0
10677
+;      ADD $x,R0
10678
+;      (CCREG is dead, and x is within range ...)
10679
+; Transform to:
10680 127 dgisselq
+;      MOV $x(R1),R0
10681 124 dgisselq
+(define_peephole2
10682
+       [(set (match_operand:SI 0 "register_operand")
10683
+               (match_operand:SI 1 "register_operand"))
10684
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0)
10685
+                               (match_operand 2 "zip_mvimm_operand_p")))
10686
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10687
+       ]
10688 127 dgisselq
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))"
10689 124 dgisselq
+       [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
10690
+;
10691 127 dgisselq
+; Match:
10692
+;      MOV A(R0),R0
10693
+;      ADD $x,R1
10694
+;      (CCREG is dead, and (A+x) is within range ...)
10695
+; Transform to:
10696
+;      MOV $x(R1),R0
10697 124 dgisselq
+;
10698 127 dgisselq
+(define_peephole2
10699
+       [(set (match_operand:SI 0 "register_operand")
10700
+               (plus:SI (match_operand:SI 1 "register_operand")
10701
+                       (match_operand 2 "zip_mvimm_operand_p")))
10702
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0)
10703
+                               (match_operand 3 "zip_mvimm_operand_p")))
10704
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10705
+       ]
10706
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))
10707
+               &&(INTVAL(operands[2])+INTVAL(operands[3])<((1<<17)))
10708
+               &&(INTVAL(operands[2])+INTVAL(operands[3])>=-(1<<17))"
10709
+       [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
10710
+       "operands[2]=GEN_INT(INTVAL(operands[2])+INTVAL(operands[3]));")
10711 124 dgisselq
+;
10712 127 dgisselq
+;
10713
+;
10714 124 dgisselq
+; Match:
10715
+;      ADD $x,R0
10716
+;      MOV R0,R1
10717
+;      (CCREG is dead, and R0 is dead)
10718
+; Transform to:
10719
+;      MOV (A+$x)(R0),R1
10720
+; ... again, how do I build this plus?
10721
+;
10722
+(define_peephole2
10723
+       [(parallel [(set (match_operand:SI 0 "register_operand")
10724
+                       (plus:SI (match_dup 0)
10725
+                               (match_operand 1 "zip_mvimm_operand_p")))
10726
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10727
+       (set (match_operand:SI 2 "register_operand") (match_dup 0))]
10728 127 dgisselq
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2, REGNO(operands[0])))&&(peep2_regno_dead_p(2,CC_REG))"
10729 124 dgisselq
+       [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))])
10730
+;
10731
+;
10732 127 dgisselq
+;
10733 124 dgisselq
+; Match:
10734 127 dgisselq
+;      ADD $x,R0
10735
+;      MOV A(R0),R1
10736
+;      (CCREG is dead, and R0 is dead)
10737
+; Transform to:
10738
+;      MOV (A+$x)(R0),R1
10739
+;
10740
+(define_peephole2
10741
+       [(parallel [
10742
+               (set (match_operand:SI 0 "register_operand")
10743
+                       (plus:SI (match_dup 0)
10744
+                               (match_operand 1 "zip_mvimm_operand_p")))
10745
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10746
+       (set (match_operand:SI 2 "register_operand")
10747
+               (plus:SI (match_dup 0)
10748
+                       (match_operand 3 "zip_mvimm_operand_p")))
10749
+       ]
10750
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))
10751
+               &&(peep2_regno_dead_p(1,REGNO(operands[0])))
10752
+               &&(INTVAL(operands[1])+INTVAL(operands[3])<((1<<17)))
10753
+               &&(INTVAL(operands[1])+INTVAL(operands[3])>=-(1<<17))"
10754
+       [(set (match_dup 0) (plus:SI (match_dup 2) (match_dup 3)))]
10755
+       "operands[3]=GEN_INT(INTVAL(operands[1])+INTVAL(operands[3]));")
10756
+;
10757
+;
10758
+;
10759
+; Match:
10760 124 dgisselq
+;      ADD     $x,R0
10761
+;      ADD     R0,Rn
10762
+;      (R0 is dead, if R0 is not Rn)
10763
+; Transform to:
10764
+;      ADD     $x(R0),Rn
10765
+;
10766
+(define_peephole2
10767
+       [(parallel [(set (match_operand:SI 0 "register_operand")
10768
+                       (plus:SI (match_dup 0)
10769
+                               (match_operand 1 "zip_opb_immv_p")))
10770
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10771
+       (parallel [(set (match_operand:SI 2 "register_operand")
10772
+                       (plus:SI (match_dup 2) (match_dup 0)))
10773
+               (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
10774
+       ]
10775 127 dgisselq
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[2]))&&(peep2_regno_dead_p(2, REGNO(operands[0])))"
10776 124 dgisselq
+       [(parallel [(set (match_dup 2)
10777
+                       (plus:SI (match_dup 2)
10778
+                               (plus:SI (match_dup 0)
10779
+                                       (match_dup 1))))
10780
+               (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
10781
+       ])
10782
+;
10783
+; Match:
10784
+;      ADD     $x,R0
10785
+;      LOD     -x(R0),R1
10786
+; Transform to:
10787
+;      LOD     (R0),R1
10788
+;      ADD     $x,R0
10789
+;
10790
+(define_peephole2
10791
+       [(parallel [(set (match_operand:SI 0 "register_operand")
10792
+                       (plus:SI (match_dup 0)
10793
+                               (match_operand 1 "zip_opb_immv_p")))
10794
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10795
+       (set (match_operand:SI 3 "register_operand")
10796
+               (mem:SI (plus:SI (match_dup 0)
10797
+                       (match_operand 2 "zip_opb_immv_p"))))
10798
+       ]
10799 127 dgisselq
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
10800 124 dgisselq
+       [(set (match_dup 3) (mem:SI (match_dup 0)))
10801
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
10802
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10803
+       ])
10804 127 dgisselq
+(define_peephole2
10805
+       [(parallel [(set (match_operand:SI 0 "register_operand")
10806
+                       (plus:SI (match_dup 0)
10807
+                               (match_operand 1 "zip_opb_immv_p")))
10808
+               (clobber (reg:CC CC_REG))])
10809
+       (set (match_operand:SI 3 "register_operand")
10810
+               (mem:SI (plus:SI (match_dup 0)
10811
+                       (match_operand 2 "zip_opb_immv_p"))))
10812
+       ]
10813
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
10814
+       [(set (match_dup 3) (mem:SI (match_dup 0)))
10815
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
10816
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10817
+       ])
10818 124 dgisselq
+;
10819
+;
10820
+;
10821
+; Match:
10822
+;      ADD     $x,R0
10823
+;      STO     R1,-x(R0)
10824
+; Transform to:
10825
+;      STO     R1,(R0)
10826
+;      ADD     $x,R0
10827
+;
10828
+(define_peephole2
10829
+       [(parallel [(set (match_operand:SI 0 "register_operand")
10830
+                       (plus:SI (match_dup 0)
10831
+                               (match_operand 1 "zip_opb_immv_p")))
10832
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10833
+       (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p")))
10834
+               (match_operand:SI 3 "register_operand"))
10835
+       ]
10836 127 dgisselq
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
10837 124 dgisselq
+       [(set (mem:SI (match_dup 0)) (match_dup 3))
10838
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
10839
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10840
+       ])
10841 127 dgisselq
+(define_peephole2
10842
+       [(parallel [(set (match_operand:SI 0 "register_operand")
10843
+                       (plus:SI (match_dup 0)
10844
+                               (match_operand 1 "zip_opb_immv_p")))
10845
+               (clobber (reg:CC CC_REG))])
10846
+       (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p")))
10847
+               (match_operand:SI 3 "register_operand"))
10848
+       ]
10849
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
10850
+       [(set (mem:SI (match_dup 0)) (match_dup 3))
10851
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
10852
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10853
+       ])
10854 124 dgisselq
+;
10855
+;
10856
+; Match:
10857
+;      ADD     $x,R0
10858
+;      ANY     R1,R2 (destination is not R0, source does not reference R0)
10859
+;      ADD     R0,Rn (could be 1 or 2, not 0)
10860
+;      (R0 is dead)
10861
+; Transform to:
10862
+;      ANY     R1,R2
10863
+;      ADD     $x(R0),Rn
10864
+;
10865
+;
10866
+;
10867 127 dgisselq
+; Match:
10868
+;      MOV     R1,R0
10869
+;      AND     #/R2,R0
10870
+;      (Ry dead ...)
10871
+; Transform to:
10872
+;      TEST    #/Rz,Rx
10873 124 dgisselq
+;
10874 127 dgisselq
+(define_peephole2
10875
+       [(set (match_operand:SI 0 "register_operand")
10876
+               (match_operand:SI 1 "register_operand"))
10877
+       (parallel [(set (match_dup 0)
10878
+                       (and:SI (match_dup 0)
10879
+                               (match_operand:SI 2 "zip_opb_single_operand_p")))
10880
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
10881
+       ]
10882
+       "((1)||(ZIP_PEEPHOLE))&&(peep2_regno_dead_p(2, REGNO(operands[0])))"
10883
+       [(set (reg:CC CC_REG) (compare:CC (and:ZI (match_dup 1) (match_dup 2))
10884
+                       (const_int 0)))])
10885
+;
10886
+; Match:
10887
+;      (call ...
10888
+;      (set (pc) (label))
10889
+;  or (in asm)
10890
+;      MOV     .Lcallx(PC),R0
10891
+;      BRA     (somewhere)
10892
+; .Lcallx
10893
+;      BRA     (somewhere-else)
10894
+; Transform to:
10895
+;
10896
+;      (sequence [(call ...
10897
+;              (set (pc) (label))])
10898
+;   or (in asm)
10899
+;      "LDI    (somewhere-else),R0
10900
+;      BRA     subroutine"
10901
+;
10902
+; While the following looks good, it doesnt work.  My guess is that the reason
10903
+; why it doesnt work is that the jump at the end crosses basic block boundaries.
10904
+;
10905
+;(define_insn "void_call_mem_unspec"
10906
+;      [(call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p" ""))] UNSPEC_RAW_CALL)
10907
+;                      (match_operand 1 "const_int_operand" "n"))
10908
+;              (clobber (reg:SI RTN_REG))
10909
+;              (clobber (reg:CC CC_REG))]
10910
+;      ""
10911
+;      "BRA\t%0,PC"
10912
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
10913
+;(define_peephole2
10914
+;      [(parallel [(call (mem:SI (match_operand:VOID 0 "zip_const_address_operand_p"))
10915
+;                      (match_operand 1 "const_int_operand"))
10916
+;              (clobber (reg:SI RTN_REG))
10917
+;              (clobber (reg:CC CC_REG))])
10918
+;      ; The match operand for the (set (pc) ...) cannot have anything but
10919
+;      ; VOIDmode, or it wont match.
10920
+;      (set (pc) (match_operand:VOID 2 "zip_const_address_operand_p"))]
10921
+;      ""
10922
+;      [(set (reg:SI RTN_REG) (match_dup 2))
10923
+;      (call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p"))] UNSPEC_RAW_CALL)
10924
+;                      (match_operand 1 "const_int_operand"))
10925
+;              (use (reg:SI RTN_REG))
10926
+;              (clobber (reg:SI RTN_REG))
10927
+;              (clobber (reg:CC CC_REG))]
10928
+;      "fprintf(stderr, \"CALL-JUMP Matched\");")
10929
+;
10930
+;
10931
+;
10932
+; So, the following *should* have worked as well.  However, this falls apart
10933
+; because the 'final' routine can't tell if we are calling a subroutine in this
10934
+; function or not.
10935
+;
10936
+;(define_peephole
10937
+       ;[(parallel [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p"))
10938
+                       ;(match_operand 1 "const_int_operand"))
10939
+               ;(clobber (reg:SI RTN_REG))
10940
+               ;(clobber (reg:CC CC_REG))])
10941
+       ;(set (pc) (label_ref (match_operand 2 "")))]
10942
+       ;""
10943
+       ;"LDI\t%2,R0\;BRA\t%0"
10944
+       ;[(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
10945
+;
10946 124 dgisselq
+; and for
10947
+;      BRA target
10948
+;      BRA target ; two branches to the same identical target in a row ...
10949
+;
10950
+;
10951
+;
10952 102 dgisselq
+; STILL MISSING:
10953 200 dgisselq
+;
10954
+;
10955
+;
10956 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-protos.h gcc-5.3.0-zip/gcc/config/zip/zip-protos.h
10957
--- gcc-5.3.0-original/gcc/config/zip/zip-protos.h      1969-12-31 19:00:00.000000000 -0500
10958 200 dgisselq
+++ gcc-5.3.0-zip/gcc/config/zip/zip-protos.h   2016-11-10 08:13:53.322577755 -0500
10959
@@ -0,0 +1,80 @@
10960 102 dgisselq
+////////////////////////////////////////////////////////////////////////////////
10961
+//
10962
+// Filename:   zip-protos.h
10963
+//
10964
+// Project:    Zip CPU backend for the GNU Compiler Collection
10965
+//
10966
+// Purpose:
10967
+//
10968
+// Creator:    Dan Gisselquist, Ph.D.
10969
+//             Gisselquist Technology, LLC
10970
+//
10971
+////////////////////////////////////////////////////////////////////////////////
10972
+//
10973
+// Copyright (C) 2016, Gisselquist Technology, LLC
10974
+//
10975
+// This program is free software (firmware): you can redistribute it and/or
10976
+// modify it under the terms of  the GNU General Public License as published
10977
+// by the Free Software Foundation, either version 3 of the License, or (at
10978
+// your option) any later version.
10979
+//
10980
+// This program is distributed in the hope that it will be useful, but WITHOUT
10981
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
10982
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
10983
+// for more details.
10984
+//
10985
+// You should have received a copy of the GNU General Public License along
10986
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
10987
+// target there if the PDF file isn't present.)  If not, see
10988
+// <http://www.gnu.org/licenses/> for a copy.
10989
+//
10990
+// License:    GPL, v3, as defined and found on www.gnu.org,
10991
+//             http://www.gnu.org/licenses/gpl.html
10992
+//
10993
+//
10994
+////////////////////////////////////////////////////////////////////////////////
10995
+#ifndef        ZIP_PROTOS_H
10996
+#define        ZIP_PROTOS_H
10997
+
10998 200 dgisselq
+extern int     zip_supported_condition(int c);
10999 102 dgisselq
+extern void    zip_expand_prologue(void);
11000
+extern void    zip_expand_epilogue(void);
11001 191 dgisselq
+extern void    zip_sibcall_epilogue(void);
11002 200 dgisselq
+extern int     zip_expand_movsicc(rtx,rtx,rtx,rtx);
11003 102 dgisselq
+extern int     zip_initial_elimination_offset(int, int);
11004
+extern void    zip_print_operand(FILE *, rtx, int);
11005
+extern void    zip_print_operand_address(FILE *, rtx);
11006
+extern enum    reg_class       zip_reg_class(int);
11007
+extern rtx     zip_return_addr_rtx(int, rtx);
11008
+extern int     zip_num_arg_regs(enum machine_mode, tree);
11009
+
11010
+extern void    zip_asm_output_def(FILE *s, const char *n, const char *v);
11011 122 dgisselq
+
11012
+extern void    zip_canonicalize_comparison(int *, rtx *, rtx *, bool);
11013 191 dgisselq
+extern bool    zip_function_ok_for_sibcall(tree, tree);
11014 102 dgisselq
+extern int     zip_address_operand(rtx op);
11015
+extern int     zip_const_address_operand(rtx op);
11016 200 dgisselq
+extern int     zip_use_return_insn(void);
11017 102 dgisselq
+extern const char *zip_set_zero_or_one(rtx, rtx);
11018
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
11019
+
11020 127 dgisselq
+extern int     zip_insn_sets_cc(rtx_insn *insn);
11021
+extern int     zip_is_conditional(rtx_insn *insn);
11022 102 dgisselq
+extern int     zip_ct_address_operand(rtx op);
11023 111 dgisselq
+extern int     zip_pd_opb_operand(rtx op);
11024 102 dgisselq
+extern int     zip_pd_mov_operand(rtx op);
11025 111 dgisselq
+extern int     zip_pd_imm_operand(rtx op);
11026
+extern int     zip_pd_mvimm_operand(rtx op);
11027 102 dgisselq
+extern int     zip_ct_const_address_operand(rtx op);
11028
+extern int     zip_pd_const_address_operand(rtx op);
11029
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
11030
+extern const char *zip_addsicc(rtx, rtx, rtx, rtx);
11031
+
11032 122 dgisselq
+extern void    zip_ifcvt_machdep_init(struct ce_if_block *ceinfo);
11033
+extern void    zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo);
11034
+extern void    zip_ifcvt_modify_final(struct ce_if_block *ceinfo);
11035
+extern void    zip_ifcvt_modify_tests(struct ce_if_block *ceinfo, rtx *true_expr, rtx *false_expr);
11036 142 dgisselq
+extern void    zip_ifcvt_modify_insn(struct ce_if_block *ceinfo, rtx pattern, rtx_insn *insn);
11037 122 dgisselq
+
11038 102 dgisselq
+#endif
11039
+
11040 200 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config/zip/zip-sync.md gcc-5.3.0-zip/gcc/config/zip/zip-sync.md
11041
--- gcc-5.3.0-original/gcc/config/zip/zip-sync.md       1969-12-31 19:00:00.000000000 -0500
11042
+++ gcc-5.3.0-zip/gcc/config/zip/zip-sync.md    2016-11-10 06:58:36.795045234 -0500
11043
@@ -0,0 +1,303 @@
11044
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11045
+;;
11046
+;; Filename:   zip-sync.md
11047
+;;
11048
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
11049
+;;
11050
+;; Purpose:    This is that portion of the machine description of the Zip CPU
11051
+;;             which is focused on atomic operations.
11052
+;;
11053
+;;
11054
+;; Creator:    Dan Gisselquist, Ph.D.
11055
+;;             Gisselquist Technology, LLC
11056
+;;
11057
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11058
+;;
11059
+;; Copyright (C) 2015, Gisselquist Technology, LLC
11060
+;;
11061
+;; This program is free software (firmware): you can redistribute it and/or
11062
+;; modify it under the terms of  the GNU General Public License as published
11063
+;; by the Free Software Foundation, either version 3 of the License, or (at
11064
+;; your option) any later version.
11065
+;;
11066
+;; This program is distributed in the hope that it will be useful, but WITHOUT
11067
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
11068
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
11069
+;; for more details.
11070
+;;
11071
+;; License:    GPL, v3, as defined and found on www.gnu.org,
11072
+;;             http://www.gnu.org/licenses/gpl.html
11073
+;;
11074
+;;
11075
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11076
+;;
11077
+;;
11078
+;
11079
+;
11080
+;
11081
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11082
+;;
11083
+;; Atomic access Op-codes
11084
+;;
11085
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11086
+;
11087
+;
11088
+;
11089
+; First, the basic atomic_ operators, add, sub, ior, and, and xor
11090
+;
11091
+(define_insn "atomic_addsi"
11092
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
11093
+               (plus:SI (match_dup 0)
11094
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
11095
+       (const (match_operand 2 "" ""))         ; Memory model used
11096
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
11097
+       (clobber (reg:CC CC_REG))]
11098
+       "(ZIP_ATOMIC)"
11099
+       "LOCK\n\tLOD %0,%3\n\tADD %1,%3\n\tSTO %3,%0\n"
11100
+       [(set_attr "predicable" "no")])
11101
+(define_insn "atomic_subsi"
11102
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
11103
+               (minus:SI (match_dup 0)
11104
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
11105
+       (const (match_operand 2 "" ""))         ; Memory model used
11106
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
11107
+       (clobber (reg:CC CC_REG))]
11108
+       "(ZIP_ATOMIC)"
11109
+       "LOCK\n\tLOD %0,%3\n\tSUB %1,%3\n\tSTO %3,%0\n"
11110
+       [(set_attr "predicable" "no")])
11111
+(define_insn "atomic_iorsi"
11112
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
11113
+               (ior:SI (match_dup 0)
11114
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
11115
+       (const (match_operand 2 "" ""))         ; Memory model used
11116
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
11117
+       (clobber (reg:CC CC_REG))]
11118
+       "(ZIP_ATOMIC)"
11119
+       "LOCK\n\tLOD %0,%3\n\tOR %1,%3\n\tSTO %3,%0\n"
11120
+       [(set_attr "predicable" "no")])
11121
+(define_insn "atomic_andsi"
11122
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
11123
+               (and:SI (match_dup 0)
11124
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
11125
+       (const (match_operand 2 "" ""))         ; Memory model used
11126
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
11127
+       (clobber (reg:CC CC_REG))]
11128
+       "(ZIP_ATOMIC)"
11129
+       "LOCK\n\tLOD %0,%3\n\tAND %1,%3\n\tSTO %3,%0\n"
11130
+       [(set_attr "predicable" "no")])
11131
+(define_insn "atomic_xorsi"
11132
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "+Q")
11133
+               (xor:SI (match_dup 0)
11134
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
11135
+       (const (match_operand 2 "" ""))         ; Memory model used
11136
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
11137
+       (clobber (reg:CC CC_REG))]
11138
+       "(ZIP_ATOMIC)"
11139
+       "LOCK\n\tLOD %0,%3\n\tXOR %1,%3\n\tSTO %3,%0\n"
11140
+       [(set_attr "predicable" "no")])
11141
+;
11142
+;
11143
+; Given how the ZipCPU is put together, all LODs and STOs are atomic.  Hence,
11144
+; we just expand these operators so that they can be used by the other already
11145
+; existent LOD/STO RTL operators.
11146
+;
11147
+(define_expand "atomic_loadsi"
11148
+       [(set (match_operand:SI 0 "register_operand" "=r")
11149
+               (match_operand:SI 1 "zip_memory_operand_p" "Q"))])
11150
+(define_expand "atomic_loaddi"
11151
+       [(set (match_operand:SI 0 "register_operand" "=r")
11152
+               (match_operand:SI 1 "zip_memory_operand_p" "Q"))])
11153
+(define_expand "atomic_storesi"
11154
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
11155
+               (match_operand:DI 1 "register_operand" "r"))])
11156
+(define_expand "atomic_storedi"
11157
+       [(set (match_operand:SI 0 "zip_memory_operand_p" "=Q")
11158
+               (match_operand:DI 1 "register_operand" "r"))])
11159
+;
11160
+;
11161
+;
11162
+;
11163
+(define_insn "atomic_exchangesi"
11164
+       [(set (match_operand:SI 0 "register_operand" "=r")
11165
+               (match_operand:SI 1 "zip_memory_operand_p" "+Q"))
11166
+       (set (match_dup 1) (match_operand:SI 2 "register_operand" "r"))
11167
+       ; (match_operand 3 "" "")               ; Memory model used
11168
+       ]
11169
+       "(ZIP_ATOMIC)"
11170
+       "LOCK\n\tLOD %1,%0\n\tSTO %2,%1\n"
11171
+       [(set_attr "predicable" "no")])
11172
+;
11173
+;
11174
+;
11175
+; Here's another set of the atomic operators, this time those that leave their
11176
+; result in operand zero.
11177
+;
11178
+(define_insn "atomic_add_fetchsi"
11179
+       [(set (match_operand:SI 0 "register_operand" "=r")
11180
+               (plus:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
11181
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11182
+       (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))
11183
+       ; (match_operand 3 "" "")               ; Memory model used
11184
+       (clobber (reg:CC CC_REG))]
11185
+       "(ZIP_ATOMIC)"
11186
+       "LOCK\n\tLOD %1,%0\n\tADD %2,%0\n\tSTO %0,%1\n"
11187
+       [(set_attr "predicable" "no")])
11188
+(define_insn "atomic_sub_fetchsi"
11189
+       [(set (match_operand:SI 0 "register_operand" "=r")
11190
+               (minus:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
11191
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11192
+       (set (match_dup 1) (minus:SI (match_dup 1) (match_dup 2)))
11193
+       (clobber (reg:CC CC_REG))]
11194
+       "(ZIP_ATOMIC)"
11195
+       "LOCK\n\tLOD %1,%0\n\tSUB %2,%0\n\tSTO %0,%1\n"
11196
+       [(set_attr "predicable" "no")])
11197
+(define_insn "atomic_or_fetchsi"
11198
+       [(set (match_operand:SI 0 "register_operand" "=r")
11199
+               (ior:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
11200
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11201
+       (set (match_dup 1) (ior:SI (match_dup 1) (match_dup 2)))
11202
+       (clobber (reg:CC CC_REG))]
11203
+       "(ZIP_ATOMIC)"
11204
+       "LOCK\n\tLOD %1,%0\n\tOR %2,%0\n\tSTO %0,%1\n"
11205
+       [(set_attr "predicable" "no")])
11206
+(define_insn "atomic_and_fetchsi"
11207
+       [(set (match_operand:SI 0 "register_operand" "=r")
11208
+               (and:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
11209
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11210
+       (set (match_dup 1) (and:SI (match_dup 1) (match_dup 2)))
11211
+       (clobber (reg:CC CC_REG))]
11212
+       "(ZIP_ATOMIC)"
11213
+       "LOCK\n\tLOD %1,%0\n\tAND %2,%0\n\tSTO %0,%1\n"
11214
+       [(set_attr "predicable" "no")])
11215
+(define_insn "atomic_xor_fetchsi"
11216
+       [(set (match_operand:SI 0 "register_operand" "=r")
11217
+               (xor:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
11218
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11219
+       (set (match_dup 1) (xor:SI (match_dup 1) (match_dup 2)))
11220
+       (clobber (reg:CC CC_REG))]
11221
+       "(ZIP_ATOMIC)"
11222
+       "LOCK\n\tLOD %1,%0\n\tXOR %2,%0\n\tSTO %0,%1\n"
11223
+       [(set_attr "predicable" "no")])
11224
+;
11225
+;
11226
+;
11227
+;
11228
+(define_insn "atomic_fetch_addsi"
11229
+       [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
11230
+               (plus:SI (match_dup 1)
11231
+                       (match_operand:SI 2 "register_operand" "=r")))
11232
+       (set (match_operand:SI 0 "register_operand" "=r")
11233
+               (match_dup 1))
11234
+       (set (match_dup 2) (plus:SI (match_dup 1) (match_dup 2)))
11235
+       ; (match_operand 3 "" "")               ; Memory model used
11236
+       (clobber (reg:CC CC_REG))]
11237
+       "(ZIP_ATOMIC)"
11238
+       "LOCK\n\tLOD %1,%0\n\tADD %0,%2\n\tSTO %2,%1\n"
11239
+       [(set_attr "predicable" "no")])
11240
+;(define_insn "atomic_fetch_subsi"
11241
+;      [(set (match_operand:SI 0 "register_operand" "=r")
11242
+;              (minus:SI (match_operand:SI 1 "zip_memory_operand_p" "+Q")
11243
+;                      (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11244
+;      (set (match_dup 1) (minus:SI (match_dup 1) (match_dup 2)))
11245
+;      (clobber (reg:CC CC_REG))]
11246
+;      "(ZIP_ATOMIC)"
11247
+;
11248
+; HERE WE HAVE A PROBLEM ... swapping the arguments does not work for a
11249
+; subtract.  It creates the SUBR (subtract reverse) instruction, which is not
11250
+; what the RTL names is supposed to capture.  Hence ... we cannot do this one.
11251
+; If we could do two ALU instructions during the LOCK, then we might make
11252
+; this work--but LOCK only provides for a single ALU instruction.
11253
+;
11254
+;      "LOCK\n\tLOD %1,%0\n\tSUB %2,%0\n\tSTO %0,%1\n"
11255
+;      "LOCK\n\tLOD %1,%0\n\tSUB %0,%2\n\tSTO %2,%1\n"
11256
+;      [(set_attr "predicable" "no")])
11257
+(define_insn "atomic_fetch_orsi"
11258
+       [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
11259
+               (ior:SI (match_dup 1)
11260
+                       (match_operand:SI 2 "register_operand" "=r")))
11261
+       (set (match_operand:SI 0 "register_operand" "=r")
11262
+               (match_dup 1))
11263
+       (set (match_dup 2) (ior:SI (match_dup 1) (match_dup 2)))
11264
+       ; (match_operand 3 "" "")               ; Memory model used
11265
+       (clobber (reg:CC CC_REG))]
11266
+       "(ZIP_ATOMIC)"
11267
+       "LOCK\n\tLOD %1,%0\n\tOR %0,%2\n\tSTO %2,%1\n"
11268
+       [(set_attr "predicable" "no")])
11269
+(define_insn "atomic_fetch_andsi"
11270
+       [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
11271
+               (and:SI (match_dup 1)
11272
+                       (match_operand:SI 2 "register_operand" "=r")))
11273
+       (set (match_operand:SI 0 "register_operand" "=r")
11274
+               (match_dup 1))
11275
+       (set (match_dup 2) (and:SI (match_dup 1) (match_dup 2)))
11276
+       ; (match_operand 3 "" "")               ; Memory model used
11277
+       (clobber (reg:CC CC_REG))]
11278
+       "(ZIP_ATOMIC)"
11279
+       "LOCK\n\tLOD %1,%0\n\tAND %0,%2\n\tSTO %2,%1\n"
11280
+       [(set_attr "predicable" "no")])
11281
+(define_insn "atomic_fetch_xorsi"
11282
+       [(set (match_operand:SI 1 "zip_memory_operand_p" "+Q")
11283
+               (xor:SI (match_dup 1)
11284
+                       (match_operand:SI 2 "register_operand" "=r")))
11285
+       (set (match_operand:SI 0 "register_operand" "=r")
11286
+               (match_dup 1))
11287
+       (set (match_dup 2) (xor:SI (match_dup 1) (match_dup 2)))
11288
+       ; (match_operand 3 "" "")               ; Memory model used
11289
+       (clobber (reg:CC CC_REG))]
11290
+       "(ZIP_ATOMIC)"
11291
+       "LOCK\n\tLOD %1,%0\n\tXOR %0,%2\n\tSTO %2,%1\n"
11292
+       [(set_attr "predicable" "no")])
11293
+;
11294
+;
11295
+;
11296
+;
11297
+(define_insn "atomic_test_and_set"
11298
+       [(set (match_operand:SI 0 "register_operand" "=r")
11299
+               (match_operand:SI 1 "zip_memory_operand_p" "+Q"))
11300
+       (set (match_dup 1)
11301
+               (if_then_else
11302
+                       (eq (match_dup 1)
11303
+                               (const_int 0))
11304
+                       (const_int 1)
11305
+                       (match_dup 1)))
11306
+       (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))
11307
+       (set (match_scratch:SI 3) (const_int 1))
11308
+       (const (match_operand 2 "" ""))]        ; Memory model used
11309
+       "(ZIP_ATOMIC)"
11310
+       "LDI    1,%3
11311
+       LOCK
11312
+       LOD     %1,%0
11313
+       TST     %0
11314
+       STO.Z   %3,%1\n"
11315
+       [(set_attr "predicable" "no")])
11316
+;
11317
+;
11318
+;
11319
+(define_insn "atomic_compare_and_swapsi"
11320
+       [(set (match_operand:SI 0 "register_operand" "=r")
11321
+               (if_then_else
11322
+                       (eq (match_operand:SI 2 "zip_memory_operand_p" "+Q")
11323
+                               (match_operand:SI 3 "zip_opb_single_operand_p" "rO"))
11324
+                       (const_int 1)
11325
+                       (const_int 0)))
11326
+       (set (match_operand:SI 1 "register_operand" "=r") (match_dup 2))
11327
+       (set (match_dup 2) (if_then_else
11328
+                       (eq (match_dup 2) (match_dup 3))
11329
+                               (match_operand:SI 4 "register_operand" "r")
11330
+                               (match_dup 0)))]
11331
+       "(ZIP_ATOMIC)"
11332
+       "CLR %0
11333
+       LOCK
11334
+       LOD %2,%1
11335
+       CMP %3,%1
11336
+       STO.Z %4,%1
11337
+       LDI.Z 1,%0"
11338
+       [(set_attr "predicable" "no")])
11339
+;
11340
+;
11341
+;
11342
+;
11343
+; STILL MISSING:
11344
+;
11345
+;      deprecated sync_* atomic functions
11346
+;
11347 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/config.gcc gcc-5.3.0-zip/gcc/config.gcc
11348
--- gcc-5.3.0-original/gcc/config.gcc   2015-09-10 10:17:53.000000000 -0400
11349
+++ gcc-5.3.0-zip/gcc/config.gcc        2016-02-14 00:53:37.389411987 -0500
11350
@@ -479,6 +479,10 @@
11351
 tilepro*-*-*)
11352
        cpu_type=tilepro
11353
        ;;
11354
+zip*)
11355
+       cpu_type=zip
11356
+       tmake_file=zip/t-zip
11357
+       ;;
11358
 esac
11359
 
11360
 tm_file=${cpu_type}/${cpu_type}.h
11361
@@ -2972,6 +2976,15 @@
11362
        c_target_objs="m32c-pragma.o"
11363
        cxx_target_objs="m32c-pragma.o"
11364
        ;;
11365
+zip-*-netbsd*)
11366
+       tm_file="${tm_file} elfos.h netbsd.h netbsd-elf.h zip/netbsd.h"
11367
+       tmake_file="${tmake_file} zip/t-zip"
11368
+       ;;
11369
+zip*)
11370
+       target_has_targetm_common=yes
11371
+       tm_file="elfos.h newlib-stdint.h ${tm_file}"
11372
+       tmake_file="${tmake_file} zip/t-zip"
11373
+       ;;
11374
 *)
11375
        echo "*** Configuration ${target} not supported" 1>&2
11376
        exit 1
11377
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/cse.c gcc-5.3.0-zip/gcc/cse.c
11378
--- gcc-5.3.0-original/gcc/cse.c        2015-02-03 15:41:38.000000000 -0500
11379 138 dgisselq
+++ gcc-5.3.0-zip/gcc/cse.c     2016-05-04 11:07:38.874831028 -0400
11380
@@ -70,6 +70,7 @@
11381
 #include "dbgcnt.h"
11382
 #include "rtl-iter.h"
11383
 
11384
+
11385
 /* The basic idea of common subexpression elimination is to go
11386
    through the code, keeping a record of expressions that would
11387
    have the same value at the current scan point, and replacing
11388
@@ -634,6 +635,16 @@
11389 102 dgisselq
 
11390
 /* Nonzero if X has the form (PLUS frame-pointer integer).  */
11391
 
11392 111 dgisselq
+// #define     DO_ZIP_DEBUGS
11393 102 dgisselq
+#ifdef DO_ZIP_DEBUGS
11394
+#include <stdio.h>
11395 138 dgisselq
+extern void    zip_debug_rtx(const_rtx);
11396
+extern void    zip_debug_rtx_pfx(char *, const_rtx);
11397 102 dgisselq
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s\n", STR); zip_debug_rtx(RTX); } while(0)
11398
+#else
11399
+#define        ZIP_DEBUG_LINE(STR,RTX)
11400
+#endif
11401
+
11402
 static bool
11403
 fixed_base_plus_p (rtx x)
11404
 {
11405 138 dgisselq
@@ -2898,6 +2909,7 @@
11406 102 dgisselq
          validate_canon_reg (&XVECEXP (x, i, j), insn);
11407
     }
11408
 
11409
+       ZIP_DEBUG_LINE("CANON-REG-RTN", x);
11410
   return x;
11411
 }
11412
 
11413 138 dgisselq
@@ -3125,6 +3137,8 @@
11414
   rtx new_rtx = 0;
11415
   int changed = 0;
11416
 
11417
+ZIP_DEBUG_LINE("CSE:FOLD-RTX", insn);
11418
+
11419
   /* Operands of X.  */
11420
   /* Workaround -Wmaybe-uninitialized false positive during
11421
      profiledbootstrap by initializing them.  */
11422
@@ -3144,14 +3158,16 @@
11423 102 dgisselq
   if (x == 0)
11424
     return x;
11425
 
11426
+       ZIP_DEBUG_LINE("FOLD-RTX", x);
11427
   /* Try to perform some initial simplifications on X.  */
11428
   code = GET_CODE (x);
11429
   switch (code)
11430
     {
11431
     case MEM:
11432
     case SUBREG:
11433
-      if ((new_rtx = equiv_constant (x)) != NULL_RTX)
11434
-        return new_rtx;
11435
+      if ((new_rtx = equiv_constant (x)) != NULL_RTX) {
11436
+       ZIP_DEBUG_LINE("FOLD-RTX-NEW", new_rtx);
11437
+        return new_rtx; }
11438
       return x;
11439
 
11440
     case CONST:
11441 138 dgisselq
@@ -3208,6 +3224,8 @@
11442 102 dgisselq
        rtx folded_arg = XEXP (x, i), const_arg;
11443
        machine_mode mode_arg = GET_MODE (folded_arg);
11444
 
11445
+       ZIP_DEBUG_LINE("FOLD-RTX-ARG = ", folded_arg);
11446
+
11447
        switch (GET_CODE (folded_arg))
11448
          {
11449
          case MEM:
11450 138 dgisselq
@@ -3317,6 +3335,7 @@
11451 102 dgisselq
        }
11452
 
11453
       apply_change_group ();
11454
+       ZIP_DEBUG_LINE("FOLD-RTX-CANONICALIZED = ", insn);
11455
     }
11456
 
11457
   /* If X is an arithmetic operation, see if we can simplify it.  */
11458 138 dgisselq
@@ -4203,6 +4222,7 @@
11459 102 dgisselq
 {
11460
   rtx dest = SET_DEST (set);
11461
   rtx src = SET_SRC (set);
11462
+       ZIP_DEBUG_LINE("TRY-BACK-SUBSTITUTE-REG", insn);
11463
 
11464
   if (REG_P (dest)
11465
       && REG_P (src) && ! HARD_REGISTER_P (src)
11466 138 dgisselq
@@ -4258,6 +4278,7 @@
11467 102 dgisselq
            }
11468
        }
11469
     }
11470
+       ZIP_DEBUG_LINE("TRY-BACK-SUBSTITUTE-REG, done", insn);
11471
 }
11472
 
11473
 /* Record all the SETs in this instruction into SETS_PTR,
11474 138 dgisselq
@@ -4351,6 +4372,7 @@
11475 102 dgisselq
   rtx tem;
11476
   rtx x = PATTERN (insn);
11477
   int i;
11478
+       ZIP_DEBUG_LINE("CANONICALIZE-INSN", insn);
11479
 
11480
   if (CALL_P (insn))
11481
     {
11482 138 dgisselq
@@ -4364,6 +4386,7 @@
11483 102 dgisselq
       canon_reg (SET_SRC (x), insn);
11484
       apply_change_group ();
11485
       fold_rtx (SET_SRC (x), insn);
11486
+       ZIP_DEBUG_LINE("CANONICALIZE-INSN, was set:", insn);
11487
     }
11488
   else if (GET_CODE (x) == CLOBBER)
11489
     {
11490 138 dgisselq
@@ -4400,6 +4423,7 @@
11491 102 dgisselq
     canon_reg (PATTERN (insn), insn);
11492
   else if (GET_CODE (x) == PARALLEL)
11493
     {
11494
+       ZIP_DEBUG_LINE("CANONICALIZE-INSN/parallel", insn);
11495
       for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
11496
        {
11497
          rtx y = XVECEXP (x, 0, i);
11498 138 dgisselq
@@ -4491,6 +4515,7 @@
11499 102 dgisselq
 
11500
      The result of apply_change_group can be ignored; see canon_reg.  */
11501
 
11502
+       ZIP_DEBUG_LINE("CANONICALIZE-INSN/done", insn);
11503
   apply_change_group ();
11504
 }
11505
 
11506
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/defaults.h gcc-5.3.0-zip/gcc/defaults.h
11507
--- gcc-5.3.0-original/gcc/defaults.h   2015-03-03 10:04:02.000000000 -0500
11508
+++ gcc-5.3.0-zip/gcc/defaults.h        2016-02-06 16:57:53.939410173 -0500
11509
@@ -480,6 +480,8 @@
11510
 #define LOG2_BITS_PER_UNIT 3
11511
 #elif BITS_PER_UNIT == 16
11512
 #define LOG2_BITS_PER_UNIT 4
11513
+#elif BITS_PER_UNIT == 32
11514
+#define LOG2_BITS_PER_UNIT 5
11515
 #else
11516
 #error Unknown BITS_PER_UNIT
11517
 #endif
11518 127 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/df-scan.c gcc-5.3.0-zip/gcc/df-scan.c
11519
--- gcc-5.3.0-original/gcc/df-scan.c    2015-01-09 15:18:42.000000000 -0500
11520
+++ gcc-5.3.0-zip/gcc/df-scan.c 2016-04-14 16:12:03.614777002 -0400
11521
@@ -61,6 +61,14 @@
11522
 
11523
 typedef struct df_mw_hardreg *df_mw_hardreg_ptr;
11524
 
11525
+// #define     DO_ZIP_DEBUGS
11526
+#ifdef DO_ZIP_DEBUGS
11527
+extern void    zip_debug_rtx(const_rtx);
11528
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
11529
+#else
11530
+#define        ZIP_DEBUG_LINE(STR,RTX)
11531
+#endif
11532
+
11533
 
11534
 #ifndef HAVE_epilogue
11535
 #define HAVE_epilogue 0
11536 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/doc/gcc.log gcc-5.3.0-zip/gcc/doc/gcc.log
11537
--- gcc-5.3.0-original/gcc/doc/gcc.log  1969-12-31 19:00:00.000000000 -0500
11538
+++ gcc-5.3.0-zip/gcc/doc/gcc.log       2016-01-30 15:18:43.262724969 -0500
11539
@@ -0,0 +1,214 @@
11540
+This is pdfTeX, Version 3.1415926-2.5-1.40.14 (TeX Live 2013/Debian) (format=pdfetex 2014.5.7)  30 JAN 2016 15:17
11541
+entering extended mode
11542
+ restricted \write18 enabled.
11543
+ file:line:error style messages enabled.
11544
+ %&-line parsing enabled.
11545
+**\catcode126=12 \def\normaltilde{~}\catcode126=13 \let~\normaltilde  \input ./
11546
+gcc.texi
11547
+(./gcc.texi (/usr/share/texmf/tex/texinfo/texinfo.tex
11548
+Loading texinfo [version 2013-09-11.11]:
11549
+\bindingoffset=\dimen16
11550
+\normaloffset=\dimen17
11551
+\pagewidth=\dimen18
11552
+\pageheight=\dimen19
11553
+\outerhsize=\dimen20
11554
+\outervsize=\dimen21
11555
+\cornerlong=\dimen22
11556
+\cornerthick=\dimen23
11557
+\topandbottommargin=\dimen24
11558
+\headlinebox=\box16
11559
+\footlinebox=\box17
11560
+\margin=\insert252
11561
+\EMsimple=\toks13
11562
+\groupbox=\box18
11563
+\groupinvalidhelp=\toks14
11564
+\mil=\dimen25
11565
+\exdentamount=\skip18
11566
+\inmarginspacing=\skip19
11567
+\centerpenalty=\count27
11568
+ pdf,
11569
+\tempnum=\count28
11570
+\lnkcount=\count29
11571
+\filename=\toks15
11572
+\filenamelength=\count30
11573
+\pgn=\count31
11574
+\toksA=\toks16
11575
+\toksB=\toks17
11576
+\toksC=\toks18
11577
+\toksD=\toks19
11578
+\boxA=\box19
11579
+\countA=\count32
11580
+\nopdfimagehelp=\toks20
11581
+ fonts,
11582
+\sffam=\fam8
11583
+\textleading=\dimen26
11584
+ markup,
11585
+\fontdepth=\count33
11586
+ glyphs,
11587
+\errorbox=\box20
11588
+
11589
+page headings,
11590
+\titlepagetopglue=\skip20
11591
+\titlepagebottomglue=\skip21
11592
+\evenheadline=\toks21
11593
+\oddheadline=\toks22
11594
+\evenfootline=\toks23
11595
+\oddfootline=\toks24
11596
+ tables,
11597
+\tableindent=\dimen27
11598
+\itemindent=\dimen28
11599
+\itemmargin=\dimen29
11600
+\itemmax=\dimen30
11601
+\itemno=\count34
11602
+\multitableparskip=\skip22
11603
+\multitableparindent=\skip23
11604
+\multitablecolspace=\dimen31
11605
+\multitablelinespace=\skip24
11606
+\colcount=\count35
11607
+\everytab=\toks25
11608
+ conditionals,
11609
+\doignorecount=\count36
11610
+ indexing,
11611
+\whatsitskip=\skip25
11612
+\whatsitpenalty=\count37
11613
+\secondaryindent=\skip26
11614
+\partialpage=\box21
11615
+\doublecolumnhsize=\dimen32
11616
+ sectioning,
11617
+\unnumberedno=\count38
11618
+\chapno=\count39
11619
+\secno=\count40
11620
+\subsecno=\count41
11621
+\subsubsecno=\count42
11622
+\appendixno=\count43
11623
+\absseclevel=\count44
11624
+\secbase=\count45
11625
+\chapheadingskip=\skip27
11626
+\secheadingskip=\skip28
11627
+\subsecheadingskip=\skip29
11628
+ toc,
11629
+\tocfile=\write0
11630
+\contentsrightmargin=\skip30
11631
+\savepageno=\count46
11632
+\lastnegativepageno=\count47
11633
+\tocindent=\dimen33
11634
+ environments,
11635
+\lispnarrowing=\skip31
11636
+\envskipamount=\skip32
11637
+\circthick=\dimen34
11638
+\cartouter=\dimen35
11639
+\cartinner=\dimen36
11640
+\normbskip=\skip33
11641
+\normpskip=\skip34
11642
+\normlskip=\skip35
11643
+\lskip=\skip36
11644
+\rskip=\skip37
11645
+\nonfillparindent=\dimen37
11646
+\tabw=\dimen38
11647
+\verbbox=\box22
11648
+
11649
+defuns,
11650
+\defbodyindent=\skip38
11651
+\defargsindent=\skip39
11652
+\deflastargmargin=\skip40
11653
+\defunpenalty=\count48
11654
+\parencount=\count49
11655
+\brackcount=\count50
11656
+ macros,
11657
+\paramno=\count51
11658
+\macname=\toks26
11659
+ cross references,
11660
+\auxfile=\write1
11661
+\savesfregister=\count52
11662
+\toprefbox=\box23
11663
+\printedrefnamebox=\box24
11664
+\infofilenamebox=\box25
11665
+\printedmanualbox=\box26
11666
+ insertions,
11667
+\footnoteno=\count53
11668
+\SAVEfootins=\box27
11669
+\SAVEmargin=\box28
11670
+
11671
+(/usr/share/texlive/texmf-dist/tex/generic/epsf/epsf.tex
11672
+This is `epsf.tex' v2.7.4 <14 February 2011>
11673
+\epsffilein=\read1
11674
+\epsfframemargin=\dimen39
11675
+\epsfframethickness=\dimen40
11676
+\epsfrsize=\dimen41
11677
+\epsftmp=\dimen42
11678
+\epsftsize=\dimen43
11679
+\epsfxsize=\dimen44
11680
+\epsfysize=\dimen45
11681
+\pspoints=\dimen46
11682
+)
11683
+\noepsfhelp=\toks27
11684
+ localization,
11685
+\nolanghelp=\toks28
11686
+\countUTFx=\count54
11687
+\countUTFy=\count55
11688
+\countUTFz=\count56
11689
+ formatting,
11690
+\defaultparindent=\dimen47
11691
+ and turning on texinfo input format.)
11692
+\openout1 = `gcc.aux'.
11693
+
11694
+@cpindfile=@write2
11695
+@fnindfile=@write3
11696
+@vrindfile=@write4
11697
+@tpindfile=@write5
11698
+@kyindfile=@write6
11699
+@pgindfile=@write7
11700
+texinfo.tex: doing @include of gcc-common.texi
11701
+
11702
+
11703
+./gcc.texi:25: I can't find file `gcc-common.texi'.
11704
+@temp ->@input gcc-common.texi
11705
+
11706
+@includezzz ...and @input #1 }@expandafter }@temp
11707
+                                                  @popthisfilestack
11708
+l.25 @include gcc-common.texi
11709
+
11710
+(Press Enter to retry, or Control-D to exit)
11711
+Please type another input file name: include/gcc-common.texi
11712
+(./include/gcc-common.texi
11713
+texinfo.tex: doing @include of gcc-vers.texi
11714
+
11715
+
11716
+./include/gcc-common.texi:11: I can't find file `gcc-vers.texi'.
11717
+@temp ->@input gcc-vers.texi
11718
+
11719
+@includezzz ...and @input #1 }@expandafter }@temp
11720
+                                                  @popthisfilestack
11721
+l.11 @include gcc-vers.texi
11722
+
11723
+(Press Enter to retry, or Control-D to exit)
11724
+Please type another input file name: include/gcc-vers.texi
11725
+./include/gcc-common.texi:11: I can't find file `include/gcc-vers.texi'.
11726
+@temp ->@input gcc-vers.texi
11727
+
11728
+@includezzz ...and @input #1 }@expandafter }@temp
11729
+                                                  @popthisfilestack
11730
+l.11 @include gcc-vers.texi
11731
+
11732
+(Press Enter to retry, or Control-D to exit)
11733
+Please type another input file name:
11734
+./include/gcc-common.texi:11: I can't find file `include/gcc-vers.texi'.
11735
+@temp ->@input gcc-vers.texi
11736
+
11737
+@includezzz ...and @input #1 }@expandafter }@temp
11738
+                                                  @popthisfilestack
11739
+l.11 @include gcc-vers.texi
11740
+
11741
+(Press Enter to retry, or Control-D to exit)
11742
+Please type another input file name:
11743
+./include/gcc-common.texi:11: Emergency stop.
11744
+@temp ->@input gcc-vers.texi
11745
+
11746
+@includezzz ...and @input #1 }@expandafter }@temp
11747
+                                                  @popthisfilestack
11748
+l.11 @include gcc-vers.texi
11749
+
11750
+End of file on the terminal!
11751
+
11752
+./include/gcc-common.texi:11:  ==> Fatal error occurred, no output PDF file pro
11753
+duced!
11754 117 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/emit-rtl.c gcc-5.3.0-zip/gcc/emit-rtl.c
11755
--- gcc-5.3.0-original/gcc/emit-rtl.c   2015-08-05 07:20:59.000000000 -0400
11756 138 dgisselq
+++ gcc-5.3.0-zip/gcc/emit-rtl.c        2016-05-02 07:48:47.925017436 -0400
11757 117 dgisselq
@@ -81,6 +81,15 @@
11758
 #include "builtins.h"
11759
 #include "rtl-iter.h"
11760
 
11761
+// #define     DO_ZIP_DEBUGS
11762
+#include <stdio.h>
11763
+#ifdef DO_ZIP_DEBUGS
11764
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
11765
+extern void    zip_debug_rtx(const_rtx);
11766
+#else
11767
+#define        ZIP_DEBUG_LINE(STR,RTX)
11768
+#endif
11769
+
11770
 struct target_rtl default_target_rtl;
11771
 #if SWITCHABLE_TARGET
11772
 struct target_rtl *this_target_rtl = &default_target_rtl;
11773 127 dgisselq
@@ -2979,6 +2988,8 @@
11774 117 dgisselq
       break;
11775
     }
11776
 
11777
+ZIP_DEBUG_LINE("Before RTX_FLAG",x);
11778
+
11779
   /* This rtx may not be shared.  If it has already been seen,
11780
      replace it with a copy of itself.  */
11781
 
11782 127 dgisselq
@@ -2989,6 +3000,8 @@
11783 117 dgisselq
     }
11784
   RTX_FLAG (x, used) = 1;
11785
 
11786
+ZIP_DEBUG_LINE("Post RTX_FLAG",x);
11787
+
11788
   /* Now scan the subexpressions recursively.
11789
      We can store any replaced subexpressions directly into X
11790
      since we know X is not shared!  Any vectors in X
11791 127 dgisselq
@@ -3665,7 +3678,9 @@
11792
     split_branch_probability = XINT (note, 0);
11793
   probability = split_branch_probability;
11794
 
11795
+ZIP_DEBUG_LINE("Before split", trial);
11796
   seq = safe_as_a <rtx_insn *> (split_insns (pat, trial));
11797
+ZIP_DEBUG_LINE("After split", seq);
11798
 
11799
   split_branch_probability = -1;
11800
 
11801
@@ -3834,6 +3849,7 @@
11802
     if (! tem->deleted () && INSN_P (tem))
11803
       tem = try_split (PATTERN (tem), tem, 1);
11804
 
11805
+
11806
   /* Return either the first or the last insn, depending on which was
11807
      requested.  */
11808
   return last
11809 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/expr.c gcc-5.3.0-zip/gcc/expr.c
11810
--- gcc-5.3.0-original/gcc/expr.c       2015-04-07 10:34:06.000000000 -0400
11811 103 dgisselq
+++ gcc-5.3.0-zip/gcc/expr.c    2016-03-08 04:07:01.426335724 -0500
11812 102 dgisselq
@@ -7999,6 +7999,8 @@
11813
    the back of the caller.
11814
    The normal operating mode is to pass FALSE for this parameter.  */
11815
 
11816
+#include "print-tree.h"
11817
+
11818
 rtx
11819
 expand_expr_real (tree exp, rtx target, machine_mode tmode,
11820
                  enum expand_modifier modifier, rtx *alt_rtl,
11821 111 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/final.c gcc-5.3.0-zip/gcc/final.c
11822
--- gcc-5.3.0-original/gcc/final.c      2015-01-15 08:28:42.000000000 -0500
11823 127 dgisselq
+++ gcc-5.3.0-zip/gcc/final.c   2016-04-20 20:52:07.186056061 -0400
11824 111 dgisselq
@@ -109,6 +109,14 @@
11825
 #include "wide-int-print.h"
11826
 #include "rtl-iter.h"
11827
 
11828 122 dgisselq
+// #define     DO_ZIP_DEBUGS
11829 111 dgisselq
+#ifdef DO_ZIP_DEBUGS
11830
+extern void zip_debug_rtx(const_rtx);
11831
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
11832
+#else
11833
+#define        ZIP_DEBUG_LINE(STR,RTX)
11834
+#endif
11835
+
11836
 #ifdef XCOFF_DEBUGGING_INFO
11837
 #include "xcoffout.h"          /* Needed for external data
11838
                                   declarations for e.g. AIX 4.x.  */
11839
@@ -2071,6 +2079,8 @@
11840
   /* Output the insns.  */
11841
   for (insn = first; insn;)
11842
     {
11843
+       ZIP_DEBUG_LINE("final()\n", insn);
11844
+
11845
       if (HAVE_ATTR_length)
11846
        {
11847
          if ((unsigned) INSN_UID (insn) >= INSN_ADDRESSES_SIZE ())
11848 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/genmodes.c gcc-5.3.0-zip/gcc/genmodes.c
11849
--- gcc-5.3.0-original/gcc/genmodes.c   2015-01-05 07:33:28.000000000 -0500
11850
+++ gcc-5.3.0-zip/gcc/genmodes.c        2016-03-04 21:27:49.669147699 -0500
11851
@@ -330,7 +330,8 @@
11852
         the size of a CC mode is four units.  */
11853
       validate_mode (m, UNSET, UNSET, UNSET, UNSET, UNSET);
11854
 
11855
-      m->bytesize = 4;
11856
+       /* For the ZipCPU, however, it is only one unit */
11857
+      m->bytesize = 1;
11858
       m->ncomponents = 1;
11859
       m->component = 0;
11860
       break;
11861
@@ -766,11 +767,12 @@
11862
 
11863
   /* So put the default value unless the target needs a non standard
11864
      value. */
11865
-#ifdef BITS_PER_UNIT
11866
-  bits_per_unit = BITS_PER_UNIT;
11867
-#else
11868
-  bits_per_unit = 8;
11869
-#endif
11870
+// #ifdef BITS_PER_UNIT
11871
+  // bits_per_unit = BITS_PER_UNIT;
11872
+// #else
11873
+  bits_per_unit = 32;
11874
+#warning "Is there a more automated way to set bits per unit?"
11875
+// #endif
11876
 
11877
 #ifdef MAX_BITSIZE_MODE_ANY_INT
11878
   max_bitsize_mode_any_int = MAX_BITSIZE_MODE_ANY_INT;
11879
@@ -1083,7 +1085,7 @@
11880
       first = modes[c];
11881
       last = 0;
11882
       for (m = first; m; last = m, m = m->next)
11883
-       ;
11884
+       if ((m->next)&&(m->next->bytesize == m->bytesize)) first = m;
11885
 
11886
       /* Don't use BImode for MIN_MODE_INT, since otherwise the middle
11887
         end will try to use it for bitfields in structures and the
11888
@@ -1268,7 +1270,7 @@
11889
            continue;
11890
          if (m->precision != (unsigned int) -1)
11891
            {
11892
-             if (m2->precision != 2 * m->precision)
11893
+             if (m2->precision < 2 * m->precision)
11894
                continue;
11895
            }
11896
          else
11897
@@ -1323,7 +1325,6 @@
11898
       tagged_printf ("MODE_MASK (%u)", m->precision, m->name);
11899
     else
11900
       tagged_printf ("MODE_MASK (%u*BITS_PER_UNIT)", m->bytesize, m->name);
11901
-
11902
   puts ("#undef MODE_MASK");
11903
   print_closer ();
11904
 }
11905
@@ -1351,12 +1352,23 @@
11906
   int c;
11907
   struct mode_data *m;
11908
 
11909
+  puts(
11910
+"\n\n/* This is a rather strange conundrum.  Alignment is used by the host in\n"
11911
+" * the assembly file, whereas the size is used by the target.  Thus, for\n"
11912
+" * now, to align to a single target word means to align to 4 8-bit bytes in\n"
11913
+" * assembly.  If you get it wrong, the assembler will try to help.  Thus,\n"
11914
+" * aligning to anything less than 4 (1 target word) will cause an alignment\n"
11915
+" * of the target word in size.  However, this tries to do a little something\n"
11916
+" * teach our compiler what we are doing.\n"
11917
+" */\n");
11918
   print_maybe_const_decl ("%sunsigned char",
11919
                          "mode_base_align", "NUM_MACHINE_MODES",
11920
                          alignment);
11921
 
11922
   for_all_modes (c, m)
11923
-    tagged_printf ("%u", m->alignment, m->name);
11924
+    tagged_printf ("%u", 4*m->bytesize,
11925
+               // m->alignment,
11926
+               m->name);
11927
 
11928
   print_closer ();
11929
 }
11930 117 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/jump.c gcc-5.3.0-zip/gcc/jump.c
11931
--- gcc-5.3.0-original/gcc/jump.c       2015-01-27 04:19:30.000000000 -0500
11932 122 dgisselq
+++ gcc-5.3.0-zip/gcc/jump.c    2016-04-06 14:06:50.207563805 -0400
11933 117 dgisselq
@@ -80,6 +80,14 @@
11934
 #include "target.h"
11935
 #include "rtl-iter.h"
11936
 
11937
+// #define     DO_ZIP_DEBUGS
11938
+#ifdef DO_ZIP_DEBUGS
11939
+#include <stdio.h>
11940
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
11941
+extern void zip_debug_rtx(const_rtx);
11942
+#else
11943
+#define        ZIP_DEBUG_LINE(STR,RTX)
11944
+#endif
11945
 /* Optimize jump y; x: ... y: jumpif... x?
11946
    Don't know if it is worth bothering with.  */
11947
 /* Optimize two cases of conditional jump to conditional jump?
11948
@@ -1136,6 +1144,7 @@
11949
   int i;
11950
   const char *fmt;
11951
 
11952
+ZIP_DEBUG_LINE("Mark jump label",insn);
11953
   switch (code)
11954
     {
11955
     case PC:
11956
@@ -1248,6 +1257,8 @@
11957
       break;
11958
     }
11959
 
11960
+ZIP_DEBUG_LINE("Post case",insn);
11961
+
11962
   fmt = GET_RTX_FORMAT (code);
11963
 
11964
   /* The primary target of a tablejump is the label of the ADDR_VEC,
11965 191 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/loop-doloop.c gcc-5.3.0-zip/gcc/loop-doloop.c
11966
--- gcc-5.3.0-original/gcc/loop-doloop.c        2015-01-15 08:28:42.000000000 -0500
11967
+++ gcc-5.3.0-zip/gcc/loop-doloop.c     2016-09-13 12:12:36.248901944 -0400
11968
@@ -62,6 +62,13 @@
11969
 #include "dumpfile.h"
11970
 #include "loop-unroll.h"
11971
 
11972
+// #define     DO_ZIP_DEBUGS
11973
+#ifdef DO_ZIP_DEBUGS
11974
+extern void    zip_debug_rtx(const_rtx);
11975
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
11976
+#else
11977
+#define        ZIP_DEBUG_LINE(STR,RTX)
11978
+#endif
11979
 /* This module is used to modify loops with a determinable number of
11980
    iterations to use special low-overhead looping instructions.
11981
 
11982
@@ -138,7 +145,7 @@
11983
 
11984
   pattern = PATTERN (doloop_pat);
11985
 
11986
-  if (GET_CODE (pattern) != PARALLEL)
11987
+  if (GET_CODE (doloop_pat) != PARALLEL)
11988
     {
11989
       rtx cond;
11990
       rtx prev_insn = prev_nondebug_insn (doloop_pat);
11991
@@ -186,10 +193,11 @@
11992
     }
11993
   else
11994
     {
11995
-      cmp = XVECEXP (pattern, 0, 0);
11996
-      inc = XVECEXP (pattern, 0, 1);
11997
+      cmp = XVECEXP (doloop_pat, 0, 0);
11998
+      inc = XVECEXP (doloop_pat, 0, 1);
11999
     }
12000
 
12001
+
12002
   /* Check for (set (reg) (something)).  */
12003
   if (GET_CODE (inc) != SET)
12004
     return 0;
12005
@@ -227,6 +235,7 @@
12006
           && XEXP (condition, 1) != const1_rtx))
12007
     return 0;
12008
 
12009
+
12010
   if ((XEXP (condition, 0) == reg)
12011
       /* For the third case:  */
12012
       || ((cc_reg != NULL_RTX)
12013
@@ -235,7 +244,7 @@
12014
       || (GET_CODE (XEXP (condition, 0)) == PLUS
12015
          && XEXP (XEXP (condition, 0), 0) == reg))
12016
    {
12017
-     if (GET_CODE (pattern) != PARALLEL)
12018
+     if (GET_CODE (doloop_pat) != PARALLEL)
12019
      /*  For the second form we expect:
12020
 
12021
          (set (reg) (plus (reg) (const_int -1))
12022
@@ -275,6 +284,7 @@
12023
     return condition;
12024
    }
12025
 
12026
+
12027
   /* ??? If a machine uses a funny comparison, we could return a
12028
      canonicalized form here.  */
12029
 
12030
@@ -500,7 +510,6 @@
12031
     default:
12032
       gcc_unreachable ();
12033
     }
12034
-
12035
   if (increment_count)
12036
     count = simplify_gen_binary (PLUS, mode, count, const1_rtx);
12037
 
12038 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/machmode.def gcc-5.3.0-zip/gcc/machmode.def
12039
--- gcc-5.3.0-original/gcc/machmode.def 2015-01-05 07:33:28.000000000 -0500
12040 111 dgisselq
+++ gcc-5.3.0-zip/gcc/machmode.def      2016-03-08 11:56:45.375491523 -0500
12041 102 dgisselq
@@ -184,11 +184,11 @@
12042
    larger types, then corresponding modes must be added here.  The
12043
    name OI is reserved for a 256-bit type (needed by some back ends).
12044
     */
12045
-INT_MODE (QI, 1);
12046
-INT_MODE (HI, 2);
12047
-INT_MODE (SI, 4);
12048
-INT_MODE (DI, 8);
12049
-INT_MODE (TI, 16);
12050
+// INT_MODE (QI, 1);
12051
+// INT_MODE (HI, 1);
12052
+INT_MODE (SI, 1);
12053
+INT_MODE (DI, 2);
12054
+INT_MODE (TI, 4);
12055
 
12056
 /* No partial integer modes are defined by default.  */
12057
 
12058 111 dgisselq
@@ -206,35 +206,35 @@
12059 102 dgisselq
    These are the IEEE mappings.  They can be overridden with
12060
    RESET_FLOAT_FORMAT or at runtime (in TARGET_OPTION_OVERRIDE).  */
12061
 
12062
-FLOAT_MODE (SF, 4, ieee_single_format);
12063
-FLOAT_MODE (DF, 8, ieee_double_format);
12064
+FLOAT_MODE (SF, 1, ieee_single_format);
12065
+FLOAT_MODE (DF, 2, ieee_double_format);
12066
 
12067
 /* Basic CC modes.
12068
    FIXME define this only for targets that need it.  */
12069 111 dgisselq
 CC_MODE (CC);
12070 102 dgisselq
 
12071
 /* Fixed-point modes.  */
12072 111 dgisselq
-FRACT_MODE (QQ, 1, 7); /* s.7 */
12073 102 dgisselq
-FRACT_MODE (HQ, 2, 15); /* s.15 */
12074
-FRACT_MODE (SQ, 4, 31); /* s.31 */
12075
-FRACT_MODE (DQ, 8, 63); /* s.63 */
12076
-FRACT_MODE (TQ, 16, 127); /* s.127 */
12077 111 dgisselq
-
12078
-UFRACT_MODE (UQQ, 1, 8); /* .8 */
12079 102 dgisselq
-UFRACT_MODE (UHQ, 2, 16); /* .16 */
12080
-UFRACT_MODE (USQ, 4, 32); /* .32 */
12081
-UFRACT_MODE (UDQ, 8, 64); /* .64 */
12082
-UFRACT_MODE (UTQ, 16, 128); /* .128 */
12083 111 dgisselq
-
12084
-ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
12085
-ACCUM_MODE (SA, 4, 16, 15); /* s16.15 */
12086
-ACCUM_MODE (DA, 8, 32, 31); /* s32.31 */
12087
-ACCUM_MODE (TA, 16, 64, 63); /* s64.63 */
12088
-
12089
-UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
12090
-UACCUM_MODE (USA, 4, 16, 16); /* 16.16 */
12091
-UACCUM_MODE (UDA, 8, 32, 32); /* 32.32 */
12092
-UACCUM_MODE (UTA, 16, 64, 64); /* 64.64 */
12093
+/* FRACT_MODE (QQ, 1, 7); /* s.7 */
12094
+/* FRACT_MODE (HQ, 1, 15); /* s.15 */
12095
+FRACT_MODE (SQ, 1, 31); /* s.31 */
12096
+FRACT_MODE (DQ, 2, 63); /* s.63 */
12097
+FRACT_MODE (TQ, 4, 127); /* s.127 */
12098
+
12099
+/* UFRACT_MODE (UQQ, 1, 8); /* .8 */
12100
+/* UFRACT_MODE (UHQ, 1, 16); /* .16 */
12101 102 dgisselq
+UFRACT_MODE (USQ, 1, 32); /* .32 */
12102
+UFRACT_MODE (UDQ, 2, 64); /* .64 */
12103
+UFRACT_MODE (UTQ, 4, 128); /* .128 */
12104 111 dgisselq
+
12105
+/* ACCUM_MODE (HA, 2, 8, 7); /* s8.7 */
12106
+ACCUM_MODE (SA, 1, 16, 15); /* s16.15 */
12107
+ACCUM_MODE (DA, 2, 32, 31); /* s32.31 */
12108
+ACCUM_MODE (TA, 4, 64, 63); /* s64.63 */
12109
+
12110
+/* UACCUM_MODE (UHA, 2, 8, 8); /* 8.8 */
12111
+UACCUM_MODE (USA, 1, 16, 16); /* 16.16 */
12112
+UACCUM_MODE (UDA, 2, 32, 32); /* 32.32 */
12113
+UACCUM_MODE (UTA, 4, 64, 64); /* 64.64 */
12114 102 dgisselq
 
12115 111 dgisselq
 /* Allow the target to specify additional modes of various kinds.  */
12116
 #if HAVE_EXTRA_MODES
12117 102 dgisselq
@@ -246,9 +246,9 @@
12118
 COMPLEX_MODES (FLOAT);
12119
 
12120
 /* Decimal floating point modes.  */
12121
-DECIMAL_FLOAT_MODE (SD, 4, decimal_single_format);
12122
-DECIMAL_FLOAT_MODE (DD, 8, decimal_double_format);
12123
-DECIMAL_FLOAT_MODE (TD, 16, decimal_quad_format);
12124
+DECIMAL_FLOAT_MODE (SD, 1, decimal_single_format);
12125
+DECIMAL_FLOAT_MODE (DD, 2, decimal_double_format);
12126
+DECIMAL_FLOAT_MODE (TD, 4, decimal_quad_format);
12127
 
12128
 /* The symbol Pmode stands for one of the above machine modes (usually SImode).
12129
    The tm.h file specifies which one.  It is not a distinct mode.  */
12130
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/machmode.h gcc-5.3.0-zip/gcc/machmode.h
12131
--- gcc-5.3.0-original/gcc/machmode.h   2015-01-05 07:33:28.000000000 -0500
12132
+++ gcc-5.3.0-zip/gcc/machmode.h        2016-02-06 17:21:49.592924065 -0500
12133
@@ -180,13 +180,7 @@
12134
 /* Get the size in bytes and bits of an object of mode MODE.  */
12135
 
12136
 extern CONST_MODE_SIZE unsigned char mode_size[NUM_MACHINE_MODES];
12137
-#if GCC_VERSION >= 4001
12138
-#define GET_MODE_SIZE(MODE) \
12139
-  ((unsigned short) (__builtin_constant_p (MODE) \
12140
-                    ? mode_size_inline (MODE) : mode_size[MODE]))
12141
-#else
12142
 #define GET_MODE_SIZE(MODE)    ((unsigned short) mode_size[MODE])
12143
-#endif
12144
 #define GET_MODE_BITSIZE(MODE) \
12145
   ((unsigned short) (GET_MODE_SIZE (MODE) * BITS_PER_UNIT))
12146
 
12147
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/objc/objc-encoding.c gcc-5.3.0-zip/gcc/objc/objc-encoding.c
12148
--- gcc-5.3.0-original/gcc/objc/objc-encoding.c 2015-01-09 15:18:42.000000000 -0500
12149
+++ gcc-5.3.0-zip/gcc/objc/objc-encoding.c      2016-03-04 22:53:40.431902505 -0500
12150
@@ -765,10 +765,14 @@
12151
        {
12152
          switch (TYPE_MODE (type))
12153
            {
12154
+#ifdef HAVE_QImode
12155
            case QImode:
12156
              charType = 'C'; break;
12157
+#endif
12158
+#ifdef HAVE_HImode
12159
            case HImode:
12160
              charType = 'S'; break;
12161
+#endif
12162
            case SImode:
12163
              {
12164
                if (type == long_unsigned_type_node)
12165
@@ -788,10 +792,14 @@
12166
        {
12167
          switch (TYPE_MODE (type))
12168
            {
12169
+#ifdef HAVE_QImode
12170
            case QImode:
12171
              charType = 'c'; break;
12172
+#endif
12173
+#ifdef HAVE_HImode
12174
            case HImode:
12175
              charType = 's'; break;
12176
+#endif
12177
            case SImode:
12178
              {
12179
                if (type == long_integer_type_node)
12180
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/postreload.c gcc-5.3.0-zip/gcc/postreload.c
12181
--- gcc-5.3.0-original/gcc/postreload.c 2015-07-17 09:50:38.000000000 -0400
12182 111 dgisselq
+++ gcc-5.3.0-zip/gcc/postreload.c      2016-03-24 21:30:23.402590035 -0400
12183
@@ -71,6 +71,14 @@
12184 102 dgisselq
 #include "df.h"
12185
 #include "dbgcnt.h"
12186
 
12187 111 dgisselq
+// #define     DO_ZIP_DEBUGS
12188 102 dgisselq
+#ifdef DO_ZIP_DEBUGS
12189
+extern void zip_debug_rtx(const_rtx);
12190
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
12191
+#else
12192
+#define        ZIP_DEBUG_LINE(STR,RTX)
12193
+#endif
12194
+
12195
 static int reload_cse_noop_set_p (rtx);
12196
 static bool reload_cse_simplify (rtx_insn *, rtx);
12197
 static void reload_cse_regs_1 (void);
12198 111 dgisselq
@@ -120,6 +128,8 @@
12199 102 dgisselq
   basic_block insn_bb = BLOCK_FOR_INSN (insn);
12200
   unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
12201
 
12202
+       ZIP_DEBUG_LINE("RELOAD-CSE-SIMPLIFY:",insn);
12203
+
12204
   if (GET_CODE (body) == SET)
12205
     {
12206
       int count = 0;
12207 111 dgisselq
@@ -147,6 +157,7 @@
12208 102 dgisselq
        apply_change_group ();
12209
       else
12210
        reload_cse_simplify_operands (insn, testreg);
12211
+       ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
12212
     }
12213
   else if (GET_CODE (body) == PARALLEL)
12214
     {
12215 111 dgisselq
@@ -205,6 +216,7 @@
12216 102 dgisselq
        apply_change_group ();
12217
       else
12218
        reload_cse_simplify_operands (insn, testreg);
12219
+       ZIP_DEBUG_LINE("End of reload_cse_simplify_operands", insn);
12220
     }
12221
 
12222
 done:
12223 111 dgisselq
@@ -246,6 +258,7 @@
12224 102 dgisselq
          cfg_changed |= reload_cse_simplify (insn, testreg);
12225
 
12226
        cselib_process_insn (insn);
12227
+       ZIP_DEBUG_LINE("End-CSE-REGS-1:",insn);
12228
       }
12229
 
12230
   /* Clean up.  */
12231 111 dgisselq
@@ -276,6 +289,8 @@
12232 102 dgisselq
 #endif
12233
   bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
12234
 
12235
+
12236
+       ZIP_DEBUG_LINE("RELOAD:Attempting to simplify set",set);
12237
   dreg = true_regnum (SET_DEST (set));
12238
   if (dreg < 0)
12239
     return 0;
12240 111 dgisselq
@@ -427,6 +442,7 @@
12241 102 dgisselq
   /* Array of alternatives, sorted in order of decreasing desirability.  */
12242
   int *alternative_order;
12243
 
12244
+       ZIP_DEBUG_LINE("Simplify-Operands", insn);
12245
   extract_constrain_insn (insn);
12246
 
12247
   if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
12248 111 dgisselq
@@ -519,6 +535,7 @@
12249 102 dgisselq
          SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
12250
     }
12251
 
12252
+       ZIP_DEBUG_LINE("Simplify-Operands - A", insn);
12253
   alternative_mask preferred = get_preferred_alternatives (insn);
12254
   for (i = 0; i < recog_data.n_operands; i++)
12255
     {
12256 111 dgisselq
@@ -617,6 +634,7 @@
12257 102 dgisselq
            }
12258
        }
12259
     }
12260
+       ZIP_DEBUG_LINE("Simplify-Operands - B", insn);
12261
 
12262
   /* Record all alternatives which are better or equal to the currently
12263
      matching one in the alternative_order array.  */
12264 111 dgisselq
@@ -666,6 +684,7 @@
12265 102 dgisselq
       validate_change (insn, recog_data.operand_loc[i],
12266
                       gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
12267
     }
12268
+       ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
12269
 
12270
   for (i = recog_data.n_dups - 1; i >= 0; i--)
12271
     {
12272 111 dgisselq
@@ -679,6 +698,7 @@
12273 102 dgisselq
                       gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
12274
     }
12275
 
12276
+       ZIP_DEBUG_LINE("Simplify-Operands - C", insn);
12277
   return apply_change_group ();
12278
 }
12279
 
12280 117 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/recog.c gcc-5.3.0-zip/gcc/recog.c
12281
--- gcc-5.3.0-original/gcc/recog.c      2015-03-20 02:07:30.000000000 -0400
12282 127 dgisselq
+++ gcc-5.3.0-zip/gcc/recog.c   2016-04-14 23:19:07.630839483 -0400
12283 117 dgisselq
@@ -68,6 +68,15 @@
12284
 #include "df.h"
12285
 #include "insn-codes.h"
12286
 
12287
+// #define     DO_ZIP_DEBUGS
12288
+#ifdef DO_ZIP_DEBUGS
12289
+extern void    zip_debug_rtx(const_rtx);
12290
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
12291
+#else
12292
+#define        ZIP_DEBUG_LINE(STR,RTX)
12293
+#endif
12294
+
12295
+
12296
 #ifndef STACK_PUSH_CODE
12297
 #ifdef STACK_GROWS_DOWNWARD
12298
 #define STACK_PUSH_CODE PRE_DEC
12299 122 dgisselq
@@ -2283,6 +2292,7 @@
12300
   recog_data.n_dups = 0;
12301
   recog_data.is_asm = false;
12302
 
12303
+ZIP_DEBUG_LINE("Extract-insn", insn);
12304
   switch (GET_CODE (body))
12305
     {
12306
     case USE:
12307
@@ -3671,7 +3681,6 @@
12308 117 dgisselq
            break;
12309
 
12310
          /* The buffer filled to the current maximum, so try to match.  */
12311
-
12312
          pos = peep2_buf_position (peep2_current + peep2_current_count);
12313
          peep2_insn_data[pos].insn = PEEP2_EOB;
12314
          COPY_REG_SET (peep2_insn_data[pos].live_before, live);
12315 122 dgisselq
@@ -3704,6 +3713,7 @@
12316 117 dgisselq
     rebuild_jump_labels (get_insns ());
12317
   if (peep2_do_cleanup_cfg)
12318
     cleanup_cfg (CLEANUP_CFG_CHANGED);
12319
+
12320
 }
12321
 #endif /* HAVE_peephole2 */
12322
 
12323
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload1.c gcc-5.3.0-zip/gcc/reload1.c
12324
--- gcc-5.3.0-original/gcc/reload1.c    2015-01-15 08:28:42.000000000 -0500
12325 192 dgisselq
+++ gcc-5.3.0-zip/gcc/reload1.c 2016-11-02 12:07:12.261675054 -0400
12326 117 dgisselq
@@ -72,6 +72,14 @@
12327
 #include "dumpfile.h"
12328
 #include "rtl-iter.h"
12329
 
12330
+// #define     DO_ZIP_DEBUGS
12331
+#ifdef DO_ZIP_DEBUGS
12332
+extern void    zip_debug_rtx(const_rtx);
12333
+#define        ZIP_DEBUG_LINE(STR,RTX) do { fprintf(stderr, "%s:%d/%s\n", __FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
12334
+#else
12335
+#define        ZIP_DEBUG_LINE(STR,RTX)
12336
+#endif
12337
+
12338
 /* This file contains the reload pass of the compiler, which is
12339
    run after register allocation has been done.  It checks that
12340
    each insn is valid (operands required to be in registers really
12341 127 dgisselq
@@ -794,6 +802,20 @@
12342 117 dgisselq
   basic_block bb;
12343
   bool inserted;
12344
 
12345
+#ifdef DO_ZIP_DEBUGS
12346
+  {
12347 127 dgisselq
+       fprintf(stderr, "BEFORE-RELOAD\n");
12348 117 dgisselq
+       int     total_count = 0, current_count = 0;
12349
+       for (insn = first; insn; insn = NEXT_INSN (insn))
12350
+               total_count++;
12351
+       for (insn = first; insn; insn = NEXT_INSN (insn)) {
12352
+               fprintf(stderr, "B %3d/%3d", current_count++, total_count);
12353
+               zip_debug_rtx(insn);
12354
+       }
12355 127 dgisselq
+       fprintf(stderr, "BEFORE-RELOAD -- END OF INSTRUCTION LIST\n");
12356 117 dgisselq
+  }
12357
+#endif
12358
+
12359
   /* Make sure even insns with volatile mem refs are recognizable.  */
12360
   init_recog ();
12361
 
12362 127 dgisselq
@@ -1366,6 +1388,20 @@
12363 117 dgisselq
 
12364
   reload_completed = !failure;
12365
 
12366
+#ifdef DO_ZIP_DEBUGS
12367
+  {
12368 127 dgisselq
+       fprintf(stderr, "AFTER-RELOAD\n");
12369 117 dgisselq
+       int     total_count = 0, current_count = 0;
12370
+       for (insn = first; insn; insn = NEXT_INSN (insn))
12371
+               total_count++;
12372
+       for (insn = first; insn; insn = NEXT_INSN (insn)) {
12373
+               fprintf(stderr, "A %3d/%3d", current_count++, total_count);
12374
+               zip_debug_rtx(insn);
12375
+       }
12376 127 dgisselq
+       fprintf(stderr, "AFTER-RELOAD -- END OF INSTRUCTION LIST\n");
12377 117 dgisselq
+  }
12378
+#endif
12379
+
12380
   return need_dce;
12381
 }
12382
 
12383 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/reload.c gcc-5.3.0-zip/gcc/reload.c
12384
--- gcc-5.3.0-original/gcc/reload.c     2015-01-15 08:28:42.000000000 -0500
12385 192 dgisselq
+++ gcc-5.3.0-zip/gcc/reload.c  2016-11-02 12:07:03.653725635 -0400
12386 122 dgisselq
@@ -136,6 +136,15 @@
12387
 #include "target.h"
12388
 #include "ira.h"
12389
 
12390
+// #define     DO_ZIP_DEBUGS
12391
+#ifdef DO_ZIP_DEBUGS
12392
+extern void zip_debug_rtx(const_rtx);
12393
+#define ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr, "%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); }while(0)
12394
+#else
12395
+#define        ZIP_DEBUG_LINE(STR,RTX)
12396
+#endif
12397
+
12398
+
12399
 /* True if X is a constant that can be forced into the constant pool.
12400
    MODE is the mode of the operand, or VOIDmode if not known.  */
12401
 #define CONST_POOL_OK_P(MODE, X)               \
12402
@@ -2700,6 +2709,8 @@
12403
   hard_regs_live_known = live_known;
12404
   static_reload_reg_p = reload_reg_p;
12405
 
12406
+ZIP_DEBUG_LINE("Find reloads\n", insn);
12407
+
12408
   /* JUMP_INSNs and CALL_INSNs are not allowed to have any output reloads;
12409
      neither are insns that SET cc0.  Insns that use CC0 are not allowed
12410
      to have any input reloads.  */
12411
@@ -2707,8 +2718,17 @@
12412 102 dgisselq
     no_output_reloads = 1;
12413
 
12414
 #ifdef HAVE_cc0
12415
+  // If the instruction depends upon cc0, such as a branch, if_then_else, or
12416
+  // cond_exec instruction, we cannot change the input so that the instruction
12417
+  // relies on another register--cc0 is specific.  This requries that the
12418
+  // references be only cc0 and (const_int 0), rather than allowing other
12419
+  // registers here as well.
12420
   if (reg_referenced_p (cc0_rtx, PATTERN (insn)))
12421
     no_input_reloads = 1;
12422
+  // If the result of an instruction is the cc0 register, that cannot
12423
+  // be changed, therefore no output reloading is allowed.  This only
12424
+  // works if instructions *only* set the cc0 register, and not multiple
12425
+  // registers.
12426
   if (reg_set_p (cc0_rtx, PATTERN (insn)))
12427
     no_output_reloads = 1;
12428
 #endif
12429 146 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/target-def.h gcc-5.3.0-zip/gcc/target-def.h
12430
--- gcc-5.3.0-original/gcc/target-def.h 2015-01-05 07:33:28.000000000 -0500
12431
+++ gcc-5.3.0-zip/gcc/target-def.h      2016-05-12 15:20:06.896745740 -0400
12432
@@ -29,24 +29,44 @@
12433
    rather than the .c file, then we need to wrap the default
12434
    definition in a #ifndef, since files include tm.h before this one.  */
12435
 
12436
+#ifndef TARGET_ASM_ALIGNED_HI_OP
12437
 #define TARGET_ASM_ALIGNED_HI_OP "\t.short\t"
12438
+#endif
12439
+#ifndef TARGET_ASM_ALIGNED_SI_OP
12440
 #define TARGET_ASM_ALIGNED_SI_OP "\t.long\t"
12441
+#endif
12442
 #define TARGET_ASM_ALIGNED_DI_OP NULL
12443
 #define TARGET_ASM_ALIGNED_TI_OP NULL
12444
 
12445
 /* GAS and SYSV4 assemblers accept these.  */
12446
 #if defined (OBJECT_FORMAT_ELF)
12447
-#define TARGET_ASM_UNALIGNED_HI_OP "\t.2byte\t"
12448
-#define TARGET_ASM_UNALIGNED_SI_OP "\t.4byte\t"
12449
-#define TARGET_ASM_UNALIGNED_DI_OP "\t.8byte\t"
12450
-#define TARGET_ASM_UNALIGNED_TI_OP NULL
12451
+# ifndef TARGET_ASM_UNALIGNED_HI_OP
12452
+#  define TARGET_ASM_UNALIGNED_HI_OP "\t.2byte\t"
12453
+# endif
12454
+# ifndef TARGET_ASM_UNALIGNED_SI_OP
12455
+#  define TARGET_ASM_UNALIGNED_SI_OP "\t.4b0te\t"
12456
+# endif
12457
+# ifndef TARGET_ASM_UNALIGNED_DI_OP
12458
+#  define TARGET_ASM_UNALIGNED_DI_OP "\t.8byte\t"
12459
+# endif
12460
+# define TARGET_ASM_UNALIGNED_TI_OP NULL
12461
 #else
12462
-#define TARGET_ASM_UNALIGNED_HI_OP NULL
12463
-#define TARGET_ASM_UNALIGNED_SI_OP NULL
12464
-#define TARGET_ASM_UNALIGNED_DI_OP NULL
12465
-#define TARGET_ASM_UNALIGNED_TI_OP NULL
12466
+# ifndef TARGET_ASM_UNALIGNED_HI_OP
12467
+#  define TARGET_ASM_UNALIGNED_HI_OP NULL
12468
+# endif
12469
+# ifndef TARGET_ASM_UNALIGNED_SI_OP
12470
+#  define TARGET_ASM_UNALIGNED_SI_OP NULL
12471
+# endif
12472
+# ifndef TARGET_ASM_UNALIGNED_DI_OP
12473
+#  define TARGET_ASM_UNALIGNED_DI_OP NULL
12474
+# endif
12475
+# define TARGET_ASM_UNALIGNED_TI_OP NULL
12476
 #endif /* OBJECT_FORMAT_ELF */
12477
 
12478
+#ifndef        TARGET_ASM_UNALIGNED_TI_OP
12479
+#define TARGET_ASM_UNALIGNED_TI_OP NULL
12480
+#endif
12481
+
12482
 #if !defined(TARGET_ASM_CONSTRUCTOR) && !defined(USE_COLLECT2)
12483
 # ifdef CTORS_SECTION_ASM_OP
12484
 #  define TARGET_ASM_CONSTRUCTOR default_ctor_section_asm_out_constructor
12485 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/testsuite/lib/target-supports.exp gcc-5.3.0-zip/gcc/testsuite/lib/target-supports.exp
12486
--- gcc-5.3.0-original/gcc/testsuite/lib/target-supports.exp    2015-11-26 05:10:58.000000000 -0500
12487
+++ gcc-5.3.0-zip/gcc/testsuite/lib/target-supports.exp 2016-01-30 15:14:21.620586694 -0500
12488
@@ -503,6 +503,11 @@
12489
        return 0
12490
     }
12491
 
12492
+    # Zip CPU doesn't support profiling (yet)
12493
+    if { [istarget zip*] }
12494
+        return 0
12495
+    }
12496
+
12497
     # MinGW does not support -p.
12498
     if { [istarget *-*-mingw*] && $test_what == "-p" } {
12499
        return 0
12500
@@ -986,6 +991,12 @@
12501
        }]
12502
     }
12503
 
12504
+    # No real hardware FPU support for ZipCPU yet--even though the instruction
12505
+    # set supports it, the CPU just isn't ready yet.
12506
+    if { [istarget zip*-*-*] } {
12507
+        return 0
12508
+    }
12509
+
12510
     # This proc is actually checking the availabilty of FPU
12511
     # support for doubles, so on the RX we must fail if the
12512
     # 64-bit double multilib has been selected.
12513
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/tree-ssa-math-opts.c gcc-5.3.0-zip/gcc/tree-ssa-math-opts.c
12514
--- gcc-5.3.0-original/gcc/tree-ssa-math-opts.c 2015-08-11 03:58:07.000000000 -0400
12515
+++ gcc-5.3.0-zip/gcc/tree-ssa-math-opts.c      2016-02-12 11:21:11.309149239 -0500
12516
@@ -972,7 +972,7 @@
12517
     {
12518
       if (val & 1)
12519
        {
12520
-         digit = val & ((1 << POWI_WINDOW_SIZE) - 1);
12521
+         digit = val & ((1l << POWI_WINDOW_SIZE) - 1);
12522
          result += powi_lookup_cost (digit, cache)
12523
                    + POWI_WINDOW_SIZE + 1;
12524
          val >>= POWI_WINDOW_SIZE;
12525
@@ -1012,7 +1012,7 @@
12526
     }
12527
   else if (n & 1)
12528
     {
12529
-      digit = n & ((1 << POWI_WINDOW_SIZE) - 1);
12530
+      digit = n & ((1l << POWI_WINDOW_SIZE) - 1);
12531
       op0 = powi_as_mults_1 (gsi, loc, type, n - digit, cache);
12532
       op1 = powi_as_mults_1 (gsi, loc, type, digit, cache);
12533
     }
12534
@@ -1651,7 +1651,7 @@
12535
 };
12536
 
12537
 #define BITS_PER_MARKER 8
12538
-#define MARKER_MASK ((1 << BITS_PER_MARKER) - 1)
12539
+#define MARKER_MASK ((1l << BITS_PER_MARKER) - 1)
12540
 #define MARKER_BYTE_UNKNOWN MARKER_MASK
12541
 #define HEAD_MARKER(n, size) \
12542
   ((n) & ((uint64_t) MARKER_MASK << (((size) - 1) * BITS_PER_MARKER)))
12543
@@ -1687,7 +1687,7 @@
12544
   /* Zero out the extra bits of N in order to avoid them being shifted
12545
      into the significant bits.  */
12546
   if (size < 64 / BITS_PER_MARKER)
12547
-    n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
12548
+    n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
12549
 
12550
   switch (code)
12551
     {
12552
@@ -1714,7 +1714,7 @@
12553
     }
12554
   /* Zero unused bits for size.  */
12555
   if (size < 64 / BITS_PER_MARKER)
12556
-    n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
12557
+    n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
12558
   return true;
12559
 }
12560
 
12561
@@ -1761,7 +1761,7 @@
12562
   n->n = CMPNOP;
12563
 
12564
   if (size < 64 / BITS_PER_MARKER)
12565
-    n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
12566
+    n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
12567
 
12568
   return true;
12569
 }
12570
@@ -2020,7 +2020,7 @@
12571
          {
12572
            int i, size = TYPE_PRECISION (n->type) / BITS_PER_UNIT;
12573
            uint64_t val = int_cst_value (rhs2), mask = 0;
12574
-           uint64_t tmp = (1 << BITS_PER_UNIT) - 1;
12575
+           uint64_t tmp = (1l << BITS_PER_UNIT) - 1;
12576
 
12577
            /* Only constants masking full bytes are allowed.  */
12578
            for (i = 0; i < size; i++, tmp <<= BITS_PER_UNIT)
12579
@@ -2064,7 +2064,7 @@
12580
              {
12581
                /* If STMT casts to a smaller type mask out the bits not
12582
                   belonging to the target type.  */
12583
-               n->n &= ((uint64_t) 1 << (type_size * BITS_PER_MARKER)) - 1;
12584
+               n->n &= ((uint64_t) 1l << (type_size * BITS_PER_MARKER)) - 1;
12585
              }
12586
            n->type = type;
12587
            if (!n->base_addr)
12588
@@ -2177,7 +2177,7 @@
12589
     {
12590
       uint64_t mask;
12591
 
12592
-      mask = ((uint64_t) 1 << (n->range * BITS_PER_MARKER)) - 1;
12593
+      mask = ((uint64_t) 1l << (n->range * BITS_PER_MARKER)) - 1;
12594
       cmpxchg >>= (64 / BITS_PER_MARKER - n->range) * BITS_PER_MARKER;
12595
       cmpnop &= mask;
12596
     }
12597
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/gcc/var-tracking.c gcc-5.3.0-zip/gcc/var-tracking.c
12598
--- gcc-5.3.0-original/gcc/var-tracking.c       2015-03-26 09:19:00.000000000 -0400
12599 117 dgisselq
+++ gcc-5.3.0-zip/gcc/var-tracking.c    2016-03-31 18:55:03.584197958 -0400
12600 102 dgisselq
@@ -143,6 +143,13 @@
12601
 #include "rtl-iter.h"
12602
 #include "fibonacci_heap.h"
12603
 
12604 117 dgisselq
+#ifdef DO_ZIP_DEBUGS
12605 102 dgisselq
+#include <stdio.h>
12606
+extern void zip_debug_rtx(const_rtx);
12607
+#define ZIP_DEBUG_LINE(STR,RTX) do {fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX); } while(0)
12608
+#else
12609
+#define ZIP_DEBUG_LINE(STR,RTX)
12610
+#endif
12611
 typedef fibonacci_heap <long, basic_block_def> bb_heap_t;
12612
 typedef fibonacci_node <long, basic_block_def> bb_heap_node_t;
12613
 
12614
@@ -6356,6 +6363,7 @@
12615
                machine_mode indmode
12616
                  = TYPE_MODE (TREE_TYPE (argtype));
12617
                rtx mem = gen_rtx_MEM (indmode, x);
12618
+                       ZIP_DEBUG_LINE("Var-tracking mem-ref", mem);
12619
                cselib_val *val = cselib_lookup (mem, indmode, 0, VOIDmode);
12620
                if (val && cselib_preserved_value_p (val))
12621
                  {
12622
@@ -6462,12 +6470,14 @@
12623
       machine_mode mode
12624
        = TYPE_MODE (TREE_TYPE (OBJ_TYPE_REF_EXPR (obj_type_ref)));
12625
       rtx clobbered = gen_rtx_MEM (mode, this_arg);
12626
+                       ZIP_DEBUG_LINE("Var-tracking mem-ref/clobbered", clobbered);
12627
       HOST_WIDE_INT token
12628
        = tree_to_shwi (OBJ_TYPE_REF_TOKEN (obj_type_ref));
12629
       if (token)
12630
        clobbered = plus_constant (mode, clobbered,
12631
                                   token * GET_MODE_SIZE (mode));
12632
       clobbered = gen_rtx_MEM (mode, clobbered);
12633
+       ZIP_DEBUG_LINE("Var-tracking mem-ref/clobbered-2", clobbered);
12634
       x = gen_rtx_CONCAT (mode, gen_rtx_CLOBBER (VOIDmode, pc_rtx), clobbered);
12635
       call_arguments
12636
        = gen_rtx_EXPR_LIST (VOIDmode, x, call_arguments);
12637
@@ -9790,6 +9800,7 @@
12638
              machine_mode indmode
12639
                = TYPE_MODE (TREE_TYPE (TREE_TYPE (parm)));
12640
              rtx mem = gen_rtx_MEM (indmode, incoming);
12641
+       ZIP_DEBUG_LINE("Var-tracking mem-ref/incoming", incoming);
12642
              cselib_val *val = cselib_lookup_from_insn (mem, indmode, true,
12643
                                                         VOIDmode,
12644
                                                         get_insns ());
12645
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgcc/config.host gcc-5.3.0-zip/libgcc/config.host
12646
--- gcc-5.3.0-original/libgcc/config.host       2015-10-01 08:01:18.000000000 -0400
12647 200 dgisselq
+++ gcc-5.3.0-zip/libgcc/config.host    2016-11-10 07:09:05.510509734 -0500
12648 102 dgisselq
@@ -195,6 +195,9 @@
12649
 tic6x-*-*)
12650
        cpu_type=c6x
12651
        ;;
12652
+zip*)
12653
+       cpu_type=zip
12654
+       ;;
12655
 esac
12656
 
12657
 # Common parts for widely ported systems.
12658 200 dgisselq
@@ -1296,6 +1299,9 @@
12659
        tmake_file="$tmake_file nvptx/t-nvptx"
12660
        extra_parts="crt0.o"
12661 102 dgisselq
        ;;
12662
+zip*)
12663
+       tmake_file="${tmake_file} t-softfp-sfdf t-softfp"
12664
+       ;;
12665 200 dgisselq
 *)
12666
        echo "*** Configuration ${host} not supported" 1>&2
12667
        exit 1
12668
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgcc/libgcc2.h gcc-5.3.0-zip/libgcc/libgcc2.h
12669
--- gcc-5.3.0-original/libgcc/libgcc2.h 2015-01-05 07:33:28.000000000 -0500
12670
+++ gcc-5.3.0-zip/libgcc/libgcc2.h      2016-11-19 08:23:48.085519135 -0500
12671
@@ -113,10 +113,10 @@
12672
    because the sizes for those types can be configured to be anything.
12673
    Instead we use the following special type names.  */
12674 102 dgisselq
 
12675 200 dgisselq
-typedef                 int QItype     __attribute__ ((mode (QI)));
12676
-typedef unsigned int UQItype   __attribute__ ((mode (QI)));
12677
-typedef                 int HItype     __attribute__ ((mode (HI)));
12678
-typedef unsigned int UHItype   __attribute__ ((mode (HI)));
12679
+typedef                 int QItype     __attribute__ ((mode (SI)));
12680
+typedef unsigned int UQItype   __attribute__ ((mode (SI)));
12681
+typedef                 int HItype     __attribute__ ((mode (SI)));
12682
+typedef unsigned int UHItype   __attribute__ ((mode (SI)));
12683
 #if MIN_UNITS_PER_WORD > 1
12684
 /* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1.  */
12685
 typedef         int SItype     __attribute__ ((mode (SI)));
12686 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-5.3.0-original/libgomp/configure.tgt gcc-5.3.0-zip/libgomp/configure.tgt
12687
--- gcc-5.3.0-original/libgomp/configure.tgt    2015-03-13 06:57:07.000000000 -0400
12688
+++ gcc-5.3.0-zip/libgomp/configure.tgt 2016-01-30 15:16:51.323521641 -0500
12689
@@ -150,6 +150,9 @@
12690
        # Need to link with -lpthread so libgomp.so is self-contained.
12691
        XLDFLAGS="${XLDFLAGS} -lpthread"
12692
        ;;
12693
+  zip*)
12694
+        config_path="bsd posix"
12695
+        ;;
12696
 
12697
   *)
12698
        ;;

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