OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

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[/] [zipcpu/] [trunk/] [sw/] [gcc-zippatch.patch] - Blame information for rev 209

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Line No. Rev Author Line
1 202 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/config.sub gcc-6.2.0-zip/config.sub
2
--- gcc-6.2.0/config.sub        2015-12-31 16:13:28.000000000 -0500
3
+++ gcc-6.2.0-zip/config.sub    2017-01-11 11:07:21.116065311 -0500
4
@@ -355,6 +355,14 @@
5
        xscaleel)
6
                basic_machine=armel-unknown
7 102 dgisselq
                ;;
8 202 dgisselq
+       zip-*-linux*)
9
+               basic_machine=zip
10
+               os=-linux
11
+               ;;
12
+       zip*)
13
+               basic_machine=zip-unknown
14
+               os=-none
15
+               ;;
16 102 dgisselq
 
17 202 dgisselq
        # We use `pc' rather than `unknown'
18
        # because (1) that's what they normally are, and
19
diff -Naur '--exclude=*.swp' gcc-6.2.0/configure gcc-6.2.0-zip/configure
20
--- gcc-6.2.0/configure 2016-03-17 18:54:19.000000000 -0400
21
+++ gcc-6.2.0-zip/configure     2017-02-06 21:54:22.244807700 -0500
22
@@ -3548,6 +3548,44 @@
23
   ft32-*-*)
24
     noconfigdirs="$noconfigdirs ${libgcj}"
25
     ;;
26
+  zip*)
27
+    noconfigdirs="$noconfigdirs ${libgcj}"
28
+    noconfigdirs="$noconfigdirs target-boehm-gc"
29
+    noconfigdirs="$noconfigdirs target-libgfortran"
30
+    # noconfigdirs="$noconfigdirs target-libsanitizer"
31
+    # noconfigdirs="$noconfigdirs target-libada"
32
+    # noconfigdirs="$noconfigdirs target-libatomic"
33
+    # noconfigdirs="$noconfigdirs target-libcilkrts"
34
+    # noconfigdirs="$noconfigdirs target-libitm"
35
+    # noconfigdirs="$noconfigdirs target-libquadmath"
36
+    # noconfigdirs="$noconfigdirs target-libstdc++-v3"
37
+    # noconfigdirs="$noconfigdirs target-libssp"
38
+    # noconfigdirs="$noconfigdirs target-libgo"
39
+    # noconfigdirs="$noconfigdirs target-libgomp"
40
+    # noconfigdirs="$noconfigdirs target-libvtv"
41
+    # noconfigdirs="$noconfigdirs target-libobjc"
42
+       # target-libgcc
43
+       #       target-liboffloadmic
44
+       #       target-libmpx   # Only gets enabled by request
45
+       #       target-libbacktrace
46
+       #       ${libgcj}
47
+       #       target-boehm-gc
48
+       #       target-libada
49
+       #       target-libatomic
50
+       #       target-libcilkrts
51
+       #       target-libgfortran
52
+       #       target-libgo
53
+       #       target-libgomp
54
+       #       target-libitm
55
+       #       target-libobjc
56
+       #       target-libquadmath
57
+       #       target-libsanitizer
58
+       #       target-libstdc++-v3
59
+       #       target-libssp
60
+       #       target-libvtv
61
+       # target-libgloss
62
+       # target-newlib
63
+    ;;
64
   *-*-lynxos*)
65
     noconfigdirs="$noconfigdirs ${libgcj}"
66
     ;;
67
@@ -3575,6 +3613,9 @@
68
     *-*-aix*)
69
        noconfigdirs="$noconfigdirs target-libgo"
70
        ;;
71
+    zip*)
72
+       noconfigdirs="$noconfigdirs target-libgo"
73
+       ;;
74
     esac
75
 fi
76
 
77
@@ -3971,6 +4012,9 @@
78 102 dgisselq
   vax-*-*)
79
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
80
     ;;
81
+  zip*)
82
+    noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof"
83 202 dgisselq
+    ;;
84 102 dgisselq
 esac
85
 
86
 # If we aren't building newlib, then don't build libgloss, since libgloss
87 202 dgisselq
@@ -6785,16 +6829,16 @@
88
 # CFLAGS_FOR_TARGET and CXXFLAGS_FOR_TARGET.
89
 if test "x$CFLAGS_FOR_TARGET" = x; then
90
   if test "x${is_cross_compiler}" = xyes; then
91
-    CFLAGS_FOR_TARGET="-g -O2"
92
+    CFLAGS_FOR_TARGET="-O3"
93
   else
94
     CFLAGS_FOR_TARGET=$CFLAGS
95
     case " $CFLAGS " in
96
-      *" -O2 "*) ;;
97
-      *) CFLAGS_FOR_TARGET="-O2 $CFLAGS_FOR_TARGET" ;;
98
+      *" -O3 "*) ;;
99
+      *) CFLAGS_FOR_TARGET="-O3 $CFLAGS_FOR_TARGET" ;;
100
     esac
101
     case " $CFLAGS " in
102
       *" -g "* | *" -g3 "*) ;;
103
-      *) CFLAGS_FOR_TARGET="-g $CFLAGS_FOR_TARGET" ;;
104
+      *) CFLAGS_FOR_TARGET="$CFLAGS_FOR_TARGET" ;;
105
     esac
106
   fi
107
 fi
108
@@ -6802,16 +6846,16 @@
109
 
110
 if test "x$CXXFLAGS_FOR_TARGET" = x; then
111
   if test "x${is_cross_compiler}" = xyes; then
112
-    CXXFLAGS_FOR_TARGET="-g -O2"
113
+    CXXFLAGS_FOR_TARGET="-O3"
114
   else
115
     CXXFLAGS_FOR_TARGET=$CXXFLAGS
116
     case " $CXXFLAGS " in
117
-      *" -O2 "*) ;;
118
-      *) CXXFLAGS_FOR_TARGET="-O2 $CXXFLAGS_FOR_TARGET" ;;
119
+      *" -O3 "*) ;;
120
+      *) CXXFLAGS_FOR_TARGET="-O3 $CXXFLAGS_FOR_TARGET" ;;
121
     esac
122
     case " $CXXFLAGS " in
123
       *" -g "* | *" -g3 "*) ;;
124
-      *) CXXFLAGS_FOR_TARGET="-g $CXXFLAGS_FOR_TARGET" ;;
125
+      *) CXXFLAGS_FOR_TARGET="$CXXFLAGS_FOR_TARGET" ;;
126
     esac
127
   fi
128
 fi
129
diff -Naur '--exclude=*.swp' gcc-6.2.0/configure.ac gcc-6.2.0-zip/configure.ac
130
--- gcc-6.2.0/configure.ac      2016-03-17 18:54:19.000000000 -0400
131
+++ gcc-6.2.0-zip/configure.ac  2017-01-10 12:43:23.819301273 -0500
132
@@ -884,6 +884,9 @@
133
   ft32-*-*)
134
     noconfigdirs="$noconfigdirs ${libgcj}"
135
     ;;
136
+  zip*)
137
+    noconfigdirs="$noconfigdirs ${libgcj}"
138
+    ;;
139
   *-*-lynxos*)
140
     noconfigdirs="$noconfigdirs ${libgcj}"
141
     ;;
142
@@ -911,6 +914,9 @@
143
     *-*-aix*)
144
        noconfigdirs="$noconfigdirs target-libgo"
145
        ;;
146
+    zip*)
147
+       noconfigdirs="$noconfigdirs target-libgo"
148
+       ;;
149
     esac
150
 fi
151
 
152
@@ -1307,6 +1313,10 @@
153 102 dgisselq
   vax-*-*)
154
     noconfigdirs="$noconfigdirs target-newlib target-libgloss"
155
     ;;
156
+  zip*)
157 202 dgisselq
+    noconfigdirs="$noconfigdirs target-libffi target-boehm-gc gdb gprof ${libgcj}"
158
+    unsupported_languages="$unsupported_languages fortran"
159 102 dgisselq
+    ;;
160
 esac
161
 
162
 # If we aren't building newlib, then don't build libgloss, since libgloss
163 202 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cfgexpand.c gcc-6.2.0-zip/gcc/cfgexpand.c
164
--- gcc-6.2.0/gcc/cfgexpand.c   2016-04-27 08:23:50.000000000 -0400
165 209 dgisselq
+++ gcc-6.2.0-zip/gcc/cfgexpand.c       2018-06-05 21:18:19.438798488 -0400
166
@@ -74,6 +74,16 @@
167 117 dgisselq
 #include "tree-chkp.h"
168
 #include "rtl-chkp.h"
169
 
170 202 dgisselq
+
171 209 dgisselq
+// #define     DO_ZIP_DEBUGS
172 117 dgisselq
+#ifdef DO_ZIP_DEBUGS
173
+#include <stdio.h>
174 202 dgisselq
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
175 117 dgisselq
+extern void    zip_debug_rtx(const_rtx);
176
+#else
177
+#define        ZIP_DEBUG_LINE(STR,RTX)
178
+#endif
179
+
180
 /* Some systems use __main in a way incompatible with its use in gcc, in these
181
    cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to
182
    give the same symbol without quotes for an alternative entry point.  You
183 209 dgisselq
@@ -1172,7 +1182,7 @@
184 202 dgisselq
                base_align = crtl->max_used_stack_slot_alignment;
185
              else
186
                base_align = MAX (crtl->max_used_stack_slot_alignment,
187
-                                 GET_MODE_ALIGNMENT (SImode)
188
+                                 GET_MODE_ALIGNMENT (word_mode)
189
                                  << ASAN_SHADOW_SHIFT);
190
            }
191
          else
192 209 dgisselq
@@ -2225,7 +2235,7 @@
193 202 dgisselq
          data.asan_vec.safe_push (offset);
194
          /* Leave space for alignment if STRICT_ALIGNMENT.  */
195
          if (STRICT_ALIGNMENT)
196
-           alloc_stack_frame_space ((GET_MODE_ALIGNMENT (SImode)
197
+           alloc_stack_frame_space ((GET_MODE_ALIGNMENT (word_mode)
198
                                      << ASAN_SHADOW_SHIFT)
199
                                     / BITS_PER_UNIT, 1);
200 111 dgisselq
 
201 209 dgisselq
@@ -5745,7 +5755,7 @@
202 202 dgisselq
       && (last = get_last_insn ())
203
       && JUMP_P (last))
204
     {
205
-      rtx dummy = gen_reg_rtx (SImode);
206
+      rtx dummy = gen_reg_rtx (word_mode);
207
       emit_insn_after_noloc (gen_move_insn (dummy, dummy), last, NULL);
208
     }
209
 
210
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cgraphbuild.c gcc-6.2.0-zip/gcc/cgraphbuild.c
211
--- gcc-6.2.0/gcc/cgraphbuild.c 2016-01-04 09:30:50.000000000 -0500
212
+++ gcc-6.2.0-zip/gcc/cgraphbuild.c     2016-12-31 16:39:44.963107994 -0500
213
@@ -32,6 +32,15 @@
214
 #include "ipa-utils.h"
215
 #include "except.h"
216
 
217
+
218 111 dgisselq
+#ifdef DO_ZIP_DEBUGS
219 202 dgisselq
+#include <stdio.h>
220
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
221
+extern void    zip_debug_rtx(const_rtx);
222 111 dgisselq
+#else
223
+#define        ZIP_DEBUG_LINE(STR,RTX)
224
+#endif
225
+
226
 /* Context of record_reference.  */
227
 struct record_reference_ctx
228
 {
229 202 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/combine.c gcc-6.2.0-zip/gcc/combine.c
230
--- gcc-6.2.0/gcc/combine.c     2016-08-08 06:06:15.000000000 -0400
231
+++ gcc-6.2.0-zip/gcc/combine.c 2017-02-03 09:25:19.676720321 -0500
232
@@ -103,6 +103,15 @@
233
 #include "rtl-iter.h"
234
 #include "print-rtl.h"
235
 
236
+#define        DO_ZIP_DEBUGS
237
+#ifdef DO_ZIP_DEBUGS
238
+#include <stdio.h>
239
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
240
+extern void    zip_debug_rtx(const_rtx);
241
+#else
242
+#define        ZIP_DEBUG_LINE(STR,RTX)
243
+#endif
244
+
245
 #ifndef LOAD_EXTEND_OP
246
 #define LOAD_EXTEND_OP(M) UNKNOWN
247
 #endif
248
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/common/config/zip/zip-common.c gcc-6.2.0-zip/gcc/common/config/zip/zip-common.c
249
--- gcc-6.2.0/gcc/common/config/zip/zip-common.c        1969-12-31 19:00:00.000000000 -0500
250
+++ gcc-6.2.0-zip/gcc/common/config/zip/zip-common.c    2017-01-11 09:41:34.483106099 -0500
251 102 dgisselq
@@ -0,0 +1,52 @@
252
+////////////////////////////////////////////////////////////////////////////////
253
+//
254
+// Filename:   common/config/zip/zip-common.c
255
+//
256
+// Project:    Zip CPU backend for the GNU Compiler Collection
257
+//
258
+// Purpose:    To eliminate the frame register automatically.
259
+//
260
+// Creator:    Dan Gisselquist, Ph.D.
261
+//             Gisselquist Technology, LLC
262
+//
263
+////////////////////////////////////////////////////////////////////////////////
264
+//
265 202 dgisselq
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
266 102 dgisselq
+//
267
+// This program is free software (firmware): you can redistribute it and/or
268
+// modify it under the terms of  the GNU General Public License as published
269
+// by the Free Software Foundation, either version 3 of the License, or (at
270
+// your option) any later version.
271
+//
272
+// This program is distributed in the hope that it will be useful, but WITHOUT
273
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
274
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
275
+// for more details.
276
+//
277
+// You should have received a copy of the GNU General Public License along
278
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
279
+// target there if the PDF file isn't present.)  If not, see
280
+// <http://www.gnu.org/licenses/> for a copy.
281
+//
282
+// License:    GPL, v3, as defined and found on www.gnu.org,
283
+//             http://www.gnu.org/licenses/gpl.html
284
+//
285
+//
286
+////////////////////////////////////////////////////////////////////////////////
287
+#include "config.h"
288
+#include "system.h"
289
+#include "coretypes.h"
290
+#include "tm.h"
291
+#include "common/common-target.h"
292
+#include "common/common-target-def.h"
293
+
294
+static const struct default_options zip_option_optimization_table[] =
295
+  {
296
+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
297
+    { OPT_LEVELS_NONE, 0, NULL, 0 }
298
+  };
299
+
300
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
301
+#define        TARGET_OPTION_OPTIMIZATION_TABLE        zip_option_optimization_table
302
+
303
+struct gcc_targetm_common      targetm_common = TARGETM_COMMON_INITIALIZER;
304 209 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops gcc-6.2.0-zip/gcc/config/zip/genzipops
305
--- gcc-6.2.0/gcc/config/zip/genzipops  1969-12-31 19:00:00.000000000 -0500
306
+++ gcc-6.2.0-zip/gcc/config/zip/genzipops      2018-03-22 18:33:09.823726748 -0400
307
@@ -0,0 +1,201 @@
308
+ELF>@@€N@8       @@@@@@øø88@8@@@ô9ô9 >>`>`˜À (>(>`(>`ÐÐTT@T@DDPåtdÄ6Ä6@Ä6@œœQåtdRåtd>>`>`ðð/lib64/ld-linux-x86-64.so.2GNU GNUÁ•F3m›ö+•Z\Lè=à–öŽ<9ò‹4B;#tm^† fWPIÀ@`libc.so.6exitsprintffopenputs__stack_chk_failunlinkstrlenfclosestderrfwriterenamefprintfaccessstrcmp__libc_start_main__gmon_start__GLIBC_2.4GLIBC_2.2.5ii
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309
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310
+é@ÿÿÿÿ%ª8 hé0ÿÿÿÿ%¢8 hé ÿÿÿÿ%š8 h
éÿÿÿÿ%8 f1íI‰Ñ^H‰âHƒäðPTIÇÀð@HÇÁ€@HÇÇ>@è7ÿÿÿôfD¸¯@`UH-¨@`HƒøH‰åv¸H…Àt]¿¨@`ÿàf„]Ã@f.„¾¨@`UHî¨@`HÁþH‰åH‰ðHÁè?HÆHÑþt¸H…Àt]¿¨@`ÿà]ÃfD€=8 uUH‰åènÿÿÿ]Æþ7 óÃ@¿ >`Hƒ?u듸H…ÀtñUH‰åÿÐ]ézÿÿÿUH‰åHƒìH‰}øH‹EøH‰Áº¸¾¿@èÃþÿÿÉÃUH‰åHƒìH‰}øH‰uðH‹UðH‹Eø¾Á @H‰Ç¸è6þÿÿÉÃUH‰åHƒì0H‰}øH‰uðH‰UèH‰MàL‰EØL‰MÐH‹}èH‹uÐH‹MÐH‹UðH‹EøHƒìÿuÿuØÿuàI‰ùI‰ð¾Ð @H‰Ç¸èÚýÿÿHƒÄ ÉÃUH‰åHìÐH‰½hÿÿÿH‰µ`ÿÿÿH‰•XÿÿÿH‰PÿÿÿL‰…HÿÿÿL‰@ÿÿÿH‹EH‰…8ÿÿÿdH‹%(H‰Eø1ÀH‹•8ÿÿÿH…pÿÿÿ¾³!@H‰Ç¸è¤ýÿÿH‹•8ÿÿÿH‹…hÿÿÿ¾È!@H‰Ç¸èDýÿÿH‹½8ÿÿÿH‹µPÿÿÿH‹XÿÿÿH‹•`ÿÿÿH‹…hÿÿÿHƒìÿµ`ÿÿÿI‰ùI‰ð¾ð!@H‰Ç¸èÿüÿÿHƒÄH‹½8ÿÿÿH‹µPÿÿÿH‹@ÿÿÿH‹•`ÿÿÿH‹…hÿÿÿHƒìÿµ`ÿÿÿI‰ùI‰ð¾€"@H‰Ç¸è¶üÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìh?#@A¹<#@I‰øH‰ÇèBþÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìhD#@A¹A#@I‰øH‰ÇèþÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìhJ#@A¹G#@I‰øH‰ÇèÀýÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìhP#@A¹M#@I‰øH‰ÇèýÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìhW#@A¹S#@I‰øH‰Çè>ýÿÿHƒÄH‹½8ÿÿÿH‹PÿÿÿH‹•@ÿÿÿH‹µ`ÿÿÿH‹…hÿÿÿHƒìh]#@A¹Y#@I‰øH‰ÇèýüÿÿHƒÄH‹EødH3%(tèçúÿÿÉÃUH‰åHì€H‰½¨ùÿÿH‰µ ùÿÿH‰•˜ùÿÿH‰ùÿÿL‰…ˆùÿÿdH‹%(H‰Eø1ÀH‹•˜ùÿÿH…ðùÿÿ¾`#@H‰Ç¸èøúÿÿH‹•˜ùÿÿH…ðûÿÿ¾$@H‰Ç¸èØúÿÿH‹•˜ùÿÿH…ðýÿÿ¾8$@H‰Ç¸è¸úÿÿL…ðýÿÿH½ðûÿÿH‹ùÿÿH•ðùÿÿH‹µ ùÿÿH‹…¨ùÿÿHƒìÿµˆùÿÿM‰ÁI‰øH‰ÇècüÿÿHƒÄH‹•˜ùÿÿH…ðùÿÿ¾¸$@H‰Ç¸èRúÿÿH‹•˜ùÿÿH…ðûÿÿ¾ˆ%@H‰Ç¸è2úÿÿH‹•˜ùÿÿH…ðýÿÿ¾Ø%@H‰Ç¸èúÿÿH‹• ùÿÿH…°ùÿÿ¾Š&@H‰Ç¸èòùÿÿL…ðýÿÿH½ðûÿÿH‹ùÿÿH•ðùÿÿHµ°ùÿÿH‹…¨ùÿÿHƒìÿµˆùÿÿM‰ÁI‰øH‰ÇèûÿÿHƒÄH‹EødH3%(tè'ùÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøHƒìÿuàÿuàÿuàI‰ùI‰ð¾˜&@H‰Ç¸èùÿÿHƒÄ ÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾(@H‰Ç¸è¹øÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾`)@H‰Ç¸èrøÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾ˆ*@H‰Ç¸è+øÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾˜+@H‰Ç¸èä÷ÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾à,@H‰Ç¸è÷ÿÿÉÃUH‰åHƒì H‰}øH‰uðH‰UèH‰MàH‹}àH‹uèH‹MèH‹UðH‹EøI‰ùI‰ð¾(.@H‰Ç¸èV÷ÿÿÉÃUH‰å¿p/@èåöÿÿ]ÃUH‰åAUATSHƒì(‰}ÌH‰uÀH‹?0 ¾²/@H‰Çè:÷ÿÿH‰EØH‹/0 H‰EЃ}Ì~!H‹EÀHƒÀH‹¶<-uè›ÿÿÿ¿è4÷ÿÿƒ}ÌŽ´H‹EÀHƒÀH‹H‰Çè‡öÿÿH‰ÃH‹Ý/ H‰ÇèuöÿÿH9Ãr~H‹É/ H‹EÀHƒÀL‹ H‹EÀHƒÀH‹H‰ÇèKöÿÿI‰ÅH‹¡/ H‰Çè9öÿÿI)ÅL‰èLàH‰ÞH‰ÇèUöÿÿ…Àu/H‹EÀHƒÀH‹¾H‰ÇèYöÿÿ…ÀuH‹EÀHƒÀH‹H‰ÇèÂõÿÿH‹EÀH‹@H‰EÐH‹EØH‰Çè÷ÿÿH‹EØA¸´/@¹¸/@º¹/@¾Á/@H‰ÇèäúÿÿH‹EØA¸È/@¹¸/@ºÌ/@¾Õ/@H‰ÇèÃúÿÿH‹EØA¸Ü/@¹¸/@ºà/@¾è/@H‰Çè¢úÿÿH‹EØA¸ï/@¹ô/@º0@¾0@H‰ÇèúÿÿH‹EØA¸0@¹ô/@º0@¾0@H‰Çè`úÿÿH‹EØA¸$0@¹¸/@º(0@¾/0@H‰Çè?úÿÿH‹EØA¸60@¹¸/@º90@¾@0@H‰ÇèúÿÿH‹EØA¸G0@¹¸/@ºK0@¾R0@H‰ÇèýùÿÿH‹EØA¸Y0@¹¸/@º]0@¾i0@H‰ÇèÜùÿÿH‹EØA¸q0@¹¸/@ºu0@¾0@H‰Çè»ùÿÿH‹EØA¸‡0@¹¸/@º‹0@¾—0@H‰ÇèšùÿÿH‹EØHƒìh3@A¹ 0@A¸x1@¹
311
+2@º2@¾3@H‰Çè¬öÿÿHƒÄH‹EØHƒìh5@A¹ 3@A¸ø3@¹
312
+2@º4@¾5@H‰ÇèxöÿÿHƒÄH‹Eؾ–5@H‰ÇèÖõÿÿH‹Eع?#@º<#@¾´5@H‰ÇèÆúÿÿH‹EعD#@ºA#@¾´5@H‰Çè«úÿÿH‹EعJ#@ºG#@¾´5@H‰ÇèúÿÿH‹EعP#@ºM#@¾´5@H‰ÇèuúÿÿH‹EعW#@ºS#@¾´5@H‰ÇèZúÿÿH‹Eع]#@ºY#@¾´5@H‰Çè?úÿÿH‹Eؾ¹5@H‰Çè#õÿÿH‹Eع?#@º<#@¾Ö5@H‰ÇèkúÿÿH‹EعD#@ºA#@¾Ö5@H‰ÇèPúÿÿH‹EعJ#@ºG#@¾Ö5@H‰Çè5úÿÿH‹EعP#@ºM#@¾Ö5@H‰ÇèúÿÿH‹EعW#@ºS#@¾Ö5@H‰ÇèÿùÿÿH‹Eع]#@ºY#@¾Ö5@H‰ÇèäùÿÿH‹Eؾà5@H‰ÇèpôÿÿH‹Eع?#@º<#@¾6@H‰ÇèFúÿÿH‹EعD#@ºA#@¾6@H‰Çè+úÿÿH‹EعJ#@ºG#@¾6@H‰ÇèúÿÿH‹EعP#@ºM#@¾6@H‰ÇèõùÿÿH‹EعW#@ºS#@¾6@H‰ÇèÚùÿÿH‹Eع]#@ºY#@¾6@H‰Çè¿ùÿÿH‹Eؾ6@H‰Çè½óÿÿH‹Eع?#@º<#@¾"6@H‰ÇèLùÿÿH‹EعD#@ºA#@¾"6@H‰Çè1ùÿÿH‹EعJ#@ºG#@¾"6@H‰ÇèùÿÿH‹EعP#@ºM#@¾"6@H‰ÇèûøÿÿH‹EعW#@ºS#@¾"6@H‰ÇèàøÿÿH‹Eع]#@ºY#@¾"6@H‰ÇèÅøÿÿH‹Eؾ'6@H‰Çè
313
+óÿÿH‹Eع?#@º<#@¾D6@H‰Çè'ùÿÿH‹EعD#@ºA#@¾D6@H‰ÇèùÿÿH‹EعJ#@ºG#@¾D6@H‰ÇèñøÿÿH‹EعP#@ºM#@¾D6@H‰ÇèÖøÿÿH‹EعW#@ºS#@¾D6@H‰Çè»øÿÿH‹Eع]#@ºY#@¾D6@H‰Çè øÿÿH‹EؾI6@H‰ÇèWòÿÿH‹Eع?#@º<#@¾f6@H‰Çè»øÿÿH‹EعD#@ºA#@¾f6@H‰Çè øÿÿH‹EعJ#@ºG#@¾f6@H‰Çè…øÿÿH‹EعP#@ºM#@¾f6@H‰ÇèjøÿÿH‹EعW#@ºS#@¾f6@H‰ÇèOøÿÿH‹Eع]#@ºY#@¾f6@H‰Çè4øÿÿH‹Eؾk6@H‰Çè¤ñÿÿH‹Eع?#@º<#@¾ˆ6@H‰ÇèOøÿÿH‹EعD#@ºA#@¾ˆ6@H‰Çè4øÿÿH‹EعJ#@ºG#@¾ˆ6@H‰ÇèøÿÿH‹EعP#@ºM#@¾ˆ6@H‰Çèþ÷ÿÿH‹EعW#@ºS#@¾ˆ6@H‰Çèã÷ÿÿH‹Eع]#@ºY#@¾ˆ6@H‰ÇèÈ÷ÿÿH‹EØH‰ÇèïÿÿH‹g( H‹UÐH‰ÖH‰Çèpïÿÿ…Àt.H‹
M( H‹n( H‹Uо6@H‰Ç¸èïÿÿ¿è^ïÿÿ¿èTïÿÿ@AWAVA‰ÿAUATL%~% UH-~% SI‰öI‰ÕL)åHƒìHÁýè'îÿÿH…ít 1Û„L‰êL‰öD‰ÿAÿÜHƒÃH9ëuêHƒÄ[]A\A]A^A_Ãf.„óÃHƒìHƒÄÃ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
314
+;;
315
+;; Filename:   zip-ops.md
316
+;;
317
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
318
+;;
319
+;; Purpose:    This is a computer generated machine description of the
320
+;;             ZipCPU's operations.  It is computer generated simply for
321
+;;     two reasons.  First, I can't seem to find a way to generate this
322
+;;     information within GCC's current constructs.  Specifically, the
323
+;;     CPU's instructions normally set the condition codes, unless they
324
+;;     are conditional instructions when they don't.  Second, the ZipCPU is
325
+;;     actually quite regular.  Almost all of the instructions have the same
326
+;;     form.  This form turns into many, many RTL instructions.  Because the
327
+;;     CPU doesn't match any of the others within GCC, that means either
328
+;;     I have a *lot* of cut, copy, paste, and edit to do to create the file
329
+;;     and upon any and every edit, or I need to build a program to generate
330
+;;     the remaining .md constructs.  Hence, I chose the latter to minimize
331
+;;     the amount of work I needed to do.
332
+;;
333
+;;
334
+;; Creator:    Dan Gisselquist, Ph.D.
335
+;;             Gisselquist Technology, LLC
336
+;;
337
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
338
+;;
339
+;; Copyright (C) 2017, Gisselquist Technology, LLC
340
+;;
341
+;; This program is free software (firmware): you can redistribute it and/or
342
+;; modify it under the terms of  the GNU General Public License as published
343
+;; by the Free Software Foundation, either version 3 of the License, or (at
344
+;; your option) any later version.
345
+;;
346
+;; This program is distributed in the hope that it will be useful, but WITHOUT
347
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
348
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
349
+;; for more details.
350
+;;
351
+;; License:    GPL, v3, as defined and found on www.gnu.org,
352
+;;             http://www.gnu.org/licenses/gpl.html
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+;;
354
+;;
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+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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+;;
357
+;;
358
+;
359
+;
360
+; %s
361
+;
362
+;
363
+(define_insn "%s_%s"
364
+       [(cond_exec (%s (reg:CC CC_REG) (const_int 0))
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+                       %s)]
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+       "%s"    ; Condition
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+       "%s.%s\t%%1,%%0 ; genzip, conditional operator" ; Template
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+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
369
+;
370
+;
371
+%s (genzipop_long);
372
+;
373
+;
374
+; %s (genzipop_long)
375
+;
376
+;
377
+;
378
+(define_insn "%s"
379
+       [%s
380
+       (clobber (reg:CC CC_REG))]
381
+       "%s"
382
+       "%s\t%%2,%%0    ; %s"
383
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
384
+;
385
+;
386
+(define_insn "%s_raw"
387
+       [%s
388
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
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+       "%s"
390
+       "%s\t%%1,%%0    ; %s_raw"
391
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
392
+;
393
+;
394
+eqZneNZltLTgeGEltuCgeuNC(set (match_operand:SI 0 "register_operand" "=r")
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+               (%s (match_operand:SI 1 "register_operand" "0")
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+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))(set (match_dup 0) (%s (match_dup 0) (match_dup 2)))(set (match_operand:SI 0 "register_operand" "=r")
397
+               (%s (match_dup 0)
398
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))(set (match_operand:SI 0 "register_operand" "=r")
399
+               (%s (match_operand:SI 1 "register_operand" "0")
400
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
401
+                               (match_operand:SI 3 "const_int_operand" "N"))))(set (match_dup 0) (%s (match_dup 0)
402
+                       (plus:SI (match_dup 2) (match_dup 3))))(set (match_operand:SI 0 "register_operand" "=r")
403
+               (%s (match_dup 0)
404
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
405
+                               (match_operand:SI 2 "const_int_operand" "N"))))%s_off;
406
+;
407
+(define_insn "%s_%s"
408
+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")
409
+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))
410
+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")
411
+                       (match_dup 0)))]
412
+       ""
413
+       "@
414
+       MOV.%s  %%1,%%0 ; cmov
415
+       LW.%s   %%1,%%0 ; cmov
416
+       LDI.%s  %%1,%%0 ; cmov
417
+       SW.%s   %%1,%%0 ; cmov"
418
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
419
+;
420
+;
421
+(define_insn "%s_%s"
422
+       [(set (match_operand:SI 0 "register_operand" "=r")
423
+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))
424
+                       (plus:SI (match_dup 0)
425
+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
426
+                       (match_dup 0)))]
427
+       ""
428
+       "ADD.%s %%1,%%0 ; cadd"
429
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
430
+;
431
+;
432
+(define_insn "%s_%s"
433
+       [(set (match_operand:SI 0 "register_operand" "=r")
434
+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))
435
+                       (xor:SI (match_dup 0)
436
+                               (const_int -1))
437
+                       (match_dup 0)))]
438
+       ""
439
+       "NOT.%s %%0     ; cnot"
440
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
441
+;
442
+;
443
+(define_insn "%s_%s"
444
+       [(set (match_operand:SI 0 "register_operand" "+r")
445
+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))
446
+                       (neg:SI (match_dup 0))
447
+                       (match_dup 0)))]
448
+       ""
449
+       "NEG.%s %%0     ; cneg"
450
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
451
+;
452
+;
453
+(define_insn "%s_%s"
454
+       [(set (match_operand:SI 0 "register_operand" "+r")
455
+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))
456
+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
457
+                       (match_dup 0)))]
458
+       ""
459
+       "AND.%s %%1,%%0 ; cand"
460
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
461
+;
462
+;
463
+(define_insn "%s_%s"
464
+       [(set (match_operand:SI 0 "register_operand" "+r")
465
+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))
466
+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
467
+                       (match_dup 0)))]
468
+       ""
469
+       "OR.%s  %%1,%%0 ; cior"
470
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
471
+;
472
+;
473
+(define_insn "%s_%s"
474
+       [(set (match_operand:SI 0 "register_operand" "+r")
475
+               (if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))
476
+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
477
+                       (match_dup 0)))]
478
+       ""
479
+       "XOR.%s %%1,%%0 ; cxor"
480
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
481
+USAGE: genzipops <new-zip-ops.md filename>.zip-ops.mdzip-ops.mdwADDplus:SIaddsi3SUBminus:SIsubsi3MPYmult:SImulsi3DIVS(ZIP_DIVIDE)div:SIdivsi3DIVUudiv:SIudivsi3ANDand:SIandsi3ORior:SIiorsi3XORxor:SIxorsi3ASRashiftrt:SIashrsi3LSLashift:SIashlsi3LSRlshiftrt:SIlshrsi3(set (match_operand:SI 0 "register_operand" "=r")
482
+               (truncate:SI (ashiftrt:DI (mult:DI
483
+                       (sign_extend:DI (match_dup 0))
484
+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
485
+                       (const_int 32))))(set (match_dup 0)
486
+               (truncate:SI (ashiftrt:DI (mult:DI
487
+                       (sign_extend:DI (match_dup 1))
488
+                       (sign_extend:DI (match_dup 2)))
489
+                       (const_int 32))))(ZIP_HAS_DI)(set (match_operand:SI 0 "register_operand" "=r")
490
+               (truncate:SI (ashiftrt:DI (mult:DI
491
+                       (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
492
+                       (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO")))
493
+                       (const_int 32))))smulsi_highpartMPYSHI(set (match_operand:SI 0 "register_operand" "=r")
494
+               (truncate:SI (ashiftrt:DI (mult:DI
495
+                       (zero_extend:DI (match_dup 0))
496
+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
497
+                       (const_int 32))))(set (match_dup 0)
498
+               (truncate:SI (ashiftrt:DI (mult:DI
499
+                       (zero_extend:DI (match_dup 1))
500
+                       (zero_extend:DI (match_dup 2)))
501
+                       (const_int 32))))(set (match_operand:SI 0 "register_operand" "=r")
502
+               (truncate:SI (ashiftrt:DI (mult:DI
503
+                       (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
504
+                       (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO")))
505
+                       (const_int 32))))umulsi_highpartMPYUHIConditional move instructionscmovConditional add instructionscaddConditional negate instructionscnegConditional not instructionscnotConditional and instructionscandConditional ior instructionsciorConditional xor instructionscxorERR: Could not create %s, leaving results in %s
506
+;˜<Ðÿÿä<Ñÿÿ´2Òÿÿ\Òÿÿ,‰ÒÿÿLéÒÿÿl§ÕÿÿŒg×ÿÿ¬¿×ÿÿÌØÿÿìMØÿÿ”Øÿÿ,ÛØÿÿL"ÙÿÿliÙÿÿŒzÙÿÿ¬¼áÿÿÌ,âÿÿzRx€Ðÿÿ*zRx$PÏÿÿðFJw€?;*3$"DÑÿÿ*A†C
ed(Ñÿÿ-A†C
h„5Ñÿÿ`A†C
[¤uÑÿÿ¾A†C
¹ÄÔÿÿÀA†C
»ä³ÕÿÿXA†C
SëÕÿÿGA†C
B$ÖÿÿGA†C
BD9ÖÿÿGA†C
Bd`ÖÿÿGA†C
B„‡ÖÿÿGA†C
B¤®ÖÿÿGA†C
BÄÕÖÿÿA†C
LäÆÖÿÿ>A†C
IŒƒDèÞÿÿeBBŽE B(ŒH0†H8ƒM@r8A0A(B BBBLßÿÿÐ@°@Ø@
ô@>`>`õþÿo˜@X@À@
507
+«@`Pˆ@X@0        þÿÿo(@ÿÿÿoðÿÿo@(>`@&@6@F@V@f@v@†@–@¦@¶@Æ@Ö@æ@›/@§/@GCC: (Ubuntu 5.4.0-6ubuntu1~16.04.9) 5.4.0 201606098@T@t@˜@À@X@@(@   X@
508
+ˆ@Ø@@
ð@@ô@@Ä6@`7@>`>` >`(>`ø?`@`ˆ@`À@`ñÿ >`0@p@.°@DÈ@`S>`zÐ@†>`¥ñÿñÿ±ð9@¿ >`ñÿË>`Ü(>`å>`øÄ6@@`!ð@1Ÿ@G9M - ˆ@`i+@Xqƒ @`Œk@À•M     @`£˜@`«¨@`²+ô@ÆÚö­ @¾Ê@G+ˆ@`8LX@GTi x@`…@”€@e×Ð@`¤  @-1@*°æ@G¸ƒ@GÀ¨@`Ì>@>Ñ-@×ëþ &ö@*,ASg¨@`s @GžØ@•À@`crtstuff.c__JCR_LIST__deregister_tm_clones__do_global_dtors_auxcompleted.7594__do_global_dtors_aux_fini_array_entryframe_dummy__frame_dummy_init_array_entrygenzipops.c__FRAME_END____JCR_END____init_array_end_DYNAMIC__init_array_start__GNU_EH_FRAME_HDR_GLOBAL_OFFSET_TABLE___libc_csu_finigenciorunlink@@GLIBC_2.2.5_ITM_deregisterTMCloneTablegencmovputs@@GLIBC_2.2.5TAILPATHgenzipopgenzip_condopTMPPATH_edatafclose@@GLIBC_2.2.5strlen@@GLIBC_2.2.5__stack_chk_fail@@GLIBC_2.4genzipop_longgencnot__libc_start_main@@GLIBC_2.2.5__data_startstrcmp@@GLIBC_2.2.5gencandfprintf@@GLIBC_2.2.5__gmon_start____dso_handle_IO_stdin_used__libc_csu_initgen_headinggencxorgencadd__bss_startmainusageaccess@@GLIBC_2.2.5fopen@@GLIBC_2.2.5_Jv_RegisterClassesrename@@GLIBC_2.2.5legalsprintf@@GLIBC_2.2.5exit@@GLIBC_2.2.5fwrite@@GLIBC_2.2.5__TMC_END___ITM_registerTMCloneTablegencnegstderr@@GLIBC_2.2.5.symtab.strtab.shstrtab.interp.note.ABI-tag.note.gnu.build-id.gnu.hash.dynsym.dynstr.gnu.version.gnu.version_r.rela.dyn.rela.plt.init.plt.got.text.fini.rodata.eh_frame_hdr.eh_frame.init_array.fini_array.jcr.dynamic.got.plt.data.bss.comment8@8#T@T 1t@t$Döÿÿo˜@˜$NÀ@À˜VX@X«^ÿÿÿo@"kþÿÿo(@(0zX@X0„Bˆ@ˆPŽØ@؉@ð”ð@ð@ò£ô@ô  ©@Á±Ä6@Ä6œ¿`7@`7”É>`>Õ>`>á >` >æ(>`(>Иø?`ø?ï@`@ˆøˆ@`ˆ@ þÀ@`¨@ 0¨@4qMà@è/ ÈI©
509
\ No newline at end of file
510
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/genzipops.c gcc-6.2.0-zip/gcc/config/zip/genzipops.c
511
--- gcc-6.2.0/gcc/config/zip/genzipops.c        1969-12-31 19:00:00.000000000 -0500
512
+++ gcc-6.2.0-zip/gcc/config/zip/genzipops.c    2017-03-07 12:03:59.062584503 -0500
513
@@ -0,0 +1,444 @@
514
+////////////////////////////////////////////////////////////////////////////////
515
+//
516
+// Filename:   genzipops.c
517
+//
518
+// Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
519
+//
520
+// Purpose:    This program generates the zip-ops.md machine description file.
521
+//
522
+//     While I understand that this is not GCC's preferred method of generating
523
+//     machine description files, there were just so many instructions to
524
+//     generate, and so many forms of them, and the GCC infrastructure didn't
525
+//     support the conditional execution model of the ZipCPU that ... I built
526
+//     it this way.
527
+//
528
+//     As of this writing, building zip-ops.md is not an automatic part of
529
+//     making GCC.  To build genzipops, just type:
530 202 dgisselq
+//
531
+//     g++ genzipops.c -o genzipops
532
+//
533
+//     And to run it, type:
534 102 dgisselq
+//
535
+//     genzipops > zip-ops.md
536 202 dgisselq
+//
537 102 dgisselq
+//     genzipops takes no arguments, and does nothing but write the machine
538 202 dgisselq
+//     descriptions to the standard output.
539 102 dgisselq
+//
540 202 dgisselq
+//
541 102 dgisselq
+// Creator:    Dan Gisselquist, Ph.D.
542 202 dgisselq
+//             Gisselquist Technology, LLC
543
+//
544
+////////////////////////////////////////////////////////////////////////////////
545
+//
546
+// Copyright (C) 2017, Gisselquist Technology, LLC
547
+//
548
+// This program is free software (firmware): you can redistribute it and/or
549
+// modify it under the terms of  the GNU General Public License as published
550
+// by the Free Software Foundation, either version 3 of the License, or (at
551
+// your option) any later version.
552
+//
553
+// This program is distributed in the hope that it will be useful, but WITHOUT
554
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
555
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
556
+// for more details.
557
+//
558
+// You should have received a copy of the GNU General Public License along
559
+// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
560
+// target there if the PDF file isn't present.)  If not, see
561 102 dgisselq
+// <http://www.gnu.org/licenses/> for a copy.
562
+//
563
+// License:    GPL, v3, as defined and found on www.gnu.org,
564
+//             http://www.gnu.org/licenses/gpl.html
565
+//
566 202 dgisselq
+//
567 102 dgisselq
+////////////////////////////////////////////////////////////////////////////////
568
+//
569
+//
570
+#include <unistd.h>
571
+#include <stdlib.h>
572
+#include <stdio.h>
573
+#include <string.h>
574
+
575
+void   legal(FILE *fp) {
576
+       fprintf(fp, ""
577
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
578
+";;\n"
579 202 dgisselq
+";; Filename:  zip-ops.md\n"
580 102 dgisselq
+";;\n"
581
+";; Project:   Zip CPU -- a small, lightweight, RISC CPU soft core\n"
582
+";;\n"
583
+";; Purpose:   This is a computer generated machine description of the\n"
584
+";;            ZipCPU\'s operations.  It is computer generated simply for\n"
585
+";;    two reasons.  First, I can\'t seem to find a way to generate this\n"
586
+";;    information within GCC\'s current constructs.  Specifically, the\n"
587
+";;    CPU\'s instructions normally set the condition codes, unless they\n"
588 202 dgisselq
+";;    are conditional instructions when they don\'t.  Second, the ZipCPU is\n"
589
+";;    actually quite regular.  Almost all of the instructions have the same\n"
590
+";;    form.  This form turns into many, many RTL instructions.  Because the\n"
591
+";;    CPU doesn\'t match any of the others within GCC, that means either\n"
592
+";;    I have a *lot* of cut, copy, paste, and edit to do to create the file\n"
593
+";;    and upon any and every edit, or I need to build a program to generate\n"
594 102 dgisselq
+";;    the remaining .md constructs.  Hence, I chose the latter to minimize\n"
595 202 dgisselq
+";;    the amount of work I needed to do.\n"
596
+";;\n"
597
+";;\n"
598
+";; Creator:   Dan Gisselquist, Ph.D.\n"
599
+";;            Gisselquist Technology, LLC\n"
600
+";;\n"
601
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
602
+";;\n"
603
+";; Copyright (C) 2017, Gisselquist Technology, LLC\n"
604
+";;\n"
605
+";; This program is free software (firmware): you can redistribute it and/or\n"
606
+";; modify it under the terms of  the GNU General Public License as published\n"
607
+";; by the Free Software Foundation, either version 3 of the License, or (at\n"
608
+";; your option) any later version.\n"
609
+";;\n"
610
+";; This program is distributed in the hope that it will be useful, but WITHOUT\n"
611
+";; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or\n"
612
+";; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License\n"
613
+";; for more details.\n"
614
+";;\n"
615
+";; License:   GPL, v3, as defined and found on www.gnu.org,\n"
616
+";;            http://www.gnu.org/licenses/gpl.html\n"
617
+";;\n"
618
+";;\n"
619
+";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n"
620
+";;\n"
621
+";;\n");
622
+}
623
+
624
+void   gen_heading(FILE *fp, const char *heading) {
625
+       fprintf(fp, ";\n;\n; %s\n;\n;\n", heading);
626
+}
627
+
628
+void   genzip_condop(FILE *fp, const char *md_opname,
629
+               const char *rtxstr, const char *insn_cond,
630
+               const char *zip_op,
631
+               const char *rtx_cond, const char *zip_cond) {
632
+
633
+       fprintf(fp, "(define_insn \"%s_%s\"\n"
634
+               "\t[(cond_exec (%s (reg:CC CC_REG) (const_int 0))\n"
635
+               "\t\t\t%s)]\n"
636
+               "\t\"%s\"\t; Condition\n"
637
+               "\t\"%s.%s\\t%%1,%%0\t; genzip, conditional operator\"\t; Template\n"
638
+               "\t[(set_attr \"predicable\" \"no\") "
639
+               "(set_attr \"ccresult\" \"unchanged\")])\n;\n;\n",
640
+               md_opname, rtx_cond, rtx_cond, rtxstr, insn_cond, zip_op, zip_cond);
641
+
642
+}
643 102 dgisselq
+
644 202 dgisselq
+void   genzipop_long(FILE *fp, const char *md_opname, const char *uncond_rtx, const char *insn_cond, const char *split_rtx, const char *dup_rtx, const char *zip_op) {
645
+       char    heading[128];
646
+       sprintf(heading, "%s (genzipop_long)", zip_op);
647 102 dgisselq
+       fprintf(fp, ";\n;\n;\n; %s (genzipop_long)\n;\n;\n;\n", zip_op);
648 202 dgisselq
+
649
+       fprintf(fp, "(define_insn \"%s\"\n"
650
+"\t[%s\n"
651
+"\t(clobber (reg:CC CC_REG))]\n"
652 102 dgisselq
+"\t\"%s\"\n"
653 202 dgisselq
+"\t\"%s\\t%%2,%%0\t; %s\"\n"
654
+"\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
655
+               md_opname, uncond_rtx, insn_cond, zip_op, md_opname);
656
+
657
+
658
+       fprintf(fp, "(define_insn \"%s_raw\"\n"
659
+"\t[%s\n"
660
+"\t(set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]\n"
661 102 dgisselq
+"\t\"%s\"\n"
662 202 dgisselq
+"\t\"%s\\t%%1,%%0\t; %s_raw\"\n"
663 102 dgisselq
+"\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"set\")])\n;\n;\n",
664 202 dgisselq
+       md_opname, dup_rtx, insn_cond, zip_op, md_opname);
665
+
666
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "eq", "Z");
667
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ne", "NZ");
668 102 dgisselq
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "lt", "LT");
669 202 dgisselq
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ge", "GE");
670
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "ltu", "C");
671
+       genzip_condop(fp, md_opname, dup_rtx, insn_cond, zip_op, "geu", "NC");
672
+}
673
+
674
+void   genzipop(FILE *fp, const char *md_opname, const char *rtx_name, const char *insn_cond, const char *zip_op) {
675
+       char    rtxstr[512], splitstr[512], dupstr[512], altname[64];
676 102 dgisselq
+
677
+       sprintf(rtxstr,
678 202 dgisselq
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
679
+"\t\t(%s (match_operand:SI 1 \"register_operand\" \"0\")\n"
680
+"\t\t\t(match_operand:SI 2 \"zip_opb_single_operand_p\" \"rO\")))", rtx_name);
681
+       sprintf(splitstr,
682
+           "(set (match_dup 0) (%s (match_dup 0) (match_dup 2)))", rtx_name);
683
+
684
+       sprintf(dupstr,
685 102 dgisselq
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
686 202 dgisselq
+"\t\t(%s (match_dup 0)\n"
687
+"\t\t\t(match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\")))", rtx_name);
688
+
689
+       genzipop_long(fp, md_opname, rtxstr, insn_cond, splitstr, dupstr, zip_op);
690
+
691
+       sprintf(rtxstr,
692
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
693 102 dgisselq
+"\t\t(%s (match_operand:SI 1 \"register_operand\" \"0\")\n"
694 202 dgisselq
+"\t\t\t(plus:SI (match_operand:SI 2 \"register_operand\" \"r\")\n"
695
+"\t\t\t\t(match_operand:SI 3 \"const_int_operand\" \"N\"))))", rtx_name);
696 102 dgisselq
+       sprintf(splitstr,
697 202 dgisselq
+           "(set (match_dup 0) (%s (match_dup 0)\n"
698
+"\t\t\t(plus:SI (match_dup 2) (match_dup 3))))", rtx_name);
699
+
700
+       sprintf(dupstr,
701
+"(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
702
+"\t\t(%s (match_dup 0)\n"
703 102 dgisselq
+"\t\t\t(plus:SI (match_operand:SI 1 \"register_operand\" \"r\")\n"
704 202 dgisselq
+"\t\t\t\t(match_operand:SI 2 \"const_int_operand\" \"N\"))))", rtx_name);
705
+
706
+       sprintf(altname, "%s_off", md_opname);
707
+
708 102 dgisselq
+       genzipop_long(fp, altname, rtxstr, insn_cond, splitstr, dupstr, zip_op);
709 202 dgisselq
+}
710 171 dgisselq
+
711 202 dgisselq
+void   gencmov(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
712
+       fprintf(fp, ";\n;\n"
713
+"(define_insn \"%s_%s\"\n"
714
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"=r,r,r,Q\")\n"
715
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
716
+               "\t\t\t(match_operand:SI 1 \"general_operand\" \"r,Q,i,r\")\n"
717
+               "\t\t\t(match_dup 0)))]\n"
718
+       "\t\"\"\n"
719 171 dgisselq
+       "\t\"@\n"
720 202 dgisselq
+       "\tMOV.%s\t%%1,%%0\t; cmov\n"
721
+       "\tLW.%s\t%%1,%%0\t; cmov\n"
722
+       "\tLDI.%s\t%%1,%%0\t; cmov\n"
723
+       "\tSW.%s\t%%1,%%0\t; cmov\"\n"
724
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
725 102 dgisselq
+       md_opname, md_cond, md_cond, zip_cond, zip_cond, zip_cond, zip_cond);
726 202 dgisselq
+
727 102 dgisselq
+}
728 202 dgisselq
+
729
+void   gencadd(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
730 102 dgisselq
+       fprintf(fp, ";\n;\n"
731 202 dgisselq
+"(define_insn \"%s_%s\"\n"
732
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
733
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
734
+                       "\t\t\t(plus:SI (match_dup 0)\n"
735
+                               "\t\t\t\t(match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
736
+                       "\t\t\t(match_dup 0)))]\n"
737
+       "\t\"\"\n"
738
+       "\t\"ADD.%s\t%%1,%%0\t; cadd\"\n"
739
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
740
+       md_opname, md_cond, md_cond, zip_cond);
741
+}
742
+
743
+void   gencnot(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
744
+       fprintf(fp, ";\n;\n"
745
+"(define_insn \"%s_%s\"\n"
746 102 dgisselq
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
747 202 dgisselq
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
748
+                       "\t\t\t(xor:SI (match_dup 0)\n"
749
+                               "\t\t\t\t(const_int -1))\n"
750
+                       "\t\t\t(match_dup 0)))]\n"
751
+       "\t\"\"\n"
752
+       "\t\"NOT.%s\t%%0\t; cnot\"\n"
753
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
754
+       md_opname, md_cond, md_cond, zip_cond);
755
+}
756
+
757
+void   gencneg(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
758
+       fprintf(fp, ";\n;\n"
759
+"(define_insn \"%s_%s\"\n"
760
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
761
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
762
+                       "\t\t\t(neg:SI (match_dup 0))\n"
763
+                       "\t\t\t(match_dup 0)))]\n"
764
+       "\t\"\"\n"
765
+       "\t\"NEG.%s\t%%0\t; cneg\"\n"
766
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
767
+       md_opname, md_cond, md_cond, zip_cond);
768
+}
769
+
770
+
771
+void   gencand(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
772
+       fprintf(fp, ";\n;\n"
773
+"(define_insn \"%s_%s\"\n"
774
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
775
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
776
+                       "\t\t\t(and:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
777
+                       "\t\t\t(match_dup 0)))]\n"
778
+       "\t\"\"\n"
779
+       "\t\"AND.%s\t%%1,%%0\t; cand\"\n"
780
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
781
+       md_opname, md_cond, md_cond, zip_cond);
782
+}
783
+
784
+
785
+void   gencior(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
786
+       fprintf(fp, ";\n;\n"
787
+"(define_insn \"%s_%s\"\n"
788
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
789
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
790
+                       "\t\t\t(ior:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
791
+                       "\t\t\t(match_dup 0)))]\n"
792
+       "\t\"\"\n"
793
+       "\t\"OR.%s\t%%1,%%0\t; cior\"\n"
794
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
795
+       md_opname, md_cond, md_cond, zip_cond);
796
+}
797
+
798
+void   gencxor(FILE *fp, const char *md_opname, const char *md_cond, const char *zip_cond) {
799
+       fprintf(fp, ";\n;\n"
800
+"(define_insn \"%s_%s\"\n"
801
+       "\t[(set (match_operand:SI 0 \"register_operand\" \"+r\")\n"
802
+               "\t\t(if_then_else:SI (%s (reg:CC CC_REG) (const_int 0))\n"
803
+                       "\t\t\t(xor:SI (match_dup 0) (match_operand:SI 1 \"zip_opb_single_operand_p\" \"rO\"))\n"
804
+                       "\t\t\t(match_dup 0)))]\n"
805
+       "\t\"\"\n"
806
+       "\t\"XOR.%s\t%%1,%%0\t; cxor\"\n"
807
+       "\t[(set_attr \"predicable\" \"no\") (set_attr \"ccresult\" \"unchanged\")])\n",
808
+       md_opname, md_cond, md_cond, zip_cond);
809
+}
810
+
811
+void   usage(void) {
812
+       printf("USAGE: genzipops <new-zip-ops.md filename>\n");
813
+}
814
+
815
+const  char    *TMPPATH = ".zip-ops.md";
816
+const  char    *TAILPATH = "zip-ops.md";
817
+
818
+int main(int argc, char **argv) {
819
+       FILE    *fp = fopen(TMPPATH, "w");
820
+       const char      *newname = TAILPATH;
821
+
822
+       if ((argc>1)&&(argv[1][0] == '-')) {
823
+               usage();
824
+               exit(EXIT_FAILURE);
825
+       }
826
+
827
+       if (argc>1) {
828
+               if ((strlen(argv[1])>=strlen(TAILPATH))
829
+                       &&(strcmp(&argv[1][strlen(argv[1])-strlen(TAILPATH)],
830
+                               TAILPATH)==0)
831
+                       &&(access(argv[1], F_OK)==0))
832
+                               unlink(argv[1]);
833
+               newname = argv[1];
834
+       }
835
+
836
+       legal(fp);
837
+       genzipop(fp, "addsi3",  "plus:SI",    "",             "ADD");
838
+       genzipop(fp, "subsi3",  "minus:SI",   "",             "SUB");
839
+       genzipop(fp, "mulsi3",  "mult:SI",    "",             "MPY");
840
+       genzipop(fp, "divsi3",  "div:SI",     "(ZIP_DIVIDE)", "DIVS");
841
+       genzipop(fp, "udivsi3", "udiv:SI",    "(ZIP_DIVIDE)", "DIVU");
842
+       genzipop(fp, "andsi3",  "and:SI",     "",             "AND");
843
+       genzipop(fp, "iorsi3",  "ior:SI",     "",             "OR");
844
+       genzipop(fp, "xorsi3",  "xor:SI",     "",             "XOR");
845
+       genzipop(fp, "ashrsi3", "ashiftrt:SI","",             "ASR");
846
+       genzipop(fp, "ashlsi3", "ashift:SI",  "",             "LSL");
847
+       genzipop(fp, "lshrsi3", "lshiftrt:SI","",             "LSR");
848
+
849
+       genzipop_long(fp, "smulsi_highpart",
850
+               "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
851
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
852
+               "\t\t\t(sign_extend:DI (match_operand:SI 1 \"register_operand\" \"0\"))\n"
853
+               "\t\t\t(sign_extend:DI (match_operand:SI 2 \"zip_opb_operand_p\" \"rO\")))\n"
854
+               "\t\t\t(const_int 32))))",
855
+               "(ZIP_HAS_DI)",
856
+               "(set (match_dup 0)\n"
857
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
858
+               "\t\t\t(sign_extend:DI (match_dup 1))\n"
859
+               "\t\t\t(sign_extend:DI (match_dup 2)))\n"
860
+               "\t\t\t(const_int 32))))",
861
+               //
862
+               "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
863
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
864
+               "\t\t\t(sign_extend:DI (match_dup 0))\n"
865
+               "\t\t\t(sign_extend:DI (match_operand:SI 1 \"zip_opb_operand_p\" \"rO\")))\n"
866
+               "\t\t\t(const_int 32))))",
867
+               "MPYSHI");
868
+       genzipop_long(fp, "umulsi_highpart",
869
+               "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
870
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
871
+               "\t\t\t(zero_extend:DI (match_operand:SI 1 \"register_operand\" \"0\"))\n"
872
+               "\t\t\t(zero_extend:DI (match_operand:SI 2 \"zip_opb_operand_p\" \"rO\")))\n"
873
+               "\t\t\t(const_int 32))))",
874
+               "(ZIP_HAS_DI)",
875
+               "(set (match_dup 0)\n"
876
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
877
+               "\t\t\t(zero_extend:DI (match_dup 1))\n"
878
+               "\t\t\t(zero_extend:DI (match_dup 2)))\n"
879
+               "\t\t\t(const_int 32))))",
880
+               //
881
+               "(set (match_operand:SI 0 \"register_operand\" \"=r\")\n"
882
+               "\t\t(truncate:SI (ashiftrt:DI (mult:DI\n"
883
+               "\t\t\t(zero_extend:DI (match_dup 0))\n"
884
+               "\t\t\t(zero_extend:DI (match_operand:SI 1 \"zip_opb_operand_p\" \"rO\")))\n"
885
+               "\t\t\t(const_int 32))))",
886
+               "MPYUHI");
887
+
888
+       gen_heading(fp, "Conditional move instructions");
889
+
890
+       gencmov(fp, "cmov", "eq", "Z");
891
+       gencmov(fp, "cmov", "ne", "NZ");
892
+       gencmov(fp, "cmov", "lt", "LT");
893
+       gencmov(fp, "cmov", "ge", "GE");
894
+       gencmov(fp, "cmov", "ltu", "C");
895
+       gencmov(fp, "cmov", "geu", "NC");
896
+
897
+       gen_heading(fp, "Conditional add instructions");
898
+
899
+       gencadd(fp, "cadd", "eq", "Z");
900
+       gencadd(fp, "cadd", "ne", "NZ");
901
+       gencadd(fp, "cadd", "lt", "LT");
902
+       gencadd(fp, "cadd", "ge", "GE");
903
+       gencadd(fp, "cadd", "ltu", "C");
904
+       gencadd(fp, "cadd", "geu", "NC");
905
+
906
+       gen_heading(fp, "Conditional negate instructions");
907
+
908
+       gencneg(fp, "cneg", "eq", "Z");
909
+       gencneg(fp, "cneg", "ne", "NZ");
910
+       gencneg(fp, "cneg", "lt", "LT");
911
+       gencneg(fp, "cneg", "ge", "GE");
912
+       gencneg(fp, "cneg", "ltu", "C");
913
+       gencneg(fp, "cneg", "geu", "NC");
914
+
915
+       gen_heading(fp, "Conditional not instructions");
916
+
917
+       gencnot(fp, "cnot", "eq", "Z");
918
+       gencnot(fp, "cnot", "ne", "NZ");
919
+       gencnot(fp, "cnot", "lt", "LT");
920
+       gencnot(fp, "cnot", "ge", "GE");
921
+       gencnot(fp, "cnot", "ltu", "C");
922
+       gencnot(fp, "cnot", "geu", "NC");
923
+
924
+       gen_heading(fp, "Conditional and instructions");
925
+
926
+       gencand(fp, "cand", "eq", "Z");
927
+       gencand(fp, "cand", "ne", "NZ");
928
+       gencand(fp, "cand", "lt", "LT");
929
+       gencand(fp, "cand", "ge", "GE");
930
+       gencand(fp, "cand", "ltu", "C");
931
+       gencand(fp, "cand", "geu", "NC");
932
+
933
+       gen_heading(fp, "Conditional ior instructions");
934
+
935
+       gencior(fp, "cior", "eq", "Z");
936
+       gencior(fp, "cior", "ne", "NZ");
937
+       gencior(fp, "cior", "lt", "LT");
938
+       gencior(fp, "cior", "ge", "GE");
939
+       gencior(fp, "cior", "ltu", "C");
940
+       gencior(fp, "cior", "geu", "NC");
941
+
942
+       gen_heading(fp, "Conditional xor instructions");
943
+
944
+       gencxor(fp, "cxor", "eq", "Z");
945
+       gencxor(fp, "cxor", "ne", "NZ");
946
+       gencxor(fp, "cxor", "lt", "LT");
947
+       gencxor(fp, "cxor", "ge", "GE");
948
+       gencxor(fp, "cxor", "ltu", "C");
949
+       gencxor(fp, "cxor", "geu", "NC");
950
+
951
+       fclose(fp);
952
+
953
+       if (rename(TMPPATH, newname) != 0) {
954
+               fprintf(stderr, "ERR: Could not create %s, leaving results in %s\n", newname, TMPPATH);
955
+               exit(EXIT_FAILURE);
956
+       } exit(EXIT_SUCCESS);
957
+}
958
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.c gcc-6.2.0-zip/gcc/config/zip/zip.c
959
--- gcc-6.2.0/gcc/config/zip/zip.c      1969-12-31 19:00:00.000000000 -0500
960
+++ gcc-6.2.0-zip/gcc/config/zip/zip.c  2018-06-05 21:17:24.151098201 -0400
961
@@ -0,0 +1,2711 @@
962
+////////////////////////////////////////////////////////////////////////////////
963
+//
964
+// Filename:   zip.c
965
+//
966
+// Project:    Zip CPU backend for the GNU Compiler Collection
967
+//
968
+// Purpose:
969
+//
970
+// Creator:    Dan Gisselquist, Ph.D.
971
+//             Gisselquist Technology, LLC
972
+//
973
+////////////////////////////////////////////////////////////////////////////////
974
+//
975
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
976
+//
977
+// This program is free software (firmware): you can redistribute it and/or
978
+// modify it under the terms of  the GNU General Public License as published
979
+// by the Free Software Foundation, either version 3 of the License, or (at
980 209 dgisselq
+// your option) any later version.
981
+//
982 102 dgisselq
+// This program is distributed in the hope that it will be useful, but WITHOUT
983
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
984
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
985
+// for more details.
986
+//
987
+// You should have received a copy of the GNU General Public License along
988
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
989
+// target there if the PDF file isn't present.)  If not, see
990
+// <http://www.gnu.org/licenses/> for a copy.
991
+//
992
+// License:    GPL, v3, as defined and found on www.gnu.org,
993
+//             http://www.gnu.org/licenses/gpl.html
994
+//
995 202 dgisselq
+//
996 102 dgisselq
+////////////////////////////////////////////////////////////////////////////////
997
+#include "config.h"
998
+#include "system.h"
999
+#include "coretypes.h"
1000
+#include "tm.h"
1001
+#include "rtl.h"
1002
+#include "dominance.h"
1003
+#include "cfg.h"
1004
+#include "cfgrtl.h"
1005
+#include "cfganal.h"
1006
+#include "lcm.h"
1007
+#include "cfgbuild.h"
1008
+#include "cfgcleanup.h"
1009
+#include "predict.h"
1010
+#include "basic-block.h"
1011
+#include "bitmap.h"
1012
+#include "df.h"
1013
+#include "hashtab.h"
1014
+#include "hash-set.h"
1015
+#include "machmode.h"
1016
+#include "symtab.h"
1017
+#include "rtlhash.h"
1018
+#include "tree.h"
1019
+#include "regs.h"
1020
+#include "hard-reg-set.h"
1021
+#include "real.h"
1022
+#include "insn-config.h"
1023
+#include "conditions.h"
1024
+#include "output.h"
1025
+#include "insn-attr.h"
1026
+#include "flags.h"
1027
+#include "expr.h"
1028
+#include "function.h"
1029
+#include "recog.h"
1030
+#include "toplev.h"
1031 202 dgisselq
+#include "ggc.h"
1032 102 dgisselq
+#include "builtins.h"
1033
+#include "calls.h"
1034
+#include "langhooks.h"
1035
+#include "optabs.h"
1036
+#include "explow.h"
1037
+#include "emit-rtl.h"
1038
+#include "ifcvt.h"
1039
+#include "genrtl.h"
1040
+
1041
+// #include "tmp_p.h"
1042
+#include "target.h"
1043
+#include "target-def.h"
1044
+// #include "tm-constrs.h"
1045
+#include "tm-preds.h"
1046
+
1047
+#include "diagnostic.h"
1048
+// #include "integrate.h"
1049
+
1050
+#include "zip-protos.h"
1051
+
1052
+static bool    zip_return_in_memory(const_tree, const_tree);
1053
+static bool    zip_frame_pointer_required(void);
1054
+
1055
+static void zip_function_arg_advance(cumulative_args_t ca, enum machine_mode mode,
1056
+               const_tree type, bool named);
1057
+static rtx zip_function_arg(cumulative_args_t ca, enum machine_mode mode, const_tree type, bool named);
1058 122 dgisselq
+
1059 202 dgisselq
+static void    zip_asm_trampoline_template(FILE *);
1060 102 dgisselq
+static void    zip_trampoline_init(rtx, tree, rtx);
1061
+static void    zip_init_builtins(void);
1062
+static tree    zip_builtin_decl(unsigned, bool);
1063
+// static void zip_asm_output_anchor(rtx x);
1064
+       void    zip_asm_output_def(FILE *s, const char *n, const char *v);
1065 122 dgisselq
+static rtx     zip_expand_builtin(tree exp, rtx target, rtx subtarget,
1066 102 dgisselq
+                       enum machine_mode tmode, int    ignore);
1067
+static bool    zip_scalar_mode_supported_p(enum machine_mode mode);
1068
+static bool    zip_libgcc_floating_mode_supported_p(enum machine_mode mode);
1069
+static int     zip_address_cost(rtx addr, enum machine_mode mode, addr_space_t as, bool spd);
1070 200 dgisselq
+static bool    zip_mode_dependent_address_p(const_rtx addr, addr_space_t);
1071
+static unsigned HOST_WIDE_INT  zip_const_anchor = 0x20000;
1072 102 dgisselq
+static          HOST_WIDE_INT  zip_min_opb_imm = -0x20000;
1073
+static          HOST_WIDE_INT  zip_max_opb_imm =  0x1ffff;
1074
+static          HOST_WIDE_INT  zip_min_anchor_offset = -0x2000;
1075
+static          HOST_WIDE_INT  zip_max_anchor_offset =  0x1fff;
1076
+static          HOST_WIDE_INT  zip_min_mov_offset = -0x1000;
1077
+static          HOST_WIDE_INT  zip_max_mov_offset =  0x0fff;
1078
+static int     zip_sched_issue_rate(void) { return 1; }
1079
+static bool    zip_legitimate_address_p(machine_mode, rtx, bool);
1080
+static bool    zip_legitimate_move_operand_p(machine_mode, rtx, bool);
1081
+       void    zip_debug_rtx_pfx(const char *, const_rtx x);
1082 202 dgisselq
+       void    zip_debug_rtx(const_rtx x);
1083 102 dgisselq
+static void    zip_override_options(void);
1084
+static bool    zip_can_eliminate(int from ATTRIBUTE_UNUSED, int to);
1085
+static int     zip_memory_move_cost(machine_mode, reg_class_t, bool);
1086
+static rtx     zip_legitimize_address(rtx x, rtx oldx, machine_mode mode);
1087
+static bool    zip_cannot_modify_jumps_p(void);
1088
+static bool    zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b);
1089
+
1090
+
1091
+#define        ZIP_ALL_DEBUG_OFF       false
1092 122 dgisselq
+#define        ZIP_ALL_DEBUG_ON        false
1093
+#define        ZIPDEBUGFLAG(A,B)       const bool A =                  \
1094 142 dgisselq
+               ((ZIP_ALL_DEBUG_ON)||(B))&&(!ZIP_ALL_DEBUG_OFF)
1095
+
1096 102 dgisselq
+enum ZIP_BUILTIN_ID_CODE {
1097
+       ZIP_BUILTIN_RTU,
1098
+       ZIP_BUILTIN_HALT,
1099
+       ZIP_BUILTIN_IDLE,
1100
+       ZIP_BUILTIN_SYSCALL,
1101
+       ZIP_BUILTIN_SAVE_CONTEXT,
1102
+       ZIP_BUILTIN_RESTORE_CONTEXT,
1103
+       ZIP_BUILTIN_BITREV,
1104
+       ZIP_BUILTIN_CC,
1105
+       ZIP_BUILTIN_UCC,
1106 111 dgisselq
+       ZIP_BUILTIN_BUSY,
1107 117 dgisselq
+       ZIP_BUILTIN_MAX
1108 122 dgisselq
+};
1109 102 dgisselq
+
1110
+static GTY (()) tree   zip_builtins[(int)ZIP_BUILTIN_MAX];
1111 202 dgisselq
+static enum insn_code  zip_builtins_icode[(int)ZIP_BUILTIN_MAX];
1112
+
1113
+#undef TARGET_ASM_ALIGNED_HI_OP
1114
+#undef TARGET_ASM_ALIGNED_SI_OP
1115 102 dgisselq
+#undef TARGET_ASM_ALIGNED_DI_OP
1116
+#define        TARGET_ASM_ALIGNED_HI_OP        "\t.short\t"
1117
+#define        TARGET_ASM_ALIGNED_SI_OP        "\t.int\t"
1118
+#define        TARGET_ASM_ALIGNED_DI_OP        "\t.quad\t"
1119
+
1120
+#undef TARGET_ASM_UNALIGNED_HI_OP
1121
+#undef TARGET_ASM_UNALIGNED_SI_OP
1122
+#undef TARGET_ASM_UNALIGNED_DI_OP
1123
+#define        TARGET_ASM_UNALIGNED_HI_OP      TARGET_ASM_ALIGNED_HI_OP
1124
+#define        TARGET_ASM_UNALIGNED_SI_OP      TARGET_ASM_ALIGNED_SI_OP
1125 117 dgisselq
+#define        TARGET_ASM_UNALIGNED_DI_OP      TARGET_ASM_ALIGNED_DI_OP
1126 171 dgisselq
+
1127 102 dgisselq
+#include "gt-zip.h"
1128
+
1129
+/* The Global 'targetm' Variable. */
1130
+struct gcc_target      targetm = TARGET_INITIALIZER;
1131
+
1132
+
1133 202 dgisselq
+enum   reg_class zip_reg_class(int);
1134
+
1135
+#define        LOSE_AND_RETURN(msgid, x)               \
1136
+       do {                                    \
1137
+               zip_operand_lossage(msgid, x);  \
1138
+               return;                         \
1139 102 dgisselq
+       } while(0)
1140 202 dgisselq
+
1141
+/* Per-function machine data. */
1142
+struct GTY(()) machine_function
1143
+{
1144
+       /* number of pretented arguments for varargs */
1145
+       int     pretend_size;
1146
+
1147 102 dgisselq
+       /* Number of bytes saved on the stack for local variables. */
1148
+       int     local_vars_size;
1149
+
1150
+       /* Number of bytes saved on stack for register save area */
1151
+       int     saved_reg_size;
1152
+       int     save_ret;
1153
+
1154
+       int     sp_fp_offset;
1155
+       bool    fp_needed;
1156
+       int     size_for_adjusting_sp;
1157
+};
1158
+
1159
+/* Allocate a chunk of memory for per-function machine-dependent data. */
1160
+
1161
+static struct machine_function *
1162
+zip_init_machine_status(void) {
1163
+       return ggc_cleared_alloc<machine_function>();
1164
+}
1165
+
1166
+static void
1167
+zip_override_options(void)
1168
+{
1169
+       init_machine_status = zip_init_machine_status;
1170
+}
1171
+
1172
+enum   reg_class
1173
+zip_reg_class(int regno)
1174
+{
1175
+       if (is_ZIP_GENERAL_REG(regno)) {
1176
+               return GENERAL_REGS;
1177
+       } else if (is_ZIP_REG(regno)) {
1178
+               return ALL_REGS;
1179
+       } return NO_REGS;
1180
+}
1181
+
1182
+/* Worker function for TARGET_RETURN_IN_MEMORY. */
1183
+static bool
1184
+zip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED) {
1185
+       const   HOST_WIDE_INT size = int_size_in_bytes(type);
1186
+       return (size == -1)||(size > 2*UNITS_PER_WORD);
1187
+}
1188
+
1189
+/* Emit an error emssage when we're in an asm, and a fatal error for "normal"
1190
+ * insn.  Formatted output isn't easily implemented, since we use output operand
1191
+ * lossage to output the actual message and handle the categorization of the
1192
+ * error.  */
1193
+
1194
+static void
1195
+zip_operand_lossage(const char *msgid, rtx op) {
1196
+       debug_rtx(op);
1197
+       zip_debug_rtx(op);
1198
+       output_operand_lossage("%s", msgid);
1199
+}
1200
+
1201
+/* The PRINT_OPERAND_ADDRESS worker.   */
1202
+void
1203
+zip_print_operand_address(FILE *file, rtx x) {
1204
+       ZIPDEBUGFLAG(dbg, false);
1205
+
1206 202 dgisselq
+       if (dbg) zip_debug_rtx(x);
1207 102 dgisselq
+       switch(GET_CODE(x)) {
1208
+               case REG:
1209
+                       gcc_assert(is_ZIP_REG(REGNO(x)));
1210
+                       gcc_assert(REGNO(x) < 16);
1211
+                       fprintf(file, "(%s)", reg_names[REGNO(x)]);
1212
+                       break;
1213
+               case SYMBOL_REF:
1214
+                       fprintf(file, "%s", XSTR(x,0));
1215
+                       break;
1216
+               case LABEL_REF:
1217
+                       x = LABEL_REF_LABEL(x);
1218
+               case CODE_LABEL:
1219
+                       { char buf[256];
1220
+                       ASM_GENERATE_INTERNAL_LABEL(buf, "L", CODE_LABEL_NUMBER(x));
1221
+#ifdef ASM_OUTPUT_LABEL_REF
1222
+                       ASM_OUTPUT_LABEL_REF(file, buf);
1223
+#else
1224 202 dgisselq
+                       assemble_name(file, buf);
1225 102 dgisselq
+#endif
1226
+                       }
1227
+                       break;
1228
+               case PLUS:
1229 127 dgisselq
+                       if (!REG_P(XEXP(x, 0))) {
1230 171 dgisselq
+                               fprintf(stderr, "Unsupported address construct\n");
1231 102 dgisselq
+                               zip_debug_rtx(x);
1232
+                               abort();
1233
+                       } gcc_assert(is_ZIP_REG(REGNO(XEXP(x,0))));
1234
+                       gcc_assert(REGNO(XEXP(x,0))<16);
1235
+                       if (CONST_INT_P(XEXP(x, 1))) {
1236
+                               if (INTVAL(XEXP(x,1))!=0) {
1237
+                                       fprintf(file, "%ld(%s)",
1238
+                                       (long)INTVAL(XEXP(x, 1)),
1239
+                                       reg_names[REGNO(XEXP(x, 0))]);
1240
+                               } else {
1241
+                                       fprintf(file, "(%s)",
1242
+                                       reg_names[REGNO(XEXP(x, 0))]);
1243
+                               }
1244
+                       } else if (GET_CODE(XEXP(x,1)) == SYMBOL_REF) {
1245
+                               fprintf(file, "%s(%s)", XSTR(x,0),
1246
+                                       reg_names[REGNO(XEXP(x, 0))]);
1247
+                       } else if ((GET_CODE(XEXP(x, 1)) == MINUS)
1248
+                               && (GET_CODE(XEXP(XEXP(x, 1), 0))==SYMBOL_REF)
1249 111 dgisselq
+                               && (GET_CODE(XEXP(XEXP(x, 1), 1))==SYMBOL_REF)) {
1250
+                               fprintf(file, "%s-%s(%s)",
1251
+                                       XSTR(XEXP(XEXP(x, 1),0),0),
1252 102 dgisselq
+                                       XSTR(XEXP(XEXP(x, 1),1),0),
1253 127 dgisselq
+                                       reg_names[REGNO(XEXP(x, 0))]);
1254 171 dgisselq
+                       } else
1255 127 dgisselq
+                               fprintf(file, "#INVALID(%s)",
1256 102 dgisselq
+                                       reg_names[REGNO(XEXP(x, 0))]);
1257
+                       /*
1258 135 dgisselq
+                       else if (GET_CODE(XEXP(addr, 1)) == LABEL)
1259 102 dgisselq
+                               fprintf(file, "%s(%s)",
1260
+                                       GET_CODE(XEXP(addr, 1)),
1261
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
1262
+                       else if ((GET_CODE(XEXP(addr, 1)) == MINUS)
1263
+                               && (GET_CODE(XEXP(GET_CODE(XEXP(addr, 1)), 0))==LABEL)
1264
+                               && (GET_CODE(XEXP(GET_CODE(XEXP(addr, 1)), 1))==LABEL)) {
1265
+                               fprintf(file, "%s-%s(%s)",
1266
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
1267
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
1268
+                                       reg_names[REGNO(GET_CODE(XEXP(addr, 0)))]);
1269
+                       }
1270
+                       */
1271
+                       break;
1272
+               // We don't support direct memory addressing within our
1273
+               // instruction set, even though the instructions themselves
1274
+               // would support direct memory addressing of the lower 18 bits
1275
+               // of memory space.
1276
+               case MEM:
1277
+                       if (dbg) zip_debug_rtx(x);
1278
+                       zip_print_operand_address(file, XEXP(x, 0));
1279
+                       break;
1280
+               case CONST_INT:
1281
+                       fprintf(file, "%ld",(long)INTVAL(x));
1282
+                       break;
1283
+               default:
1284
+                       fprintf(stderr, "Unknown address format\n");
1285
+                       zip_debug_rtx(x);
1286
+                       abort(); break;
1287
+                       // output_addr_const(file, x);
1288
+               break;
1289
+       }
1290
+}
1291
+
1292
+/* The PRINT_OPERAND worker. */
1293
+
1294
+void
1295
+zip_print_operand(FILE *file, rtx x, int code)
1296
+{
1297
+       rtx operand = x;
1298
+       int     rgoff = 0;
1299
+
1300 111 dgisselq
+       // fprintf(file, "Print Operand!\n");
1301 135 dgisselq
+
1302 111 dgisselq
+       /* New code entries should just be added to the switch below.  If
1303 102 dgisselq
+        * handling is finished, just return.  If handling was just a
1304 111 dgisselq
+        * modification of the operand, the modified operand should be put in
1305
+        * "operand", and then do a break to let default handling
1306 102 dgisselq
+        * (zero-modifier) output the operand.
1307
+        */
1308
+       switch(code) {
1309
+               case 0:
1310
+                       /* No code, print as usual. */
1311
+                       break;
1312
+               case 'L':
1313
+                       /* Lower of two registers, print one up */
1314
+                       rgoff = 1;
1315
+                       break;
1316
+               case 'R':
1317
+               case 'H':
1318
+                       /* Higher of a register pair, print normal */
1319
+                       break;
1320
+
1321
+               default:
1322
+                       LOSE_AND_RETURN("invalid operand modifier letter", x);
1323
+       }
1324
+
1325
+       /* Print an operand as without a modifier letter. */
1326
+       switch (GET_CODE(operand)) {
1327
+       case REG:
1328
+               if (REGNO(operand)+rgoff >= FIRST_PSEUDO_REGISTER)
1329
+                       internal_error("internal error: bad register: %d", REGNO(operand));
1330
+               fprintf(file, "%s", reg_names[REGNO(operand)+rgoff]);
1331
+               return;
1332
+       case SCRATCH:
1333
+               LOSE_AND_RETURN("Need a scratch register", x);
1334
+               return;
1335
+
1336
+       case CODE_LABEL:
1337
+       case LABEL_REF:
1338
+       case SYMBOL_REF:
1339
+       case PLUS:
1340
+               PRINT_OPERAND_ADDRESS(file, operand);
1341
+               return;
1342
+       case MEM:
1343
+               PRINT_OPERAND_ADDRESS(file, XEXP(operand, 0));
1344
+               return;
1345
+
1346
+       default:
1347
+               /* No need to handle all strange variants, let
1348
+                * output_addr_const do it for us.
1349
+                */
1350
+               if (CONSTANT_P(operand)) {
1351
+                       output_addr_const(file, operand);
1352
+                       return;
1353
+               }
1354
+
1355
+               zip_debug_rtx(x);
1356
+               LOSE_AND_RETURN("unexpected operand", x);
1357
+       }
1358
+}
1359
+
1360
+static bool
1361
+zip_frame_pointer_required(void)
1362
+{
1363
+       // This should really depend upon whether we have variable sized
1364
+       // arguments in our frame or not.  Once this fails, let's look
1365
+       // at what the problem was and then whether or not we can detect
1366
+       // it.
1367
+       //
1368
+       // Use a GCC global to determine our answer
1369
+       if (cfun->calls_alloca)
1370
+               return true;
1371
+
1372
+       // If the stack frame is too large to access saved registers with
1373
+       // immediate offsets, then we *must* use a frame pointer
1374
+       unsigned stack_size = 36;
1375 202 dgisselq
+       stack_size += (ACCUMULATE_OUTGOING_ARGS ? crtl->outgoing_args_size : 0);
1376 102 dgisselq
+
1377
+       //
1378
+       // if cfun->machine->size_for_adjusting_sp might ever be larger than
1379
+       //       zip_max_anchor_offset, then we MUST have a frame pointer.
1380
+       //
1381
+       // cfun->machine->size_for_adjusting_sp =
1382
+       //              get_frame_size
1383
+       //              + saved_reg_size (will always be <= 36)
1384
+       //              + outgoing_args_size;
1385
+       //              + pretend_args_size;
1386
+
1387
+       if(crtl->args.pretend_args_size > 0)
1388
+               stack_size += crtl->args.pretend_args_size;
1389 103 dgisselq
+       stack_size += get_frame_size();
1390
+       // Align our attempted stack size
1391 202 dgisselq
+       stack_size = ((stack_size+3)&-4);
1392
+
1393
+       // Now here's our test
1394
+       if (stack_size >= zip_max_anchor_offset)
1395
+               return true;
1396
+       return (frame_pointer_needed);
1397
+/*
1398
+*/
1399
+}
1400
+
1401
+/* Determine whether or not a register needs to be saved on the stack or not.
1402
+ */
1403
+static bool
1404
+zip_save_reg(int regno) {
1405
+       if (regno == 0)
1406
+               return ((!crtl->is_leaf)
1407
+                       ||((df_regs_ever_live_p(0))&&(!call_used_regs[0])));
1408
+       else if ((regno == zip_GOT)&&(!ZIP_PIC))
1409
+               return  ((df_regs_ever_live_p(regno))
1410
+                               &&(!call_used_regs[regno]));
1411
+       else if (regno == zip_FP)
1412
+               return((zip_frame_pointer_required())||((df_regs_ever_live_p(regno))
1413
+                               &&(!call_used_regs[regno])));
1414
+       else if (regno < zip_FP)
1415
+               return  ((df_regs_ever_live_p(regno))
1416 102 dgisselq
+                               &&(!call_used_regs[regno]));
1417
+       return false;
1418
+}
1419
+
1420
+/* Compute the size of the local area and the size to be adjusted by the
1421
+ * prologue and epilogue.
1422
+ *
1423
+ * Here's what we are looking at (top is the current, bottom is the last ...)
1424
+ *
1425
+ *     Stack Pointer ->
1426
+ *                     Outgoing arguments
1427
+ *                     Local variables (could be variable size)
1428
+ *     Frame Pointer ->        (= Stack Pointer + sp_fp_offset)
1429
+ *                     Saved return address, if saved
1430
+ *                     Other Saved registers
1431
+ *                     Saved frame pointer (if used)
1432
+ *                     Saved R12, if used
1433
+ *                     (Stack pointer is not saved)
1434
+ *                     (PRETEND-ARGS)
1435
+ *     Original stack pointer ->       (= Stack_Pointer +size_for_adjusting_sp)
1436
+ *                     Called arguments (not passed in registers)
1437
+ *                     Return arguments (not R1, args.pretend_args_size)
1438
+ *             (Prior function's stack frame ... )
1439
+ *
1440
+ */
1441
+static void
1442
+zip_compute_frame(void) {
1443
+       int     regno;
1444
+       int     args_size;
1445
+       ZIPDEBUGFLAG(dbg, false);
1446 124 dgisselq
+
1447 102 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-COMPUTE-FRAME: %s\n", current_function_name());
1448
+       // gcc_assert(crtl);
1449
+       gcc_assert(cfun);
1450
+       gcc_assert(cfun->machine);
1451
+
1452
+       args_size=(ACCUMULATE_OUTGOING_ARGS ? crtl->outgoing_args_size : 0);
1453
+
1454 171 dgisselq
+       if(crtl->args.pretend_args_size > 0) {
1455 102 dgisselq
+               args_size += crtl->args.pretend_args_size;
1456
+               if (dbg) fprintf(stderr, "%s pretend_args_size : %d\n", current_function_name(),
1457
+                       crtl->args.pretend_args_size);
1458
+               cfun->machine->pretend_size = crtl->args.pretend_args_size;
1459
+       }
1460
+
1461
+       cfun->machine->local_vars_size = get_frame_size();
1462
+
1463
+       // Force frame alignment of the local variable section
1464
+       cfun->machine->local_vars_size += 3;
1465 202 dgisselq
+       cfun->machine->local_vars_size &= -4;
1466 102 dgisselq
+
1467 171 dgisselq
+       // Save callee-saved registers.
1468 102 dgisselq
+       cfun->machine->saved_reg_size = 0;
1469
+       for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
1470
+               if (zip_save_reg(regno))
1471
+                       cfun->machine->saved_reg_size += 4;
1472
+       }
1473
+
1474
+       cfun->machine->fp_needed = (zip_frame_pointer_required());
1475
+
1476 171 dgisselq
+       if ((cfun->machine->fp_needed)&&
1477
+                       (!df_regs_ever_live_p(zip_FP))) {
1478 102 dgisselq
+               cfun->machine->saved_reg_size += 4;
1479
+       }
1480
+
1481
+       cfun->machine->sp_fp_offset = crtl->outgoing_args_size
1482
+                               + cfun->machine->local_vars_size;
1483 202 dgisselq
+       cfun->machine->size_for_adjusting_sp = cfun->machine->local_vars_size
1484
+                       + cfun->machine->saved_reg_size
1485
+                       + args_size;
1486
+       if(dbg) {
1487 102 dgisselq
+               fprintf(stderr, "\t---- STACK PTR ----\n");
1488
+               fprintf(stderr, "\tOUTGOIN-SIZE: %d\n",
1489
+                       crtl->outgoing_args_size);
1490
+               fprintf(stderr, "\tLOCALS-SIZE : %d\n",
1491 202 dgisselq
+                       cfun->machine->local_vars_size);
1492 102 dgisselq
+               fprintf(stderr, "\t---- FRAME PTR ----%s\n",
1493
+                       cfun->machine->fp_needed?"":" (Eliminated)");
1494
+               fprintf(stderr, "\tREGISTERS   : %d\n",
1495
+                       cfun->machine->saved_reg_size);
1496
+               fprintf(stderr, "\tPRETEND SIZE: %d\n",
1497
+                       crtl->args.pretend_args_size);
1498 202 dgisselq
+               fprintf(stderr, "\t---- ARG PTR (Original SP, should be eliminated) ----\n");
1499 102 dgisselq
+               fprintf(stderr, "\t----\n");
1500
+               fprintf(stderr, "\tARGS-SIZE   : %d\n", args_size);
1501 171 dgisselq
+               fprintf(stderr, "\tSP_FP_OFFSET: %d\n",
1502
+                       cfun->machine->sp_fp_offset);
1503 102 dgisselq
+               fprintf(stderr, "\tSP-ADJUSTMNT: %d\n",
1504
+                       cfun->machine->size_for_adjusting_sp);
1505
+       }
1506 124 dgisselq
+}
1507 171 dgisselq
+
1508
+void
1509
+zip_save_registers(rtx basereg_rtx, int sp_offset_to_first_register) {
1510 124 dgisselq
+       rtx     insn;
1511
+       ZIPDEBUGFLAG(dbg, false);
1512 171 dgisselq
+
1513
+       // Compute Frame has already been calculated before coming into here
1514 124 dgisselq
+       //
1515
+       // zip_compute_frame();
1516 171 dgisselq
+       if (dbg)  fprintf(stderr, "PROLOGUE::SAVE-REGISTER\n");
1517
+
1518
+       int offset = 0, regno;
1519
+       for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
1520
+               if (zip_save_reg(regno)) {
1521 124 dgisselq
+                       if (dbg) fprintf(stderr,
1522
+                               "PROLOGUE::SAVE-REGISTER Saving R%d in %d+%d(SP)\n",
1523
+                               regno, sp_offset_to_first_register, offset);
1524
+                       insn=emit_insn(gen_movsi_sto_off(
1525
+                               basereg_rtx,
1526 102 dgisselq
+                               GEN_INT(sp_offset_to_first_register +offset),
1527
+                               gen_rtx_REG(SImode, regno)));
1528
+                       RTX_FRAME_RELATED_P(insn) = 1;
1529 202 dgisselq
+                       offset += 4;
1530 102 dgisselq
+               }
1531 202 dgisselq
+       } if (dbg)  fprintf(stderr, "%d registers saved%s\n", offset,
1532 102 dgisselq
+               (crtl->saves_all_registers)?", should be all of them":", less than all");
1533 202 dgisselq
+
1534
+}
1535
+
1536
+/*
1537
+ * zip_expand_small_prologue()
1538
+ *
1539
+ * To be used when the sp_fp_offset is less then zip_max_opb_offset.
1540
+ *
1541
+ *
1542
+ * Approach:
1543
+ *     SUB size_for_adjusting_sp,SP
1544
+ *     SW REG,0(SP)
1545
+ *     SW REG,4(SP)
1546
+ *     SW REG,8(SP)
1547
+ *     ....
1548
+ *     SW REG,#(SP)
1549
+ *
1550
+ * and if we need a frame register, we'll either do ...
1551
+ *     MOV sp_fp_offset+SP,FP
1552
+ * or if the offset is too large, we'll do ...
1553
+ *     MOV SP,FP
1554
+ *     ADD sp_fp_offset,FP
1555
+ *
1556
+ */
1557
+void
1558
+zip_expand_small_prologue(void) {
1559
+       ZIPDEBUGFLAG(dbg, false);
1560
+       rtx     insn;
1561
+
1562
+       zip_compute_frame();
1563
+
1564
+       if (dbg)  fprintf(stderr, "PROLOGUE:::EXPAND-SMALL-PROLOGUE(SP-FP offset is %d)\n",
1565
+               cfun->machine->sp_fp_offset);
1566
+
1567
+       insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
1568
+                       gen_int_mode(cfun->machine->size_for_adjusting_sp,
1569
+                               SImode)));
1570
+       RTX_FRAME_RELATED_P(insn) = 1;
1571
+
1572
+       zip_save_registers(stack_pointer_rtx, cfun->machine->sp_fp_offset);
1573
+
1574
+       if (cfun->machine->fp_needed) {
1575
+               if (dbg)  fprintf(stderr, "PROLOGUE:::EXPAND-SMALL-PROLOGUE(FP-NEEDED)\n");
1576
+               if (dbg) zip_debug_rtx(stack_pointer_rtx);
1577
+               if (dbg) zip_debug_rtx(frame_pointer_rtx);
1578
+               if (cfun->machine->sp_fp_offset < zip_max_mov_offset) {
1579
+                       if (dbg)  fprintf(stderr,
1580
+                               "PROLOGUE:::EXPAND-SMALL-PROLOGUE() "
1581
+                               "gen_movsi_reg_off(FP, SP, %d), %d < %ld\n",
1582 102 dgisselq
+                               cfun->machine->sp_fp_offset,
1583
+                               cfun->machine->sp_fp_offset,
1584 202 dgisselq
+                               zip_max_mov_offset);
1585
+                       insn = emit_insn(gen_movsi_reg_off(frame_pointer_rtx,
1586
+                               stack_pointer_rtx,
1587
+                               GEN_INT(cfun->machine->sp_fp_offset)));
1588 102 dgisselq
+                       RTX_FRAME_RELATED_P(insn) = 1;
1589
+               } else {
1590 202 dgisselq
+                       rtx     fp_rtx;
1591 102 dgisselq
+
1592 202 dgisselq
+                       fp_rtx = gen_rtx_REG(SImode, zip_FP);
1593 102 dgisselq
+
1594
+                       insn = emit_insn(gen_movsi(fp_rtx, stack_pointer_rtx));
1595 202 dgisselq
+                       RTX_FRAME_RELATED_P(insn) = 1;
1596 102 dgisselq
+
1597
+                       insn = emit_insn(gen_addsi3(fp_rtx, fp_rtx,
1598 202 dgisselq
+                               GEN_INT(cfun->machine->sp_fp_offset)));
1599
+                       RTX_FRAME_RELATED_P(insn) = 1;
1600
+               }
1601
+       }
1602
+}
1603
+
1604
+/*
1605
+ * zip_expand_large_prologue()
1606 124 dgisselq
+ *
1607
+ * The prologue function will be called when the size_for_adjusting_sp is too
1608 202 dgisselq
+ * large to fit into a single OPB-immediate as part of a subtract.
1609
+ *
1610
+ * Approach:
1611
+ *     SUB (size_for_adjusting_sp-sp_fp_offset),SP
1612
+ *     SW R0,(SP)
1613
+ *     SW R5,4(SP)
1614
+ *     SW R6,8SP)
1615
+ *     SW R7,(SP)
1616
+ *     ...
1617
+ *     SW FP,(SP)
1618
+ *
1619
+ *     LDI sp_fp_offset,FP
1620
+ *     SUB FP,SP
1621 102 dgisselq
+ *     ADD SP,FP
1622
+ */
1623
+void
1624 202 dgisselq
+zip_expand_large_prologue(void) {
1625
+       ZIPDEBUGFLAG(dbg, false);
1626
+       rtx     insn, fp_rtx;
1627
+
1628
+       gcc_assert(cfun->machine->fp_needed);
1629
+
1630
+       if (dbg)        fprintf(stderr, "PROLOGUE::expand-large(%d-%d)\n",
1631
+                               cfun->machine->size_for_adjusting_sp,
1632
+                               cfun->machine->sp_fp_offset);
1633
+       insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
1634
+               gen_int_mode(cfun->machine->size_for_adjusting_sp
1635
+                               -cfun->machine->sp_fp_offset, SImode)));
1636
+       RTX_FRAME_RELATED_P(insn) = 1;
1637
+
1638
+       zip_save_registers(stack_pointer_rtx, 0);
1639
+
1640
+       fp_rtx = gen_rtx_REG(SImode, zip_FP);
1641
+
1642
+       insn = emit_insn(gen_movsi(fp_rtx,
1643
+               gen_int_mode(cfun->machine->sp_fp_offset, SImode)));
1644
+       RTX_FRAME_RELATED_P(insn) = 1;
1645
+
1646
+       insn = emit_insn(gen_subsi3(stack_pointer_rtx, stack_pointer_rtx,
1647
+                       fp_rtx));
1648
+       RTX_FRAME_RELATED_P(insn) = 1;
1649
+
1650
+       insn = emit_insn(gen_addsi3(fp_rtx, fp_rtx, stack_pointer_rtx));
1651
+       RTX_FRAME_RELATED_P(insn) = 1;
1652
+}
1653
+
1654
+void
1655
+zip_expand_prologue(void) {
1656
+       ZIPDEBUGFLAG(dbg, false);
1657
+
1658
+       zip_compute_frame();
1659
+
1660
+       if (dbg)  fprintf(stderr, "PROLOGUE: Computing Prologue instructions\n");
1661
+       if (dbg)  fprintf(stderr, "PROLOGUE: SP-FP offset is %d\n",
1662
+                       cfun->machine->sp_fp_offset);
1663
+       if (cfun->machine->size_for_adjusting_sp != 0) {
1664
+               if (cfun->machine->size_for_adjusting_sp <= zip_max_anchor_offset) {
1665
+                       if (dbg)  fprintf(stderr, "PROLOGUE: "
1666
+                                       "%d <= %ld, so going small\n",
1667
+                                       cfun->machine->size_for_adjusting_sp,
1668
+                                       zip_max_opb_imm);
1669
+                       zip_expand_small_prologue();
1670
+               } else {
1671
+                       zip_expand_large_prologue();
1672
+               }
1673
+       }
1674
+}
1675
+
1676
+int
1677
+zip_use_return_insn(void)
1678
+{
1679
+       if ((!reload_completed)||(cfun->machine->fp_needed)
1680
+                       ||(get_frame_size()!=0)) {
1681
+               // If R0 ever gets pushed to the stack, then we cannot
1682
+               // use a master return from anywhere.  We need to clean up the
1683
+               // stack first.
1684
+               if ((!crtl->is_leaf)||((df_regs_ever_live_p(0))
1685
+                                               &&(!call_used_regs[0]))) {
1686
+                       return 0;
1687
+               }
1688
+       }
1689
+       zip_compute_frame();
1690
+       return (cfun->machine->size_for_adjusting_sp == 0)?1:0;
1691
+}
1692
+
1693
+/* As per the notes in M68k.c, quote the function epilogue should not depend
1694
+ * upon the current stack pointer.  It should use the frame pointer only,
1695
+ * if there is a frame pointer.  This is mandatory because of alloca; we also
1696 200 dgisselq
+ * take advantage of it to omit stack adjustments before returning ...
1697 102 dgisselq
+ *
1698
+ * Let's see if we can use their approach here.
1699
+ *
1700
+ * We can't.  Consider our choices:
1701
+ *     LW (FP),R0
1702
+ *     LW 4(FP),R4
1703
+ *     LW 8(FP),R5
1704
+ *     LW 12(FP),R6
1705
+ *     LW 16(FP),FP
1706 200 dgisselq
+ *     ... Then what is the stack pointer?
1707 102 dgisselq
+ * or
1708
+ *     LW (FP),R0
1709
+ *     LW 4(FP),R4
1710 200 dgisselq
+ *     LW 8(FP),R5
1711 102 dgisselq
+ *     LW 12(FP),R6
1712
+ *     MOV FP,SP
1713
+ *     LW 16(SP),FP
1714 202 dgisselq
+ *     ... Which suffers unnecessary pipeline stalls, and certainly doesn't
1715 102 dgisselq
+ *     exploit our pipeline memory function
1716
+ * or
1717
+ *     MOV FP,SP
1718
+ *     LW (SP),R0
1719
+ *     LW 4(SP),R4
1720
+ *     LW 8(SP),R5
1721 202 dgisselq
+ *     LW 12(SP),R6
1722
+ *     LW 16(SP),FP
1723
+ * Which will be our choice.  Note that we do use the stack pointer, eventually.
1724
+ *
1725
+ */
1726 102 dgisselq
+void
1727
+zip_expand_epilogue(void) {
1728 202 dgisselq
+       int     regno, offset;
1729
+       ZIPDEBUGFLAG(dbg, false);
1730
+       rtx     insn;
1731
+
1732 102 dgisselq
+       zip_compute_frame();
1733 202 dgisselq
+
1734 102 dgisselq
+       if (dbg) fprintf(stderr, "EPILOG::\n");
1735
+       if (cfun->machine->fp_needed) {
1736
+               // This is done special--if you can't trust the stack pointer
1737
+               // enough so that you must have a frame pointer, then you can't
1738 202 dgisselq
+               // trust its offset enough to restore from it.  Hence, we start
1739
+               // by moving the frame pointer to the stack pointer to recover
1740
+               // the stack pointer back to a usable value.
1741
+               if (dbg) fprintf(stderr, "EPILOG::Moving frame pointer to stack register\n");
1742
+               insn = emit_insn(gen_movsi_raw(stack_pointer_rtx, frame_pointer_rtx));
1743 102 dgisselq
+               RTX_FRAME_RELATED_P(insn) = 1;
1744
+       }
1745
+
1746
+       if (cfun->machine->saved_reg_size != 0) {
1747
+               if (cfun->machine->fp_needed)
1748
+                       offset = 0;
1749 202 dgisselq
+               else
1750 138 dgisselq
+                       offset = cfun->machine->sp_fp_offset;
1751 102 dgisselq
+               if (dbg) fprintf(stderr, "EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
1752
+               for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
1753
+                       if (zip_save_reg(regno)) {
1754
+                               if (dbg) fprintf(stderr, "EPILOG::RESTORING R%d from SP+%d\n", regno, offset);
1755
+                               rtx reg = gen_rtx_REG(SImode, regno);
1756 124 dgisselq
+                               insn = emit_insn(gen_movsi_lod_off(
1757
+                                               reg,
1758
+                                               stack_pointer_rtx,
1759
+                                               GEN_INT(offset)));
1760
+                               add_reg_note(insn, REG_CFA_RESTORE, reg);
1761 102 dgisselq
+                               RTX_FRAME_RELATED_P(insn) = 1;
1762 202 dgisselq
+                               offset += 4;
1763 138 dgisselq
+                       }
1764 102 dgisselq
+               }
1765
+       }
1766
+
1767 124 dgisselq
+       if (cfun->machine->fp_needed) {
1768
+               // Restore the stack pointer back to the original, the
1769
+               // difference being the difference from the frame pointer
1770
+               // to the original stack
1771 102 dgisselq
+               insn = emit_insn(gen_addsi3(stack_pointer_rtx,
1772
+                       stack_pointer_rtx,
1773
+                       GEN_INT(cfun->machine->size_for_adjusting_sp
1774 202 dgisselq
+                               -cfun->machine->sp_fp_offset)));
1775 138 dgisselq
+               RTX_FRAME_RELATED_P(insn) = 1;
1776
+       } else {
1777
+               // else now the difference is between the stack pointer and
1778 124 dgisselq
+               // the original stack pointer.
1779 202 dgisselq
+               if (dbg) fprintf(stderr, "EPILOG::ADDSI3(StackPtr, %d)\n",
1780 138 dgisselq
+                               cfun->machine->size_for_adjusting_sp);
1781
+               insn = emit_insn(gen_addsi3(stack_pointer_rtx, stack_pointer_rtx,
1782 202 dgisselq
+                       GEN_INT(cfun->machine->size_for_adjusting_sp)));
1783 102 dgisselq
+               RTX_FRAME_RELATED_P(insn) = 1;
1784
+       }
1785
+       if (dbg) fprintf(stderr, "EPILOG::EMITTING-RETURN\n");
1786
+
1787 124 dgisselq
+       // The return RTX is not allowed to be frame related
1788
+       insn = emit_jump_insn(ret_rtx);
1789
+       // RTX_FRAME_RELATED_P(insn) = 1;
1790
+}
1791 202 dgisselq
+
1792 138 dgisselq
+void
1793 124 dgisselq
+zip_sibcall_epilogue(void) {
1794
+       int     regno, offset;
1795 138 dgisselq
+       ZIPDEBUGFLAG(dbg, false);
1796 124 dgisselq
+       rtx     insn;
1797
+
1798
+       zip_compute_frame();
1799 102 dgisselq
+
1800
+       if (dbg) fprintf(stderr, "EPILOG::\n");
1801 202 dgisselq
+       if (cfun->machine->fp_needed) {
1802 124 dgisselq
+               // This is done special--if you can't trust the stack pointer
1803 138 dgisselq
+               // enough so that you must have a frame pointer, then you can't
1804 102 dgisselq
+               // trust its offset enough to restore from it.  Hence, we start
1805
+               // by moving the frame pointer to the stack pointer to recover
1806
+               // the stack pointer back to a usable value.
1807 138 dgisselq
+               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::Moving frame pointer to stack register\n");
1808
+               insn = emit_insn(gen_movsi_raw(stack_pointer_rtx, frame_pointer_rtx));
1809
+               RTX_FRAME_RELATED_P(insn) = 1;
1810 102 dgisselq
+       }
1811
+
1812 191 dgisselq
+       if (cfun->machine->saved_reg_size != 0) {
1813
+               if (cfun->machine->fp_needed)
1814
+                       offset = 0;
1815 202 dgisselq
+               else
1816 191 dgisselq
+                       offset = cfun->machine->sp_fp_offset;
1817
+               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::Saved_REG_Size = %d\n", cfun->machine->saved_reg_size);
1818
+               for(regno=0; regno < FIRST_PSEUDO_REGISTER; regno++) {
1819
+                       if (zip_save_reg(regno)) {
1820
+                               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::RESTORING R%d\n", regno);
1821
+                               rtx reg = gen_rtx_REG(SImode, regno);
1822
+                               insn = emit_insn(gen_movsi_lod_off(
1823
+                                               reg,
1824
+                                               stack_pointer_rtx,
1825
+                                               GEN_INT(offset)));
1826
+                               add_reg_note(insn, REG_CFA_RESTORE, reg);
1827
+                               RTX_FRAME_RELATED_P(insn) = 1;
1828 202 dgisselq
+                               offset += 4;
1829 191 dgisselq
+                       }
1830
+               }
1831
+       }
1832
+
1833
+       if (cfun->machine->fp_needed) {
1834
+               // Restore the stack pointer back to the original, the
1835
+               // difference being the difference from the frame pointer
1836
+               // to the original stack
1837
+               insn = emit_insn(gen_addsi3(stack_pointer_rtx, stack_pointer_rtx,
1838
+                       GEN_INT(cfun->machine->size_for_adjusting_sp
1839
+                               -cfun->machine->sp_fp_offset)));
1840
+               RTX_FRAME_RELATED_P(insn) = 1;
1841
+       } else {
1842
+               // else now the difference is between the stack pointer and
1843
+               // the original stack pointer.
1844
+               if (dbg) fprintf(stderr, "SIBCALL-EPILOG::ADDSI3(StackPtr, %d)\n",
1845 202 dgisselq
+                               cfun->machine->size_for_adjusting_sp);
1846 191 dgisselq
+               insn = emit_insn(gen_addsi3(stack_pointer_rtx,stack_pointer_rtx,
1847
+                       GEN_INT(cfun->machine->size_for_adjusting_sp)));
1848 202 dgisselq
+               RTX_FRAME_RELATED_P(insn) = 1;
1849 191 dgisselq
+       }
1850
+}
1851
+
1852
+rtx
1853
+zip_return_addr_rtx(int count, rtx frame ATTRIBUTE_UNUSED)
1854
+{
1855
+       //
1856
+       // Don't try to compute anything other than frame zero.
1857 202 dgisselq
+       //
1858 191 dgisselq
+       if (count != 0)
1859
+               return NULL_RTX;
1860
+
1861
+       // Make sure we've computed our frame, do we need to save registers?
1862
+       zip_compute_frame();
1863
+
1864
+       if (zip_save_reg(zip_LR)) {
1865
+               if (cfun->machine->fp_needed)
1866 202 dgisselq
+                       return gen_rtx_MEM(SImode, frame_pointer_rtx);
1867 191 dgisselq
+               else
1868
+                       return gen_rtx_MEM(SImode, gen_rtx_PLUS(Pmode,
1869
+                                       stack_pointer_rtx,
1870
+                                       GEN_INT(cfun->machine->sp_fp_offset)));
1871
+       } else {
1872 202 dgisselq
+               return gen_rtx_REG(Pmode, zip_LR);
1873
+
1874
+       }
1875
+}
1876
+
1877
+/* Implement RETURN_ADDR_RTX(COUNT, FRAMEADDR).
1878
+ *
1879
+ * We currently only support calculating the return address for the current
1880
+ * frame.
1881
+ */
1882
+
1883
+/*
1884
+rtx
1885
+zip_return_addr_rtx(int count, rtx frame ATTRIBUTE_UNUSED)
1886
+{
1887
+       if (count)
1888
+               return NULL_RTX;
1889
+
1890
+       zip_compute_frame();
1891
+
1892
+       // saved return address for current function is at fp - 1
1893
+       if (cfun->machine->save_ret)
1894
+               return gen_rtx_MEM(Pmode, plus_constant(frame_pointer_rtx,
1895
+                               -UNITS_PER_WORD));
1896
+       return get_hard_reg_initial_val(Pmode, RETURN_ADDRESS_REGNUM);
1897 102 dgisselq
+}
1898
+*/
1899
+
1900
+/* Implements the macro INITIAL_ELIMINATION_OFFSET,
1901
+ * return the OFFSET.
1902
+ */
1903
+int
1904
+zip_initial_elimination_offset(int from, int to) {
1905
+       int     ret = 0;
1906
+       zip_compute_frame();
1907
+
1908
+/*
1909
+       if (((from) == FRAME_POINTER_REGNUM)&&((to) == STACK_POINTER_REGNUM)) {
1910
+               ret = cfun->machine->sp_fp_offset;
1911
+       } else if (((from)=ARG_POINTER_REGNUM)&&((to)==STACK_POINTER_REGNUM)) {
1912
+               // Since the ARG_POINTER_REGNUM is defined to be identical
1913
+               // to the FRAME_POINTER_REGNUM, this "if" will never ever
1914
+               // get called.
1915
+               ret = cfun->machine->sp_fp_offset;
1916
+       } else if (((from)=ARG_POINTER_REGNUM)&&((to)==FRAME_POINTER_REGNUM)) {
1917
+               // Since we define ARG_POINTER_REGNUM to be FRAME_POINTER_REGNUM
1918
+               // we're asked for the offset between the frame pointer and
1919
+               // itself.  The result had better be zero.
1920
+               //
1921
+               ret = 0;
1922
+       } else {
1923
+               abort();
1924
+       }
1925
+*/
1926
+
1927
+       // Let's try using an ARG_POINTER != FRAME_POINTER
1928 171 dgisselq
+       if (((from) == FRAME_POINTER_REGNUM)&&((to) == STACK_POINTER_REGNUM)) {
1929 102 dgisselq
+               ret = cfun->machine->sp_fp_offset;
1930
+       } else if (((from)=ARG_POINTER_REGNUM)&&((to)==STACK_POINTER_REGNUM)) {
1931 117 dgisselq
+               // Since the ARG_POINTER_REGNUM is defined to be identical
1932 171 dgisselq
+               // to the FRAME_POINTER_REGNUM, this "if" will never ever
1933
+               // get called.
1934
+               ret = cfun->machine->size_for_adjusting_sp;
1935 117 dgisselq
+       } else if (((from)=ARG_POINTER_REGNUM)&&((to)==FRAME_POINTER_REGNUM)) {
1936 102 dgisselq
+               ret = cfun->machine->size_for_adjusting_sp
1937 171 dgisselq
+                       - cfun->machine->sp_fp_offset;
1938
+       } else {
1939
+               abort();
1940
+       }
1941 117 dgisselq
+
1942 102 dgisselq
+       return ret;
1943
+}
1944
+
1945 171 dgisselq
+/*
1946 102 dgisselq
+ * Code taken from m68k ...
1947 171 dgisselq
+ */
1948
+static bool
1949
+zip_can_eliminate(int from, int to)
1950
+{
1951
+       // fprintf(stderr, "CAN_ELIMINATE::QUERYING(%d,%d)\n", from, to);
1952
+       if ((from == zip_FP)&&(to == zip_SP))
1953
+               return !cfun->machine->fp_needed;
1954
+       return true;
1955
+}
1956
+
1957
+/* Compute the number of word sized registers needed to hold a function
1958
+ * argument of mode INT_MODE and tree type TYPE.
1959
+ */
1960
+int
1961
+zip_num_arg_regs(enum machine_mode mode, const_tree type) {
1962 102 dgisselq
+       int     size;
1963
+
1964
+       if (targetm.calls.must_pass_in_stack(mode, type))
1965
+               return 0;
1966
+
1967
+       if ((type)&&(mode == BLKmode))
1968
+               size = int_size_in_bytes(type);
1969
+       else
1970
+               size = GET_MODE_SIZE(mode);
1971
+
1972
+       return (size + UNITS_PER_WORD - 1)/UNITS_PER_WORD;
1973
+}
1974
+
1975
+static void
1976
+zip_function_arg_advance(cumulative_args_t ca, machine_mode mode,
1977 171 dgisselq
+               const_tree type, bool named ATTRIBUTE_UNUSED) {
1978 102 dgisselq
+       CUMULATIVE_ARGS *cum;
1979
+       int     nreg;
1980
+
1981
+       cum = get_cumulative_args(ca);
1982
+       nreg = zip_num_arg_regs(mode, type);
1983
+       if (((*cum)+nreg) > NUM_ARG_REGS)
1984
+               (*cum) = NUM_ARG_REGS;
1985
+       else
1986
+               (*cum) += nreg;
1987
+}
1988
+
1989
+static rtx
1990
+zip_function_arg(cumulative_args_t ca, machine_mode mode,
1991
+               const_tree type ATTRIBUTE_UNUSED, bool named) {
1992
+       CUMULATIVE_ARGS *cum;
1993
+
1994
+       if (!named)
1995
+               return NULL_RTX;
1996
+       cum = get_cumulative_args(ca);
1997
+
1998
+       if ((*cum) >= NUM_ARG_REGS)
1999
+               return NULL_RTX;
2000
+       return
2001
+               gen_rtx_REG(mode, (*cum)+1);
2002
+}
2003
+
2004
+/* DECL is the declaration of the function being targeted by the call, and EXP
2005
+ * is the CALL_EXPR representing the call.
2006
+ */
2007
+bool   zip_function_ok_for_sibcall(ATTRIBUTE_UNUSED tree decl, tree exp) {
2008
+       // calls.c already checks whether or not the parameter stack space
2009
+       // is identical, so ... let's hope this all works and find out.
2010
+
2011
+       //
2012
+       // Actually, this will fail:  If the sibling uses R5 to pass registers
2013
+       // in and we don't, then there will be no way to restore R5.  This is
2014
+       // true for the current configuration.  It will be true for future
2015
+       // configurations if the sibling ever uses a register that must be
2016
+       // saved as a parameter register.
2017
+       //
2018
+       // We can check this ... if we can count how many registers the
2019
+       // sibling call will use.
2020
+       //
2021
+       CUMULATIVE_ARGS cum_v;
2022
+       cumulative_args_t       cum;
2023
+       tree            parameter;
2024 191 dgisselq
+       machine_mode    mode;
2025
+       tree            ttype;
2026
+       rtx             parm_rtx;
2027
+       int             i;
2028
+       static const char zip_call_used_register[] = CALL_USED_REGISTERS;
2029
+
2030
+       INIT_CUMULATIVE_ARGS(cum_v, NULL, NULL, 0,0);
2031
+       cum = pack_cumulative_args(&cum_v);
2032
+       for (i=0; i<call_expr_nargs(exp); i++) {
2033
+
2034
+               parameter = CALL_EXPR_ARG(exp, i);
2035
+
2036
+               if ((!parameter) || (TREE_CODE(parameter)==ERROR_MARK))
2037
+                       return true;
2038
+               ttype = TREE_TYPE(parameter);
2039
+               gcc_assert(ttype);
2040
+               mode = ttype->type_common.mode;
2041
+
2042
+               if (pass_by_reference(&cum_v, mode, ttype, true)) {
2043
+                       mode = Pmode;
2044
+                       ttype = build_pointer_type(ttype);
2045
+               }
2046
+
2047
+               parm_rtx = zip_function_arg(cum, mode, ttype, 0);
2048
+               zip_function_arg_advance(cum, mode, ttype, 0);
2049
+               if (!parm_rtx)
2050
+                       continue;
2051
+
2052
+               // If it is a register
2053
+               //      and it is *NOT* a CALL_USED_REGISTER
2054
+               //      then we can't do this.
2055
+               //
2056
+               // Example: func(R1,..R4,R5)
2057
+               //      can be followed by func2(R1,.., up to R5)
2058
+               //      (not supported, though... just to simplify our test
2059
+               //      below)
2060
+               // Example: func(R1,..R4)
2061
+               //      cannot be followed by func2(R1,..,R5)
2062
+               //      We would blow R5 away by our prologue, even if it was
2063
+               //      properly set.
2064
+               // Example: func(R1,..R5)
2065
+               //      can be followed by func2(R1,.., up to R4)
2066
+               //      func2 may save R5 (which doesn't need saving) but that's
2067
+               //              irrelevant
2068
+               // Example: func(R1,..up to R4)
2069
+               //      can be followed by func2(R1,.., up to R4)
2070
+               //
2071
+               if (REG_P(parm_rtx)&&(REGNO(parm_rtx))
2072
+                               &&(REGNO(parm_rtx)<sizeof(zip_call_used_register))
2073
+                               &&(!zip_call_used_register[REGNO(parm_rtx)]))
2074
+                       return false;
2075
+       }
2076
+
2077
+       return true;
2078
+
2079
+       // We also need to check if the return types are the same ... or
2080
+       // will GCC handle that for us?
2081
+}
2082
+
2083
+void   zip_canonicalize_comparison(int *code, rtx *op0, rtx *op1,
2084
+               bool preserve_op0)
2085
+{
2086
+       ZIPDEBUGFLAG(dbg, false);
2087
+       bool    reverse = false;
2088
+
2089
+       if (dbg) fprintf(stderr, "CANONICALIZE ...%s\n", (preserve_op0)?"(Preserve Op0)":"");
2090
+       if (dbg) zip_debug_rtx_pfx("CODE", gen_rtx_fmt_ee((rtx_code)*code, VOIDmode, gen_rtx_REG(CCmode,zip_CC), const0_rtx));
2091
+       if (dbg) zip_debug_rtx_pfx("OP0 ", *op0);
2092
+       if (dbg) zip_debug_rtx_pfx("OP1 ", *op1);
2093
+
2094
+       // Z    ->      Z
2095
+       // NZ   ->      !Z
2096
+       // LT   ->      N
2097
+       // GE   ->      !N
2098
+       // LTU  ->      C
2099
+       // GEU  ->      !C
2100
+       //
2101
+       // LTE  ->      GTE w/ swapped operands
2102
+       // GT   ->      LT  w/ swapped operands
2103 122 dgisselq
+       // GTU  ->      LTU w/ swapped operands
2104
+       // LEU  ->      GEU w/ swapped operands
2105
+       //
2106 202 dgisselq
+
2107
+       if ((CONST_INT_P(*op0))||(GET_CODE(*op0) == PLUS)) {
2108 102 dgisselq
+               rtx     tmp = *op0;
2109 122 dgisselq
+               *op0 = *op1;
2110
+               *op1 = tmp;
2111
+               *code = (int)swap_condition((enum rtx_code)*code);
2112
+       }
2113
+
2114 202 dgisselq
+       if (*code == GTU) {
2115
+               if (REG_P(*op1)) {
2116
+                       //; Reverse the comparison
2117
+                       reverse = true;
2118
+               } else if (CONST_INT_P(*op1)) {
2119
+                       //; A >  B
2120
+                       //; A >= B+1
2121
+                       //; Add one to the integer constant,
2122
+                       //; And use a GEU comparison
2123
+                       *code = GEU;
2124
+                       *op1 = GEN_INT(INTVAL(*op1)+1);
2125
+               } else {
2126
+                       //; Reverse the comparison
2127
+                       reverse = true;
2128
+               }
2129 122 dgisselq
+       } else if (*code == LEU) {
2130 202 dgisselq
+               if (REG_P(*op1)) {
2131 122 dgisselq
+                       reverse = true;
2132
+               } else if (CONST_INT_P(*op1)) {
2133
+                       //; A <= B
2134 202 dgisselq
+                       //; A <  B+1
2135
+                       //; Add one to the integer constant,
2136
+                       //; And use a GTU comparison
2137
+                       *op1 = GEN_INT(INTVAL(*op1)+1);
2138
+                       *code = LTU;
2139
+               } else {
2140
+                       reverse = true;
2141
+               }
2142
+       } else if (*code == LE) {
2143
+               if (REG_P(*op1)) {
2144
+                       reverse = true;
2145
+               } else if (CONST_INT_P(*op1)) {
2146
+                       //; A <  B
2147
+                       //; A <= B-1
2148 122 dgisselq
+                       //; Add one to the integer constant,
2149 202 dgisselq
+                       //; And use a GTU comparison
2150
+                       *op1 = GEN_INT(INTVAL(*op1)-1);
2151
+                       *code = LT;
2152
+               } else {
2153
+                       reverse = true;
2154
+               }
2155
+       } else if (*code == GT) {
2156
+               if (REG_P(*op1)) {
2157
+                       //; Reverse the comparison
2158
+                       reverse = true;
2159
+               } else if (CONST_INT_P(*op1)) {
2160
+                       //; A >  B
2161
+                       //; A >= B+1
2162
+                       //; Add one to the integer constant,
2163
+                       //; And use a GTU comparison
2164
+                       *op1 = GEN_INT(INTVAL(*op1)+1);
2165
+                       *code = GE;
2166
+               } else {
2167
+                       reverse = true;
2168
+               }
2169
+       }
2170
+
2171
+       if (reverse) {
2172
+               rtx tem = *op0;
2173
+               *op0 = *op1;
2174
+               *op1 = tem;
2175
+               *code = (int)swap_condition((enum rtx_code)*code);
2176
+       }
2177
+}
2178
+
2179
+static bool
2180
+zip_fixed_condition_code_regs(unsigned int *a, unsigned int *b) {
2181
+       *a = zip_CC;
2182
+       *b = INVALID_REGNUM;
2183
+       return true;
2184
+}
2185
+
2186
+
2187
+/* totally buggy - we can't return pointers to nested functions */
2188
+static void
2189 122 dgisselq
+zip_asm_trampoline_template(FILE *f)
2190 202 dgisselq
+{
2191
+       fprintf(f, "\tbrev\t0,r1\n");
2192
+       fprintf(f, "\tldilo\t0,r1\n");
2193
+       fprintf(f, "\tjmp r1\n");
2194
+}
2195
+
2196
+/* Worker function for TARGET_TRAMPOLINE_INIT. */
2197 122 dgisselq
+static void
2198
+zip_trampoline_init(rtx m_tramp ATTRIBUTE_UNUSED,
2199
+       tree fndecl ATTRIBUTE_UNUSED,
2200
+       rtx chain_value ATTRIBUTE_UNUSED) {
2201
+// #warning "This needs to be filled out"
2202
+       abort();
2203
+}
2204
+
2205
+static tree
2206
+def_builtin(const char *name, enum insn_code icode, enum ZIP_BUILTIN_ID_CODE code,
2207 102 dgisselq
+       tree type)
2208
+{
2209 202 dgisselq
+       tree t = add_builtin_function(name,type,code, BUILT_IN_MD, NULL, NULL_TREE);
2210
+
2211 138 dgisselq
+       if(t) {
2212
+               zip_builtins[code] = t;
2213 102 dgisselq
+               zip_builtins_icode[code] = icode;
2214
+       }
2215
+
2216
+       return t;
2217
+
2218
+}
2219
+
2220
+void   zip_init_builtins(void) {
2221
+
2222
+  tree void_ftype_void = build_function_type_list(void_type_node, NULL_TREE);
2223
+#ifdef HAVE_zip_rtu
2224
+  def_builtin("zip_rtu", CODE_FOR_zip_rtu, ZIP_BUILTIN_RTU, void_ftype_void);
2225
+#endif
2226
+#ifdef HAVE_zip_halt
2227
+  def_builtin("zip_halt",  CODE_FOR_zip_halt,  ZIP_BUILTIN_HALT, void_ftype_void);
2228
+#endif
2229 202 dgisselq
+#ifdef HAVE_zip_busy
2230 102 dgisselq
+  def_builtin("zip_busy",  CODE_FOR_zip_busy,  ZIP_BUILTIN_BUSY, void_ftype_void);
2231
+#endif
2232
+#ifdef HAVE_zip_idle
2233
+  def_builtin("zip_idle", CODE_FOR_zip_idle, ZIP_BUILTIN_IDLE, void_ftype_void);
2234
+#endif
2235
+
2236
+#ifdef HAVE_zip_syscall
2237
+// Support int SYSCALL(callID, int a, int b, int c);
2238
+  def_builtin("zip_syscall", CODE_FOR_zip_syscall, ZIP_BUILTIN_SYSCALL,
2239
+                       build_function_type_list(void_type_node, NULL_TREE));
2240
+#endif
2241
+
2242
+#ifdef HAVE_zip_save_context
2243
+  def_builtin("zip_save_context", CODE_FOR_zip_save_context, ZIP_BUILTIN_SAVE_CONTEXT,
2244
+               build_function_type_list(void_type_node, ptr_type_node, 0));
2245
+#endif
2246
+
2247
+#ifdef HAVE_zip_restore_context
2248
+  def_builtin("zip_restore_context", CODE_FOR_zip_restore_context, ZIP_BUILTIN_RESTORE_CONTEXT,
2249 171 dgisselq
+       build_function_type_list(void_type_node, ptr_type_node, 0));
2250
+#endif
2251
+
2252 102 dgisselq
+#ifdef HAVE_zip_bitrev
2253
+  def_builtin("zip_bitrev", CODE_FOR_zip_bitrev, ZIP_BUILTIN_BITREV,
2254
+       build_function_type_list(unsigned_type_node, unsigned_type_node,
2255
+               NULL_TREE));
2256
+#endif
2257
+
2258
+#ifdef HAVE_zip_cc
2259
+  def_builtin("zip_cc", CODE_FOR_zip_cc, ZIP_BUILTIN_CC,
2260
+       build_function_type_list(unsigned_type_node, NULL_TREE));
2261
+#endif
2262
+
2263
+#ifdef HAVE_zip_ucc
2264
+  def_builtin("zip_ucc", CODE_FOR_zip_ucc, ZIP_BUILTIN_UCC,
2265
+       build_function_type_list(unsigned_type_node, NULL_TREE));
2266
+#endif
2267
+
2268
+}
2269
+
2270
+static tree
2271
+zip_builtin_decl(unsigned zip_builtin_code, bool initialize_p ATTRIBUTE_UNUSED)
2272
+{
2273
+  if (zip_builtin_code >= ZIP_BUILTIN_MAX)
2274
+    return error_mark_node;
2275
+
2276
+  return zip_builtins[zip_builtin_code];
2277
+}
2278
+
2279
+static rtx
2280
+zip_expand_builtin(tree exp, rtx target,
2281
+               rtx subtarget ATTRIBUTE_UNUSED,
2282
+               machine_mode tmode ATTRIBUTE_UNUSED,
2283 117 dgisselq
+               int     ignore ATTRIBUTE_UNUSED)
2284
+{
2285
+       tree    fndecl = TREE_OPERAND(CALL_EXPR_FN(exp), 0);
2286
+       bool    nonvoid = (TREE_TYPE(TREE_TYPE(fndecl)) != void_type_node);
2287
+       enum    ZIP_BUILTIN_ID_CODE code=(enum ZIP_BUILTIN_ID_CODE)DECL_FUNCTION_CODE(fndecl);
2288 102 dgisselq
+       enum    insn_code icode = zip_builtins_icode[code];
2289
+       rtx     pat, op[5];
2290
+       call_expr_arg_iterator  iter;
2291
+       tree    arg;
2292
+
2293
+       if ((code == ZIP_BUILTIN_SAVE_CONTEXT)
2294
+                       ||(code == ZIP_BUILTIN_RESTORE_CONTEXT)) {
2295
+               arg = first_call_expr_arg(exp, &iter);
2296
+               if (arg == error_mark_node)
2297
+                       return NULL_RTX;
2298
+               op[0] = expand_normal(arg);
2299
+               if (GET_CODE(op[0]) != REG)
2300
+                       op[0] = force_reg(Pmode, op[0]);
2301
+               pat = GEN_FCN(icode)(op[0]);
2302
+       } else if (code == ZIP_BUILTIN_BITREV) {
2303 202 dgisselq
+               arg = first_call_expr_arg(exp, &iter);
2304
+               if (arg == error_mark_node) {
2305 102 dgisselq
+                       return NULL_RTX;
2306
+               }
2307
+               op[0] = expand_normal(arg);
2308
+               if (!target)
2309
+                       target = gen_reg_rtx(SImode);
2310
+               pat = GEN_FCN(icode)(target, op[0]);
2311
+       } else if ((code == ZIP_BUILTIN_CC)||(code == ZIP_BUILTIN_UCC)) {
2312
+               if (!target)
2313
+                       target = gen_reg_rtx(SImode);
2314
+               pat = GEN_FCN(icode)(target);
2315
+       } else // RTU, HALT, IDLE
2316
+               pat = GEN_FCN(icode)();
2317
+       if (!pat)
2318
+               return NULL_RTX;
2319
+       emit_insn(pat);
2320
+       return (nonvoid ? target : const0_rtx);
2321
+}
2322
+
2323
+static bool
2324
+zip_scalar_mode_supported_p(enum machine_mode mode)
2325
+{
2326
+       if ((ZIP_HAS_DI)&&(mode == DImode))
2327
+               return true;
2328
+       if ((mode==SImode)||(mode==HImode)||(mode==QImode))
2329
+               return true;
2330
+       if (mode==SFmode)       // &&(ZIP_FPU)
2331 117 dgisselq
+               return true;    // If (!ZIP_CPU), will need to be emulated
2332 102 dgisselq
+       if (mode==DFmode)       // Must always be emulated
2333
+               return true;
2334
+       return false;
2335
+}
2336
+
2337
+static bool
2338
+zip_libgcc_floating_mode_supported_p(enum machine_mode mode)
2339
+{
2340
+       return ((mode)==SFmode)||((mode)==DFmode);
2341
+}
2342
+
2343
+static int
2344 202 dgisselq
+zip_address_cost(rtx addr ATTRIBUTE_UNUSED,
2345
+       enum machine_mode mode ATTRIBUTE_UNUSED,
2346
+       addr_space_t as ATTRIBUTE_UNUSED, bool spd ATTRIBUTE_UNUSED) {
2347
+       return 1;
2348
+}
2349
+
2350
+static bool
2351
+zip_mode_dependent_address_p(const_rtx addr ATTRIBUTE_UNUSED,
2352
+       addr_space_t as ATTRIBUTE_UNUSED) {
2353
+       return false;
2354
+}
2355 102 dgisselq
+
2356
+static void
2357
+zip_debug_print(const char *pfx, int lvl, const char *str) {
2358 202 dgisselq
+       int     i;
2359
+       i = lvl;
2360 102 dgisselq
+       if ((true)||(lvl == 0))
2361
+               fprintf(stderr, "%s", pfx);
2362
+       else
2363
+               i += strlen(pfx);
2364
+       while(i-->0)
2365
+               fprintf(stderr, "  ");
2366
+       fprintf(stderr, "%s\n", str);
2367
+}
2368
+
2369
+static void
2370
+zip_debug_print_m(const char *pfx, int lvl, const char *str, enum machine_mode m) {
2371
+       int     i;
2372
+
2373
+       i = lvl;
2374
+       if ((true)||(lvl == 0))
2375
+               fprintf(stderr, "%s", pfx);
2376
+       else
2377
+               i = lvl+strlen(pfx);
2378
+       while(i-->0)
2379
+               fprintf(stderr, "  ");
2380
+       switch(m) {
2381
+               case VOIDmode:
2382
+                       fprintf(stderr, "%s:V\n", str);
2383
+                       break;
2384
+               case BLKmode:
2385
+                       fprintf(stderr, "%s:BLK\n", str);
2386
+                       break;
2387
+               case BImode:
2388
+                       fprintf(stderr, "%s:BI\n", str);
2389
+                       break;
2390
+               case QImode:
2391
+                       fprintf(stderr, "%s:QI\n", str);
2392
+                       break;
2393
+               case HImode:
2394
+                       fprintf(stderr, "%s:HI\n", str);
2395
+                       break;
2396
+#ifdef HAVE_SImode
2397
+               case SImode:
2398
+                       fprintf(stderr, "%s:SI\n", str);
2399
+                       break;
2400
+#endif
2401
+#ifdef HAVE_DImode
2402
+               case DImode:
2403
+                       fprintf(stderr, "%s:DI\n", str);
2404
+                       break;
2405
+#endif
2406
+               case CCmode:
2407
+                       fprintf(stderr, "%s:CC\n", str);
2408
+                       break;
2409
+               default:
2410
+                       fprintf(stderr, "%s:?\n", str);
2411
+       }
2412
+}
2413
+
2414
+static void
2415
+zip_debug_rtx_1(const char *pfx, const_rtx x, int lvl) {
2416 202 dgisselq
+       if (x == NULL_RTX) {
2417 102 dgisselq
+               zip_debug_print(pfx, lvl, "(NULL-RTX)");
2418
+               return;
2419
+       } else if (GET_CODE(x) > NUM_RTX_CODE) {
2420 202 dgisselq
+               char    buf[64];
2421
+               sprintf(buf, "(BAD-RTX-CODE %d)", GET_CODE(x));
2422
+               zip_debug_print(pfx, lvl, buf);
2423
+               gcc_assert(0 && "Bad RTX Code");
2424
+               return;
2425
+       } switch(GET_CODE(x)) { // rtl.def
2426 122 dgisselq
+       case PARALLEL:
2427
+               zip_debug_print(pfx, lvl, "(PARALLEL");
2428
+               if (XVEC(x,0) != NULL)
2429 102 dgisselq
+                       for(int j=0; j<XVECLEN(x,0);j++)
2430
+                               zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
2431
+               zip_debug_print(pfx, lvl, ")");
2432
+               debug_rtx(x);
2433
+               break;
2434
+       case INT_LIST: zip_debug_print(pfx, lvl, "(INT-LIST"); break;
2435
+       case SEQUENCE:
2436
+               zip_debug_print(pfx, lvl, "(SEQUENCE");
2437
+               for(int j=0; j<XVECLEN(x,0);j++)
2438
+                       zip_debug_rtx_1(pfx, XVECEXP(x,0,j), lvl+1);
2439
+               zip_debug_print(pfx, lvl, ")");
2440
+               debug_rtx(x);
2441
+               break;
2442
+       case ADDRESS: zip_debug_print(pfx, lvl, "(ADDRESS"); break;
2443 117 dgisselq
+       case DEBUG_INSN: zip_debug_print(pfx, lvl, "(DEBUG-INSN"); break;
2444 102 dgisselq
+       case INSN:
2445
+               zip_debug_print(pfx, lvl, "(INSN");
2446 122 dgisselq
+               /*
2447
+               { const rtx_insn *tmp_rtx;
2448 202 dgisselq
+               for(tmp_rtx = as_a <const rtx_insn *>(x); tmp_rtx != 0; tmp_rtx = NEXT_INSN(tmp_rtx)) {
2449
+                       zip_debug_rtx_1(tmp_rtx, lvl+1);
2450
+               }}
2451 122 dgisselq
+               */
2452
+               zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
2453
+               zip_debug_print(pfx, lvl, ")");
2454 102 dgisselq
+               debug_rtx(x);
2455 122 dgisselq
+               break;
2456
+       case JUMP_INSN: zip_debug_print(pfx, lvl, "(JUMP-INSN");
2457
+               zip_debug_rtx_1(pfx, PATTERN(x), lvl+1);
2458
+               zip_debug_print(pfx, lvl, ")");
2459
+               /*
2460
+               if (JUMP_LABEL(x)) {
2461
+                       if (GET_CODE(JUMP_LABEL(x)) == LABEL_REF) {
2462 102 dgisselq
+                               char    buf[64];
2463
+                               sprintf(buf, "(LABEL *.L%d))", CODE_LABEL_NUMBER(LABEL_REF_LABEL(JUMP_LABEL(x))));
2464
+                               zip_debug_print(pfx, lvl+1, buf);
2465
+                       } else if (GET_CODE(JUMP_LABEL(x))==CODE_LABEL) {
2466
+                               char    buf[64];
2467
+                               sprintf(buf, "(CODE_LABEL *.L%d))", CODE_LABEL_NUMBER(JUMP_LABEL(x)));
2468
+                               zip_debug_print(pfx, lvl+1, buf);
2469
+                       } else
2470
+                       zip_debug_print(pfx, lvl+1, "(w/Label))");
2471
+               } else
2472
+                       zip_debug_print(pfx, lvl+1, "(NO label))");
2473
+               debug_rtx(x);
2474 117 dgisselq
+               */
2475 102 dgisselq
+               break;
2476
+       case CALL:
2477 111 dgisselq
+               zip_debug_print(pfx, lvl, "(CALL (Adr) (Args)");
2478
+               zip_debug_rtx_1(pfx, XEXP(x,0), lvl+1);
2479
+               zip_debug_rtx_1(pfx, XEXP(x,1), lvl+1);
2480 102 dgisselq
+               zip_debug_print(pfx, lvl, ")");
2481 111 dgisselq
+               break;
2482
+       case CALL_INSN: zip_debug_print(pfx, lvl, "(CALL-INSN");
2483
+               debug_rtx(x);
2484
+               break;
2485
+       case BARRIER: zip_debug_print(pfx, lvl, "(BARRIER)"); break;
2486
+       case RETURN: zip_debug_print(pfx, lvl, "(RETURN)"); break;
2487
+       case NOTE:
2488
+               {       char buf[128];
2489
+                       sprintf(buf, "(NOTE %s)", GET_REG_NOTE_NAME(GET_MODE(x)));
2490
+                       zip_debug_print(pfx, lvl, buf);
2491 102 dgisselq
+               }break;
2492 111 dgisselq
+       case COND_EXEC: zip_debug_print(pfx, lvl, "(COND_EXEC)");
2493
+               debug_rtx(x);
2494
+               break;
2495 102 dgisselq
+       case ASM_INPUT: zip_debug_print(pfx, lvl, "(ASM INPUT)"); break;
2496
+       case ASM_OPERANDS: zip_debug_print(pfx, lvl, "(ASM OPERANDS)"); break;
2497
+       case UNSPEC: zip_debug_print(pfx, lvl, "(UNSPEC)"); break;
2498
+       case UNSPEC_VOLATILE: zip_debug_print(pfx, lvl, "(UNSPEC_VOLATILE)"); break;
2499
+       case CODE_LABEL:
2500
+               {
2501
+                       char    buf[128];
2502
+                       sprintf(buf, "(CODE_LABEL *.L%d)", CODE_LABEL_NUMBER(x));
2503
+                       zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
2504
+               } break;
2505
+       case SET:
2506
+               zip_debug_print_m(pfx, lvl, "(SET", GET_MODE(x));
2507
+               zip_debug_rtx_1(pfx, SET_DEST(x),lvl+1);
2508
+               zip_debug_rtx_1(pfx, SET_SRC(x),lvl+1);
2509
+               zip_debug_print(pfx, lvl, ")");
2510
+               debug_rtx(x);
2511
+               break;
2512
+       case REG: {
2513
+               char buf[25], mstr[4];
2514
+               mstr[0] = '\0';
2515
+               if (GET_MODE(x) == QImode)
2516
+                       strcpy(mstr, ":QI");
2517
+               else if (GET_MODE(x) == HImode)
2518
+                       strcpy(mstr, ":HI");
2519
+               else if (GET_MODE(x) == VOIDmode)
2520
+                       strcpy(mstr, ":V");
2521 192 dgisselq
+               if (REGNO(x) == zip_PC)
2522 111 dgisselq
+                       sprintf(buf, "(PC%s)", mstr);
2523 102 dgisselq
+               else if (REGNO(x) == zip_CC)
2524
+                       sprintf(buf, "(CC%s)", mstr);
2525
+               else if (REGNO(x) == zip_SP)
2526
+                       sprintf(buf, "(SP%s)", mstr);
2527 117 dgisselq
+               else if (REGNO(x) == zip_FP)
2528
+                       sprintf(buf, "(REG%s FP)", mstr);
2529 102 dgisselq
+               else if (REGNO(x) == zip_GOT)
2530 117 dgisselq
+                       sprintf(buf, "(REG%s GBL)", mstr);
2531 102 dgisselq
+               else if (FUNCTION_VALUE_REGNO_P(REGNO(x)))
2532 122 dgisselq
+                       sprintf(buf, "(REG%s RTN-VL)", mstr);
2533 127 dgisselq
+               else if (REGNO(x) == RETURN_ADDRESS_REGNUM)
2534
+                       sprintf(buf, "(REG%s RTN-AD)", mstr);
2535 202 dgisselq
+               else
2536
+                       sprintf(buf, "(REG%s %d)", mstr, REGNO(x));
2537
+               if (mstr[0])
2538
+                       zip_debug_print(pfx, lvl, buf);
2539 127 dgisselq
+               else
2540
+                       zip_debug_print_m(pfx, lvl, buf, GET_MODE(x));
2541 102 dgisselq
+               } break;
2542 127 dgisselq
+       case IF_THEN_ELSE: // 51
2543 102 dgisselq
+               zip_debug_print(pfx, lvl, "(IF-THEN-ELSE");
2544 127 dgisselq
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2545 102 dgisselq
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2546 127 dgisselq
+               zip_debug_rtx_1(pfx, XEXP(x,2),lvl+1);
2547 102 dgisselq
+               zip_debug_print(pfx, lvl, ")");
2548 127 dgisselq
+               break;
2549 102 dgisselq
+       case PC:
2550 127 dgisselq
+               zip_debug_print(pfx, lvl, "(PC)");
2551 102 dgisselq
+               break;
2552 127 dgisselq
+       case CC0:
2553 102 dgisselq
+               zip_debug_print(pfx, lvl, "(CC0)");
2554 127 dgisselq
+               break;
2555 122 dgisselq
+       case COMPARE:
2556 127 dgisselq
+               zip_debug_print_m(pfx, lvl, "(COMPARE", GET_MODE(x));
2557
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2558
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2559
+               zip_debug_print(pfx, lvl, ")");
2560
+               break;
2561 102 dgisselq
+       case CONST:
2562
+               zip_debug_print_m(pfx, lvl, "(CONST", GET_MODE(x));
2563
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2564
+               zip_debug_print(pfx, lvl, ")");
2565
+               break;
2566
+       case CONST_INT:
2567
+               { char buf[128];
2568
+               if (GET_MODE(x)==QImode)
2569
+                       sprintf(buf, "(CONST_INT:QI %ld)", (long)INTVAL(x));
2570
+               else if (GET_MODE(x)==VOIDmode)
2571
+                       sprintf(buf, "(CONST_INT:V %ld, %016lx)", (long)INTVAL(x),
2572
+                               (unsigned long)INTVAL(x));
2573
+               else
2574
+                       sprintf(buf, "(CONST_INT:? %ld)", (long)INTVAL(x));
2575
+               zip_debug_print(pfx, lvl, buf);
2576 127 dgisselq
+               } break;
2577 102 dgisselq
+       case LABEL_REF:
2578
+               { char buf[256];
2579
+               sprintf(buf, "(LABEL *.L%d)", CODE_LABEL_NUMBER(LABEL_REF_LABEL(x)));
2580
+               zip_debug_print(pfx, lvl, buf);
2581 111 dgisselq
+               }
2582
+               break;
2583
+       case SYMBOL_REF:
2584
+               {
2585
+                       char buf[1024];
2586 102 dgisselq
+                       sprintf(buf, "(SYMBOL: %s)", XSTR(x,0));
2587 192 dgisselq
+                       // fprintf(file, "%s", XSTR(x,0));
2588 202 dgisselq
+                       zip_debug_print(pfx, lvl, buf);
2589
+               }
2590 102 dgisselq
+               break;
2591 202 dgisselq
+       case MEM:
2592
+               zip_debug_print_m(pfx, lvl, "(MEM", GET_MODE(x));
2593 102 dgisselq
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2594 135 dgisselq
+               zip_debug_print(pfx, lvl, ")");
2595 102 dgisselq
+               break;
2596
+       /*
2597
+       case VALUE:
2598 122 dgisselq
+               {
2599 111 dgisselq
+                       char buf[64];
2600
+                       sprintf(buf, "(VALUE: %d)", INTVAL(XEXP,0));
2601
+                       zip_debug_print_m(pfx, lvl, "buf", GET_MODE(x));
2602 102 dgisselq
+               }
2603
+               break;
2604
+       */
2605 202 dgisselq
+       case PLUS:
2606 102 dgisselq
+               zip_debug_print_m(pfx, lvl, "(PLUS", GET_MODE(x));
2607
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2608
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2609
+               zip_debug_print(pfx, lvl, ")");
2610
+               break;
2611
+       case MINUS:
2612
+               zip_debug_print_m(pfx, lvl, "(MINUS", GET_MODE(x));
2613
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2614
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2615
+               zip_debug_print(pfx, lvl, ")");
2616
+               break;
2617
+       case AND:
2618
+               zip_debug_print_m(pfx, lvl, "(AND", GET_MODE(x));
2619
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2620
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2621
+               zip_debug_print(pfx, lvl, ")");
2622
+               break;
2623
+       case IOR:
2624
+               zip_debug_print_m(pfx, lvl, "(OR", GET_MODE(x));
2625
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2626
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2627
+               zip_debug_print(pfx, lvl, ")");
2628
+               break;
2629
+       case XOR:
2630
+               zip_debug_print_m(pfx, lvl, "(XOR", GET_MODE(x));
2631
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2632
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2633
+               zip_debug_print(pfx, lvl, ")");
2634
+               break;
2635
+       case MULT:
2636
+               zip_debug_print_m(pfx, lvl, "(MULT", GET_MODE(x));
2637
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2638
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2639
+               zip_debug_print(pfx, lvl, ")");
2640
+               break;
2641
+       case EQ:        //
2642
+               zip_debug_print_m(pfx, lvl, "(EQ", GET_MODE(x));
2643
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2644
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2645
+               zip_debug_print(pfx, lvl, ")");
2646
+               break;
2647
+       case NE:        //
2648
+               zip_debug_print_m(pfx, lvl, "(NE", GET_MODE(x));
2649
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2650
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2651
+               zip_debug_print(pfx, lvl, ")");
2652
+               break;
2653
+       case GE:        //
2654
+               zip_debug_print_m(pfx, lvl, "(GE", GET_MODE(x));
2655
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2656
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2657
+               zip_debug_print(pfx, lvl, ")");
2658
+               break;
2659
+       case GT:        //
2660
+               zip_debug_print_m(pfx, lvl, "(GT", GET_MODE(x));
2661
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2662
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2663
+               zip_debug_print(pfx, lvl, ")");
2664
+               break;
2665
+       case LE:        //
2666
+               zip_debug_print_m(pfx, lvl, "(LE", GET_MODE(x));
2667
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2668
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2669
+               zip_debug_print(pfx, lvl, ")");
2670
+               break;
2671
+       case LT:        //
2672
+               zip_debug_print_m(pfx, lvl, "(LT", GET_MODE(x));
2673
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2674
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2675
+               zip_debug_print(pfx, lvl, ")");
2676
+               break;
2677
+       case GEU:       //
2678
+               zip_debug_print_m(pfx, lvl, "(GEU", GET_MODE(x));
2679
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2680
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2681
+               zip_debug_print(pfx, lvl, ")");
2682
+               break;
2683
+       case GTU:       //
2684
+               zip_debug_print_m(pfx, lvl, "(GTU", GET_MODE(x));
2685
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2686
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2687
+               zip_debug_print(pfx, lvl, ")");
2688
+               break;
2689
+       case LEU:       //
2690
+               zip_debug_print_m(pfx, lvl, "(LEU", GET_MODE(x));
2691
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2692
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2693
+               zip_debug_print(pfx, lvl, ")");
2694
+               break;
2695
+       case LTU:       //
2696
+               zip_debug_print_m(pfx, lvl, "(LTU", GET_MODE(x));
2697
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2698
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2699
+               zip_debug_print(pfx, lvl, ")");
2700
+               break;
2701
+       case SCRATCH:   //
2702
+               zip_debug_print_m(pfx, lvl, "(SCRATCH)", GET_MODE(x));
2703
+               break;
2704
+       case SUBREG:
2705
+               { char buf[64], mstr[8];
2706
+               if (GET_MODE(x) == QImode)
2707
+                       strcpy(mstr, ":QI");
2708
+               else if (GET_MODE(x) == HImode)
2709
+                       strcpy(mstr, ":HI");
2710
+               else if (GET_MODE(x) == SImode)
2711
+                       strcpy(mstr, ":SI");
2712
+               else if (GET_MODE(x) == DImode)
2713
+                       strcpy(mstr, ":DI");
2714
+               else if (GET_MODE(x) == SFmode)
2715
+                       strcpy(mstr, ":SF");
2716
+               else if (GET_MODE(x) == DFmode)
2717
+                       strcpy(mstr, ":DF");
2718
+               else if (GET_MODE(x) == VOIDmode)
2719
+                       strcpy(mstr, ":V");
2720
+               else
2721
+                       strcpy(mstr, ":?");
2722
+               if (REG_P(XEXP(x,0))) {
2723
+                       int hreg = REGNO(XEXP(x,0)), mod = GET_MODE(XEXP(x,0)),
2724
+                               sb = SUBREG_BYTE(x);
2725 202 dgisselq
+                       if (mod==SFmode)
2726
+                       sprintf(buf,"(SUBREG%s (REG:SF %d)/%d)",mstr,hreg, sb);
2727
+                       else if (mod==DFmode)
2728
+                       sprintf(buf,"(SUBREG%s (REG:DF %d)/%d)",mstr,hreg, sb);
2729
+                       else if (mod==DImode)
2730
+                       sprintf(buf,"(SUBREG%s (REG:DI %d)/%d)",mstr,hreg, sb);
2731
+                       else if (mod==SImode)
2732 209 dgisselq
+                       sprintf(buf,"(SUBREG%s (REG:SI %d)/%d)",mstr,hreg, sb);
2733
+                       else if (mod==HImode)
2734
+                       sprintf(buf,"(SUBREG%s (REG:HI %d)/%d)",mstr,hreg, sb);
2735
+                       else if (mod==QImode)
2736
+                       sprintf(buf,"(SUBREG%s (REG:QI %d)/%d)",mstr,hreg, sb);
2737
+                       else if (mod==VOIDmode)
2738 202 dgisselq
+                       sprintf(buf,"(SUBREG%s (REG:V %d)/%d)",mstr,hreg, sb);
2739
+                       else
2740
+                       sprintf(buf,"(SUBREG%s %d:?/%d)",mstr,hreg, sb);
2741
+                       zip_debug_print(pfx, lvl, buf);
2742 111 dgisselq
+               } else if (MEM_P(XEXP(x,0))) {
2743 202 dgisselq
+                       sprintf(buf, "(SUBREG%s /%d", mstr,SUBREG_BYTE(x));
2744
+                       zip_debug_print(pfx, lvl, buf);
2745 209 dgisselq
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2746
+                       zip_debug_print(pfx, lvl, ")");
2747
+               } else {
2748
+                       sprintf(buf, "(SUBREG%s UNK /%d", mstr,SUBREG_BYTE(x));
2749
+                       zip_debug_print(pfx, lvl, buf);
2750
+                       zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2751
+                       zip_debug_print(pfx, lvl, ")");
2752
+               }}
2753 202 dgisselq
+               break;
2754
+       case ASHIFT:
2755
+               zip_debug_print_m(pfx, lvl, "(ASHIFT", GET_MODE(x));
2756
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2757
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2758
+               zip_debug_print(pfx, lvl, ")");
2759
+               break;
2760
+       case ASHIFTRT:
2761 111 dgisselq
+               zip_debug_print_m(pfx, lvl, "(ASHIFTRT", GET_MODE(x));
2762
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2763 202 dgisselq
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2764 111 dgisselq
+               zip_debug_print(pfx, lvl, ")");
2765
+               break;
2766
+       case LSHIFTRT:
2767
+               zip_debug_print_m(pfx, lvl, "(LSHIFTRT", GET_MODE(x));
2768 202 dgisselq
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2769 111 dgisselq
+               zip_debug_rtx_1(pfx, XEXP(x,1),lvl+1);
2770
+               zip_debug_print(pfx, lvl, ")");
2771
+               break;
2772
+       case ZERO_EXTRACT:
2773
+               zip_debug_print_m(pfx, lvl, "(ZERO_EXTRACT", GET_MODE(x));
2774 127 dgisselq
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2775
+               zip_debug_print(pfx, lvl, ")");
2776
+               break;
2777
+       case ZERO_EXTEND:
2778
+               zip_debug_print_m(pfx, lvl, "(ZERO_EXTEND", GET_MODE(x));
2779
+               zip_debug_rtx_1(pfx, XEXP(x,0),lvl+1);
2780
+               zip_debug_print(pfx, lvl, ")");
2781
+               break;
2782
+       default:
2783
+               { char buf[128];
2784
+               sprintf(buf, "(? = %d) -- calling DEBUG-RTX", GET_CODE(x));
2785
+               zip_debug_print(pfx, lvl, buf);
2786
+               debug_rtx(x);
2787
+               } break;
2788
+       }
2789
+}
2790
+
2791
+void
2792 202 dgisselq
+zip_debug_rtx_pfx(const char *pfx, const_rtx x) {
2793
+       zip_debug_rtx_1(pfx, x, 0);
2794
+}
2795
+
2796
+void
2797
+zip_debug_rtx(const_rtx x) {
2798
+       zip_debug_rtx_pfx("", x);
2799
+}
2800
+
2801
+void
2802 102 dgisselq
+zip_debug_ccode(int ccode) {
2803 111 dgisselq
+       switch(ccode) {
2804 102 dgisselq
+       case    EQ: fprintf(stderr, "EQ"); break;
2805
+       case    NE: fprintf(stderr, "NE"); break;
2806
+       case    GE: fprintf(stderr, "GE"); break;
2807
+       case    LT: fprintf(stderr, "LT"); break;
2808
+       case    LTU: fprintf(stderr, "LTU"); break;
2809
+       case    GEU: fprintf(stderr, "GEU"); break;
2810
+       case    GT: fprintf(stderr, "GT[!]"); break;
2811
+       case    LE: fprintf(stderr, "LE[!]"); break;
2812
+       case    GTU: fprintf(stderr, "GTU[!]"); break;
2813
+       case    LEU: fprintf(stderr, "LEU[!]"); break;
2814
+       default:
2815
+               fprintf(stderr, "%d", ccode); break;
2816
+       }
2817
+}
2818
+
2819
+void
2820
+zip_debug_insn(rtx_insn *insn ATTRIBUTE_UNUSED) {
2821
+}
2822 142 dgisselq
+
2823
+void
2824
+zip_debug_bb(basic_block bb) {
2825
+       rtx_insn        *insn;
2826
+
2827
+       fprintf(stderr, "************ BASIC-BLOCK ***************\n");
2828 202 dgisselq
+       FOR_BB_INSNS(bb, insn)
2829 142 dgisselq
+       {
2830 202 dgisselq
+               zip_debug_rtx(insn);
2831
+       }
2832
+}
2833
+
2834 142 dgisselq
+
2835
+static bool
2836
+zip_legitimate_opb(rtx x, bool strict)
2837
+{
2838
+       ZIPDEBUGFLAG(dbg, false);
2839
+
2840 102 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB\n");
2841
+       if (dbg) zip_debug_rtx_pfx("Test: ", x);
2842
+
2843
+       if (NULL_RTX == x)
2844
+               return false;
2845
+       else if ((GET_MODE(x) != QImode)
2846
+                       &&(GET_MODE(x) != HImode)
2847
+                       &&(GET_MODE(x) != SImode)
2848
+                       &&(GET_MODE(x) != VOIDmode)) {
2849
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> Mode failure\n");
2850
+               return false;
2851
+       } else if ((strict)&&(REG_P(x))) {
2852
+               if (REGNO(x)<zip_CC) {
2853
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
2854
+                       return true;
2855
+               } else return false;
2856 122 dgisselq
+       } else if (register_operand(x, GET_MODE(x))) {
2857 102 dgisselq
+               // This also handles subregs
2858 202 dgisselq
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> (Reg)\n");
2859 102 dgisselq
+               return true;
2860 111 dgisselq
+       } else if ((CONST_INT_P(x))
2861 102 dgisselq
+               &&(INTVAL(x) >= zip_min_opb_imm)
2862
+               &&(INTVAL(x) <= zip_max_opb_imm)) {
2863
+               if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (Const) %ld <= %ld <= %ld\n", (long)zip_min_opb_imm, (long)INTVAL(x), (long)zip_max_opb_imm);
2864
+               return true;
2865 202 dgisselq
+       // } else if ((GET_CODE(x) == LABEL_REF)||(GET_CODE(x)==CODE_LABEL)) {
2866
+               // return true;
2867
+       } else if (GET_CODE(x) == PLUS) {
2868
+               // Is it a valid register?
2869 122 dgisselq
+               rtx     regrtx = XEXP(x, 0);
2870 102 dgisselq
+               if ((!strict)&&(!REG_P(regrtx))) {
2871 122 dgisselq
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No (No reg in +%s)\n",
2872
+                       (GET_CODE(XEXP(x,1))==REG)?", reg in op[1]":"");
2873
+                       return false;
2874
+               } else if ((strict)&&((!REG_P(XEXP(x,0)))||(REGNO(XEXP(x,0))>=zip_CC))) {
2875
+                       return false;
2876
+               } if ((GET_CODE(XEXP(x, 1)) == CONST_INT)
2877
+                       &&(INTVAL(XEXP(x, 1)) <= zip_max_anchor_offset)
2878
+                       &&(INTVAL(XEXP(x, 1)) >= zip_min_anchor_offset)) {
2879
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> YES! (reg+int)\n");
2880 111 dgisselq
+                       // if((INTVAL(XEXP(x,1))<0)&&(REGNO(XEXP(x,0))==zip_SP))
2881
+                               // gcc_unreachable();
2882
+                       return true;
2883 136 dgisselq
+               } if ((GET_CODE(XEXP(x, 1)) == LABEL_REF)
2884 111 dgisselq
+                       ||(GET_CODE(XEXP(x, 1)) == CODE_LABEL)
2885 122 dgisselq
+                       ||(GET_CODE(XEXP(x, 1)) == SYMBOL_REF)) {
2886
+                       // While we can technically support this, the problem
2887 102 dgisselq
+                       // is that the symbol address could be anywhere, and we
2888
+                       // have no way of recovering if it's outside of our
2889 202 dgisselq
+                       // 14 allowable bits.
2890
+                       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No. (reg+lbl)\n");
2891 111 dgisselq
+                       return false;
2892 102 dgisselq
+               }
2893
+       }
2894 122 dgisselq
+
2895 102 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-LEGITIMATE-OPB -> No\n");
2896
+       if (dbg) zip_debug_rtx(x);
2897
+       return false;
2898
+}
2899 111 dgisselq
+
2900 103 dgisselq
+static bool
2901
+zip_legitimate_move_operand_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict) {
2902 102 dgisselq
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
2903
+
2904 122 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND\n");
2905 102 dgisselq
+       if (dbg) zip_debug_rtx_pfx("VMov?: ", x);
2906
+
2907
+       if (!zip_legitimate_opb(x, strict))
2908
+               return false;
2909
+       else if ((GET_CODE(x)==PLUS)&&(CONST_INT_P(XEXP(x,1)))) {
2910 111 dgisselq
+               if ((INTVAL(XEXP(x, 1)) > zip_max_mov_offset)
2911 102 dgisselq
+                       ||(INTVAL(XEXP(x, 1)) < zip_min_mov_offset)) {
2912
+                       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> NO! (reg+int), int out of bounds: %ld\n", (long)INTVAL(XEXP(x,1)));
2913
+                       return false;
2914
+               }
2915 111 dgisselq
+       }
2916 102 dgisselq
+
2917
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOVE-OPERAND -> Yes\n");
2918
+       if (dbg) zip_debug_rtx(x);
2919
+       return true;
2920
+}
2921
+
2922 202 dgisselq
+int
2923 102 dgisselq
+zip_pd_mov_operand(rtx op)
2924
+{
2925
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
2926
+
2927 122 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-VALID-MOV(predicate) for OPERAND\n");
2928 102 dgisselq
+       return zip_legitimate_move_operand_p(VOIDmode, op, !can_create_pseudo_p());
2929 122 dgisselq
+}
2930
+
2931
+int
2932 135 dgisselq
+zip_pd_mvimm_operand(rtx op)
2933 102 dgisselq
+{
2934
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
2935
+
2936
+       if (dbg) fprintf(stderr, "ZIP-VALID-MVIMM(predicate) for OPERAND\n");
2937 122 dgisselq
+       if (!CONST_INT_P(op))
2938 102 dgisselq
+               return false;
2939 122 dgisselq
+       if (INTVAL(op) > zip_max_mov_offset)
2940 102 dgisselq
+               return false;
2941
+       if (INTVAL(op) < zip_min_mov_offset)
2942
+               return false;
2943
+       return true;
2944
+}
2945 202 dgisselq
+
2946 102 dgisselq
+int
2947
+zip_pd_imm_operand(rtx op)
2948
+{
2949
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
2950
+
2951
+       if (dbg) fprintf(stderr, "ZIP-VALID-IMM(predicate) for OPERAND\n");
2952 111 dgisselq
+       if (!CONST_INT_P(op))
2953
+               return false;
2954 202 dgisselq
+       if (INTVAL(op) > zip_max_anchor_offset)
2955 111 dgisselq
+               return false;
2956
+       if (INTVAL(op) < zip_min_anchor_offset)
2957
+               return false;
2958
+       return true;
2959
+}
2960
+
2961
+int
2962
+zip_address_operand(rtx op)
2963
+{
2964
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
2965
+
2966
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS for OPERAND\n");
2967
+       if ((REG_P(op))&&(REGNO(op)==zip_CC))
2968
+               return false;
2969 202 dgisselq
+       else if ((GET_CODE(op) == PLUS)&&(REG_P(XEXP(op,0)))
2970 111 dgisselq
+                       &&(REGNO(XEXP(op,0))==zip_CC))
2971
+               return false;
2972
+       else
2973
+               return zip_legitimate_opb(op, !can_create_pseudo_p());
2974
+}
2975
+
2976
+int
2977
+zip_pd_opb_operand(rtx op)
2978
+{
2979
+       ZIPDEBUGFLAG(dbg, false);
2980
+
2981
+       if (dbg) fprintf(stderr, "ZIP-OPB(predicate) for OPERAND\n");
2982 102 dgisselq
+       return zip_legitimate_opb(op, false); //, !can_create_pseudo_p());
2983
+}
2984 202 dgisselq
+
2985 102 dgisselq
+int
2986
+zip_ct_address_operand(rtx op)
2987 111 dgisselq
+{
2988
+       ZIPDEBUGFLAG(dbg, false);
2989
+
2990
+       if (dbg) fprintf(stderr, "ZIP-ADDRESS(constraint) for OPERAND\n");
2991
+       return zip_legitimate_opb(op, !can_create_pseudo_p());
2992
+}
2993
+
2994 102 dgisselq
+int
2995
+zip_const_address_operand(rtx x) {
2996
+       ZIPDEBUGFLAG(dbg, false);
2997 111 dgisselq
+
2998 102 dgisselq
+       if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS?\n");
2999 202 dgisselq
+       if (dbg) zip_debug_rtx(x);
3000 102 dgisselq
+       if ((GET_MODE(x) != SImode)&&(GET_MODE(x) != VOIDmode)) {
3001 111 dgisselq
+               fprintf(stderr, "is ZIP-CONST-ADDRESS? -> NO, BAD MODE\n");
3002 122 dgisselq
+               return false;
3003 102 dgisselq
+       }
3004
+       if ((GET_CODE(x) == LABEL_REF)
3005
+                       ||(GET_CODE(x) == CODE_LABEL)
3006
+                       ||(GET_CODE(x) == SYMBOL_REF)) {
3007
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (LBL)\n");
3008 202 dgisselq
+               return true;
3009 102 dgisselq
+       } else if (CONST_INT_P(x)) {
3010
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> YES! (INT)\n");
3011 111 dgisselq
+               return true;
3012 102 dgisselq
+       } else if (GET_CODE(x) == PLUS) {
3013
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(PLUS)\n");
3014
+               return ((zip_const_address_operand(XEXP(x,0)))
3015
+                       &&(CONST_INT_P(XEXP(x,1))));
3016 202 dgisselq
+       } else if (GET_CODE(x) == MINUS) {
3017 102 dgisselq
+               if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS(MINUS)\n");
3018
+               return ((zip_const_address_operand(XEXP(x,0)))
3019
+                       &&(zip_const_address_operand(XEXP(x,1))));
3020 127 dgisselq
+       }
3021
+
3022 102 dgisselq
+       if (dbg) fprintf(stderr, "is ZIP-CONST-ADDRESS? -> No\n");
3023 127 dgisselq
+       if (dbg) zip_debug_rtx(x);
3024 102 dgisselq
+       return false;
3025
+}
3026
+
3027 127 dgisselq
+int
3028 102 dgisselq
+zip_ct_const_address_operand(rtx x) {
3029
+       ZIPDEBUGFLAG(dbg, false);
3030 127 dgisselq
+
3031 102 dgisselq
+       if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(constraint)\n");
3032
+       return zip_const_address_operand(x);
3033
+}
3034
+
3035
+int
3036
+zip_pd_const_address_operand(rtx x) {
3037
+       ZIPDEBUGFLAG(dbg, false);
3038
+
3039
+       if (dbg) fprintf(stderr, "ZIP-CONST-ADDRESS(predicate)\n");
3040
+       return zip_const_address_operand(x);
3041
+}
3042
+
3043
+
3044
+static bool
3045
+zip_legitimate_address_p(machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool strict)
3046
+{
3047
+       ZIPDEBUGFLAG(dbg, false);
3048
+
3049 202 dgisselq
+       if (dbg) fprintf(stderr, "Zip-LEGITIMATE-ADDRESS-P\n");
3050 102 dgisselq
+       if (dbg) zip_debug_rtx(x);
3051
+
3052
+       // Only insist the register be a valid register if strict is true
3053
+       if (zip_legitimate_opb(x, strict))
3054
+               return true;
3055
+       // else if (zip_const_address_operand(x))
3056
+               // return true;
3057 202 dgisselq
+
3058 102 dgisselq
+       return false;
3059
+}
3060
+
3061
+static rtx
3062
+zip_legitimize_address(rtx x, rtx oldx ATTRIBUTE_UNUSED, machine_mode mode ATTRIBUTE_UNUSED) {
3063
+       ZIPDEBUGFLAG(dbg, false);
3064
+
3065
+
3066
+       if (dbg) zip_debug_rtx_pfx("LEGITIMIZE: ", x);
3067 202 dgisselq
+       if (zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
3068 102 dgisselq
+               return x;
3069
+
3070
+       if (dbg) zip_debug_rtx_pfx("ILLEGITIMATE: ", x);
3071
+       if (GET_CODE(x)==PLUS) {
3072
+               // if ((zip_legitimate_address_p(mode, XEXP(x,0),
3073 111 dgisselq
+               //              !can_create_pseudo_p()))
3074 102 dgisselq
+               //      &&(GETMODE(XEXP(x,1))==CONST_INT)) {
3075 111 dgisselq
+               //}
3076
+               if (!REG_P(XEXP(x,0)))
3077 102 dgisselq
+                       XEXP(x,0) = force_reg(Pmode,XEXP(x,0));
3078
+               if ((!zip_legitimate_address_p(mode, x, !can_create_pseudo_p()))
3079
+                       &&(!CONST_INT_P(XEXP(x,1))))
3080
+                       x = force_reg(GET_MODE(x),x);
3081 111 dgisselq
+       } else if (MEM_P(x))
3082
+               x = force_reg(GET_MODE(x),x);
3083 202 dgisselq
+
3084 111 dgisselq
+       if (dbg) zip_debug_rtx_pfx("LEGITIMATE: ", x);
3085 202 dgisselq
+       return x;
3086 111 dgisselq
+}
3087
+
3088
+void
3089
+zip_asm_output_def(FILE *stream, const char *name, const char *value)
3090 202 dgisselq
+{
3091 111 dgisselq
+       fprintf(stream, "\t.equ %s, %s\n", name, value);
3092 202 dgisselq
+}
3093
+
3094
+const char *zip_set_zero_or_one(rtx condition, rtx dst) {
3095
+       ZIPDEBUGFLAG(dbg, false);
3096 111 dgisselq
+
3097 202 dgisselq
+       if (dbg) fprintf(stderr, "ZIP::SET-ZERO-OR-ONE\n");
3098 111 dgisselq
+       if (dbg) zip_debug_rtx_pfx("CND", condition);
3099
+       if (dbg) zip_debug_rtx_pfx("REG", dst);
3100
+       switch(GET_CODE(condition)) {
3101
+       case EQ:        return "LDI\t0,%0\n\tLDILO.Z\t1,%0\t; set01_eq";
3102
+       case NE:        return "LDI\t0,%0\n\tLDILO.NZ\t1,%0\t; set01_ne";
3103
+       case LT:        return "LDI\t0,%0\n\tLDILO.LT\t1,%0\t; set01_lt";
3104
+       case GT:        return "LDI\t1,%0\n\tLDILO.LT\t1,%0\n\tLDILO.Z\t1,%0\t; set01_gt";
3105
+       case LE:        return "LDI\t0,%0\n\tLDILO.LT\t1,%0\n\tLDILO.Z\t1,%0\t; set01_le";
3106
+       case GE:        return "LDI\t0,%0\n\tLDILO.GE\t1,%0\t; set01_ge";
3107
+       case LTU:       return "LDI\t0,%0\n\tLDILO.C\t1,%0\t; set01_ltu";
3108 102 dgisselq
+       case GEU:       return "LDI\t0,%0\n\tLDILO.NC\t1,%0\t; set01_geu";
3109
+       case GTU:       return "LDI\t1,%0\n\tLDILO.C\t0,%0\n\tLDILO.Z\t0,%0\t; set01_gtu";
3110
+       case LEU:       return "LDI\t0,%0\n\tLDILO.C\t1,%0\n\tLDILO.Z\t1,%0\t; set01_leu";
3111 202 dgisselq
+       default:
3112 102 dgisselq
+               zip_debug_rtx(condition);
3113
+               internal_error("CSTORE Unsupported condition");
3114 202 dgisselq
+               return NULL;
3115
+       }
3116 102 dgisselq
+}
3117
+
3118
+int
3119
+zip_supported_condition(int c) {
3120
+       switch(c) {
3121 202 dgisselq
+       case EQ: case NE: case LT: case GE: case LTU: case GEU:
3122
+               return 1;
3123
+               break;
3124
+       default:
3125
+               break;
3126
+       } return 0;
3127
+}
3128
+
3129
+bool
3130
+zip_signed_comparison(int c) {
3131 102 dgisselq
+       switch(c) {
3132
+       case NE: case LT: case EQ: case GE:
3133
+               return true;
3134
+       default:
3135
+               break;
3136
+       } return false;
3137
+}
3138 200 dgisselq
+
3139 127 dgisselq
+int
3140
+zip_expand_movdi(rtx dst, rtx src) {
3141 202 dgisselq
+       ZIPDEBUGFLAG(dbg, false);
3142 200 dgisselq
+
3143 127 dgisselq
+       if (dbg) fprintf(stderr, "\nZIP::MOVDI\n");
3144
+       if (dbg) zip_debug_rtx_pfx("  DST", dst);
3145
+       if (dbg) zip_debug_rtx_pfx("  SRC", src);
3146 200 dgisselq
+
3147 102 dgisselq
+       // MOV !REG->!REG
3148
+       if ((!REG_P(dst))&&(!REG_P(src))&&(can_create_pseudo_p())) {
3149 127 dgisselq
+               // This includes:
3150
+               //      MOV MEM->MEM
3151
+               //      MOV IMM->MEM
3152 202 dgisselq
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- !REG->!REG\n");
3153 127 dgisselq
+
3154
+               rtx tmp = gen_reg_rtx(DImode);
3155
+               emit_insn(gen_movdi(tmp, src));
3156
+               emit_insn(gen_movdi(dst, tmp));
3157
+               return 1;
3158
+       }
3159 200 dgisselq
+
3160 202 dgisselq
+       // MOV REG->REG
3161
+       if ((REG_P(dst))&&(REG_P(src))) {
3162
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->REG\n");
3163
+
3164 209 dgisselq
+               emit_insn(gen_movdi_raw(dst, src));
3165
+               return 1;
3166 127 dgisselq
+       }
3167 202 dgisselq
+
3168
+       // MOV SUBREG->REG
3169
+       if ((REG_P(dst))&&(SUBREG_P(src))) {
3170
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- SUBREG->REG\n");
3171
+
3172
+               if (GET_MODE(src)==DImode) {
3173 127 dgisselq
+                       emit_insn(gen_movdi_raw(dst, src));
3174 202 dgisselq
+                       return 1;
3175
+               }
3176
+       }
3177
+
3178 142 dgisselq
+       // MOV REG->SUBREG
3179
+       if ((SUBREG_P(dst))&&(REG_P(src))) {
3180 202 dgisselq
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->SUBREG\n");
3181
+
3182
+               if (GET_MODE(dst)==DImode) {
3183 127 dgisselq
+                       emit_insn(gen_movdi_raw(dst, src));
3184 202 dgisselq
+                       return 1;
3185
+               }
3186
+       }
3187 127 dgisselq
+
3188 209 dgisselq
+       // MOV REG->MEM (a store instruction)
3189
+       if ((MEM_P(dst))&&(REG_P(src))) {
3190
+               rtx     addr = XEXP(dst,0);
3191
+               long    offset = 0;
3192
+               if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))
3193
+                       offset = INTVAL(XEXP(addr,1));
3194
+
3195
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- REG->MEM\n");
3196
+               if (REG_P(addr)) {
3197
+                       emit_insn(gen_movdi_raw(dst, src));
3198
+                       return 1;
3199
+               } else if ((GET_CODE(addr)==PLUS)
3200
+                       &&(REG_P(XEXP(addr,0)))
3201
+                       &&(CONST_INT_P(XEXP(addr,1)))
3202
+                       &&(offset>=(long)zip_min_anchor_offset)
3203
+                       &&(offset+4<(long)zip_max_anchor_offset)) {
3204
+                       // Demonstrated and works
3205
+                       emit_insn(gen_movdi_raw(dst, src));
3206
+                       return 1;
3207
+               } else if (can_create_pseudo_p()) {
3208 202 dgisselq
+                       rtx tmp = gen_reg_rtx(Pmode);
3209
+                       emit_insn(gen_movsi(tmp, addr));
3210
+                       emit_insn(gen_movdi_raw(gen_rtx_MEM(DImode, tmp), src));
3211
+                       return 1;
3212
+               }
3213
+       }
3214 127 dgisselq
+
3215 202 dgisselq
+       // MOV MEM->REG (a load instruction)
3216
+       if ((REG_P(dst))&&(MEM_P(src))) {
3217
+               rtx addr = XEXP(src,0);
3218
+               long    offset = 0;
3219
+               if ((GET_CODE(addr)==PLUS)&&(CONST_INT_P(XEXP(addr,1))))
3220
+                       offset = INTVAL(XEXP(addr,1));
3221
+
3222
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM->REG\n");
3223
+               if (REG_P(addr)) {
3224
+                       if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM[R]->REG\n");
3225
+                       emit_insn(gen_movdi_raw(dst, src));
3226
+                       return 1;
3227
+               } else if ((GET_CODE(addr)==PLUS)
3228
+                       &&(REG_P(XEXP(addr,0)))
3229
+                       &&(CONST_INT_P(XEXP(addr,1)))
3230
+                       &&(offset>=(long)zip_min_anchor_offset)
3231
+                       &&(offset+4<(long)zip_max_anchor_offset)) {
3232 102 dgisselq
+                       if (dbg) fprintf(stderr, "ZIP::MOVDI -- MEM[#+R]->REG -- DONE\n");
3233
+                       emit_insn(gen_movdi_raw(dst, src));
3234
+                       return 1;
3235 202 dgisselq
+               } else if (can_create_pseudo_p()) {
3236
+                       if (dbg) fprintf(stderr, "ZIP::MOVDI -- LDI #,R, MEM[R]->REG\n");
3237
+                       rtx tmp = gen_reg_rtx(Pmode);
3238
+                       emit_insn(gen_movsi(tmp, addr));
3239
+                       emit_insn(gen_movdi_raw(dst,
3240
+                               gen_rtx_MEM(DImode, tmp)));
3241 142 dgisselq
+                       return 1;
3242 202 dgisselq
+               } else if (dbg)
3243
+                       fprintf(stderr, "ZIP::MOVDI -- MEM[?]->REG (no match)\n");
3244
+       }
3245
+
3246
+       // MOV #->REG (An LDI instruction, but for DIwords)
3247
+       if ((CONST_INT_P(src))&&(REG_P(dst))) {
3248
+               if (dbg) fprintf(stderr, "ZIP::MOVDI -- IMM->REG\n");
3249
+               emit_insn(gen_movdi_raw(dst, src));
3250
+               return 1;
3251
+       }
3252
+
3253
+       return 0;
3254
+}
3255
+
3256
+const char *
3257
+zip_addsicc(rtx dst, rtx condition, rtx ifsrc, rtx addv) {
3258
+       // We know upon entry that REG_P(dst) must be true
3259
+       if (!REG_P(dst))
3260
+               internal_error("%s","ADDSICC into something other than register");
3261
+
3262
+       if ((REG_P(dst))&&(REG_P(ifsrc))&&(REG_P(addv))
3263
+               &&(REGNO(dst)!=REGNO(ifsrc))) {
3264 142 dgisselq
+               switch (GET_CODE(condition)) {
3265 127 dgisselq
+               case EQ: return "MOV.Z\t%2,%0\n\tADD.Z\t%3,%0";
3266 202 dgisselq
+               case NE: return "MOV.NZ\t%2,%0\n\tADD.NZ\t%3,%0";
3267
+               case LT: return "MOV.LT\t%2,%0\n\tADD.LT\t%3,%0";
3268
+
3269
+               case LE: return "MOV.LT\t%3,%0\n\tMOV.Z\t%3,%0\n\tADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
3270
+               case GE: return "MOV.GE\t%2,%0\n\tADD.GE\t%3,%0";
3271 142 dgisselq
+
3272 127 dgisselq
+               case GT: return "BLT\t%.Laddsi%=\n\tBZ\t%%.Laddsi%=\n\tMOV\t%2,%0\n\tADD\t%3,%0\n.Laddsi%=:";
3273 202 dgisselq
+               case LTU: return "MOV.C\t%2,%0\n\tADD.C\t%3,%0";
3274
+
3275 142 dgisselq
+               case LEU: return "MOV.C\t%2,%0\n\tMOV.Z\t%2,%0\n\tADD.C\t%3,%0\n\tADD.Z\t%3,%0";
3276 202 dgisselq
+               case GEU: return "MOV.NC\t%2,%0\n\tADD.NC\t%3,%0";
3277
+               case GTU: return "BZ\t%.Laddsi%=\n\tMOV.NC\t%3,%0\n\tADD.NC\t%3,%0\n.Laddsi%=:";
3278
+               default:
3279
+                       internal_error("%s", "Zip/No usable addsi expansion");
3280
+                       break;
3281 127 dgisselq
+               }
3282 202 dgisselq
+       }
3283
+
3284
+       if ((REG_P(ifsrc))&&(REGNO(dst)==REGNO(ifsrc))) {
3285
+               switch (GET_CODE(condition)) {
3286
+               case EQ: return "ADD.Z\t%3,%0";
3287
+               case NE: return "ADD.NZ\t%3,%0";
3288 127 dgisselq
+               case LT: return "ADD.LT\t%3,%0";
3289 202 dgisselq
+               case LE: return "ADD.LT\t%3,%0\n\tADD.Z\t%3,%0";
3290
+               case GE: return "ADD.GE\t%3,%0";
3291 142 dgisselq
+               case GT: return "ADD.GE\t%3,%0\n\tSUB.Z\t%3,%0";
3292 202 dgisselq
+               case LTU: return "ADD.C\t%3,%0";
3293
+               case LEU: return "ADD.C\t%3,%0\n\tADD.Z\t%3,%0";
3294
+               case GEU: return "ADD.NC\t%3,%0";
3295
+               case GTU: return "SUB.Z\t%3,%0\n\tADD.NC\t%3,%0";
3296
+               default:
3297
+                       internal_error("%s", "Zip/No usable addsi expansion");
3298
+                       break;
3299
+               }
3300
+       } else {
3301
+               // MOV A+REG,REG
3302 142 dgisselq
+               switch (GET_CODE(condition)) {
3303
+               case EQ: return "MOV.Z\t%3+%2,%0";
3304 102 dgisselq
+               case NE: return "MOV.NZ\t%3+%2,%0";
3305
+               case LT: return "MOV.LT\t%3+%2,%0";
3306
+               case GT: return "BLT\t.Laddcc%=\n\tBZ\t.Laddcc%=\n\tMOV\t%3+%2,%0\n.Laddcc%=";
3307
+               case LE: return "MOV.LT\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
3308
+               case GE: return "MOV.GE\t%3+%2,%0";
3309
+               case LTU: return "MOV.C\t%3+%2,%0";
3310
+               case LEU: return "MOV.C\t%3+%2,%0\n\tMOV.Z\t%3+%2,%0";
3311 202 dgisselq
+               case GEU: return "MOV.NC\t%3+%2,%0";
3312 102 dgisselq
+               case GTU: return "BZ\t.Laddcc%=\n\tMOV.NC\t%3+%2,%0\n\t.Laddcc%=:";
3313
+               default:
3314 202 dgisselq
+                       internal_error("%s", "Zip/No usable addsi(reg,reg) expansion");
3315
+                       break;
3316 102 dgisselq
+               }
3317
+       }
3318
+
3319
+       return "BREAK";
3320
+}
3321
+
3322
+static int     zip_memory_move_cost(machine_mode mode, reg_class_t ATTRIBUTE_UNUSED, bool in ATTRIBUTE_UNUSED) {
3323
+       int     rv = 14;
3324
+       if ((mode == DImode)||(mode == DFmode))
3325
+               rv += 2;
3326 202 dgisselq
+       return rv;
3327 102 dgisselq
+}
3328
+
3329
+// #warning "How do we tell the compiler LDI label is expensive as 2 ops"?
3330
+static bool    zip_cannot_modify_jumps_p(void) {
3331 202 dgisselq
+       // Let's try their suggested approach, keeping us from modifying jumps
3332
+       // after reload.  This should also allow our peephole2 optimizations
3333 102 dgisselq
+       // to adjust things back to what they need to be if necessary.
3334
+       return (reload_completed || reload_in_progress);
3335
+}
3336
+
3337
+rtx_insn       *zip_ifcvt_info;
3338
+
3339
+void
3340
+zip_ifcvt_modify_tests(ce_if_block *ce_info ATTRIBUTE_UNUSED, rtx *true_expr, rtx *false_expr) {
3341
+       const bool      dbg = ((ZIP_ALL_DEBUG_ON)||(false))&&(!ZIP_ALL_DEBUG_OFF);
3342 103 dgisselq
+       if (dbg) fprintf(stderr, "IFCVT-MODIFY-TESTS\n");
3343 102 dgisselq
+       if (*true_expr) switch(GET_CODE(*true_expr)) {
3344
+               // These are our unsupported conditions
3345
+               case LE:
3346
+               case GT:
3347
+               case LEU:
3348
+               case GTU:
3349 103 dgisselq
+                       if (dbg) fprintf(stderr, "TRUE, missing expr\n");
3350 117 dgisselq
+                       if (dbg) zip_debug_rtx(*true_expr);
3351
+                       *true_expr = NULL_RTX;
3352
+                       break;
3353
+               default: // LT, GT, GTE, LTU, NE, EQ
3354
+                       break;
3355
+       }
3356 122 dgisselq
+
3357
+       if (*false_expr) switch(GET_CODE(*false_expr)) {
3358
+               case LE:
3359
+               case GT:
3360
+               case LEU:
3361 202 dgisselq
+               case GTU:
3362 122 dgisselq
+                       if (dbg) fprintf(stderr, "FALSE, missing expr\n");
3363
+                       if (dbg) zip_debug_rtx(*false_expr);
3364 202 dgisselq
+                       *false_expr = NULL_RTX;
3365 122 dgisselq
+               default:
3366 202 dgisselq
+                       break;
3367
+       }
3368 122 dgisselq
+       if ((dbg)&&((!*true_expr)||(!*false_expr)))
3369
+               fprintf(stderr, "IFCVT-MODIFY-TESTS -- FAIL\n");
3370
+}
3371
+
3372
+void
3373
+zip_ifcvt_machdep_init(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
3374
+/*
3375
+if (!ceinfo->then_bb)
3376
+       return;
3377
+rtx_insn *insn;
3378
+FOR_BB_INSNS(ceinfo->then_bb, insn) {
3379 202 dgisselq
+       fprintf(stderr, "IFCVT -- INIT\n");
3380
+       zip_debug_rtx_pfx("INIT-BB", insn);
3381 122 dgisselq
+}
3382
+*/
3383
+/*
3384
+       zip_ifcvt_info = NULL;
3385
+       rtx_insn *insn, *ifinsn = NULL;
3386
+       FOR_BB_INSNS(ceinfo->test_bb, insn) {
3387
+               rtx     p;
3388
+               p = single_set(insn);
3389
+               if (!p) continue;
3390
+               if (SET_DEST(p)==pc_rtx) {
3391
+                       ifinsn = insn;
3392
+               }
3393 142 dgisselq
+               if (!REG_P(SET_DEST(p)))
3394 122 dgisselq
+                       continue;
3395 142 dgisselq
+               if (GET_MODE(SET_DEST(p))!=CCmode)
3396
+                       continue;
3397
+               if (REGNO(SET_DEST(p))!=zip_CC)
3398
+                       continue;
3399
+               zip_ifcvt_info = insn;
3400
+       }
3401 122 dgisselq
+
3402
+       if (zip_ifcvt_info)
3403
+               zip_debug_rtx_pfx("PUTATIVE-CMP",zip_ifcvt_info);
3404
+       if (ifinsn)
3405
+               zip_debug_rtx_pfx("PRIOR-JMP",ifinsn);
3406
+*/
3407
+}
3408
+
3409
+void
3410
+zip_ifcvt_modify_insn(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED,
3411
+               rtx pattern ATTRIBUTE_UNUSED,
3412
+               rtx_insn *insn ATTRIBUTE_UNUSED) {
3413
+       // zip_debug_rtx_pfx("MODIFY-INSN: ", insn);
3414
+}
3415
+
3416
+void
3417
+zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
3418
+/*
3419
+       fprintf(stderr, "IFCVT -- CANCEL\n");
3420
+       zip_ifcvt_info = NULL;
3421
+*/
3422
+}
3423
+
3424
+void
3425
+zip_ifcvt_modify_final(struct ce_if_block *ceinfo ATTRIBUTE_UNUSED) {
3426
+/*
3427
+rtx_insn *insn;
3428
+FOR_BB_INSNS(ceinfo->test_bb, insn) {
3429 142 dgisselq
+       fprintf(stderr, "IFCVT -- FINAL\n");
3430
+       zip_debug_rtx_pfx("FINAL-TEST-BB", insn);
3431
+}
3432
+       zip_ifcvt_info = NULL;
3433
+*/
3434
+}
3435
+
3436
+
3437
+int    zip_insn_sets_cc(rtx_insn *insn) {
3438
+       return (get_attr_ccresult(insn)==CCRESULT_SET);
3439
+}
3440
+
3441
+const char *
3442
+zip_cbranchdi_const(rtx comparison,
3443
+               rtx a ATTRIBUTE_UNUSED,
3444
+               rtx b,
3445
+               rtx label ATTRIBUTE_UNUSED) {
3446
+       gcc_assert(CONST_INT_P(b));
3447
+       long value = INTVAL(b);
3448
+
3449
+       // Look into the combine routines to find out why this routine never
3450
+       // gets called.
3451
+
3452
+       switch(GET_CODE(comparison)) {
3453
+       case EQ:
3454
+               if (value < 0)
3455
+                 return "CMP\t-1,%H1\t; cbranchdi/# EQ (neg)\n\tCMP.Z\t%2,%L1\n\tBZ\t%3";
3456
+               else
3457 127 dgisselq
+                 return "CMP\t0,%H1\t; cbranchdi/# EQ\n\tCMP.Z\t%2,%L1\n\tBZ\t%3";
3458
+       case NE:
3459
+               if (value < 0)
3460
+                 return "CMP\t-1,%H1\t; cbranchdi/# NE (neg)\n\tCMP.Z\t%2,%L1\n\tBNZ\t%3";
3461 202 dgisselq
+               else
3462
+                 return "CMP\t0,%H1\t; cbranchdi/# NE\n\tCMP.Z\t%2,%L1\n\tBNZ\t%3";
3463
+       case LE:
3464
+               if (value == 0)
3465
+                       return "CMP\t0,%H1\t; cbranchdi/# LE 0\n\tBLT\t%3\n\tCMP.Z\t0,%L1\n\tBZ\t%3";
3466
+               else if (value == -1)
3467
+                       return "CMP\t0,%H1\t; cbranchdi/# LE -1\n\tBLT\t%3";
3468
+               else if (value < 0) {
3469
+                       char    tmp[128];
3470
+                       sprintf(tmp, "CMP\t-1,%%H1\t; cbranchdi/# LE (neg)\n"
3471
+                               "\tBLT\t.Lcmpdile%%=\n"
3472
+                               "\tBNZ\t%%3\n"
3473
+                               "\tCMP\t%ld,%%L1\n"
3474
+                               "\tBC\t%%3", (value+1l)&0x0ffffffff);
3475
+                       return ggc_alloc_string(tmp, -1);
3476
+               } else { //; value > 0
3477
+                       char    tmp[128];
3478
+                       sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# LE\n"
3479
+                               "\tBLT\t%%3\n"
3480
+                               "\tBNZ\t.Lcmple%%=\n"
3481
+                               "\tCMP\t%ld,%%L1\n"
3482
+                               "\tBC\t%%3\n"
3483
+                               ".Lcmple%%=:", value-1);
3484
+                       return ggc_alloc_string(tmp, -1);
3485
+               }
3486
+       case LT:
3487
+               if (value == 0)
3488
+                       return "CMP\t0,%H1\t; cbranchdi/# LT 0\n\tBLT\t%3";
3489
+               else if (value < 0)
3490
+                       return "CMP\t-1,%H1\t; cbranchdi/# LT neg\n\tCMP.Z\t%2,%L1\n\tBC\t%3";
3491
+               else
3492
+                       return "CMP\t0,%H1\t; cbranchdi/# LT\n"
3493
+                               "\tBLT\t%3\n"
3494
+                               "\tBNZ\t.Lcmplt%=\n"
3495
+                               "\tCMP\t%2,%L1\n"
3496
+                               "\tBC\t%3\n"
3497
+                               ".Lcmplt%=:";
3498
+       case GT:
3499
+               if (value == 0)
3500
+                       return "CMP\t1,%H1\t; cbranchdi/# GT 0\n"
3501
+                               "\tBGE\t%3\n"
3502
+                               "\tBNZ\t.Lcmpgt%=\n"
3503
+                               "\tCMP\t0,%L1\n"
3504
+                               "\tBNZ\t%3\n"
3505
+                               ".Lcmpgt%=:";
3506
+               else if (value == -1)
3507
+                       return "CMP\t0,%H1\t; cbranchdi/# GT -1\n"
3508
+                               "\tBGE\t%3\n";
3509
+               else if (value < 0) {
3510
+                       char    tmp[128];
3511
+                       sprintf(tmp, "CMP\t-1,%%H1\t; cbranchdi/# GT neg\n"
3512
+                               "\tBLT\t.Lcmpgt%%=\n"
3513
+                               "\tBNZ\t%%3\n"
3514
+                               "\tCMP\t%ld,%%H3\n"
3515
+                               "\tBNC\t%%3\n"
3516
+                               ".Lcmpgt%%=:", value+1l);
3517
+                       return ggc_alloc_string(tmp, -1);
3518
+               } else {
3519
+                       char    tmp[128];
3520
+                       sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# GT\n"
3521
+                               "\tBLT\t.Lcmpgt%%=\n"
3522
+                               "\tBNZ\t%%3\n"
3523
+                               "\tCMP\t%ld,%%L1\n"
3524
+                               "\tBNC\t%%3\n"
3525
+                               ".Lcmpgt%%=:", value+1l);
3526
+                       return ggc_alloc_string(tmp, -1);
3527
+               }
3528
+       case GE:
3529
+               if (value == 0)
3530
+                       return "CMP\t0,%H1\t; cbranchdi/# GE 0\n"
3531
+                               "\tBLT\t.Lcmpge%=\n"
3532
+                               "\tBNZ\t%3\n"
3533
+                               "\tCMP\t0,%L1\n"
3534
+                               "\tBNC\t%3\n"
3535
+                               ".Lcmpge%=:";
3536
+               else if (value == -1)
3537
+                       return "CMP\t-1,%H1\t; cbranchdi/# GE -1\n"
3538
+                               "\tBLT\t.Lcmpge%=\n"
3539
+                               "\tBNZ\t%3\n"
3540
+                               "\tCMP\t-1,%L1\n"
3541
+                               "\tBZ\t%3\n"
3542
+                               ".Lcmpge%=:";
3543
+               else if (value < 0)
3544
+                       return "CMP\t-1,%H1\t; cbranchdi/# GE <\n"
3545
+                               "\tBLT\t.Lcmpge%=\n"
3546
+                               "\tBNZ\t%3\n"
3547
+                               "\tCMP\t%2,%L1\n"
3548
+                               "\tBNC\t%3\n"
3549
+                               ".Lcmpge%=:";
3550
+               else
3551
+                       return "CMP\t0,%H1\t; cbranchdi/# GE\n"
3552
+                               "\tBLT\t.Lcmpge%=\n"
3553
+                               "\tBNZ\t%3\n"
3554
+                               "\tCMP\t%2,%L1\n"
3555
+                               "\tBNC\t%3\n"
3556
+                               ".Lcmpge%=:";
3557
+       case LTU:
3558
+               if (value == 0) { //; Impossible, cannot be < 0 unsignd
3559
+                       return "; cbranchdi/# LTU 0 (Impossible!)";
3560
+               } else
3561
+                       return "CMP\t0,%H1\t; cbranchdi/#\n\tCMP.Z\t%2,%L1\n\tBC\t%3\n";
3562
+       case LEU:
3563
+               if (value == 0) { //; Only possible if == 0
3564
+                       return "CMP\t0,%%H0\t; cbranchdi/# LEU 0\n"
3565
+                               "\tCMP.Z\t0,%%L0\n"
3566
+                               "\tBZ\t%3";
3567
+               } else {
3568
+                       //; Subtract one, and LTU works
3569
+                       char    tmp[128];
3570
+                       sprintf(tmp, "CMP\t0,%%H1\t; cbranchdi/# LEU\n"
3571
+                               "\tCMP.Z\t%ld,%%L1\n"
3572
+                               "\tBC\t%%3\n", value-1);
3573
+                       return ggc_alloc_string(tmp, -1);
3574
+               }
3575
+       case GTU:
3576
+               if (value == 0) {
3577
+                       //; Equivalent to not equal to zero
3578
+                       return "CMP\t0,%H1\t; cbranchdi/# GTU 0\n\tCMP.Z\t0,%L1\n\tBNZ\t%3";
3579
+               } else {
3580
+                       char    tmp[128];
3581
+                       sprintf(tmp,
3582
+                               "CMP\t0,%%H1\t; cbranchdi/# GTU\n"
3583
+                               "\tBNZ\t%%3\n"
3584
+                               "\tCMP\t%ld,%%L1\n"
3585
+                               "\tBNC\t%%3\n", value+1);
3586
+                       return ggc_alloc_string(tmp, -1);
3587
+               }
3588
+       case GEU:
3589
+               if (value == 0) //; Unsigned, always true
3590
+                       return "BRA\t%3\t; cbranchdi/# GEU 0";
3591
+               else
3592
+                       return "CMP\t0,%H1\t; cbranchdi/# GEU\n"
3593
+                               "\tBNZ\t%3\n"
3594
+                               "\tCMP\t%2,%L1\n"
3595
+                               "\tBNC\t%3";
3596
+       default:
3597
+               gcc_unreachable();
3598
+       }
3599
+}
3600
+
3601
+const char *
3602
+zip_cbranchdi_reg(rtx comparison,
3603
+               rtx a ATTRIBUTE_UNUSED,
3604
+               rtx b ATTRIBUTE_UNUSED,
3605
+               rtx label ATTRIBUTE_UNUSED) {
3606
+
3607
+       switch(GET_CODE(comparison)) {
3608
+               case EQ:
3609
+                       return "CMP\t%H2,%H1\t; cbranchdi/r EQ\n\tCMP.Z\t%L2,%L1\n\tBZ\t%3";
3610
+               case NE:
3611
+                       return "CMP\t%H2,%H1\t; cbranchdi/r NE\n\tCMP.Z\t%L2,%L1\n\tBNZ\t%3";
3612
+               case LE:
3613
+                       return "CMP\t%H2,%H1\t; cbranchdi/r LE\n"
3614
+                               "\tBLT\t%3\n"
3615
+                               "\tBNZ\t.Ldi%=\n"
3616
+                               "\tCMP\t%L1,%L2\n"
3617
+                               "\tBNC\t%3\n"
3618
+                               ".Ldi%=:";
3619 127 dgisselq
+               case GT:
3620 202 dgisselq
+                       return "CMP\t%H1,%H2\t; cbranchdi/r GT\n"
3621
+                               "\tBLT\t%3\n"
3622
+                               "\tBNZ\t.Ldi%=\n"
3623
+                               "\tCMP\t%L1,%L2\n"
3624
+                               "\tBC\t%3\n"
3625
+                               ".Ldi%=:";
3626
+               case LT:
3627
+                       return "CMP\t%H2,%H1\t; cbranchdi/r LT\n"
3628
+                               "\tBLT\t%3\n"
3629
+                               "\tBNZ\t.Ldi%=\n"
3630
+                               "\tCMP\t%L2,%L1\n"
3631
+                               "\tBC\t%3\n"
3632
+                               ".Ldi%=:";
3633
+               case GE:
3634
+                       return "CMP\t%H1,%H2\t; cbranchdi/r GE\n"
3635
+                               "\tBLT\t%3\n"
3636
+                               "\tBNZ\t.Ldi%=\n"
3637
+                               "\tCMP\t%L2,%L1\n"
3638
+                               "\tBNC\t%3\n"
3639
+                               ".Ldi%=:";
3640
+               case LTU:
3641
+                       return "CMP\t%H2,%H1\t; cbranchdi/r LTU\n"
3642
+                               "\tCMP.Z\t%L2,%L1\n"
3643
+                               "\tBC\t%3\n";
3644
+               case LEU:
3645
+                       return "CMP\t%H1,%H2\t; cbranchdi/r LEU\n"
3646
+                               "\tBC\t.Ldi%=\n"        //; H1 > H2, skip
3647
+                               "\tCMP.Z\t%L1,%L2\n"    //; (H1==H2) test L1-L2
3648
+                               "\tBNC\t%3\n"           //; If (L1>=L2)||(H1>H2)
3649
+                               ".Ldi%=:";
3650
+               case GTU:
3651
+                       return "CMP\t%H1,%H2\t; cbranchdi/r GTU\n"
3652
+                               "\tCMP.Z\t%L1,%L2\n"
3653
+                               "\tBC\t%3";
3654
+               case GEU:
3655
+                       return "CMP\t%H2,%H1\t; cbranchdi/r GEU\n"
3656
+                               "\tBC\t.Ldi%=\n"
3657
+                               "\tCMP.Z\t%L2,%L1\n"
3658
+                               "\tBNC\t%3\n"
3659
+                               ".Ldi%=:";
3660
+               default:
3661
+                       gcc_unreachable();
3662
+       }
3663
+}
3664
+
3665
+const char *
3666
+zip_cbranchdi(rtx comparison, rtx a, rtx b, rtx label) {
3667
+       if (REG_P(b))
3668
+               return zip_cbranchdi_reg(comparison, a, b, label);
3669
+       else
3670
+               return zip_cbranchdi_const(comparison, a, b, label);
3671
+}
3672
+
3673
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zipdbg.h gcc-6.2.0-zip/gcc/config/zip/zipdbg.h
3674
--- gcc-6.2.0/gcc/config/zip/zipdbg.h   1969-12-31 19:00:00.000000000 -0500
3675
+++ gcc-6.2.0-zip/gcc/config/zip/zipdbg.h       2017-02-17 16:47:25.727651898 -0500
3676
@@ -0,0 +1,8 @@
3677
+#define        DO_ZIP_DEBUGS
3678
+#ifdef DO_ZIP_DEBUGS
3679
+#include <stdio.h>
3680
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
3681
+extern void    zip_debug_rtx(const_rtx);
3682
+#else
3683
+#define        ZIP_DEBUG_LINE(STR,RTX)
3684
+#endif
3685
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-di.md gcc-6.2.0-zip/gcc/config/zip/zip-di.md
3686
--- gcc-6.2.0/gcc/config/zip/zip-di.md  1969-12-31 19:00:00.000000000 -0500
3687
+++ gcc-6.2.0-zip/gcc/config/zip/zip-di.md      2018-06-05 18:57:29.386399718 -0400
3688
@@ -0,0 +1,548 @@
3689
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3690
+;;
3691
+;; Filename:   zip-di.md
3692
+;;
3693
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
3694
+;;
3695
+;; Purpose:    This is the machine description of the Zip CPU as needed by the
3696
+;;             GNU compiler collection (GCC).  Specifically, this is the
3697
+;;     section of the description associated with 64-bit values and
3698
+;;     arithmetic.
3699
+;;
3700
+;;
3701
+;; Creator:    Dan Gisselquist, Ph.D.
3702
+;;             Gisselquist Technology, LLC
3703
+;;
3704
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3705
+;;
3706
+;; Copyright (C) 2015-2018, Gisselquist Technology, LLC
3707 209 dgisselq
+;;
3708
+;; This program is free software (firmware): you can redistribute it and/or
3709 202 dgisselq
+;; modify it under the terms of  the GNU General Public License as published
3710
+;; by the Free Software Foundation, either version 3 of the License, or (at
3711
+;; your option) any later version.
3712
+;;
3713
+;; This program is distributed in the hope that it will be useful, but WITHOUT
3714
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
3715
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
3716
+;; for more details.
3717
+;;
3718
+;; License:    GPL, v3, as defined and found on www.gnu.org,
3719
+;;             http://www.gnu.org/licenses/gpl.html
3720
+;;
3721
+;;
3722
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3723
+;;
3724
+;;
3725
+;
3726 209 dgisselq
+;
3727 202 dgisselq
+;
3728
+(define_expand "movdi"
3729
+       [(set (match_operand:DI 0 "nonimmediate_operand" "")
3730
+               (match_operand:DI 1 "general_operand" ""))]
3731
+       "(ZIP_HAS_DI)"
3732
+       {
3733
+               if (zip_expand_movdi(operands[0], operands[1]))
3734
+                       DONE;
3735
+               FAIL;
3736
+       }
3737
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
3738
+;
3739
+;
3740
+;
3741
+(define_insn "movdi_raw"
3742
+       [(set (match_operand:DI 0 "nonimmediate_operand" "=r,Q,r,r")
3743
+               (match_operand:DI 1 "general_operand" "r,r,Q,i"))]
3744
+       "(ZIP_HAS_DI)"
3745
+       {
3746
+               if ((REG_P(operands[0]))&&(REG_P(operands[1])))
3747
+                       return  "MOV %H1,%H0\t; MOV:DI\n\tMOV %L1,%L0";
3748
+               else if (MEM_P(operands[0]))    //; StoreDI
3749
+                       return  "SW %H1,%0\t; Store:DI\n\tSW %L1,4+%0";
3750
+               else if (MEM_P(operands[1])) {  //; LoadDI
3751
+                       //; Deal with the case of
3752
+                       //;     LOD (R0),R0
3753
+                       //;     LOD 4(R0),R1
3754
+                       //; By reversing the order of the operands, to
3755
+                       //;     LOD 4(R0),R1
3756
+                       //;     LOD (R0),R0
3757
+                       //; This isn't efficient, so let's do whatever we can to
3758
+                       //; avoid this, still ... if we do it, we can make it
3759
+                       //; work
3760
+                       rtx     address = XEXP(operands[1],0);
3761
+                       int     hazard = 0;
3762
+                       if ( (REG_P(address))
3763
+                               &&((REGNO(address))==(REGNO(operands[0]))) )
3764
+                               hazard = 1;
3765
+                       else if ( (PLUS == (GET_CODE(address)))
3766
+                               &&(REGNO(XEXP(address,0))==(REGNO(operands[0]))) )
3767
+                               hazard = 1;
3768
+                       if (hazard)
3769
+                               return  "LW 4+%1,%L0\t; Load:DI\n\tLW %1,%H0";
3770 209 dgisselq
+                       else
3771
+                               return  "LW %1,%H0\t; Load:DI\n\tLW 4+%1,%L0";
3772
+               } else if (CONST_INT_P(operands[1])) {
3773
+                       char    tmp[128];
3774
+                       HOST_WIDE_INT   v = INTVAL(operands[1]);
3775
+                       sprintf(tmp, "LDI\t0x%08x,%%H0\t; LDI #:DI,%%H0\n\tLDI\t0x%08x,%%L0",
3776
+                               (unsigned)(v>>32),
3777
+                               (unsigned)(v));
3778
+                       return ggc_alloc_string(tmp, -1);
3779
+               } else
3780
+                       gcc_unreachable();
3781
+       }
3782
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
3783
+;
3784
+;
3785
+;
3786
+; ADD
3787
+;
3788
+;
3789
+(define_insn "adddi3" ; Fastest/best instruction always goes first
3790
+       [(set (match_operand:DI 0 "register_operand" "=r")
3791
+               (plus:DI (match_operand:DI 1 "register_operand" "0")
3792
+                       (match_operand:DI 2 "register_operand" "r")))
3793 202 dgisselq
+       (clobber (reg:CC CC_REG))
3794
+       ]
3795
+       "(ZIP_HAS_DI)"
3796
+       "ADD    %L2,%L0\n\tADD.C\t1,%H0\n\tADD\t%H2,%H0"
3797
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
3798
+;
3799
+;
3800
+;
3801
+; SUB
3802
+;
3803
+;
3804
+(define_insn "subdi3"
3805
+       [(set (match_operand:DI 0 "register_operand" "=r")
3806
+               (minus:DI (match_operand:DI 1 "register_operand" "0")
3807
+                       (match_operand:DI 2 "register_operand" "r")))
3808
+       (clobber (reg:CC CC_REG))
3809
+       ]
3810
+       "(ZIP_HAS_DI)"
3811
+       "SUB    %L2,%L0\n\tSUB.C\t1,%H0\n\tSUB\t%H2,%H0"
3812
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
3813
+;
3814
+;
3815
+;
3816
+; AND
3817
+;
3818
+;
3819
+(define_insn "anddi3"
3820
+       [(set (match_operand:DI 0 "register_operand" "=r")
3821
+               (and:DI (match_operand:DI 1 "register_operand" "%0")
3822
+                       (match_operand:DI 2 "register_operand" "r")))
3823
+       (clobber (reg:CC CC_REG))
3824
+       ]
3825
+       "(ZIP_HAS_DI)"
3826
+       "AND    %L2,%L0\t; AND:DI\n\tAND\t%H2,%H0"
3827
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
3828
+;
3829
+;
3830
+;
3831
+; iOR
3832
+;
3833
+;
3834
+(define_insn "iordi3"
3835
+       [(set (match_operand:DI 0 "register_operand" "=r")
3836
+               (ior:DI (match_operand:DI 1 "register_operand" "%0")
3837
+                       (match_operand:DI 2 "register_operand" "r")))
3838
+       (clobber (reg:CC CC_REG))
3839
+       ]
3840
+       "(ZIP_HAS_DI)"
3841
+       "OR     %L2,%L0\t; OR:DI\n\tOR\t%H2,%H0"
3842
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
3843
+;
3844
+;
3845
+;
3846
+; XOR
3847
+;
3848
+;
3849
+(define_insn "xordi3"
3850
+       [(set (match_operand:DI 0 "register_operand" "=r")
3851
+               (xor:DI (match_operand:DI 1 "register_operand" "%0")
3852
+                       (match_operand:DI 2 "register_operand" "r")))
3853
+       (clobber (reg:CC CC_REG))
3854
+       ]
3855
+       "(ZIP_HAS_DI)"
3856
+       "XOR    %L2,%L0\t; XOR:DI\n\tXOR\t%H2,%H0"
3857
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
3858
+;
3859
+;
3860
+; NEG
3861
+;
3862
+;
3863
+(define_insn "negdi2"
3864
+       [(set (match_operand:DI 0 "register_operand" "=r")
3865
+               (neg:DI (match_operand:DI 1 "register_operand" "0")))
3866
+       (clobber (reg:CC CC_REG))
3867
+       ]
3868
+       "(ZIP_HAS_DI)"
3869
+       "XOR    -1,%L0\t; NEG:DI\n\tXOR\t-1,%H0\n\tADD\t1,%L0\n\tADD.C\t1,%H0"
3870
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
3871
+;
3872
+;
3873
+;
3874
+; ABS
3875
+;
3876
+;
3877
+(define_insn "absdi2"
3878
+       [(set (match_operand:DI 0 "register_operand" "=r")
3879
+               (abs:DI (match_operand:DI 1 "register_operand" "0")))
3880
+       (clobber (match_scratch:SI 2 "=r"))
3881
+       (clobber (reg:CC CC_REG))
3882
+       ]
3883
+       "(ZIP_HAS_DI)"
3884
+       "CLR    %2      ; ABSDI
3885
+       TEST    %H0
3886
+       LDILO.LT        1,%2
3887
+       XOR.LT  -1,%L0
3888
+       XOR.LT  -1,%H0
3889
+       ADD     %2,%L0
3890
+       ADD.C   1,%H0"
3891
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
3892
+;
3893
+;
3894
+; NOT
3895
+;
3896
+;
3897
+(define_insn "one_cmpldi2"
3898
+       [(set (match_operand:DI 0 "register_operand" "=r")
3899
+               (not:DI (match_operand:DI 1 "register_operand" "0")))
3900
+       (clobber (reg:CC CC_REG))
3901
+       ]
3902
+       "(ZIP_HAS_DI)"
3903
+       "XOR    -1,%L0\t; NOT:DI\n\tXOR\t-1,%H0"
3904
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
3905
+;
3906
+;
3907
+; Unsigned min/max
3908
+;
3909
+;
3910
+(define_insn "umindi3"
3911
+       [(set (match_operand:DI 0 "register_operand" "=r")
3912
+               (umin:DI (match_operand:DI 1 "register_operand" "%0")
3913
+                       (match_operand:DI 2 "register_operand" "r")))
3914
+       (clobber (reg:CC CC_REG))
3915
+       ]
3916
+       "(ZIP_HAS_DI)"
3917
+       "CMP    %H0,%H2 ; umin:DI
3918
+       CMP.Z   %L0,%L2
3919
+       MOV.C   %H2,%H0
3920
+       MOV.C   %L2,%L0"
3921
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
3922
+(define_insn "umaxdi3"
3923
+       [(set (match_operand:DI 0 "register_operand" "=r")
3924
+               (umax:DI (match_operand:DI 1 "register_operand" "%0")
3925
+                       (match_operand:DI 2 "register_operand" "r")))
3926
+       (clobber (reg:CC CC_REG))
3927
+       ]
3928
+       "(ZIP_HAS_DI)"
3929
+       "CMP    %H2,%H0 ; umax:DI
3930
+       CMP.Z   %L2,%L0
3931
+       MOV.C   %H2,%H0
3932
+       MOV.C   %L2,%L0"
3933
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
3934
+;
3935
+;
3936
+; Multiply
3937
+;
3938
+;
3939
+(define_expand "muldi3"
3940
+       [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
3941
+               (mult:DI (match_operand:DI 1 "register_operand" "r")
3942
+                       (match_operand:DI 2 "register_operand" "r")))
3943
+       (clobber (match_dup 1))
3944
+       (clobber (match_dup 2))
3945
+       (clobber (match_scratch:SI 3 "=r"))
3946
+       (clobber (reg:CC CC_REG))])]
3947
+       "(ZIP_HAS_DI)")
3948
+;
3949
+(define_insn "muldi3_raw"
3950
+       [(set (match_operand:DI 0 "register_operand" "=r")
3951
+               (mult:DI (match_operand:DI 1 "register_operand" "r")
3952
+                       (match_operand:DI 2 "register_operand" "r")))
3953
+       (clobber (match_dup 1))
3954
+       (clobber (match_dup 2))
3955
+       (clobber (match_scratch:SI 3 "=r"))
3956
+       (clobber (reg:CC CC_REG))]
3957
+       "(ZIP_HAS_DI)"
3958
+       {
3959
+               int     regno[3];
3960
+               regno[0] = REGNO(operands[0]);
3961
+               regno[1] = REGNO(operands[1]);
3962
+               regno[2] = REGNO(operands[2]);
3963
+               //; We need to adjust what we are doing based upon which
3964
+               //; registers are in common.  We have a couple of cases:
3965
+               //;
3966
+               if ((regno[0] == regno[1])&&(regno[0] == regno[2])) {
3967
+                       //; RA = RA * RA
3968
+                       //;
3969
+                       //; (H0:L0) = (H0:L0) * (H0:L0)
3970
+                       //; (H0:L0) = (H0*2^32 + L0) * (H0 * 2^32 + L0)
3971
+                       //; (H0:L0) = (H0*H0*2^64 + (H0*L0+L0*H0)*2^32 + L0 *L0)
3972
+                       //;     = (H0*L0+L0*H1):(L0*L0)
3973
+                       //;    :L0  = LOPART(L0 * L0)
3974
+                       //;  H0     = HIPART(L0 * L0)
3975
+                       //;  H0    += LOPART(H0 * L0)
3976
+                       //;  H0    += LOPART(L0 * H0)
3977
+                       //;
3978
+                       //;  Rx = L0
3979
+                       //;  H0 *= L0  ( =   LOPART( HI * LO )
3980
+                       //;  H0 <<= 1  ( = 2*LOPART( HI * LO ) )
3981
+                       //;  Rx *= L0  ( =   HIPART( LO * LO )
3982
+                       //;  L0 *= L0  ( =   LOPART( LO * LO )
3983
+                       //;  H0 += Rx  ( = 2*LOPART( HI * LO ) + HIPART( LO *LO)
3984
+                       //;
3985
+                       return "; muldi3_raw/A (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
3986
+                               "\tMOV\t%L0,%3\n"
3987
+                               "\tMPY\t%L0,%H0\n"
3988
+                               "\tLSL\t1,%H0\n"
3989
+                               "\tMPYUHI\t%L0,%3\n"
3990
+                               "\tMPY\t%L0,%L0\n"
3991
+                               "\tADD\t%3,%H0";
3992
+               } else if ((regno[0] != regno[1])&&(regno[1] == regno[2])) {
3993
+                       //; RA = RB * RB
3994
+                       //;
3995
+                       //; (H0:L0) = (H1:L1) * (H1:L1)
3996
+                       //; (H0:L0) = (H1*2^32 + L1) * (H1 * 2^32 + L1)
3997
+                       //; (H0:L0) = (H1*H1*2^64 + (H1*L1+L1*H1)*2^32 + L1 * L1)
3998
+                       //;     = (H1*L1+L1*H1):(L1*L1)
3999
+                       //;    :L0  = LOPART(L1 * L1)
4000
+                       //;  H0     = HIPART(L1 * L1)
4001
+                       //;  H0    += LOPART(H1 * L1)
4002
+                       //;  H0    += LOPART(L1 * H1)
4003
+                       //;
4004
+                       //; -------------------
4005
+                       //;     L0  = L1
4006
+                       //;     L0  = LOPART(L0 * L1)
4007
+                       //;     H0  = H1
4008
+                       //;     H0  = LOPART(H0 * L1)
4009
+                       //;     H0 <<= 1;       i.e. *= 2
4010
+                       //;     L1  = HIPART(L1 * L1)
4011
+                       //;     H0 += L1
4012
+                       //;
4013
+                       return "; muldi3_raw/B (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
4014
+                       "\tMOV\t%L1,%L0\n"
4015
+                       "\tMPY\t%L1,%L0\n"
4016
+                       "\tMOV\t%H1,%H0\n"
4017
+                       "\tMPY\t%H1,%H0\n"
4018
+                       "\tLSL\t1,%H0\n"
4019
+                       "\tMPY\t%L1,%L1\n"
4020
+                       "\tADD\t%L2,%H0";
4021
+               } else if ((regno[0] == regno[1])&&(regno[1] != regno[2])) {
4022
+                       //; RA = RA * RB, with scratch Rx
4023
+                       //;
4024
+                       //; (H0:L0) = (H0:L0) * (H1:L1)
4025
+                       //; (H0:L0) = (H0*2^32 + L0) * (H1 * 2^32 + L1)
4026
+                       //; (H0:L0) = (H0*H1*2^64 + (H0*L1+L0*H1)*2^32 + L0 *L1)
4027
+                       //;     = (H0*L1+L0*H1):(L0*L1)
4028
+                       //;     Rx  = L0
4029
+                       //;    :L0  = LOPART(L1 * R0)
4030
+                       //;  H0     = LOPART(H0 * L1)
4031
+                       //;  H0    += H1 = LOPART(Rx * H1)
4032
+                       //;  H0    += HIPART(L1 * Rx)
4033
+                       //;
4034
+                       return "; muldi3_raw/C (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
4035
+                       "\tMOV\t%L0,%3\n"
4036
+                       "\tMPY\t%L1,%L0\n"
4037
+                       "\tMOV\t%L1,%H0\n"
4038
+                       "\tMPY\t%H1,%H0\n"
4039
+                       "\tMPY\t%3,%H1\n"
4040
+                       "\tADD\t%H1,%H0\n"
4041
+                       "\tMPY\t%3,%L1\n"
4042
+                       "\tADD\t%L1,%H0";
4043
+               } else {
4044
+                       //; RA = RB * RC
4045
+                       //;
4046
+                       //; (H0:L0) = (H1:L1) * (H2:L2)
4047
+                       //; (H0:L0) = (H1*2^32 + L1) * (H2 * 2^32 + L2)
4048
+                       //; (H0:L0) = (H1*H2*2^64 + (H1*L2+L1*H2)*2^32 + L1 *L2)
4049
+                       //;     = (H1*L2+L1*H2):(L1*L2)
4050
+                       //;    :L0  = LOPART(L1 * L2)
4051
+                       //;  H0     = HIPART(L1 * L2)
4052
+                       //;  H0    += LOPART(H1 * L2)
4053
+                       //;  H0    += LOPART(L1 * H2)
4054
+                       //;
4055
+                       //; We can re-order this to try to save some registers
4056
+                       //;
4057
+                       //;     H1 *= L0                // Was H1 * L2
4058
+                       //;    :L0  = LOPART(L1 * L2)
4059
+                       //;  H0     = LOPART(L1 * R1)
4060
+                       //;  H0    += HIPART(L1 * H2)
4061
+                       //;  H0    += H1
4062
+                       //;
4063
+                    return "; muldi3_raw/D (%H0:%L0) = (%H1:%L1) * (%H2:%L2)\n"
4064
+                       "\tMPY  %L2,%H1 ; H1 = H1 * L2\n"
4065
+                       "\tMPY  %L1,%H2 ; H2 = L1 * L2\n"
4066
+                       "\tMOV  %L2,%L0 ; H0:L0 = L1 * L2\n"
4067
+                       "\tMOV  %L2,%H0\n"
4068
+                       "\tMPY  %L1,%L0\n"
4069
+                       "\tMPYUHI       %L1,%H0\n"
4070
+                       "\tADD  %H2,%H0 ; H0 += (H2 = L1 * H2)\n"
4071
+                       "\tADD  %H1,%H0 ; H0 += (H1 = H1 * L2)";
4072
+               }
4073
+       }
4074
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
4075
+;
4076
+;
4077
+; Still missing DI instructions for smin:DI, smax:DI, movdicc, adddicc,
4078
+;      div:di, divu:di (library routine)
4079
+;
4080
+;
4081
+;
4082
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4083
+;;
4084
+;; Conditional arithmetic instructions
4085
+;;
4086
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4087
+;
4088
+;
4089
+;
4090
+;
4091
+(define_insn "cstoredi4" ; Store 0 or 1 in %0 based on cmp between %2&%3
4092
+       [(set (match_operand:SI 0 "register_operand" "=r")
4093
+               (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
4094
+                       [(match_operand:DI 2 "register_operand" "r")
4095
+                               (match_operand:DI 3 "register_operand" "r")])
4096
+                       (const_int 1) (const_int 0)))
4097
+       (clobber (reg:CC CC_REG))]
4098
+       "(ZIP_HAS_DI)&&(0)"
4099
+       {
4100
+               switch(GET_CODE(operands[1])) {
4101
+               case EQ:        return "CLR\t%0\t; CSTORE-EQ\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.Z\t1,%0\n";
4102
+               case NE:        return "CLR\t%0\t; CSTORE-NE\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.NZ\t1,%0\n";
4103
+               //; Missing LT
4104
+               //; Missing LE
4105
+               //; Missing GT
4106
+               //; Missing GE
4107
+               case LTU:       return "CLR\t%0\t; CSTORE-LTU\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.C\t1,%0\n";
4108
+               case LEU:
4109
+                       return "CLR\t%0\t; CSTORE-LEU\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.NC\t1,%0\n";
4110
+               case GTU:       return "CLR\t%0\t; CSTORE-GTU\n\tCMP\t%H2,%H3\n\tCMP.Z\t%L2,%L3\n\tLDILO.C\t1,%0\n";
4111
+               case GEU:
4112
+                       return "CLR\t%0\t; CSTORE-GEU\n\tCMP\t%H3,%H2\n\tCMP.Z\t%L3,%L2\n\tLDILO.NC\t1,%0\n";
4113
+               default:
4114
+                       gcc_unreachable();
4115
+               }
4116
+       }
4117
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
4118
+;
4119
+;
4120
+;
4121
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4122
+;;
4123
+;; Comparison instructions, both compare and test
4124
+;;
4125
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4126
+;
4127
+;
4128
+;
4129
+(define_expand "cmpdi"
4130
+       [(set (reg:CC CC_REG) (compare:CC
4131
+               (match_operand:DI 0 "register_operand" "r")
4132
+               (match_operand:DI 1 "nonmemory_operand" "")))]
4133
+       ""
4134
+       {
4135
+               if (!REG_P(operands[1])) {
4136
+                       if (can_create_pseudo_p()) {
4137
+                               //; fprintf(stderr, "Generating pseudo register for compare\n");
4138
+                               rtx tmp = gen_reg_rtx(DImode);
4139
+                               emit_insn(gen_movdi(tmp,operands[1]));
4140
+                               operands[1] = tmp;
4141
+                               emit_insn(gen_cmpdi_reg(operands[0],tmp));
4142
+                               DONE;
4143
+                       } else FAIL;
4144
+               }
4145
+       })
4146
+(define_insn "cmpdi_reg"
4147
+       [(set (reg:CC CC_REG) (compare:CC
4148
+               (match_operand:SI 0 "register_operand" "r")
4149
+               (match_operand:SI 1 "register_operand" "r")))]
4150
+       ""
4151
+       "CMP\t%H1,%H0
4152
+       CMP.Z\t%L1,%L0"
4153
+       [(set_attr "ccresult" "set")])
4154
+;
4155
+;
4156
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4157
+;;
4158
+;; Conditional move instructions, since these won't accept conditional
4159
+;;     execution RTL
4160
+;;
4161
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4162
+;
4163
+(define_expand "cbranchdi4"
4164
+       [(set (pc) (if_then_else
4165
+               (match_operator 0 "ordered_comparison_operator"
4166
+                       [(match_operand:DI 1 "register_operand" "r")
4167
+                               (match_operand:DI 2 "nonimmediate_operand" "")])
4168
+                       (label_ref (match_operand 3 "" ""))
4169
+                       (pc)))
4170
+       (clobber (reg:CC CC_REG))]
4171
+       "(ZIP_HAS_DI)"
4172
+       {
4173
+               if (!REG_P(operands[2])) {
4174
+                       if ((CONST_INT_P(operands[2]))
4175
+                               &&(INTVAL(operands[2])> -(1l<<17))
4176
+                               &&(INTVAL(operands[2])<(1l<<17)-1)) {
4177
+                               emit_jump_insn(gen_cbranchdi4_internal(operands[0],
4178
+                                       operands[1], operands[2], operands[3]));
4179
+                               DONE;
4180
+                       } if (can_create_pseudo_p()) {
4181
+                               rtx tmp = gen_reg_rtx(DImode);
4182
+                               emit_insn(gen_movsi(tmp, operands[2]));
4183
+                               operands[2] = tmp;
4184
+                       }
4185
+               }
4186
+
4187
+               if (REG_P(operands[2])) {
4188
+                       emit_jump_insn(gen_cbranchdi4_internal(operands[0],
4189
+                               operands[1], operands[2], operands[3]));
4190
+                       DONE;
4191
+               }
4192
+       })
4193
+(define_insn "cbranchdi4_internal"
4194
+       [(set (pc) (if_then_else
4195
+               (match_operator 0 "ordered_comparison_operator"
4196
+                       [(match_operand:DI 1 "register_operand" "r,r,r")
4197
+                               (match_operand:DI 2 "nonmemory_operand" "K,x,r")])
4198
+                       (label_ref (match_operand 3 "" ""))
4199
+                       (pc)))
4200
+       (clobber (reg:CC CC_REG))]
4201
+       "(ZIP_HAS_DI)"
4202
+       {
4203
+               return zip_cbranchdi(operands[0], operands[1], operands[2], operands[3]);
4204
+       }
4205
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
4206
+;
4207
+;
4208
+;
4209
+;
4210
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4211
+;;
4212
+;; Unimplemented (or not yet implemented) RTL Codes
4213
+;;
4214
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4215
+;
4216
+;
4217
+;
4218
+;
4219
+;(define_insn "addvdi4"
4220
+;      )
4221
+;(define_insn "subvdi4"
4222
+;      )
4223
+;(define_insn "mulvdi4"
4224
+;      )
4225
+;(define_insn "umulvdi4"
4226
+;      )
4227
+;(define_insn "umulvdi4"
4228
+;      )
4229
+;(define_insn "negvdi3"
4230
+;      )
4231
+;
4232
+;(define_insn "maddsidi4"
4233
+;(define_insn "umaddsidi4"
4234
+;(define_insn "msubsidi4"
4235
+;(define_insn "umsubsidi4"
4236
+;
4237
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-float.md gcc-6.2.0-zip/gcc/config/zip/zip-float.md
4238
--- gcc-6.2.0/gcc/config/zip/zip-float.md       1969-12-31 19:00:00.000000000 -0500
4239
+++ gcc-6.2.0-zip/gcc/config/zip/zip-float.md   2017-01-10 14:01:42.029341062 -0500
4240
@@ -0,0 +1,138 @@
4241
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4242
+;;
4243
+;; Filename:   zip-float.md
4244
+;;
4245
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
4246
+;;
4247
+;; Purpose:    This is the machine description of the ZipCPU floating point
4248
+;;             unit (if installed).
4249
+;;
4250
+;;
4251
+;; Creator:    Dan Gisselquist, Ph.D.
4252
+;;             Gisselquist Technology, LLC
4253
+;;
4254
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4255
+;;
4256
+;; Copyright (C) 2015,2017, Gisselquist Technology, LLC
4257
+;;
4258
+;; This program is free software (firmware): you can redistribute it and/or
4259
+;; modify it under the terms of  the GNU General Public License as published
4260 200 dgisselq
+;; by the Free Software Foundation, either version 3 of the License, or (at
4261
+;; your option) any later version.
4262
+;;
4263
+;; This program is distributed in the hope that it will be useful, but WITHOUT
4264
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
4265
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
4266
+;; for more details.
4267
+;;
4268
+;; License:    GPL, v3, as defined and found on www.gnu.org,
4269
+;;             http://www.gnu.org/licenses/gpl.html
4270
+;;
4271
+;;
4272
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4273
+;;
4274
+;;
4275
+;
4276 202 dgisselq
+;
4277 200 dgisselq
+;
4278
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4279
+;;
4280
+;; Floating point Op-codes
4281
+;;
4282
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4283
+;
4284
+;
4285
+;
4286
+(define_insn "addsf3"
4287
+       [(set (match_operand:SF 0 "register_operand" "=r")
4288
+               (plus:SF (match_operand:SF 1 "register_operand" "0")
4289
+                       (match_operand:SF 2 "register_operand" "r")))
4290
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
4291
+       "(ZIP_FPU)"
4292
+       "FPADD  %2,%0"
4293
+       [(set_attr "ccresult" "unknown")])
4294
+(define_insn "subsf3"
4295
+       [(set (match_operand:SF 0 "register_operand" "=r")
4296
+               (minus:SF (match_operand:SF 1 "register_operand" "0")
4297
+                       (match_operand:SF 2 "register_operand" "r")))
4298
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
4299
+       "(ZIP_FPU)"
4300
+       "FPSUB  %2,%0"
4301
+       [(set_attr "ccresult" "unknown")])
4302
+(define_insn "mulsf3"
4303
+       [(set (match_operand:SF 0 "register_operand" "=r")
4304
+               (mult:SF (match_operand:SF 1 "register_operand" "0")
4305
+                       (match_operand:SF 2 "register_operand" "r")))
4306
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
4307
+       "(ZIP_FPU)"
4308
+       "FPMUL  %2,%0"
4309
+       [(set_attr "ccresult" "unknown")])
4310
+(define_insn "divsf3"
4311
+       [(set (match_operand:SF 0 "register_operand" "=r")
4312
+               (div:SF (match_operand:SF 1 "register_operand" "0")
4313
+                       (match_operand:SF 2 "register_operand" "r")))
4314
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
4315
+       "(ZIP_FPU)"
4316
+       "FPDIV  %2,%0"
4317
+       [(set_attr "ccresult" "unknown")])
4318
+; (define_insn "floatsisf2"
4319
+;      [(set (match_operand:SF 0 "register_operand" "=r"
4320
+;              (float:QI (match_operand:SF 1 "register_operand" "r"))))
4321
+;      (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
4322
+;      "(ZIP_FPU)"
4323
+;      "FPI2F  %1,%0")
4324
+; (define_insn "floatunssisf2" ... ?)
4325
+; (define_insn "fix_truncsfsi2"
4326
+;      [(set (match_operand:QI 0 "register_operand" "=r"
4327
+;              (float:SF (match_operand:SF 1 "register_operand" "r"))))
4328
+;      (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))]
4329
+;      "(ZIP_FPU)"
4330
+;      "FPI2F  %1,%0")
4331
+; (define_insn "nearbyintsf2" ... ?)
4332
+; (define_insn "truncsfsi2" ... ?)
4333
+(define_expand "negsf2"
4334
+       [(set (match_operand:SF 0 "register_operand" "=r")
4335
+               (neg:SF (match_operand:SF 1 "register_operand" "0")))
4336
+       ]
4337
+       ""
4338
+       {
4339
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
4340 202 dgisselq
+               if (can_create_pseudo_p()) {
4341 200 dgisselq
+                       rtx tmp = gen_reg_rtx(SImode);
4342
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x80000000,SImode)));
4343
+                       emit_insn(gen_xorsi3(operands[0], operands[0], tmp));
4344
+                       DONE;
4345
+               } else {
4346 202 dgisselq
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
4347 200 dgisselq
+                       emit_insn(gen_iorsi3(operands[0], operands[0],
4348
+                               gen_int_mode(1,SImode)));
4349
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
4350
+                       DONE;
4351
+               }
4352
+       })
4353
+(define_expand "abssf2"
4354
+       [(set (match_operand:SF 0 "register_operand" "=r")
4355
+               (abs:SF (match_operand:SF 1 "register_operand" "0")))
4356
+       ]
4357
+       ""
4358
+       {
4359
+               operands[0] = gen_rtx_SUBREG(SImode, operands[0], 0);
4360
+               if (can_create_pseudo_p()) {
4361
+                       rtx tmp = gen_reg_rtx(SImode);
4362
+                       emit_insn(gen_movsi_ldi(tmp,gen_int_mode(0x7fffffff,SImode)));
4363
+                       emit_insn(gen_andsi3(operands[0], operands[0], tmp));
4364
+                       DONE;
4365
+               } else {
4366
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
4367
+                       emit_insn(gen_andsi3(operands[0], operands[0],
4368
+                               gen_int_mode(-2,SImode)));
4369
+                       emit_insn(gen_zip_bitrev(operands[0],operands[0]));
4370
+                       DONE;
4371
+               }
4372
+       })
4373
+;
4374
+;
4375
+; STILL MISSING:
4376
+;
4377
+;
4378
+;
4379
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.h gcc-6.2.0-zip/gcc/config/zip/zip.h
4380
--- gcc-6.2.0/gcc/config/zip/zip.h      1969-12-31 19:00:00.000000000 -0500
4381
+++ gcc-6.2.0-zip/gcc/config/zip/zip.h  2018-06-05 22:22:38.581639662 -0400
4382
@@ -0,0 +1,4114 @@
4383
+////////////////////////////////////////////////////////////////////////////////
4384
+//
4385
+// Filename:   gcc/config/zip/zip.h
4386
+//
4387
+// Project:    Zip CPU backend for the GNU Compiler Collection
4388
+//
4389
+// Purpose:
4390
+//
4391
+// Creator:    Dan Gisselquist, Ph.D.
4392
+//             Gisselquist Technology, LLC
4393
+//
4394
+////////////////////////////////////////////////////////////////////////////////
4395
+//
4396
+// Copyright (C) 2016-2017, Gisselquist Technology, LLC
4397
+//
4398
+// This program is free software (firmware): you can redistribute it and/or
4399 202 dgisselq
+// modify it under the terms of  the GNU General Public License as published
4400
+// by the Free Software Foundation, either version 3 of the License, or (at
4401 209 dgisselq
+// your option) any later version.
4402 202 dgisselq
+//
4403 102 dgisselq
+// This program is distributed in the hope that it will be useful, but WITHOUT
4404
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
4405
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
4406
+// for more details.
4407
+//
4408
+// You should have received a copy of the GNU General Public License along
4409
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
4410
+// target there if the PDF file isn't present.)  If not, see
4411
+// <http://www.gnu.org/licenses/> for a copy.
4412
+//
4413
+// License:    GPL, v3, as defined and found on www.gnu.org,
4414
+//             http://www.gnu.org/licenses/gpl.html
4415
+//
4416 202 dgisselq
+//
4417 102 dgisselq
+////////////////////////////////////////////////////////////////////////////////
4418
+#ifndef        GCC_ZIP_H
4419
+#define        GCC_ZIP_H
4420
+
4421
+
4422
+//
4423
+//
4424
+// Zip CPU configuration defines
4425
+//
4426
+//
4427
+#define        ZIP_USER        0        // Assume we are in supervisor mode
4428
+#define        ZIP_MULTIPLY    1       // Assume we have multiply instructions
4429
+#define        ZIP_DIVIDE      1       // Assume we have divide instructions
4430
+#define        ZIP_FPU         0        // Assume we have no floating point instructions
4431
+#define        ZIP_PIPELINED   1       // Assume our instructions are pipelined
4432
+#define        ZIP_THUMB       1       // Assume we have the THUMB feature
4433
+#define        ZIP_ATOMIC      (ZIP_PIPELINED)
4434
+#define        ZIP_PIC         0        // Attempting to produce PIC code, with GOT
4435
+#define        ZIP_HAS_DI      1
4436
+// Should we use the peephole optimizations?
4437
+#define        ZIP_PEEPHOLE    1       // 0 means no peephole optimizations.
4438
+#define        ZIP_NOT_AN_INSTRUCTION  "NAI\t;// This is not an instruction.  Getting here implies a compiler error.  Please contact help support\n"
4439
+
4440
+// Zip has 16 registers in each user mode.
4441
+//     Register 15 is the program counter (PC)
4442
+//     Register 14 is the condition codes (CC)
4443
+//     Register 13 is the stack pointer   (SP)
4444 127 dgisselq
+//     Register 12 (may be) the Global Offset Table pointer (GOT)
4445 102 dgisselq
+//     Register  0 (may be) the return address pointer
4446
+// Registers 16-31 may only be used in supervisor mode.
4447
+#define        is_ZIP_GENERAL_REG(REGNO)       ((REGNO)<13)
4448
+#define        is_ZIP_REG(REGNO)               ((REGNO)<33)
4449
+
4450
+#define        zip_AP_PSEUDO   32
4451
+#define        zip_PC          15
4452 202 dgisselq
+#define        zip_CC          14
4453 200 dgisselq
+#define        zip_SP          13
4454 102 dgisselq
+#define        zip_FP          12
4455
+#define        zip_GOT         11
4456 127 dgisselq
+// #define     zip_AP          10      // We're using a PSEUDO REG instead
4457
+#define        zip_R5          5       // Used for the static chain, if it exists
4458 202 dgisselq
+#define        zip_R1          1
4459 102 dgisselq
+#define        zip_R0          0
4460
+#define        zip_LR          zip_R0  // Link Register is also R0
4461
+
4462
+#define        ZIP_FIRST_ARG_REGNO     1
4463
+#define        ZIP_LAST_ARG_REGNO      5
4464
+#define        NUM_ARG_REGS            (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
4465
+#define        MAX_PARM_REGS           (ZIP_LAST_ARG_REGNO-ZIP_FIRST_ARG_REGNO+1)
4466
+
4467
+/* The overall framework of an assembler file */
4468 171 dgisselq
+
4469 102 dgisselq
+#define        ASM_COMMENT_START       ";"
4470 171 dgisselq
+#define        ASM_APP_ON              ""
4471 103 dgisselq
+#define        ASM_APP_OFF             ""
4472
+
4473
+#define        FILE_ASM_OP             "\t.file\n"
4474
+
4475
+/* Output and Generation of Labels */
4476 171 dgisselq
+#define        GLOBAL_ASM_OP           "\t.global\t"
4477 202 dgisselq
+
4478 103 dgisselq
+#define        BITS_PER_WORD           32
4479
+
4480 202 dgisselq
+
4481 102 dgisselq
+/* A C compound statement to output to stdio stream STREAM the assembler syntax
4482
+ * for an instruction operand X. */
4483
+#define        PRINT_OPERAND(STREAM, X, CODE)  zip_print_operand(STREAM, X, CODE)
4484 111 dgisselq
+#define        PRINT_OPERAND_ADDRESS(STREAM, X) zip_print_operand_address(STREAM, X)
4485
+
4486 102 dgisselq
+/* Passing arguments in registers */
4487
+#define        FUNCTION_VALUE_REGNO_P(REGNO)   ((REGNO)==zip_R1)
4488
+
4489
+/* Define how to find the value returned by a function.  VALTYPE is the data
4490
+ * type of the value (as a tree).  If the precise function being called is known
4491
+ * FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */
4492
+#define        FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG(TYPE_MODE(VALTYPE), zip_R1)
4493
+
4494
+/* Define how to find the value returned by a library function assuming the
4495
+ * value has mode MODE.
4496
+ */
4497
+#define        LIBCALL_VALUE(MODE)     gen_rtx_REG(MODE, zip_R1)
4498 202 dgisselq
+
4499 102 dgisselq
+
4500
+/* STACK AND CALLING */
4501
+
4502
+
4503
+/* Define this macro as a C expression that is nonzero for registers that are
4504
+ * used by the epilogue or the return pattern.  The stack and frame pointer
4505
+ * registers are already assumed to be used as needed.
4506
+ */
4507
+#define        EPILOGUE_USES(R)        (R == RETURN_ADDRESS_REGNUM)
4508
+
4509
+
4510
+/* The best alignment to use in cases where we have a choice. */
4511
+#define        FASTEST_ALIGNMENT       BITS_PER_WORD
4512
+
4513
+/* Generate Code for Profiling
4514
+ */
4515
+#define        FUNCTION_PROFILER(FILE,LABELNO)         (abort(), 0)
4516
+
4517
+
4518
+/* A C expression which is nonzero if register number NUM is suitable for use
4519
+ * as an index register in operand addresses.
4520
+ */
4521
+#define        REGNO_OK_FOR_INDEX_P(NUM)       0
4522
+
4523
+
4524
+/* A C compound statement with a conditional 'goto LABEL;' executed if X
4525
+ * (an RTX) is a legitimate memory address on the target machine for a memory
4526
+ * operand of mode MODE.
4527
+ */
4528
+/* 17.03 Controlling the Compilation Driver, 'gcc' */
4529
+// DRIVER_SELF_SPECS
4530
+// OPTION_DEFAULT_SPECS
4531 127 dgisselq
+// CPP_SPEC
4532 102 dgisselq
+// CPLUSPLUS_CPP_SPEC
4533
+// CC1_SPEC
4534
+// CC1PLUS_SPEC
4535
+/* ASM_SPEC ... A C string constant that tells the GCC driver program options
4536
+ * to pass to the assembler.  It can also specify how to translate options you
4537
+ * give to GCC into options for GCC to pass to the assembler.  See the file
4538
+ * 'sun3.h' for an example of this.
4539
+ *
4540
+ * Do not define thismacro if it does not need to do anything.
4541
+ */
4542
+// #undef      ASM_SPEC
4543
+// ASM_FINAL_SPEC
4544
+// ASM_NEEDS_DASH_FOR_PIPED_INPUT
4545
+
4546
+/* LINK_SPEC ... A C string constant that tells the GCC driver program options
4547
+ * to pass to the linker.  It can also specify how to translate options you give
4548 111 dgisselq
+ * to GCC into options for GCC to pass to the linker.
4549
+ *
4550
+ * Do not define this macro if it does not need to do anything.
4551
+ */
4552
+
4553
+/* LIB_SPEC ... Another C string constant very much like LINK_SPEC.  The
4554
+ * difference between the two is that LIB_SPEC is used at the end of the
4555
+ * command given to the linker.
4556
+ *
4557
+ * If this macro is not defined, a default is provided that loads the standard
4558
+ * C library from the usual place.  See 'gcc.c'.
4559
+ *
4560
+ * ZipCPU ... We need this at its default value.  It is necessary to build
4561
+ * the various GCC libraries that depend upon one another and newlib.  Hence,
4562
+ * as an example we *must* include the library containing strnlen or libgfortran
4563
+ * will not.  Alternatively, we might figure out how to pass arguments to the
4564
+ * compiler via the configure process ... but we'll just allow this to have its
4565
+ * default value for now.
4566
+ */
4567
+// #undef      LIB_SPEC
4568
+// #define     LIB_SPEC        "%{!g:-lc} %{g:-lg} -lzip"
4569
+// #define     LIB_SPEC        ""
4570
+
4571
+/* LIBGCC_SPEC ... Another C string constant that tells the GCC driver program
4572
+ * hoow and when to place a reference to 'libgcc.a' into the linker command
4573
+ * line.  This constant is placed both before and after the value of LIB_SPEC.
4574
+ *
4575
+ * If this macro is not defined, the GCC driver provides a default that passes
4576
+ * the string '-lgcc' to the linker.
4577
+ */
4578
+// #undef      LIBGCC_SPEC
4579 202 dgisselq
+// #define     LIBGCC_SPEC     ""
4580
+
4581
+/* REAL_LIBGCC_SPEC ... By default, if ENABLE_SHARED_LIBGCC is defined, the
4582
+ * LIBGCC_SPEC is not directly used by the driver program but is instead
4583
+ * modified to refer to different versions of 'libgcc.a' depending on the
4584
+ * values of the command line flags '-static', '-shared', '-static-libgcc',
4585
+ * and '-shared-libgcc'.  On targets where these modifications are
4586 111 dgisselq
+ * inappropriate, define REAL_LIBGCC_SPEC instead.  REAL_LIBGCC_SPEC tells the
4587 202 dgisselq
+ * driver how to place a reference to 'libgcc' on the link command line, but
4588 111 dgisselq
+ * unlike LIBGCC_SPEC, it is used unmodified.
4589 202 dgisselq
+ */
4590 111 dgisselq
+#define        REAL_LIBGCC_SPEC        ""
4591
+
4592
+// USE_LD_AS_NEEDED
4593
+// LINK_EH_SPEC
4594
+
4595
+/* STARTFILE_SPEC ... Another C string constant used much like LINK_SPEC.  The
4596
+ * difference between the two is that STARTFILE_SPEC is used at the very
4597
+ * beginning of the command given to the linker.
4598 209 dgisselq
+ *
4599
+ * If this macro is not defined, a default is provided that loads the standard
4600 111 dgisselq
+ * C startup file from the usual place.  See 'gcc.c'
4601
+ */
4602
+#undef STARTFILE_SPEC
4603
+#define        STARTFILE_SPEC  ""
4604
+
4605
+/* ENDFILE_SPEC ... Another C string constant used much like LINK_SPEC.  The
4606
+ * difference between the two is that ENDFILE_SPEC is used at the very end
4607
+ * of the command given to the linker.
4608
+ *
4609
+ * Do not define this macro if it does not do anything.
4610
+ */
4611
+// #undef      ENDFILE_SPEC
4612
+// #define     ENDFILE_SPEC    ""
4613
+
4614
+// THREAD_MODEL_SPEC
4615
+// SYSROOT_SUFFIX_SPEC
4616
+// SYSROOT_HEADERS_SUFFIX_SPEC
4617
+// EXTRA_SPECS
4618
+// LINK_LIBGCC_SPECIAL_1
4619
+// LINK_GCC_C_SEQUENCE_SPEC
4620
+// LINK_COMMAND_SPEC
4621
+// TARGET_ALWAYS_STRIP_DOTDOT
4622
+// MULTILIB_DEFAULTS
4623
+// RELATIVE_PREFIX_NOT_LINKDIR
4624
+// MD_EXEC_PREFIX
4625
+// STANDARD_STARTFILE_PREFIX
4626
+// STANDARD_STARTFILE_PREFIX_1
4627
+// STANDARD_STARTFILE_PREFIX_2
4628
+// MD_STARTFILE_PREFIX
4629
+// MD_STARTFILE_PREFIX_1
4630
+// INIT_ENVIRONMENT
4631
+// LOCAL_INCLUDE_DIR
4632
+#undef LOCAL_INCLUDE_DIR
4633
+
4634
+// NATIVE_SYSTEM_HEADER_COMPONENT
4635
+// INCLUDE_DEFAULTS
4636
+
4637
+/* 17.03 Run-time Target Specification */
4638
+
4639
+/* TARGET_CPU_CPP_BUILTINS() ... This function-like macro expands to a block of
4640
+ * code that defines built-in preprocessor macros and assertions for the target
4641
+ * CPU, using the functions builtin_define, builtin_define_std, and
4642
+ * builtin_assert.  When the front end calls this macro it provides a trailing
4643
+ * semicolon, and since it has finished command line option proccessing your
4644
+ * code can use those results freely.
4645
+ *
4646
+ * ZipCPU --- We should probably capture in this macro what capabilities the
4647
+ * command line parameters we've been given indicate that our CPU has.  That
4648
+ * way, code can be adjusted depending upon the CPU's capabilities.
4649
+ */
4650
+#define        TARGET_CPU_CPP_BUILTINS()                               \
4651
+       { builtin_define("__ZIPCPU__");                         \
4652
+       builtin_define("__BIG_ENDIAN__");                       \
4653
+       builtin_define("__IEEE_BIG_ENDIAN");                    \
4654
+       builtin_define("_LDBL_EQ_DBL");                         \
4655
+       if (ZIP_FPU) builtin_define("__ZIPFPU__");              \
4656
+       else builtin_define("_SOFT_FLOAT");                     \
4657 102 dgisselq
+       if (ZIP_ATOMIC) builtin_define("__ZIPATOMIC__");        \
4658
+       }
4659
+       // If (zip_param_has_fpu)  builtin_define("__ZIPFPU__");
4660
+       // If (zip_param_has_div)  builtin_define("__ZIPDIV__");
4661
+       // If (zip_param_has_mpy)  builtin_define("__ZIPMPY__");
4662
+       // If (zip_param_has_lock) builtin_define("__ZIPLOCK__");
4663
+       // If (zip_param_supervisor) builtin_define("__ZIPUREGS__");
4664
+       // If (we support int64s) builtin_define("___int64_t_defined");
4665
+
4666
+/* TARGET_OS_CPP_BUILTINS() ... Similarly to TARGET_CPU_CPP_BUILTINS but this
4667
+ * macro is optional and is used for the target operating system instead.
4668
+ */
4669
+
4670 202 dgisselq
+/* Option macros: (we need to define these eventually ... )
4671
+ *
4672 209 dgisselq
+ *     TARGET_HANDLE_OPTION
4673 202 dgisselq
+ *     TARGET_HANDLE_C_OPTION
4674
+ *     TARGET_OBJ_CONSTRUCT_STRING_OBJECT
4675
+ *     TARGET_OBJ_DECLARE_UNRESOLVED_CLASS_REFERENCE
4676
+ *     TARGET_OBJ_DECLARE_CLASS_DEFINITION
4677 102 dgisselq
+ *     TARGET_STRING_OBJECT_REF_TYPE_P
4678
+ *     TARGET_CHECK_STRING_OBJECT_FORMAT_ARG
4679
+ *     TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE(VOID)
4680
+ *     C_COMMON_OVERRIDE_OTPTIONS
4681
+ *     TARGET_OPTION_OPTIMIZATION_TABLE
4682
+ *     TARGET_OPTION_INIT_STRUCT
4683
+ *     TARGET_OPTION_DEFAULT_PARAMS
4684
+ */
4685
+
4686
+/* SWITCHABLE_TARGET
4687
+ *
4688
+ * Zip CPU doesn't need this, so it defaults to zero.  No need to change it
4689
+ * here.
4690
+ */
4691
+
4692
+/* TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(VOID) ... Returns true if the
4693
+ * target supports IEEE 754 floating-point exceptions and rounding modes, false
4694
+ * otherwise.  This is intended to relate to the float and double types, but not
4695
+ * necessarily "long double".  By default, returns true if the adddf3
4696
+ * instruction pattern is available and false otherwise, on the assumption that
4697
+ * hardware floating point supports exceptions and rounding modes but software
4698
+ * floating point does not.
4699
+ *
4700
+ * ZipCPU floating point is barely going to be functional, I doubt it will
4701
+ * support all of these bells and whistles when full functionality is even
4702
+ * achieved.  Therefore, we won't support these modes.  However, we can't just
4703
+ * set this to zero, so let's come back to this.
4704
+ */
4705
+// #undef      TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
4706
+// #define     TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P(X) 0
4707
+
4708
+/* 17.04 Defining data structures for per-function information */
4709
+
4710
+/* INIT_EXPANDERS ... Macro called to initialize any target specific
4711
+ * information.  This macro is called once per function, before generation of
4712
+ * any RTL has begun.  The intention is to allow the initialization of the
4713
+ * function pointer init_machine_status.
4714
+ */
4715
+// #warning "I may need to define this to handle function return addresses ..."
4716
+
4717
+
4718
+/* 17.05 Storage Layout */
4719
+
4720
+
4721
+/* Storage Layout */
4722
+#define        BITS_BIG_ENDIAN         0        // MSB has highest number
4723
+#define        BYTES_BIG_ENDIAN        1       // 1 if MSB is lowest number
4724
+#define        WORDS_BIG_ENDIAN        1       // 1 if MSW is lowest number
4725 103 dgisselq
+#define        FLOAT_WORDS_BIG_ENDIAN  1
4726 102 dgisselq
+#define        UNITS_PER_WORD          4       // Storage units in a word, pwr of 2:1-8
4727
+/* POINTER_SIZE ... Width of a pointer in bits.  You must specify a value no
4728
+ * wider than the width of Pmode.  If it is not equal to the width of Pmode,
4729
+ * you must define POINTERS_EXTEND_UNSIGNED. If you do not specify a value the
4730
+ * default is BITS_PER_WORD.
4731
+ *
4732
+ * ZipCPU --- All of our pointers are 32-bits, the width of our address bus.
4733
+ */
4734
+#define        POINTER_SIZE            32      // Ptr width in bits
4735
+
4736
+/* POINTERS_EXTEND_UNSIGNED ... A C expression that determines how pointers
4737 202 dgisselq
+ * should be extended from ptr_mode to either Pmode or word_mode.  It is greater
4738 102 dgisselq
+ * than zero if pointers should be zero-extended, zero if they should be sign
4739
+ * extended, and negative if some other conversion is needed.  In the last case,
4740 202 dgisselq
+ * the extension is done by the target's ptr_extend instruction.
4741 102 dgisselq
+ *
4742
+ * You need not define this macro if the ptr_mode, Pmode, and word_mode are all
4743
+ * the same width.
4744
+ *
4745
+ * ZipCPU --- We don't need to define this macro, since PMode and ptr_mode, and
4746 202 dgisselq
+ * our word_mode (SImode) all have the same width.
4747 102 dgisselq
+ */
4748
+// #define     POINTERS_EXTEND_UNSIGNED        1
4749
+
4750
+/* PROMOTE_MODE(m,unsignedp,type) ... A macro to update m and unsignedp when an
4751
+ * object whose type is type and which has he specified mode and signedness is
4752
+ * to be stored in a register.  This macro is only called when type is a scalar
4753
+ * type.
4754
+ *
4755 202 dgisselq
+ * On most RISC machines, which only have operations that operate on a full
4756 102 dgisselq
+ * register, define this macro to set m to word_mode if m is an integer mode
4757
+ * narrower than BITS_PER_WORD.  In most cases, only integer modes should be
4758
+ * widened because wider precision floating-point operations are usually more
4759
+ * expensive than their narrower counterparts.
4760
+ *
4761
+ * For most machines, the macro definition does not change unsigndep.  However,
4762
+ * some machines, have instructions that preferentially handle either signed or
4763
+ * unsigned quantities of certain modes.  For example, on the DEC Alpha, 32-bit
4764
+ * loads from memory and 32-bit add instructions sign-extend the result to
4765 202 dgisselq
+ * 64-bits. On such machines, set unsignedp according to which kind of extension
4766
+ * is more efficient.
4767 102 dgisselq
+ *
4768 202 dgisselq
+ * Do not define this macro if it would never modify m.
4769 102 dgisselq
+ *
4770
+ * ZipCPU ---
4771
+ */
4772
+#define        PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
4773
+       do {                                                    \
4774
+               if ((GET_MODE_CLASS(MODE) == MODE_INT)          \
4775
+                               && (GET_MODE_SIZE(MODE) < 4)) { \
4776
+                       (MODE) = SImode;                        \
4777
+                       (UNSIGNEDP) = 1;                        \
4778
+               }                                               \
4779
+       } while(0)
4780
+
4781
+// TARGET_PROMOTE_FUNCTION_MODE
4782
+#define        TARGET_PROMOTE_FUNCTION_MODE    default_promote_function_mode_always_promote
4783
+
4784
+/* PARM_BOUNDARY ... Normal alignment required for function parameters on the
4785
+ * stack, in bits.  All stack parameters receive at least this much alignment
4786
+ * regardless of data type.  On most machines, this is the same as the size of
4787
+ * an integer.
4788
+ */
4789
+#define        PARM_BOUNDARY   32
4790 202 dgisselq
+
4791 102 dgisselq
+/* STACK_BOUNDARY ... Define this macro to the minimum alignment enforced by
4792 202 dgisselq
+ * hardware for the stack pointer on this machine.  The definition is a C
4793
+ * expression for the desired alignment (measured in bits).  This value is used
4794
+ * as a default if PREFERRED_STACK_BOUNDARY is not defined.  On most machines,
4795
+ * this should be the same as PARM_BOUNDARY.
4796
+ */
4797
+#define        STACK_BOUNDARY  PARM_BOUNDARY
4798
+
4799
+/* PREFERRED_STACK_BOUNDARY ... Define this ... */
4800 102 dgisselq
+#define        PREFERRED_STACK_BOUNDARY        STACK_BOUNDARY
4801
+
4802 202 dgisselq
+/* INCOMING_STACK_BOUNDARY ... Define this macro if the incoming stack boundary
4803
+ * may be different from PREFERRED_STACK_BOUNDARY.  This macro must evaluate
4804 102 dgisselq
+ * to a value equal to or larger than STACK_BOUNDARY.
4805
+ */
4806
+#define        INCOMING_STACK_BOUNDARY STACK_BOUNDARY
4807
+
4808
+/* FUNCTION_BOUNDARY ... Alignment required for a function entry point, in bits.
4809
+ */
4810
+#define        FUNCTION_BOUNDARY       32
4811
+
4812
+/* BIGGEST_ALIGNMENT ... Biggest alignment that any data type can require on
4813
+ * this machine, in bits.  Note that this is not the biggest alignment that is
4814
+ * supported, just the biggest alignment that, when violated, may cause a fault.
4815
+ */
4816
+#define BIGGEST_ALIGNMENT      32
4817
+
4818
+/* MALLOC_ABI_ALIGNMENT
4819
+ */
4820 127 dgisselq
+
4821 102 dgisselq
+/* ATTRIBUTE_ALIGNED_VALUE
4822 127 dgisselq
+ */
4823
+
4824
+/* MINIMUM_ATOMIC_ALIGNMENT ... If defined, the smallest alignment, that can be
4825 102 dgisselq
+ * given to an object that can be referenced in one operation, without
4826 127 dgisselq
+ * disturbing any nearby object.  Normally, this is BITS_PER_UNIT, but may be
4827 102 dgisselq
+ * larger on machines that don't have byte or halfword store operations.
4828
+ */
4829
+#define        MINIMUM_ATOMIC_ALIGNMENT        BITS_PER_UNIT
4830
+
4831
+/* BIGGEST_FIELD_ALIGNMENT ... Biggest alignment that any structure or union
4832
+ * field can require on this machine, in bits.  If defined, this overrides
4833
+ * BIGGEST_ALIGNMENT for structure and union fields only, unless the field
4834
+ * alignment has been set by the __attribute__((aligned(n))) construct.
4835
+ */
4836
+#define        BIGGEST_FIELD_ALIGNMENT BITS_PER_WORD
4837
+
4838 127 dgisselq
+/* ADJUST_FIELD_ALIGN(FIELD, COMPUTED) ... An expression for the alignment of
4839
+ * a structure field FIELD if the alignment computed in the usual way (including
4840
+ * applying BIGGEST_ALIGNMENT and BIGGEST_FIELD_ALIGNMENT) is COMPUTED.
4841
+ */
4842
+// #define     ADJUST_FIELD_ALIGN(A,B) BITS_PER_WORD
4843
+
4844 102 dgisselq
+/* MAX_STACK_ALIGNMENT ... Biggest stack alignment guaranteed by the backend.
4845
+ * Use this macro to specify the maximum alignment of a variable on the stack.
4846
+ *
4847
+ * If not defined, the default value is STACK_BOUNDARY
4848
+ */
4849
+// #define     MAX_STACK_ALIGNMENT     BITS_PER_WORD
4850
+
4851 127 dgisselq
+/* MAX_OFILE_ALIGNMENT
4852
+ */
4853
+
4854
+/* DATA_ALIGNMENT(TYPE, BASIC-ALIGN) ... If defined, a C expression to compute
4855
+ * the alignment for a variable in the static store.  TYPE is the data type, and
4856 202 dgisselq
+ * BASIC-ALIGN is the alignment that the object would ordinarily have.  The
4857 127 dgisselq
+ * value of this macro is used instead of that alignment to align the object.
4858 202 dgisselq
+ *
4859
+ * If this macro is not defined, then BASIC-ALIGN is used.
4860
+ *
4861 127 dgisselq
+ * ZipCPU --
4862 202 dgisselq
+ */
4863 127 dgisselq
+// #define     DATA_ALIGNMENT(TYPE, ALIGN)     BITS_PER_WORD
4864 202 dgisselq
+
4865
+
4866
+/* DATA_ABI_ALIGNMENT(TYPE,BASIC-ALIGN)
4867
+ */
4868 127 dgisselq
+
4869 202 dgisselq
+/* CONSTANT_ALIGNMENT(CONST, BASIC-ALIGN) ... If defined, a C expression to
4870 127 dgisselq
+ * compute the alignment given to a constant that is being placed in memory.
4871
+ * CONST is the constant and BASIC-ALIGN is the alignment that the object
4872
+ * would ordinarily have.  The value of this macro is used instead of that
4873
+ * alignment to align the object.
4874
+ *
4875
+ * If this macro is not defined, then BASIC-ALIGN is used.
4876
+ *
4877
+ * ZipCPU -- in hindsiht, if this macro is not defined then the compiler is
4878
+ * broken.  We'll define it as above.
4879
+ *
4880
+ */
4881 202 dgisselq
+#define        CONSTANT_ALIGNMENT(EXP, ALIGN)  BITS_PER_WORD
4882 127 dgisselq
+
4883 202 dgisselq
+/* LOCAL_ALIGNMENT(TYPE,BASIC-ALIGN) ... If defined ...
4884 127 dgisselq
+ */
4885
+// #define     LOCAL_ALIGNMENT(TYP,ALIGN)      BITS_PER_WORD
4886
+
4887
+/* TARGET_VECTOR_ALIGNMENT
4888
+ */
4889
+
4890
+/* STACK_SLOT_ALIGNMENT
4891
+ */
4892
+#define        STACK_SLOT_ALIGNMENT(T,M,B)     BITS_PER_WORD
4893
+
4894
+/* LOCAL_DECL_ALIGNMEN(DECL)
4895
+ */
4896
+// #define     LOCAL_DECL_ALIGNMENT(DECL)      BITS_PER_WORD
4897
+
4898
+/* MINIMUM_ALIGNMENT
4899
+ */
4900
+// #define     MINIMUM_ALIGNMENT(EXP,MOD,ALIGN)        BITS_PER_WORD
4901
+
4902
+/* EMPTY_FIELD_BOUNDARY
4903
+ * Alignment of field after 'int : 0' in a structure.
4904
+ */
4905 202 dgisselq
+#define        EMPTY_FIELD_BOUNDARY    BITS_PER_WORD
4906 127 dgisselq
+
4907
+/* STRUCTURE_SIE_BOUNDARY
4908
+ * ZipCPU -- Every structures size must be a multiple of 32-bits.
4909
+ */
4910
+#define        STRUCTURE_SIZE_BOUNDARY BITS_PER_WORD
4911
+
4912
+/* STRICT_ALIGNMENT ... Set this nonzero if move instructions will actually
4913
+ * fail to work when given unaligned data.  If instructions will merely go
4914
+ * slower in that case, define this macro as 0.
4915
+ *
4916 202 dgisselq
+ * ZipCPU --
4917 127 dgisselq
+ */
4918
+#define        STRICT_ALIGNMENT        1
4919
+
4920 202 dgisselq
+/* PCC_BITFIELD_TYPE_MATTERS -- define this if you wish to imitate the the way
4921 127 dgisselq
+ * other C compilers handle alignment of bit-fields and the structures that
4922
+ * contain them.
4923
+ *
4924
+ * The behavior is that the type written for a named bit-field (int, short, or
4925
+ * other integer type) imposes an alignment for the entire structure, as if the
4926
+ * structure really did contain an ordinary field of that type.  In addition,
4927
+ * the bit-field is placed within the structure so that it would fit within
4928
+ * such a field, not crossing a boundary for it.
4929
+ *
4930
+ * Thus, no most machines, a named bit-field whose type is written as int would
4931
+ * not cross a four-byte boundary, and would force four-byte alignment for the
4932 102 dgisselq
+ * whole structure.  (The alignment used may not be four bytes; it is controlled
4933
+ * by other alignment parameters.)
4934
+ *
4935 125 dgisselq
+ * An unnamed bit-field will not affect the alignment of the containing
4936 202 dgisselq
+ * structure.
4937 102 dgisselq
+ *
4938 202 dgisselq
+ * If the macro is defined, its definition should be a C expression, a non
4939 102 dgisselq
+ * zero value for the expression enables this behavior.
4940 127 dgisselq
+ * Look at the fundamental type that is used for a bit-field and use that to
4941
+ * impose alignment on the enclosing structure.  struct s{int a:8}; should
4942
+ * have the same alignment as 'int', not 'char'.
4943
+ */
4944
+#undef PCC_BITFIELD_TYPE_MATTERS
4945
+#define        PCC_BITFIELD_TYPE_MATTERS       0
4946
+
4947
+/* MAX_FIXED_MODE_SIZE ... An integer expression for the size in bits of the
4948
+ * largest integer machine mode that should actually be used.  All integer
4949
+ * machine modes of this size or smaller can be used for structures and unions
4950
+ * with the appropriate sizes.  If this macro is undefined,
4951
+ * GET_MODE_BITSIZE(DImode) is assumed.
4952
+ *
4953
+ * ZipCPU ... Get_MODE_BITSIZE(DImode) will be 64, and this really is the
4954
+ * size in bits of the largest integer machine mode.  However, that's the case
4955
+ * with most DI implementations: A long is two words, spliced together.  We'd
4956
+ * like to support that eventually, but we need to get there.  Hence, let's use
4957
+ * compile time flag (ZIP_HAS_DI) that we can enable when we're ready.
4958
+ */
4959
+#undef MAX_FIXED_MODE_SIZE
4960
+#ifdef ZIP_HAS_DI
4961
+# define MAX_FIXED_MODE_SIZE   GET_MODE_BITSIZE(DImode)
4962
+#else
4963
+# define MAX_FIXED_MODE_SIZE   GET_MODE_BITSIZE(SImode)
4964
+#endif
4965
+
4966
+
4967 102 dgisselq
+
4968
+/* 17.06 Layout of Source Language Data Types */
4969
+
4970
+#undef LONG_TYPE_SIZE
4971
+#undef LONG_LONG_TYPE_SIZE
4972
+//
4973 202 dgisselq
+#define        LONG_TYPE_SIZE  64
4974
+#define        LONG_LONG_TYPE_SIZE     64
4975 102 dgisselq
+// SHORT_FRAC_TYPE_SIZE
4976
+// LONG_FFRACT_TYPE_SIZE
4977
+// LONG_LONG_FRACT_TIME_SIZE
4978
+
4979 202 dgisselq
+/* LIBGCC2_GNU_PREFIX ... This macro corresponds to the TARGET_GNU_PREFIX target
4980
+ * hook and should be defined if that hook is overriden to be true.  It causes
4981
+ * function names in libgcc to be changed to use a __gnu_ prefix for their name
4982 102 dgisselq
+ * rather than the default __.  A port which uses this macro should also arrange
4983 202 dgisselq
+ * to use t-gnu-prefix in the libgcc config.host.
4984 102 dgisselq
+ *
4985
+ * ZipCPU -- I see no reason to define and therefore change this behavior.
4986
+ */
4987 202 dgisselq
+
4988 102 dgisselq
+/* TARGET_FLT_EVAL_METHOD ... A C expression for the value for FLT_EVAL_METHOD
4989
+ * in float.h,, assuming, if applicable, that the floating-point control word
4990
+ * is in its default state.  If you do not define this macro the value of
4991
+ * FLT_EVAL_METHOD will be zero.
4992
+ *
4993 200 dgisselq
+ * ZipCPU --- ???
4994 102 dgisselq
+ */
4995
+
4996
+/* WIDEST_HARDWARE_FP_SIZE ... A C expression for the size in bits of the widest
4997
+ * floating-point format supported by the hardware.  If you define this macro,
4998
+ * you must specify a value less than or equal to the value of LONG_DOUBLE_...
4999
+ * If you do not define this macro, the value of LONG_DOUBLE_TYPE_SIZE is the
5000
+ * default.
5001
+ *
5002
+ * ZipCPU supports 32-bit IEEE floats--IF THE SUPPORT IS COMPILED IN!  This
5003
+ * really needs to be determined, then, based upon a compile time parameter
5004
+ * where the one compiling the code states whether or not the H/W even has
5005
+ * floating point support.
5006
+ *
5007
+ * For now, we'll assume it does--but once we implement GCC parameters, we'll
5008
+ * need to change this.
5009
+ */
5010
+#undef WIDEST_HARDWARE_FP_SIZE
5011
+// #warning "Definition needs to change if no FPU present"
5012
+#define        WIDEST_HARDWARE_FP_SIZE FLOAT_TYPE_SIZE
5013
+
5014
+/* DEFAULT_SIGNED_CHAR ... An expression whose value is 1 or 0, according to
5015
+ * whether the type char should be signed or unsigned by default.  The user
5016
+ * can always override this default with the options -fsigned-char and
5017
+ * -funsigned-char.
5018
+ *
5019
+ * ZipCPU--Our hardware produces unsigned characters (and shorts) by default,
5020
+ * so let's stick to that.
5021
+ */
5022
+#define        DEFAULT_SIGNED_CHAR     0
5023
+
5024
+/* TARGET_DEFAULT_SHORT_ENUMS(VOID) ... This target hook should return true if
5025
+ * the compiler should give an enum type only as many bytes as it takes to
5026
+ * represent the range of possible values of that type.  It should return
5027
+ * false if all enum types should be allocated like int.
5028
+ *
5029
+ * The default is to return false.  This is what the ZipCPU needs, so we won't
5030
+ * override it.
5031
+ */
5032
+
5033
+/* SIZE_TYPE ... A C expression for a string describing the name of the data
5034
+ * type to use for size values.  The typedef name size_t is defined using the
5035
+ * contents of the string.
5036
+ *
5037
+ * If you don't define this macro, the default is "long unsigned int".  Since
5038
+ * on the ZipCPU this is a 32-bit number, and all ZipCPU values are 32-bits,
5039 202 dgisselq
+ * the default seems perfect for us.
5040
+ */
5041 102 dgisselq
+#define        SIZE_TYPE       "unsigned int"
5042 202 dgisselq
+
5043 102 dgisselq
+/* SIZETYPE ... GCC defines internal types () for expressions dealing with size.
5044
+ * This macro is a C expression for a string describing the name of the data
5045 103 dgisselq
+ * type from which the precision of sizetype is extracted.  The string has the
5046 102 dgisselq
+ * same restrictions as SIZE_TYPE string.  If you don't define this macro, the
5047
+ * default is SIZE_TYPE --- which seems good enough for us.
5048
+ */
5049
+
5050
+/* PTRDIFF_TYPE ... A C expression for a string describing the name of the data
5051
+ * type to use for the result of subtracting two pointers.  The typedef name
5052
+ * ptrdiff_t is defined using the contents of the string.  See SIZE_TYPE for
5053
+ * more information.
5054
+ *
5055
+ * The default is "long int" which for the ZipCPU is 32-bits---still good enough
5056
+ * for us.
5057
+ */
5058
+#define        PTRDIFF_TYPE    "int"
5059
+
5060
+/* WCHAR_TYPE ... A C expression for a string describing the name of the data
5061
+ * type to use for wide characters.  The typedef name wchar_t is defined using
5062
+ * the contents of  the string.  If you don't define this macro, the default is
5063
+ * 'int'--good enough for ZipCPU.
5064
+ */
5065
+// #define     WCHAR_TYPE      "int"
5066
+
5067
+/* WCHAR_TYPE_SIZE ... A C expression for the size in bits of the data type for
5068
+ * wide characters.  This is used in cpp, which cannot make use of WCHAR_TYPE.
5069
+ *
5070
+ * ZipCPU -- This defaults to INT_TYPE_SIZE, which will work for us
5071 127 dgisselq
+ */
5072 102 dgisselq
+// #define     WCHAR_TYPE_SIZE 32
5073
+
5074
+/* WINT_TYPE ... A C expression for a string describing the name of the data
5075
+ * type to use for wide characters passed to printf and returned from getwc.
5076
+ * The typedef name wint_t is defined using the contents of the string.  See
5077
+ *
5078
+ * ZipCPU -- The default should work well enough for us.
5079
+ */
5080
+// #define     WINT_TYPE       "int"
5081
+
5082
+/* INTMAX_TYPE ... A C expression for a string describing the name of the
5083
+ * data type that can represent any value of any standard or extended signed
5084
+ * integer type.  The typedef name intmax_t is defined using the contents of
5085 202 dgisselq
+ * the string.
5086 102 dgisselq
+ *
5087
+ * If you don't define this macro, the default is the first of "int", "long int"
5088
+ * or "long long int" that has as much precision as "long long int".
5089 202 dgisselq
+ */
5090
+
5091 102 dgisselq
+/* UINTMAX_TYPE ... same as INTMAX_TYPE, but for unsigned
5092 202 dgisselq
+ */
5093 102 dgisselq
+
5094
+#undef SIG_ATOMIC_TYPE
5095
+#if (ZIP_ATOMIC != 0)
5096
+#define        SIG_ATOMIC_TYPE "int"
5097
+#else
5098 202 dgisselq
+#define        SIG_ATOMIC_TYPE NULL    // We have no atomic types, but registers
5099 102 dgisselq
+#endif
5100 202 dgisselq
+#undef INT8_TYPE
5101 102 dgisselq
+#define        INT8_TYPE               "char"
5102
+#undef INT16_TYPE
5103
+#define        INT16_TYPE              "short int"
5104
+#undef INT32_TYPE
5105
+#define        INT32_TYPE              "int"
5106
+#undef UINT8_TYPE
5107
+#define        UINT8_TYPE              "unsigned char"
5108
+#undef UINT16_TYPE
5109
+#define        UINT16_TYPE             "short unsigned int"
5110
+#undef UINT32_TYPE
5111
+#define        UINT32_TYPE             "unsigned int"
5112
+#undef INT_LEAST8_TYPE
5113
+#define        INT_LEAST8_TYPE         "char"
5114
+#undef INT_LEAST16_TYPE
5115
+#define        INT_LEAST16_TYPE        "short int"
5116
+#undef INT_LEAST32_TYPE
5117
+#define        INT_LEAST32_TYPE        "int"
5118
+#undef UINT_LEAST8_TYPE
5119
+#define        UINT_LEAST8_TYPE        "unsigned char"
5120
+#undef UINT_LEAST16_TYPE
5121 202 dgisselq
+#define        UINT_LEAST16_TYPE       "short unsigned int"
5122 102 dgisselq
+#undef UINT_LEAST32_TYPE
5123 202 dgisselq
+#define        UINT_LEAST32_TYPE       "unsigned int"
5124 102 dgisselq
+#undef INT_FAST8_TYPE
5125
+#define        INT_FAST8_TYPE          "char"
5126
+#undef INT_FAST16_TYPE
5127 202 dgisselq
+#define        INT_FAST16_TYPE         "short int"
5128 102 dgisselq
+#undef INT_FAST32_TYPE
5129 202 dgisselq
+#define        INT_FAST32_TYPE         "int"
5130 102 dgisselq
+#undef UINT_FAST8_TYPE
5131
+#define        UINT_FAST8_TYPE         "unsigned char"
5132
+#undef UINT_FAST16_TYPE
5133 202 dgisselq
+#define        UINT_FAST16_TYPE        "short unsigned int"
5134 102 dgisselq
+#undef UINT_FAST32_TYPE
5135 202 dgisselq
+#define        UINT_FAST32_TYPE        "unsigned int"
5136 102 dgisselq
+#undef INTPTR_TYPE
5137
+#define        INTPTR_TYPE             "unsigned int"
5138
+#undef UINTPTR_TYPE
5139 202 dgisselq
+#define        UINTPTR_TYPE            "unsigned int"
5140 102 dgisselq
+
5141 202 dgisselq
+#undef INT64_TYPE
5142 102 dgisselq
+#undef UINT64_TYPE
5143
+#undef INT_LEAST64_TYPE
5144
+#undef UINT_LEAST64_TYPE
5145 202 dgisselq
+#undef INT_FAST64_TYPE
5146 102 dgisselq
+#undef UINT_FAST64_TYPE
5147 202 dgisselq
+
5148 102 dgisselq
+#if (ZIP_HAS_DI != 0)
5149
+#define        INT64_TYPE              "long int"
5150
+#define        UINT64_TYPE             "long unsigned int"
5151 202 dgisselq
+#define        INT_LEAST64_TYPE        "long int"
5152 102 dgisselq
+#define        UINT_LEAST64_TYPE       "long unsigned int"
5153 202 dgisselq
+#define        INT_FAST64_TYPE         "long int"
5154 102 dgisselq
+#define        UINT_FAST64_TYPE        "long unsigned int"
5155
+#else
5156
+#define        INT64_TYPE              NULL
5157
+#define        UINT64_TYPE             NULL
5158
+#define        INT_LEAST64_TYPE        NULL
5159
+#define        UINT_LEAST64_TYPE       NULL
5160
+#define        INT_FAST64_TYPE         NULL
5161
+#define        UINT_FAST64_TYPE        NULL
5162
+#endif
5163
+
5164
+#define        TARGET_PTRMEMFUNC_VBI_LOCATION  ptrmemfunc_vbit_in_pfn
5165
+
5166
+
5167
+/* 17.07 Register Usage / Register definitions */
5168
+
5169
+/* FIRST_PSEUDO_REGISTER ... Number of hardware registers known to the compiler.
5170
+ * They receive numbers 0 through FIRST_PSEUDO_REGISTER-1; thus the first
5171
+ * pseudo register's numbrer really is assigned the number
5172
+ * FIRST_PSEUDO_REGISTER.
5173
+ *
5174
+ * ZipCPU---There are 16 registers in the ZipCPU, numbered 0-15 with the CC
5175
+ * and PC register being numbered 14 and 15 respectively.  The ZipCPU has
5176
+ * another 16 registers, identical to the first, but user mode registers.  These
5177
+ * are number the same as the first (0-15) in user mode, but numbered (16-31)
5178
+ * in supervisor mode.  In addition, we create a pretend argument pointer
5179
+ * register, zip_AP_PSEUDO, to refer to our arguments.  This final register,
5180
+ * although it gets a valid number, will be eliminated in optimization.
5181
+ */
5182
+#define        FIRST_PSEUDO_REGISTER   (zip_AP_PSEUDO+1)
5183
+
5184
+/* FIXED_REGISTERS ... An initializer that says which registers are used for
5185
+ * fixed purposes all throughout the compiled code and are therefore not
5186
+ * available for general allocation.  These would include the stack pointer, the
5187
+ * frame pointer (except on machines where that can be used as a general
5188
+ * register when no frame pointer is needed), the program counter on machines
5189
+ * where that is considered one of the addressable registers, and any other
5190
+ * numbered register with a standard use.
5191
+ *
5192
+ * This information is expressed as a sequence of numbers, separated by commas,
5193
+ * and surrounded by braces.  The nth number is 1 if register n is fixed, 0
5194
+ * otherwise.
5195 171 dgisselq
+ *
5196
+ * For the Zip CPU, we have three fixed registers that are not available for
5197
+ * general allocation:
5198
+ *
5199
+ *     SP      The stack pointer
5200
+ *     CC      The condition codes and CPU state register
5201 102 dgisselq
+ *     PC      The program counter
5202 171 dgisselq
+ *
5203 102 dgisselq
+ * Other registers, such as FP (the frame pointer) or GBL (the global offset
5204
+ * table pointer) are registers that we hope will not be so fixed.
5205
+ *
5206
+ * Okay, just updated this process.  We now have more registers that are not
5207
+ * available for general allocation:
5208
+ *     uR0-uPC         User registers
5209
+ *     PSEUDO-AP       The pseudo arg pointer
5210
+ */
5211
+#define        FIXED_REGISTERS         { 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, 1 }
5212
+
5213
+/* CALL_USED_REGISTERS ... like FIXED_REGISTERS but has 1 for each register
5214
+ * that is clobbered (in general) by function calls as well as for fixed
5215
+ * registers.  This macro therefore identifies the registers that are not
5216
+ * available for general allocation of values that must live across function
5217
+ * calls.
5218
+ *
5219
+ * If a register has 0 in CALL_USED_REGISTERS, the compiler automatically saves
5220
+ * it on function entry and restores it on function exit, if the register is
5221
+ * used within the function.
5222
+ *
5223
+ * On the Zip CPU, we must save R0 (the return address), and (let's pick) any
5224
+ * register above R5.
5225 171 dgisselq
+ */
5226
+#define        CALL_USED_REGISTERS     { 0,1,1,1, 1,0,0,0, 0,0,0,0, 0,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1, 1,1,1,1,  1 }
5227
+
5228
+/* CALL_REALLY_USED_REGISTERS ...  optional macro that, if not defined, defaults
5229
+ * to the value of CALL_USED_REGISTERS.
5230 102 dgisselq
+ */
5231 171 dgisselq
+
5232 102 dgisselq
+/* HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) ... A C expression that is nonzero
5233
+ * if it is not permissible to store a value of mode MODE in hard register REGNO
5234
+ * across a call without some part of it being clobbbered.  For most machines,
5235
+ * this macro need not be defined.  It is only required for machines that do
5236
+ * not preserve the entire contents of a register across a call.
5237
+ *
5238
+ * ZipCPU--Always preserves the entire contents of those registers that are
5239
+ * preserved across calls, so this shouldnt need to be defined.
5240
+ */
5241
+// #define     HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE)      (REGNO==0)
5242
+
5243
+/* TARGET_CONDITIONAL_REGISTER_USAGE(VOID) ... This hook may conditionally
5244
+ * modify five variables fixed_regs, call_used_regs, global_regs, reg_names, and
5245
+ * reg_class_contents, to take into account any dependence of these register
5246 171 dgisselq
+ * sets on target flags.  The first three of these are of type char[]
5247 102 dgisselq
+ * (interpreted as Boolean vectors).  global_regs is a const char *[] and
5248
+ * reg_class_contents is a HARD_REG_SET.  Before the macro is called,
5249
+ * fixed_regs, call_used_regs, reg_class_contents, and reg_names have been
5250
+ * initialized from FIXED_REGISTERS, CALL_USED_REGISTERS, REG_CLASS_CONTENTS,
5251
+ * and REGISTER_NAMES, respectively.  global_regs has been cleared, and any
5252
+ * -ffixed-reg, -fcall-used-reg, and -fcall-saved-reg command options have been
5253
+ * applied.
5254
+ *
5255
+ * ZipCPU -- I may need to return and define this depending upon how the
5256 103 dgisselq
+ * GBL register allocation goes.  But for now, we'll leave this at its default
5257 102 dgisselq
+ * value.
5258 127 dgisselq
+ */
5259
+// #warning "Revisit me after FP and GBL allocation"
5260 102 dgisselq
+
5261 127 dgisselq
+/* INCOMING_REGNO(out) ... Define this macro if the target machine has register
5262 102 dgisselq
+ * windows. ...
5263
+ *
5264
+ * Zip CPU has no register windows.
5265
+ */
5266
+
5267
+/* OUTGOING_REGNO ... same thing.
5268
+ * LOCAL_REGNO ... same thing.
5269
+ */
5270
+
5271
+/* PC_REGNUM ... If the program counter has a register number, define this as
5272
+ * that register number.  Otherwise do not define it.
5273
+ */
5274
+#define        PC_REGNUM       zip_PC
5275 171 dgisselq
+
5276
+
5277 102 dgisselq
+/* REG_ALLOC_ORDER ... If defined, an initializer for a vector of integers,
5278
+ * containing the number of hard registers in the order in which GCC should
5279
+ * prefer to use them (from most preferred to least.
5280
+ *
5281
+ * If this macro is not defined, registers are used lowest numbered first (all
5282
+ * else being equal).
5283
+ *
5284
+ * Since the default is the ZipCPU desired case, we won't define this here.
5285
+ */
5286
+
5287
+/* ADJUST_REG_ALLOC_ORDER ... on most machines it is not necessary to define
5288 171 dgisselq
+ * this macro, so we won't either.
5289 102 dgisselq
+ */
5290
+
5291
+/* HONOR_REG_ALLOC_ORDER ...
5292
+ */
5293
+
5294
+/* HONOR_REG_ALLOC_ORDER ... on most machines it is not necessary to define
5295
+ * this macro, so we won't either.
5296
+ */
5297
+
5298
+/* HARD_REGNO_NREGS(REGNO, MODE) ... A C expression for the number of
5299
+ * consecutive hard registers, starting at register number REGNO, required to
5300
+ * hold a value of mode MODE.
5301 103 dgisselq
+ *
5302 102 dgisselq
+ * On a machine where all registers are exactly one word, a suitable definition
5303
+ * is given of ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)/UNITS_PER_WORD.
5304
+ *
5305
+ */
5306
+#undef HARD_REGNO_NREGS
5307
+#define        HARD_REGNO_NREGS(REGNO, MODE)   ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1)\
5308
+               / (UNITS_PER_WORD))
5309
+
5310
+/* HARD_REGNO_NREGS_HAS_PADDING(REGNO,MODE) ... A C expression that is nonzero
5311
+ * if a value of mode MODE, stored in memory, ends with padding that causes it
5312
+ * to take up more space than in registers starting at register number REGNO
5313
+ * (as determined by multiplying GCC's notion of the size of the register when
5314
+ * containing this mode by the number of registers returned by HARD_REGNO_NREGS)
5315
+ * By default this is zero.
5316
+ *
5317
+ * Zip CPU --- The default looks good enough to me.
5318
+ */
5319
+
5320
+/* HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE)
5321
+ *
5322
+ * ZipCPU ---
5323
+ */
5324
+
5325
+/* REGMODE_NATURAL_SIZE(MODE) -- Define this macro if the natural size of
5326
+ * registers that hold values of mode mode is not the word size.  It is a C
5327
+ * expression that should give the natural size in bytes for the specified mode.
5328
+ * It is used by the register allocator to try to optimize its results.
5329
+ *
5330
+ * ZipCPU ---
5331
+ */
5332
+// #define     REGMODE_NATURAL_SIZE(MODE)      (((MODE)==DImode)?2:1)
5333
+
5334
+/* HARD_REGNO_MODE_OK ... A C expression that is nonzero if it is permissible
5335
+ * to store a value of mode MODE in a hard register number REGNO (or in several
5336
+ * registers starting with that one).  For a machine where all registers are
5337
+ * equivalent, a suitable definition is '1'.  You need not include code to check
5338
+ * for the numbers of fixed registers, because the allocation mechanism
5339
+ * considered them to be always occupied.
5340
+ *
5341
+ * ZipCPU --- As long as you are already avoiding the fixed registers, the
5342
+ * suitable default definition mentioned above should be sufficient.
5343
+ */
5344
+#undef HARD_REGNO_MODE_OK
5345
+#define        HARD_REGNO_MODE_OK(R,M) (R<zip_CC)
5346
+
5347
+/* HARD_REGNO_RENAME_OK(FROM,TO) ... A C expression that is nonzero if it is
5348
+ * okay to rename a hard register FROM to another hard register TO.  One common
5349
+ * use of this macro is to prevernt renaming of a register to another register
5350
+ * that is not saved by a prologue in an interrupt handler.  The default is
5351
+ * always nonzero.
5352
+ *
5353
+ * ZipCPU --- The default looks good enough to us.
5354
+ */
5355 103 dgisselq
+#undef HARD_REGNO_RENAME_OK
5356 102 dgisselq
+#define        HARD_REGNO_RENAME_OK(FROM,TO)   ((is_ZIP_GENERAL_REG(FROM))&&(is_ZIP_GENERAL_REG(TO)))
5357
+
5358
+
5359
+/* MODES_TIABLE_P(M1, M2) ... A C expression that is nonzero if a value of mode
5360
+ * M1 is accessible in mode M2 without copying.
5361
+ *
5362
+ * ZipCPU --- well, that's true for us (although we support scant few modes) ...
5363
+ * so lets' set to one.
5364
+ */
5365 103 dgisselq
+#define        MODES_TIEABLE_P(M1,M2)  1
5366 102 dgisselq
+
5367
+/* TARGET_HARD_REGNO_SCRATCH_OK(REGNO)
5368
+ * This target hook should return true if it is OK to use a hard register
5369
+ * REGNO as a scratch register in peephole2.  One common use of this macro is
5370
+ * to prevent using of a register that is not saved by a prologue in an
5371
+ * interrupt handler.  The default version of this hook always returns true.
5372
+ *
5373
+ * ZipCPU --- the default works for us as well.  If you are in an interrupt
5374
+ * context, you have an entirely new set of registers (the supervisor set), so
5375
+ * this is a non-issue.
5376
+ */
5377
+
5378
+/* AVOID_CCMODE_COPIES ... define this macro if the compiler should avoid
5379
+ * copies to/from CCmode register(s).  You should only define this macro if
5380 202 dgisselq
+ * support for copying to/from CCmode is incomplete.
5381 102 dgisselq
+ *
5382
+ * ZipCPU --- CCmode register copies work like any other, so we'll keep with the
5383
+ * default definition.
5384
+ */
5385
+
5386
+/* STACK_REGS ... Define this if the machine has any stack-like registers.
5387
+ *
5388
+ * Zip CPU has no stack-like registers, as their definition is different from
5389 202 dgisselq
+ * the ZipCPU stack pointer register.
5390 102 dgisselq
+ */
5391
+
5392
+/* 17.08 Register Classes */
5393
+
5394
+/* enum reg_class ... An enumerate type that must be defined with all the
5395
+ * register class names as enumerated values.  NO_REGS must be first.  ALL_REGS
5396
+ * must be the last register class, followed by one more enumerated value,
5397
+ * LIM_REG_CLASSES, which is not a register class but rather tells how many
5398
+ * classes there are.
5399
+ *
5400
+ * ZipCPU --- We'll defined register 0-13 as general registers, 14-15 in
5401
+ * all_regs, and go from there.
5402
+ */
5403
+enum   reg_class {
5404
+       NO_REGS, GENERAL_REGS,
5405
+       USER_REGS,
5406
+       ALL_REGS, LIM_REG_CLASSES
5407
+};
5408
+
5409
+/* N_REG_CLASSES ... the number of distinct register classes, defined as follows
5410
+ */
5411
+#define        N_REG_CLASSES   (int)LIM_REG_CLASSES
5412
+
5413
+/* REG_CLASS_NAMES ... An initializer containing the names of the register
5414
+ * classes as C string constants.  These names are used in writing some of the
5415
+ * debugging dumps.
5416
+ */
5417
+#define        REG_CLASS_NAMES { "NO_REGS", "GENERAL_REGS", "USER_REGS", "ALL_REGS" }
5418
+
5419
+/* REG_CLASS_CONTENTS ... An initializer containing the contents of the register
5420
+ * classes, as integers which are bit masks.  The nth integer specifies the
5421
+ * contents of class n.  That way the integer mask is interpreted as that
5422
+ * register r is in the class if (mask&(1<<r)) is 1.
5423
+ *
5424
+ * When the machine has more than 32 registers, an integer does not suffice.
5425
+ * Then the integers are replaced by sub-initializers, braced groupings
5426
+ * containing several integers.  Each sub-initializer must be suitable as an
5427
+ * initializer for the type HARD_REG_SET which is defined in 'hard-reg-set.h'.
5428
+ * In this situation, the first integer in each subinitializer corresponds to
5429
+ * registers 0-31, the second integer to registers 32-634, and so on.
5430
+ *
5431
+ * ZipCPU --- This is straight forward, three register classes, etc.
5432
+ */
5433
+#define        REG_CLASS_CONTENTS { { 0x000000000, 0}, {0x00003fff, 0}, {0x0ffff0000, 0}, {0x0ffffffff, 1} }
5434
+
5435
+/* REGNO_REG_CLASS ... A C expression whose value is a register class
5436
+ * containing hard register REGNO.  In general there is more than one such
5437 171 dgisselq
+ * class;  Choose a class which is minimal, meaning that no smaller class also
5438 102 dgisselq
+ * contains the register.
5439
+ */
5440 127 dgisselq
+#define        REGNO_REG_CLASS(R)      (is_ZIP_REG(R)?(((R)<=13)?GENERAL_REGS:ALL_REGS):NO_REGS)
5441 102 dgisselq
+
5442
+/* BASE_REG_CLASS ... A macro whose definition is the name of the class to which
5443
+ * a valid base register must belong.  A base register is one used in an address
5444 171 dgisselq
+ * which is the register value plus a displacement.
5445
+ */
5446
+#undef BASE_REG_CLASS
5447
+#define        BASE_REG_CLASS  GENERAL_REGS
5448
+
5449
+/* MODE_BASE_CLASS(MODE) ... This is a variation of the BASE_REG_CLASS macro
5450 102 dgisselq
+ * which allows the selection of a bse register in a mode dependent manner.  If
5451
+ * mode is VOIDmode then it should return the same value as BASE_REG_CLASS.
5452
+ */
5453 171 dgisselq
+#undef MODE_BASE_CLASS
5454 102 dgisselq
+#define        MODE_BASE_CLASS(MODE)   GENERAL_REGS
5455
+
5456
+/* MODE_BASE_REG_REG_CLASS(MODE) ... A C expression whose value is the register
5457
+ * class to which a valid base register must belong in order to be used in a
5458
+ * base plus index register address.  You should define this macro if base plus
5459
+ * index addresses have different requirements than other base register uses.
5460 171 dgisselq
+ *
5461 102 dgisselq
+ * Zip CPU does not support the base plus index addressing mode, thus ...
5462
+ */
5463
+// #undef      MODE_BASE_REG_REG_CLASS
5464
+// #define     MODE_BASE_REG_REG_CLASS(MODE)   NO_REGS
5465
+
5466
+/* INDEX_REG_CLASS ... A macro whose definition is the name of the class to
5467
+ * which a valid index register must belong.  An index register is one used in
5468
+ * an address where its value is either multiplied by a scale factor or added
5469
+ * to another register (as well as added to a displacement).
5470
+ *
5471
+ * ZipCPU -- Has no index registers.
5472
+ */
5473
+#undef INDEX_REG_CLASS
5474
+#define        INDEX_REG_CLASS NO_REGS
5475
+
5476
+/* REGNO_OK_FOR_BASE_P(NUM) ... A C expression which is nonzero if register
5477
+ * number num is suitable for use as a base register in operand addresses.
5478
+ */
5479
+#undef REGNO_OK_FOR_BASE_P
5480
+# define REGNO_OK_FOR_BASE_P(NUM)      ((NUM>=FIRST_PSEUDO_REGISTER)||(NUM != zip_CC))
5481
+
5482
+/* REGNO_MODE_OK_FOR_BASE_P ... A C expressison that is just like
5483 111 dgisselq
+ * REGNO_OK_FOR_BASE_P, except that that expression may examine the mode of the
5484
+ * memory reference in MODE.  You should define this macro if the mode of the
5485 102 dgisselq
+ * memory reference affects whether a register may be used as a base register.
5486
+ *
5487
+ * ZipCPU --- the mode doesn't affect anything, so we don't define this.
5488
+ */
5489
+
5490
+/* REGNO_MODE_OK_FOR_REG_BASE_P(NUM, MODE) ... base plus index operand
5491
+ * addresses, accessing memory in mode mode.
5492
+ *
5493
+ * Use of this macro is deprecated.
5494
+ */
5495
+
5496
+/* REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) ... A C expression which is
5497
+ * nonzero if a register number N is suitable for use as a base register in
5498
+ * operand addresses, accessing memory in mode M in address space AS.  This is
5499
+ * similar to REGNO_MODE_OK_FOR_BASE_P, except that the expression may examine
5500 127 dgisselq
+ * the context in which the register appears in the memory reference.
5501 102 dgisselq
+ *
5502
+ * ZipCPU---We aren't specific in how we use our registers.
5503
+ */
5504 111 dgisselq
+#define        REGNO_MODE_CODE_OK_FOR_BASE_P(N,M,AS,OC,IC) REGNO_OK_FOR_BASE_P(N)
5505 102 dgisselq
+
5506
+/* REGNO_OK_FOR_INDEX_P(REGNO) ... A C expression which is nonzero if register
5507
+ * num is suitable for use as an index register in opernad addressess.  It may
5508
+ * be either a suitable hard register or a pseudo register that has been
5509
+ * allocated such as a hard register.
5510
+ *
5511
+ * ZipCPU has no index registers, therefore we declare this to be zero.
5512
+ */
5513
+#undef REGNO_OK_FOR_INDEX_P
5514
+#define        REGNO_OK_FOR_INDEX_P(REGNO)     0
5515
+
5516 111 dgisselq
+/* TARGET_PREFERRED_RENAME_CLASS(RCLASS) ... A target hook that places
5517 102 dgisselq
+ * additional preference on the register class to use when it is necessary to
5518
+ * rename a register in class RCLASS to another class, or perhaps NO_REGS, if no
5519
+ * preferred register class is found or hook preferred_rename_class is not
5520
+ * implemented.  SOmething returning a more restrictive class makes better code.
5521
+ * For example, on ARM, thumb-2 instructions using LO_REGS may be smaller than
5522
+ * instructions using GENERIC_REGS.  By returning LO_REGS from
5523
+ * preferred_rename_class, code size can be reduced.
5524
+ */
5525
+// #undef TARGET_PREFERRED_RENAME_CLASS
5526
+// #define     TARGET_PREFERRED_RENAME_CLASS(RCLASS)   RCLASS
5527
+
5528
+/* TARGET_PREFERRED_RELOAD_CLASS(X,RC) ... A target hook that places additional
5529 111 dgisselq
+ * restri tions on the register class to use when it is necessary to copy value
5530 102 dgisselq
+ * X into a register in class RC.  The value is a register class; rehaps RC, or
5531
+ * perhaps a smaller class.
5532
+ *
5533
+ * The default fversion of this hook always returns value of RC argument, which
5534
+ * sounds quite appropriate for the ZipCPU.
5535
+ */
5536
+
5537
+/* PREFERRED_RELOAD_CLASS(X,CLASS) ... A C expression that places additional
5538
+ * restrictions on the register class to use when it is necessary to copy
5539
+ * value X into a register in class CLASS.  On many machines, the following
5540
+ * definition is safe: PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
5541
+ * Sometimes returning a more restrictive class makes better code.  For example,
5542
+ * on the 68k, when x is an integer constant that is in range for a moveq
5543
+ * instruction, the value of this macro is always DATA_REGS as long as CLASS
5544
+ * includes the data registers.  Requiring a data register guarantees that a
5545
+ * 'moveq' will be used.
5546
+ *
5547
+ * ZipCPU --- you can't load certain values into all members of ALL_REGS.  For
5548
+ * example, loading (sleep and !gie) into the CC register could halt the CPU.
5549
+ * Hence, we only allow loads into the GENERAL_REG class.
5550
+ */
5551
+#define        PREFERRED_RELOAD_CLASS(X, CLASS)        GENERAL_REGS
5552
+
5553
+/* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS(RTX,RCLASS) ... Like TARGET_PREFERRED_..
5554
+ * RELOAD_CLASS, but for output instead of input reloads.
5555
+ *
5556
+ * ZipCPU --- there's gotta be a valid default behaviour for this.
5557
+ */
5558
+
5559
+/* LIMIT_RELOAD_CLASS(MODE, CL) ...
5560
+ *
5561
+ * Don't define this macro unless the target machine has limitations which
5562
+ * require the macro to do something nontrivial.  ZipCPU doesn't, so we won't.
5563
+ */
5564 111 dgisselq
+
5565 102 dgisselq
+/* TARGET_SECONDARY_RELOAD
5566
+ * SECONDARY_ ...
5567
+ * Don't think we need these ...
5568
+ */
5569
+
5570
+/* CLASS_MAX_NREGS(CLASS,MODE) ... A C expression for the maximum number of
5571
+ * consecutive registers of class CLASS needed to hold a value of mode MODE.
5572
+ *
5573
+ * This is closely related to the macro HARD_REGNO_NREGS.  In fact, the value
5574
+ * of the macro CLASS_MAX_REGS(CL,M) should be the maximum value of
5575
+ * HARD_REGNO_NREGS(REGNO,MODE) for all REGNO values in the class CLASS.
5576
+ *
5577
+ * This macro helps control the handling of multiple word values in the reload
5578
+ * pass.
5579
+ *
5580
+ * ZipCPU --- We'll just use HARDNO_REGNO_NREGS, since CLASS is independent for
5581
+ * us.  We'll also choose register R0, since ... well, since it simply doesn't
5582
+ * matter.  (HARD_REGNO_NREGS ignores this anyway)
5583
+ */
5584
+#define        CLASS_MAX_NREGS(CLASS, MODE)    HARD_REGNO_NREGS(0,MODE)
5585
+
5586
+/* CANNOT_CHANGE_MODE_CLASS
5587
+ * ???
5588
+ */
5589
+
5590
+/* TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
5591
+ */
5592
+
5593
+/* TARRGET_LRA_P
5594
+ * Default looks good.
5595
+ */
5596
+
5597
+/* TARGET_REGISTER_PRIORITY(INT) ... A target hook which returns the register
5598
+ * priority number to which the register HARD_REGNO belongs to.  The bigger the
5599
+ * number
5600
+ *
5601
+ * The default version of this target hook returns always zero---good enough for
5602
+ * the ZipCPU.
5603
+ */
5604
+
5605
+/* TARGET_REGISTER_USAGE_LEVELING_P(VOID) ... A target hook which returns true
5606
+ * if we need register usage leveling.  That means if a few hard registers are
5607
+ * equally good for the assignment, we choose the least used hard register.  The
5608
+ * register usage leveling may be profitable for some targets.  Don't use usage
5609
+ * leveling for targets with conditional execution or targets with big register
5610
+ * files as it hurts if-conversion and cross-jumping optimizations.  The default
5611
+ * version of this target hook returns always false.
5612
+ *
5613
+ * ZipCPU --- Default is the right answer.
5614
+ */
5615
+
5616
+/* TARGET_DIFFERENT_ADDR_DISPLACEMENT_P ...
5617
+ * Default looks good.
5618 111 dgisselq
+ */
5619 102 dgisselq
+
5620
+/* TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P ...
5621
+ * Default looks good.
5622
+ */
5623
+
5624
+/* TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT ....
5625
+ */
5626
+
5627
+/* TARGET_SPILL_CLASS
5628
+ *
5629
+ * ZipCPU --- If we were running in supervisor mode only, this might be the
5630
+ * user set of registers.  However, we're not building for that mode (now),
5631
+ * so we'll leave this at the default of NO_REGS.
5632
+ */
5633
+
5634
+/* TARGET_CSTORE_MODE(ICODE) ... Defines the machine mode to use for the
5635
+ * boolean result of conditional store patterns.  The ICODE argument is the
5636
+ * instruction code for the cstore being performed.  Not defining this hook is
5637
+ * the same as accepting the mode encoded into operand 0 of the cstore expander
5638
+ * patterns.
5639
+ *
5640
+ * ??? ZipCPU --- I don't follow this documentation.  We'll leave this at the
5641
+ * default therefore.
5642
+ */
5643
+
5644
+/* 17.09 Stack Layout and Calling Conventions */
5645
+
5646
+
5647
+/* STACK_GROWS_DOWNWARD ... Define this macro if pushing a word onto the stack
5648
+ * moves the stack pointer to a smaller address, and false otherwise.
5649
+ *
5650
+ * ZipCPU ... well, our stack does grow downward, but it doesn't do so auto-
5651
+ * magically.  We have to move the stack pointer ourselves.  However, since this
5652
+ * is our convention, we'll define it as such.
5653
+ */
5654
+#undef STACK_GROWS_DOWNWARD
5655 202 dgisselq
+#define        STACK_GROWS_DOWNWARD    1
5656 102 dgisselq
+
5657
+/* STACK_PUSH_CODE ... This macro defines the operation used when something is
5658
+ * pushed on the stack.  In RTL, a push operation will be
5659
+ * (set (mem( STACK_PUSH_CODE(reg sp))) ...) The choiecs are PRE_DEC, POST_DEC,
5660
+ * PRE_INC, and POST_INC.  Which of these is correct depends on the stack
5661
+ * direction and on whether the stack pointer points to the last item on the
5662
+ * stack or whether it points to the space for the next item on the stack.
5663
+ * The default is PRE_DECC when STACK_GROWS_DOWNWARD is true, which is almost
5664
+ * always right, and PRE_INC otherwise, which is often wrong.
5665
+ *
5666
+ * ZipCPU --- None of these is right, so let's leave this at the default and
5667
+ * see how badly we get mangled.  In particular, ZipCPU doesn't have any of the
5668
+ * PRE_DEC, POST_DEC, PRE_INC, or POST_INC addressing modes used here.
5669
+ */
5670
+
5671
+/* FRAME_GROWS_DOWNWARD ... Define this macro to nonzero if the addresses of
5672
+ * local variable slots are at negative offsets from the frame pointer.
5673
+ *
5674
+ * ZipCPU --- If the frame pointer is defined as the stack pointer upon the
5675
+ * start of function execution, and that stack pointer grows downward, then
5676
+ * this should be the case as well.
5677
+ */
5678
+#undef FRAME_GROWS_DOWNWARD
5679
+#define        FRAME_GROWS_DOWNWARD    1
5680
+// #define     FRAME_GROWS_DOWNWARD    0        // This was ECO32's value
5681
+
5682
+
5683
+/* ARGS_GROW_DOWNWARD ... Define this macro if successive arguments to a
5684
+ * function occupy decreasing addresses on the stack.
5685
+ *
5686
+ * ZipCPU -- we can leave this up to the compiler's preferred implementation,
5687
+ * it is of no consequence to the hardware.
5688
+ */
5689
+
5690
+/* STARTING_FRAME_OFFSET ... Offset from the frame pointer to the first local
5691
+ * variable slot to be allocated.  If FRAME_GROWS_DOWNWARD, find the next slot's
5692
+ * offset by subtracting the first slot's length from STARTING_FRAME_OFFSET.
5693
+ * Otherwise it is found by adding the length of the first slot to the value
5694
+ * START_FRAME_OFFSET.
5695 103 dgisselq
+ *
5696 102 dgisselq
+ * ZipCPU --- I'm not certain on this, let's come back after we look at how
5697
+ * the code is getting generated.  However, the ECO32 code I am copying from
5698
+ * suggests that 0 is the right value, so we'll use that here.
5699
+ */
5700
+// #warning "Re-evaluate me" --- I did.  This still looks good.
5701
+#define        STARTING_FRAME_OFFSET   0
5702
+
5703
+/* STACK_ALIGNMENT_NEEDED ... Define to zero to disable final alignment of the
5704
+ * stack during reload.  The nonzero default for this macro is suitable for most
5705
+ * ports.
5706
+ *
5707
+ * ZipCPU --- Yes, our stack needs to be aligned.  The default should work
5708
+ * nicely.
5709
+ */
5710
+
5711
+/* STACK_POINTER_OFFSET ... Offset from the SP register to the first location at
5712 171 dgisselq
+ * which outgoing arguments are placed.  If not specified, the default value
5713 102 dgisselq
+ * of zero is used.  This is the proper value for most machines.
5714
+ */
5715
+#define        STACK_POINTER_OFFSET    0
5716
+
5717
+/* FIRST_PARM_OFFSET ... Offset from the argument pointer register to the first
5718
+ * argument's address.  On some machines it may depend on the data type of the
5719
+ * function.
5720 171 dgisselq
+ */
5721 102 dgisselq
+#define        FIRST_PARM_OFFSET(F)    0
5722
+
5723
+/* STACK_DYNAMIC_OFFSET(F) ... Offset from the stack pointer register to an item
5724
+ * dynamically allocated on the stack, e.g., by alloca.  The default value for
5725
+ * this macro is STACK_POINTER_OFFSET plus the length of the outgoing arguments.
5726
+ * The default is correct for most machines, ...
5727 202 dgisselq
+ *
5728
+ * ZipCPU --- so we'll use it for the ZipCPU.
5729 102 dgisselq
+ */
5730
+
5731
+/* INITIAL_FRAME_ADDRESS_RTX ... A C expression whose value is RTL representing
5732
+ * the address of the initial stack frame.  This address is passed to
5733
+ * RETURN_ADDR_RTX and DYNAMIC_CHAIN_ADDRESS.  If you don't define this macro,
5734
+ * a reasonable default value will be used.  Define this macro in order to make
5735
+ * frame pointer elimination work in the presence of __builtin_frame_address(C)
5736
+ * and __builtin_return_address(C) for (C) not equal to zero.
5737
+ *
5738
+ * ZipCPU --- Let's try the reasonable default and see what happens.
5739 171 dgisselq
+ */
5740 102 dgisselq
+
5741
+/* SETUP_FRAME_ADDRESSES ... A C expression that produces the machine-specific
5742
+ * code to setup the stack so that arbitrary frames can be accessed.  For
5743
+ * example, on the SPARC, we must flush all of the register windows to the stack
5744
+ * before we can access arbitrary stack frames.  You will seldom need to define
5745
+ * this macro.  The default is to do nothing.
5746
+ *
5747
+ * ZipCPU --- which is what we shall do here.
5748
+ */
5749
+
5750
+/* TARGET_BUILTIN_SETJMP_FRAME_VALUE(VOID) ... This target hook should return
5751
+ * an RTX that is used to store the address of the current frame into the
5752
+ * builtin setjmp buffer.  The default value, virtual_stack_vars_rtx, is correct
5753
+ * for most machines.  One reason you may need to define this target hook is if
5754
+ * hard_frame_pointer_rtx is the appropriate value on your machine.
5755
+ *
5756
+ * ZipCPU --- leave this undefined, since the default value should be correct
5757
+ * for "most" machines.
5758
+ */
5759
+
5760
+/* FRAME_ADDR_RTX ... most machines do not need to define it.
5761
+ */
5762
+
5763
+/* RETURN_ADDR_RTX(COUNT,FRAMEADDR) ... A C expression whose value is RTL
5764
+ * representing the value of the return address for the frame COUNT steps up
5765
+ * from the current frame, after the prologue.  FRAMEADDR is the frame pointer
5766
+ * of the COUNT frame, or the frame pointer of the COUNT-1 frame if
5767
+ * RETURN_ADDR_IN_PREVIOUS_FRAME is nonzero.  The value of the expression must
5768
+ * always be the correct address when COUNT is nonzero, but may be NULL_RTX if
5769
+ * there is no way to determine the return address of other frames.
5770
+ *
5771
+ * ZipCPU --- Our answer for the current frame is ... it depends.  If we can
5772
+ * force the use of a frame in every debug context, we could compute this for
5773
+ * COUNT != 0.  For now, we'll just look at the registers we save and return
5774
+ * where the return address is in the current frame.  To do that, though, we
5775
+ * need some help from C.
5776
+ */
5777
+#undef RETURN_ADDR_RTX
5778
+#define        RETURN_ADDR_RTX(COUNT,FRAMEADDR)        zip_return_addr_rtx(COUNT,FRAMEADDR)
5779
+
5780
+/* RETURN_ADDR_IN_PREVIOUS_FRAME ... Define this macro to nonzero value if the
5781
+ * return address of a particular stack frame is accessed from the frame pointer
5782
+ * of the previous stack frame.  The zero default for this macro is suitable
5783
+ * for most ports.
5784
+ *
5785
+ * ZipCPU---Default works here as well.
5786
+ */
5787
+
5788
+/* INCOMING_RETURN_ADDR_RTX ... A C expression whose value is RTL representing
5789
+ * the location of the incoming return address at the beginning of any function,
5790
+ * before the prologue.  This RTL is either a REG, indicating that the return
5791 202 dgisselq
+ * value is saved in 'REG', or a MEM representing the location in the stack.
5792
+ * If this RTL is a REG, you should define DWARF_RETURN_COLUMN to
5793
+ * DWARF_FRAME_REGNUM(REGNO).
5794
+ *
5795
+ * ZipCPU --- While our incoming return address could theoretically be in any
5796 102 dgisselq
+ * register, our machine description file is going to place it into register
5797
+ * R0, so that's what we return here.
5798 202 dgisselq
+ */
5799 102 dgisselq
+#undef INCOMING_RETURN_ADDR_RTX
5800
+#define        INCOMING_RETURN_ADDR_RTX        gen_rtx_REG(SImode, zip_LR)
5801
+
5802
+
5803
+/* DWARF_ALT_FRAME_RETURN_COLUMN
5804
+ */
5805
+
5806
+/* DWARF_ZERO_REG ... A C exrpession whose value is an integer giving a DWARF2
5807
+ * register number that is considered to always have the value zero.  This
5808
+ * should only be defined if the target has an architected zero register (ZipCPU
5809
+ * does not), and someone decided it was a good idea to use that register number
5810
+ * to terminate the stack backtrace.  New ports should avoid this (so the
5811
+ * ZipCPU port will avoid it as well).
5812
+ *
5813
+ */
5814
+
5815
+/* TARGET_DWARF_HANDLE_FRAME_UNSPEC
5816
+ */
5817
+
5818
+/* INCOMING_FRAME_SP_OFFSET ... A C expression whose value is an integer giving
5819
+ * the offset, in bytes, from the value of the stack pointer register to the
5820 202 dgisselq
+ * top of the stack frame at the beginning of any function, before the prologue.
5821 102 dgisselq
+ * The top of the frame is defined to be the value of the stack pointer in the
5822
+ * previous frame, just before the call instruction.
5823
+ *
5824
+ * You only need to define this macro if you want to support call frame
5825
+ * debugging information like that provided by DWARF 2.
5826
+ *
5827
+ * ZipCPU---Our value is zero.
5828
+ */
5829
+#define        INCOMING_FRAME_SP_OFFSET        0
5830
+
5831
+/* ARG_POINTER_CFA_OFFSET
5832
+ */
5833
+
5834
+/* FRAME_POINTER_CFA_OFFSET
5835
+ */
5836
+
5837
+/* CFA_FRAME_BASE_OFFSET
5838 171 dgisselq
+ */
5839
+
5840
+/* 17.09.02 Exception handling support */
5841
+
5842
+/* EH_RETURN_DATA_REGNO(N) ... A C expression whose value is the Nth register
5843
+ * number used for data by exception handlers, or INVALID_REGNUM if fewer than
5844
+ * N registers are usable.  The exception handling library routines communicate
5845
+ * with the exception handlers via a set of agreed upon registers.  Ideally
5846
+ * these registers should be call clobbered; it is possible to use call-saved
5847
+ * registers, but may negatively impact code size.  The target must support at
5848 102 dgisselq
+ * least 2 data registers, but should define 4 if their are enough free
5849
+ * registers.
5850
+ *
5851
+ * You must define this macro if you want to support call frame exception
5852
+ * handling like that provided by DWARF 2.
5853
+ *
5854
+ * ZipCPU -- We copy much of our definition from Moxie.
5855
+ */
5856
+#define        EH_RETURN_DATA_REGNO(N) ((N<3)?(N+ZIP_FIRST_ARG_REGNO):INVALID_REGNUM)
5857
+
5858
+/* EH_RETURN_STACKADJ_RTX ... A C expression whose value is RTL representing
5859
+ * a location in which to store a stack adjustment to be applied before function
5860
+ * return.  This is used to unwind the stack to an exception handler's call
5861
+ * frame.  It will be assigned zero on code paths that return normally.
5862
+ *
5863
+ * Do not define this macro if the stack pointer is saved and restored by the
5864
+ * regular prolog and epilog code in the call frame itself (which it is for the
5865
+ * ZipCPU); in this case, the exception handling library routines will update
5866
+ * the stack location to be restored in place.  Otherwise, you must define this
5867
+ * macro if you want to support call frame exception handling like that provided
5868
+ * by DWARF 2.
5869
+ *
5870
+ */
5871
+
5872
+/* EH_RETURN_HANDLER_RTX ... A C expression whose value is RTL representing a
5873 202 dgisselq
+ * location in which to store the address of an exception handler to which we
5874
+ * should return.  It will not be assigned on code paths that return normally.
5875 102 dgisselq
+ *
5876 202 dgisselq
+ * Typcally this is the location in the call frame at which the normal return
5877 102 dgisselq
+ * address is stored.  For targets that return by popping an address of the
5878
+ * stack, this might be a memory address just below the target call frame
5879
+ * rather than inside the current call frame.  If defined,
5880
+ * EH_RETURN_STACKADJ_RTX will have already been assigned, so it may be used
5881
+ * to calculate the location of the target call frame.
5882
+ *
5883
+ * If you want to support call frame exception handling, you must define either
5884
+ * this macro or the eh_return instruction pattern.
5885
+ *
5886
+ * ZipCPU --- We again copy from Moxie
5887
+ */
5888
+#define        EH_RETURN_HANDLER_RTX   \
5889
+       gen_frame_mem(Pmode, plus_constant(Pmode, frame_pointer_rtx, UNITS_PER_WORD))
5890
+
5891
+/*
5892
+ *
5893
+ *
5894
+ *
5895
+ *   REST OF SECTION SKIPPED ...
5896
+ *
5897
+ *
5898 202 dgisselq
+ *
5899 102 dgisselq
+ */
5900
+
5901
+/* 17.09.03 Specifying how stack checking is done */
5902
+
5903
+/* STACK_CHECK_BUILTIN ... a non-zero value if stack checking is done by the
5904
+ * configuration files in a machine-dependent manner.  You should define this
5905 202 dgisselq
+ * macro if stack checking is required by the ABI of your machine or if you
5906
+ * would like to do stack checking in some more efficient way than the generic
5907 102 dgisselq
+ * appraoch.  The default value of this macro is zero.
5908 202 dgisselq
+ *
5909
+ * ZipCPU --- The default makes sense for us.
5910 102 dgisselq
+ */
5911
+// #define STACK_CHECK_BUILTIN 0
5912
+
5913
+/* STACK_CHECK_STATIC_BUILTIN ... A nonzero value if static stack checking is
5914
+ * done by the configuration files in a machine-dependent manner.  You should
5915
+ * define this macro if you would like to do static stack checking in some more
5916
+ * efficient way than the generic approach.  The default value of this macro
5917
+ * is zero.
5918
+ *
5919
+ * ZipCPU --- The default makes sense for us.
5920
+ */
5921
+
5922
+/* STACK_CHECK_PROBE_INTERVAL_EXP ...  An integer specifying the interval at
5923
+ * which GCC must generate stack probe instructions, defined as 2 raised to this
5924
+ * interval.  You will normally define this macro so that the interval is no
5925
+ * larger than the size of the "guard pages" at the end of a stack area.  The
5926
+ * default value of 12 (4096-byte interval) is suitable for most systems.
5927
+ *
5928
+ * ZipCPU --- Default.
5929
+ */
5930
+
5931
+/* STACK_CHECK_MOVING_SP ... An integer which is non-zero if GCC should move
5932
+ * the stack pointer page by page when doing probes.  This can be necessary
5933
+ * on systems where the stack pointer contains the bottom address of the memory
5934
+ * area accessible to the executing thread at any point in time.  In this
5935
+ * situation, an alternate signal stack is required in order to be able to
5936
+ * recover from a stack overflow.  The default value of this macro is zero.
5937
+ *
5938
+ * ZipCPU -- Default.
5939
+ */
5940
+
5941
+/* STACK_CHECK_PROTECT
5942
+ */
5943
+/* STACK_CHECK_MAX_FRAME_SIZE
5944
+ * ... you should normally not change the default value of this macro.
5945
+ */
5946
+/* STACK_CHECK_FIXED_FRAME_SIZE
5947
+ * ... you ... will normally use the default of four words.
5948
+ */
5949
+
5950
+/* STACK_CHECK_MAX_VAR_SIZE
5951
+ * ... you will normally not need to override that default.
5952
+ */
5953
+
5954
+/* 17.09.04 Registers that Address the Stack Frame*/
5955
+
5956
+/* STACK_POINTER_REGNUM ... The register number of the stack pointer register,
5957
+ * which must also be a fixed register according to FIXED_REGISTERS.  On most
5958
+ * machines, the hardware determines which register this is.
5959
+ */
5960
+#undef STACK_POINTER_REGNUM
5961
+#define        STACK_POINTER_REGNUM    zip_SP
5962
+
5963
+/* FRAME_POINTER_REGNUM ... The register number of the frame pointer register,
5964
+ * which is used to access certain automatic variables in the stack frame.  On
5965
+ * some machines, the hardware determines which register this is.  On other
5966
+ * machines you can choose any register you wish for this purpose.
5967
+ *
5968
+ * ZipCPU --- While I'd like to dump this pointer, since I don't really see
5969
+ * a need for it, alloca() requires it.  Therefore let's assine a register to
5970
+ * this purpose and watch what the compiler does with it.
5971
+ */
5972
+#define        FRAME_POINTER_REGNUM    zip_FP
5973
+
5974
+/* HARD_FRAME_POINTER_REGNUM ... On some machines the offset between the frame
5975
+ * pointer and starting offset of the automatic variables is not known until
5976
+ * after register allocation has been done (for example, because the saved
5977
+ * registers are between these two locations).  On those machines, define
5978
+ * FRAME_POINTER_REGNUM the number of a special, fixed register to be used
5979
+ * internally until the offset is known, and define HARD_FRAME_POINTER_REGNUM
5980
+ * to be the actual hard register number used for the frame pointer.
5981
+ *
5982
+ * Do not define this macro if it would be the same as FRAME_POINTER_REGNUM
5983
+ *
5984
+ * ZipCPU --- we do not define this macro.
5985
+ */
5986
+#define HARD_FRAME_POINTER_REGNUM      zip_FP
5987
+
5988
+/* ARG_POINTER_REGNUM ... The register number of the arg pointer register, which
5989
+ * is used to access the function's argument list.  On some machines, this is
5990
+ * the same as the frame pointer register.  On some machines, the hardware
5991
+ * determines which register this is.  On other machines, you can choose any
5992
+ * register you wish for this purpose.  If this is not the same register as the
5993
+ * frame pointer register, then you must mark it as a fixed register according
5994
+ * to FIXED_REGISTERs, or arrange to be able to eliminate it.
5995
+ *
5996
+ * ZipCPU --- We really don't want to lose another register to something
5997
+ * pointless, so let's set this to be the frame pointer register.  Especially
5998
+ * given the ZipCPU's ease of accessing things via offsets of registers, this
5999
+ * should work for a rather large stack frame.
6000
+ *
6001
+ * However ... we had problems with passing 6+ variables on the stack, so let's
6002
+ * try creating a pseudo register for this, and appropriately adjusting the
6003
+ * offset between this pseudo register and the stack pointer ...
6004
+ */
6005
+#define        ARG_POINTER_REGNUM      zip_AP_PSEUDO
6006 103 dgisselq
+
6007 102 dgisselq
+/* HARD_FRAME_POINTER_IS_FRAME_POINTER ... define this to be a preprocessor
6008
+ * constant that is nonzero if hard_frame_pointer_rtx and frame_pointer_rtx
6009
+ * should be the same.  The default definition is sufficient for us.
6010
+ */
6011
+
6012
+/* HARD_FRAME_POINTER_IS_ARG_POINTER ...
6013
+ * ZipCPU doesn't need this macro
6014
+ */
6015
+
6016
+/* RETURN_ADDRESS_POINTER_REGNUM ... The register number of the return address
6017
+ * pointer register, which is used to access the current function's return
6018
+ * address from the stack.  On some machines, the return address is not at a
6019
+ * fixed offset from the frame pointer or stack pointer or argument pointer.
6020 171 dgisselq
+ * This register can be defined to point to the return address on the stack, and
6021
+ * then to be converted by ELIMINABLE_REGS into either the frame pointer or the
6022
+ * stack pointer.
6023
+ *
6024 102 dgisselq
+ * Do not define this macro unless there is no other way to get the return
6025 171 dgisselq
+ * address from the stack.
6026 102 dgisselq
+ *
6027
+ * ZipCPU---we need this.
6028
+ */
6029
+#define        RETURN_ADDRESS_REGNUM   zip_LR
6030
+
6031
+
6032
+/* STATIC_CHAIN_REGNUM ... Register numbers used for passing a function's
6033
+ * static chain pointer.  If register windows are used, the register number as
6034
+ * seen by the called function is STATIC_CHAIN_INCOMING_REGNUM, while the
6035
+ * register number as seen by the calling function is STATIC_CHAIN_REGNUM.  If
6036
+ * these register are the same, STATIC_CHAIN_INCOMING_REGNUM need not be
6037
+ * defined.
6038
+ *
6039
+ * ZipCPU --- even without register windows, we still need to pick an
6040
+ * (arbitrary) register to pass the pointer to the static chain in the case of
6041
+ * nested functions.  Let's arbitrarily pick R5, and ... see how that works for
6042
+ * us.
6043
+ */
6044
+#define        STATIC_CHAIN_REGNUM     zip_R5
6045
+
6046
+/* TARGET_STATIC_CHAIN ... This hook replaces the use of STATIC_CHAIN_REGNUM et
6047
+ * al for targets that may use different static chain locations for different
6048
+ * nested functions.  This may be required if the target has function attributes
6049 202 dgisselq
+ * that affect the calling conventions of the function and those calling
6050 102 dgisselq
+ * conventions use different static chain locations.
6051
+ *
6052
+ * ZipCPU --- don't need this.
6053
+ */
6054
+// #define     TARGET_STATIC_CHAIN     zip_R11
6055
+
6056
+
6057
+/* DWARF_FRAME_REGISTERS ... This macro specifies  the maximum number of hard
6058
+ * registers that can be saved in a call frame.  This is used to size data
6059 202 dgisselq
+ * structures used in DWARF2 exception handling.
6060
+ *
6061
+ * Prior to GCC 3.0, this macro was needed in order to establish a stable
6062
+ * exception handling ABI in the face of adding new hard registers for ISA
6063 102 dgisselq
+ * extensions.  In GCC 3.0 and later, the EH ABI is insulated from changes in
6064 202 dgisselq
+ * the number of hard registers.  Nevertheless, this macro can still be used to
6065 102 dgisselq
+ * reduce the runtime memory requirements of the exception handling routines,
6066
+ * which can be substantial if the ISA contains a lot of registers that are not
6067
+ * call-saved.
6068
+ *
6069
+ * If this macro is not defined, it defaults to FIRST_PSEUDO_REGISTER.
6070
+ *
6071
+ * ZipCPU --- The default is not sufficient.  The CC and PC registers need to
6072
+ * be saved and examined as well in any debug/exception context.  Hence, we
6073
+ * define this to be all of our registers.
6074 202 dgisselq
+ */
6075 102 dgisselq
+#undef DWARF_FRAME_REGISTERS
6076
+#define        DWARF_FRAME_REGISTERS   16
6077
+
6078
+/* PRE_GCC3_DWARF_FRAME_REGISTERS ... This macro is similar to DWARF_FRAME_REG..
6079
+ * but is provided for backward compatibility in pre GCC 3.0 compiled code.
6080
+ *
6081
+ * If not defined, it defaults to DWARF_FRAME_REGISTERS---which is perfect for
6082
+ * the ZipCPU.
6083
+ */
6084
+
6085
+/* DWARF_REG_TO_UNWIND_COLUMN(REGNO) ... Define this macro if the target's
6086
+ * representation for dwarf registers is different than the internal
6087
+ * representation for unwind column.  Given a dwarf register, this macro should
6088
+ * return the unwind column number to use instead.
6089
+ *
6090
+ * ... ???
6091
+ */
6092
+
6093
+/* DWARF_FRAME_REGNUM(REGNO) ... Define this macro is the target's
6094
+ * representation for dwarf registers used in .eh_frame or .debug_frame is
6095
+ * different from that used in other debug info sections.  Given a GCC hard
6096
+ * register number, this macro should return the .eh_frame register number.
6097
+ * The default is DBX_REGISTER_NUMBER(REGNO).
6098
+ *
6099
+ * ZipCPU --- provided we define DBX_REGISTER_NUMBER(REGNO) well, this default
6100
+ * should still work for us.
6101
+ */
6102
+
6103
+/* DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) ... Define this macro to map register
6104
+ * numbers held in the call frame info that GCC has collected using
6105
+ * DWARF_FRAME_REGNO to those that should be output in .debug_frame (for_eh is
6106
+ * zero) and .eh_frame (for_eh is non-zero). The default is to return REGNO.
6107
+ *
6108
+ * ZipCPU --- Default is good enough.
6109
+ */
6110
+
6111
+/* REG_VALUE_IN_UNWIND_CONTEXT ... Define this macro if the target stores
6112
+ * register values as _Unwind_Word type in unwind context.  It should be defined
6113
+ * if target register size is larger than the size of void *.  The default
6114
+ * is to store register values as void *type.
6115
+ *
6116
+ * ZipCPU --- Default is what we need.
6117
+ */
6118
+
6119
+/* ASSUME_EXTENDED_UNWIND_CONTEXT ... Define this macro to be 1 if the target
6120
+ * always uses extended unwind context with version, args_size, and by_value
6121
+ * fields.  If it is undefined, it will always be defined to 1 when REG_VALUE_IN_UNWIND_CONTEXT is defined and 0 otherwise.
6122
+ *
6123
+ */
6124
+
6125
+
6126
+/* 17.09.05 Eliminating Frame Pointer and Arg Pointer */
6127
+
6128
+/* TARGET_FRAME_POINTER_REQUIRED(VOID) ... This target hook should return true
6129
+ * if a function must have and use a frame pointer.  This target hook is
6130
+ * called in the reload pass.  If its return value is true, the function will
6131
+ * have a frame pointer.
6132
+ *
6133
+ * This target hook can in principle examine the current function and decide
6134
+ * according to the facts, but on most machines the constant false or the
6135
+ * constant true suffices.  Use false when the machine allows code to be
6136
+ * generated with no frame pointer, and doing so saves some time or space.
6137
+ * Use true when there is no possible advantage to avoiding a frame pointer.
6138
+ *
6139
+ * ZipCPU---if we add in a frame pointer, we become register starved.  Hence,
6140
+ * we'll treat this as a constant false--which is also the default value.
6141
+ */
6142
+#define        target_frame_pointer_required   zip_frame_pointer_required
6143
+
6144
+/* INITIAL_FRAME_POINTER_OFFSET ... A C statement to store in the variable
6145
+ * depth-var the difference between the frame pointer and the stack pointer
6146
+ * values immediately after the function prologue.  The value would be computed
6147
+ * from information such as the result of get_frame_size() and the tables of
6148
+ * registers regs_ever_live and call_used_regs.
6149
+ *
6150
+ * If ELIMINABLE_REGS is defined, this macro will not be used and need not be
6151
+ * defined.  Otherwise, it must be defined even if TARGET_FRAME_POINTER_REQD
6152
+ * always returns true; in that case you may set depth-var to anything.
6153
+ *
6154
+ * ZipCPU --- we intend to set ELIMINABLE_REGS, so this is not necessary.
6155
+ */
6156
+// #define     INITIAL_FRAME_POINTER_OFFSET(DEPTH)     (DEPTH) = 0
6157
+
6158
+
6159
+/* ELIMINABLE_REGS ... If defined, this macro specifies a table of register
6160
+ * pairs used to eliminate unneeded registers that point into the stack frame.
6161
+ * If it is not defined, the only elimination attempted by the compiler is to
6162
+ * replace references to the frame pointer with references to the stack pointer.
6163
+ *
6164
+ * On some machines, the position of the argument pointer is not known until
6165
+ * the compilation is completed.  In such a case, a separate hard register
6166
+ * must be used for the argument pointer.  This register can be eliminated by
6167
+ * replacing it with either the frame pointer or the argument pointer,
6168
+ * depending on whether or not the frame pointer has been eliminated.
6169
+ *
6170
+ * ZipCPU we'll take their suggestion and define this as:
6171
+ */
6172
+#undef ELIMINABLE_REGS
6173
+#define        ELIMINABLE_REGS \
6174
+       {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },  \
6175
+        { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },  \
6176
+        { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
6177
+
6178
+/* bool TARGET_CAN_ELIMINATE(FROM,TO) ... This target function should return
6179
+ * true if the compiler is allowed to try to replace register number FROM with
6180
+ * register number TO.  This target hook need only be defined if ELIMINABLE_REGS
6181
+ * is defined, and will usually return true since most of the cases preventing
6182
+ * register elimination are things that the compiler  already knows about.
6183
+ *
6184
+ * ZipCPU ... does the compiler  know about my decision as to whether or not
6185
+ * the frame pointer was needed?  Yes it does, but it's kept separately.  We'll
6186
+ * just say everything can be eliminated.
6187
+ */
6188
+#define TARGET_CAN_ELIMINATE   zip_can_eliminate
6189
+
6190
+/* INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) ... This macro is similar to
6191
+ * INITIAL_FRAME_POINTER_OFFSET.  It specifies the initial difference between
6192
+ * the specified pair of registers.  This macro must be defined if
6193
+ * ELIMINABLE_REGS is defined.
6194
+ *
6195
+ * ZipCPU---We had at one time set this to a default offset of 0.  This didn't
6196
+ * work.  It turns out that this is not only the *initial* elimination offset,
6197
+ * but also the offset along the way.  Hence, when a variable needs to be
6198
+ * spilled to the stack, this offset must change.  Reload goes and checks for
6199
+ * this, and adjusts registers if the offset has changed.  Hence, without this,
6200
+ * we get negative (i.e. illegal) stack offsets.
6201
+ */
6202
+#define        INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)            \
6203
+       do { (OFFSET) = zip_initial_elimination_offset((FROM), (TO)); } \
6204
+       while(0)                                        \
6205 117 dgisselq
+
6206
+/* 17.09.06 Passing function arguments on the stack */
6207 102 dgisselq
+
6208
+/* TARGET_PROMOTE_PROTOTYPES ... Returns true if an argument declared in a
6209
+ * prototype as an integral type smaller than int should actually be
6210
+ * passed as an int.  In addition to avoiding errors in certain cases of
6211
+ * mismatch, it also makes for better code on certain machines.  The default is
6212
+ * to not promote prototypes.
6213
+ *
6214
+ * Since everything is an int on the ZipCPU, let's promote anything smaller
6215 117 dgisselq
+ * (which should still be an int) up to an int anyway.
6216
+ */
6217
+#undef TARGET_PROMOTE_PROTOTYPES
6218
+#define        TARGET_PROMOTE_PROTOTYPES       hook_bool_const_tree_true
6219
+
6220
+/* PUSH_ARGS ... A C expression.  If nonzero, push instructions will be used to
6221 102 dgisselq
+ * pass outgoing arguments.  If the target machine does not have a push
6222
+ * instruction, set it to zero.  That directs GCC to use an alternate strategy:
6223
+ * to allocate the entire argument block and then store the arguments into it.
6224
+ * When PUSH_ARGS is nonzero, PUSH_ROUNDING must be defined too.
6225
+ *
6226
+ * ZipCPU does not have a push instruction, so we set this to zero.
6227
+ */
6228
+#undef PUSH_ARGS
6229
+#define        PUSH_ARGS       0
6230
+
6231
+/* PUSH_ARGS_REVERSED ... A C expression.  If nonzero, function arguments will
6232
+ * be evaluated last to first, rather than first to last.  If this macro is
6233
+ * not defined, it defaults to PUSH_ARGS on targets where the stack and args
6234
+ * grow in opposite directions, and zero otherwise.
6235
+ *
6236
+ * ZipCPU---Let's evaluate our arguments first to last.
6237
+ */
6238
+#define        PUSH_ARGS_REVERSED      1
6239
+
6240
+/* PUSH_ROUNDING(NPUSHED) ... A C expression that is the number of bytes
6241
+ * actually pushed onto the stack when an instruction attempts to push
6242
+ * (NPUSHED) bytes.
6243
+ *
6244
+ * ZipCPU---We cannot push bytes.  Let's leave this undefined and see what
6245
+ * happens.
6246
+ */
6247
+// #warning "No appropriate definition seemed right."
6248
+
6249
+/* ACCUMULATE_OUTGOING_ARGS ... A C expression.  If non-zero, the maximum amount
6250
+ * of space required for outgoing arguments will be computed and placed into
6251
+ * crtl->outgoing_args_size.  No space will be pushed onto the stack for each
6252
+ * call; instead the function prologue should increase the stack frame size by
6253
+ * this amount.
6254
+ *
6255
+ * ZipCPU---This is *cool* and so necessary---it saves an extra two instructions
6256
+ * each time we try to call a function/routine.  Yes, we want and *need* this
6257
+ * for good performance.  I mean, think of it, free performance increase?  Who
6258
+ * could argue with that?
6259
+ */
6260
+#undef ACCUMULATE_OUTGOING_ARGS
6261
+#define        ACCUMULATE_OUTGOING_ARGS        1
6262
+
6263
+
6264
+/* REG_PARM_STACK_SPACE(FN) ... Define this macro if functions should assume
6265
+ * that stack space has been allocated for arguments even when their values
6266
+ * are passed in registers.  The value of this macro is the size, in bytes, of
6267
+ * the area reserved for arguments passed in registers for the function
6268
+ * represented by FN, which can be zero if GCC is calling a library function.
6269
+ * The argument FN can be the FUNCTION_DECL, or the type itself of the function.
6270
+ *
6271 171 dgisselq
+ * This space can be allocated by the caller, or be part of the machine
6272
+ * dependent stack frame: OUTGOING_REG_PARM_STACK_SPACE says which.
6273
+ *
6274 102 dgisselq
+ * ZipCPU --- Why allocate space you won't use?  Let's leave this undefined
6275
+ * therefore.
6276
+ */
6277
+// #undef      REG_PARM_STACK_SPACE
6278
+
6279
+
6280
+
6281
+/* INCOMING_REG_PARM_STACK_SPACE(FN) ... Like REG_PARM_STACK_SPACE, but for
6282
+ * incoming register arguments.  Define this macro if space guaranteed when
6283
+ * compiling a function body is different to space required when making a call,
6284 191 dgisselq
+ * a situation that can arise with K&R style function definitions.
6285 102 dgisselq
+ *
6286
+ */
6287
+
6288
+/* OUTGOING_REG_PARM_STACK_SPACE(FN) ... Define this to a nonzero value if it
6289
+ * is the responsibility of the caller to allocate the area reserved for
6290
+ * arguments passed in registers when calling a function of FN.  FN may be NULL
6291
+ * if the function called is a library function.
6292
+ *
6293
+ * ZipCPU---Why allocate space you don't need?
6294
+ */
6295
+#define        OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)   0
6296
+
6297
+
6298
+/* STACK_PARMS_IN_REG_PARM_AREA ... Define this macro if REG_PARM_STACK_SPACE
6299
+ * is defined, buyt the stack parameters don't skip the area specified by it.
6300
+ *
6301
+ * ZipCPU---We didn't define REG_PARM_STACK_SPACE, so we won't define this.
6302
+ */
6303
+
6304
+/* TARGET_RETURN_POPS_ARGS(DECL,FNTYPE,SZ) ... This target hook returns the
6305
+ * number of bytes of its own arguments that a function pops on returning, or 0
6306
+ * if the function pops no arguments and the caller must therefore pop them all
6307
+ * after the function returns.
6308
+ *
6309
+ * ZipCPU --- If we define this, we'll lose our gain from
6310
+ * ACCUMULATE_OUTOING_ARGS.  Thus, we leave this undefined.
6311
+ */
6312
+
6313
+/* CALL_POPS_ARGS(CUM) ... A C expression that should indicate the number of
6314
+ * bytes a call sequence pops off of the stack.  It is added to the value of
6315
+ * RETURN_POPS_ARGS when compiling a function call.  CUM is the variable in
6316
+ * which all arguments to the function have been accumulated.
6317
+ *
6318
+ * ZipCPU---The call sequence, by itself, doesn't touch the stack.  Therefore
6319
+ * this is zero.
6320
+ */
6321
+#undef CALL_POPS_ARGS
6322
+#define        CALL_POPS_ARGS(CUM)     0
6323
+
6324
+
6325
+/* 17.09.07 Passing arguments in registers */
6326
+
6327
+/* TARGET_FUNCTION_ARG ... Return an RTX indicating whether a function argument
6328
+ * is passed in a register, and if so, which register.
6329
+ */
6330
+/*
6331
+ * This has been poisoned ... so let's not define it anymore and look for
6332
+ * a better way to do this ...
6333
+ *
6334
+ * #define     FUNCTION_ARG(CUM, MODE, TYPE, NAMED) (((NAMED) == 0) ? NULL_RTX
6335
+ *     : targetm.calls.must_pass_in_stack(MODE, TYPE)  ? NULL_RTX
6336
+ *     : (CUM) > ZIP_LAST_ARG_REGNO                    ? NULL_RTX
6337
+ *     : gen_rtx_REG(MODE, CUM))
6338
+ */
6339
+#define        TARGET_FUNCTION_ARG     zip_function_arg
6340
+
6341
+
6342
+/* TARGET_MUST_PASS_IN_STACK(MODE, TYPE) ... This target hook should return
6343
+ * true if we should not pass TYPE solely in registers.  The file 'expr.h'
6344
+ * defines a definition that is usually appropriate, refer to 'expr.h' for
6345
+ * additional documentation.
6346
+ *
6347
+ * ZipCPU ... Ok, so I looked into expr.h and didn't find anything that looked
6348
+ * like this.  So ... I don't know.
6349
+ */
6350
+// #undef      TARGET_MUST_PASS_IN_STACK
6351
+// #define     TARGET_MUST_PASS_IN_STACK       zip_must_pass_in_stack
6352
+
6353
+/* TARGET_FUNCTION_INCOMING_ARG ... Define this hook if the target machine
6354
+ * has register windows, ... which ZipCPU does not have.
6355
+ */
6356
+
6357
+/* TARGET_USE_PSEUDO_PIC_REG(void) ... This hook should return 1 in case
6358
+ * pseudo register should be created for pic_offset_table_rtx during function
6359
+ * expand.
6360
+ *
6361
+ * This should be defined by global parameters, isn't it?
6362 171 dgisselq
+ */
6363
+
6364
+/* TARGET_INIT_PIC_REG(v) ... Perform a target dependent initialization of
6365
+ * pic_offset_table_rtx.  This hook is called at the start of register
6366
+ * allocation.
6367
+ *
6368
+ * ZipCPU---Let's revisit this.
6369 102 dgisselq
+ */
6370
+// #warning "Come back and relook at relocations"
6371
+
6372
+/* TARGET_ARG_PARTIAL_BYTES ... This target hook returns the number of bytes
6373
+ * at the beginning of an argument that must be put in registers.  The value
6374
+ * must be zero for arguments that are passed entirely in registers or that
6375
+ * are entirely pushed on the stack.
6376
+ */
6377
+// #undef      TARGET_ARG_PARTIAL_BYTES
6378
+// #define     TARGET_ARG_PARTIAL_BYTES        zip_arg_partial_bytes
6379
+
6380
+/* TARGET_PASS_BY_REFERENCE(CUM,MOD,TREE,NAMED) ... This target hook should
6381
+ * return true if an argument at the position indicated by CUM should be passed
6382
+ * by reference.  This predicate is queried after target independent reasons
6383
+ * for being pssed by reference, such as TREE_ADDRESSABLE(TREE).
6384
+ *
6385
+ */
6386
+// #undef      TARGET_PASS_BY_REFERENCE
6387
+// #define     TARGET_PASS_BY_REFERENCE        zip_pass_by_reference
6388
+
6389
+/* CUMULATIVE ARGS ...  A C type for declaring a variable that is used as the
6390
+ * first argument of 'FUNCTION_ARG' and other related values.
6391
+ *
6392
+ * ZipCPU---We're in trouble if an 'int' won't work, so let's just use that.
6393
+ */
6394
+#define        CUMULATIVE_ARGS int
6395
+
6396
+/*
6397
+ * OVERRIDE_ABI_FORMAT
6398
+ */
6399
+
6400
+/* INIT_CUMULATIVE_ARGS ... A C statement (sans semicolon) for initializing the
6401
+ * variable CUM for the state at the beginning of the argument list.
6402
+ *
6403
+ *
6404
+ * ZipCPU---The first argument is passed in register ZIP_FIRST_ARG_REGNO, or
6405
+ * R1 (unless it has been redefined above ...)
6406
+ */
6407
+#define        INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) (CUM = 0)
6408
+
6409
+/* INIT_CUMULATIVE_LIBCALL_ARGS
6410
+ * INIT_CUMULATIVE_INCOMING_ARGS
6411
+ *
6412
+ * These default to the last INIT_CUM_ARGS value above.
6413
+ */
6414
+
6415
+/* TARGET_FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) .. This hook updates
6416
+ * the summarizer variable pointed to by CUM to advance past an argument in
6417
+ * the argument list.  The values MODE, TYPE, and NAMED describe that
6418
+ * argument.  Once this is done, the variable CUM is suitable for analyzing the
6419
+ * following argument with TARGET_FUNCTION_ARG, etc.  This hook need not do
6420
+ * anything if the argument in question was passed on the stack.  The compiler
6421
+ * knows how to track the amount of stack space used for arguments without
6422
+ * any special help.
6423
+ *
6424
+ * ZipCPU---Here we simply copy from ECO32.
6425
+ */
6426
+#define        TARGET_FUNCTION_ARG_ADVANCE     zip_function_arg_advance
6427
+
6428
+/*
6429
+ * TARGET_ARG_OFFSET(MODE, TYPE) ... If defined, a C expression that is the
6430
+ * number of bytes to add to the offset of the argument passed in memory.
6431
+ * This is needed for the SPU, which passes char and short arguments in the
6432
+ * preferred slot that is in the middle of the quad word instead of starting
6433
+ * at the top.
6434
+ *
6435
+ * ZipCPU -- sounds like the default would be (more) appropriate.
6436
+ */
6437
+/*
6438
+ * FUNCTION_ARG_PADDING        --- not necessary, since we shouldn't be padding
6439
+ * PAD_VARARGS_DOWN    --- not necessary, since we shouldn't be padding
6440
+ * BLOCK_REG_PADDING
6441
+ * TARGET_FUNCTION_ARG_BOUNDARY
6442
+ * TARGET_FUNCTION_ARG_ROUND_BOUNDARY
6443
+ */
6444
+
6445
+/* FUNCTION_ARG_REGNO_P(REGNO) ... A C expression that is nonzero if REGNO is
6446
+ * the number of a hard register in which function arguments are sometimes
6447
+ * passed.  This does not include implicit arguments such as the static chain
6448
+ * and the structure-value address.  On many machines, no registers can be used
6449 171 dgisselq
+ * for this purpose since all function arguments are pushed on the stack.
6450
+ */
6451
+#define        FUNCTION_ARG_REGNO_P(r) ((r >= ZIP_FIRST_ARG_REGNO)&&(r<=ZIP_LAST_ARG_REGNO))
6452
+
6453
+/* TARGET_SPLIT_COMPLEX_ARG(TYPE) ... This hook should return true if parameter
6454
+ * of type TYPE are passed as two scalar parameters.  By default, GCC will
6455
+ * attempt to pack complex arguments into the target's word size.  Some ABI's
6456
+ * require complex arguments to be split and treated as their individual
6457
+ * components.
6458 102 dgisselq
+ *
6459
+ * The default value of this hook is NULL, which is treated as always false,
6460
+ * and which should be good enough for ZipCPU--which can go either way.
6461
+ */
6462
+
6463
+/* TARGET_BUILD_BUILTIN_VA_LIST ... This hook returns a type node for va_list
6464
+ * for the target.  The default version of the hook returns void*.
6465
+ *
6466
+ */
6467
+
6468
+/* TARGET_ENUM_VA_LIST_P
6469
+ */
6470
+
6471
+/* TARGET_FN_ABI_VA_LIST ... This hook returns the va_list type of the calling
6472
+ * convention specified by FN.  The default version of this returns va_list_type_node.
6473
+ */
6474
+
6475
+/* TARGET_FN_ABI_VA_LIST
6476
+ */
6477
+
6478
+/* TARGET_CANONICAL_VA_LIST_TYPE
6479
+ */
6480
+
6481
+/* TARGET_GIMPLIFY_VA_ARG_EXPR
6482
+ */
6483
+
6484
+/* TARGET_VALID_POINTER_MODE(MODE) ... Define this to return nonzero if the
6485
+ * port can handle pointers with machine mode MODE.  The default version of this
6486
+ * hook returns true for both ptr_mode and Pmode.
6487
+ *
6488
+ * ZipCPU---if Pmode is properly defined (above, and I think it is), then the
6489
+ * default behavior is quite appropriate.
6490
+ */
6491
+
6492
+/* TARGET_REF_MAY_ALIAS_ERRNO(REFP) ... Define this to return nonzero if the
6493
+ * memory reference REF may alias with the system C library errno location.
6494
+ * The default version of this hook assumes the system C library errno location
6495
+ * is either a declaration of type int or accessed by dereferencing a pointer
6496
+ * to int.
6497
+ *
6498
+ * ZipCPU --- Default sounds good to me.
6499
+ */
6500
+
6501
+
6502
+/* TARGET_SCALAR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if
6503
+ * the port is prepared to handle instructions involving scalar mode MODE.  For
6504
+ * a scalar mode to be considered supported, all the basic arithmetic and
6505
+ * comparisons must work.
6506
+ *
6507
+ * The default version of this hook returns true for any mode required to
6508
+ * handle the basic C types (as defined by the port).  Included here are the
6509
+ * double-word arithmetic supported by the code in optabs.c.
6510
+ *
6511
+ * ZipCPU --- This controls whether a data type of the given mode can even be
6512
+ * declared in C/C++.  Without support for such a mode, you can't even declare
6513
+ * a data type of this type.  Hence, we should support SFmode and DFmode, even
6514
+ * though the hardware *may* support SFmode, and it will *never* support DFmode.
6515
+ */
6516
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
6517
+#define        TARGET_SCALAR_MODE_SUPPORTED_P  zip_scalar_mode_supported_p
6518
+
6519
+/* TARGET_VECTOR_MODE_SUPPORTED_P(MODE) ... Define this to return nonzero if the
6520
+ * port is prepared to handle instructions involving vector mode MODE.  At the
6521
+ * very least, it must have move patterns for this mode.
6522
+ *
6523 202 dgisselq
+ * ZipCPU---does not support any vector modes.
6524 102 dgisselq
+ */
6525
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
6526
+#define        TARGET_VECTOR_MODE_SUPPORTED_P  hook_bool_mode_false
6527
+
6528
+/* TARGET_ARRAY_MODE_SUPPORTED_P(MODE, NELEMS) ... Return true if GCC should
6529
+ * try to use a scalar mode to store an array of NELEMS elements, given that
6530 202 dgisselq
+ * each element has mode MODE.  Returning true here overrides the usual
6531
+ * MAX_FIXED_MODE limit and allows GCC to use any defined integer mode.
6532
+ *
6533
+ * ZipCPU---Sounds good.
6534
+ */
6535 102 dgisselq
+// #undef      TARGET_ARRAY_MODE_SUPPORTED_P
6536
+// #define     TARGET_ARRAY_MODE_SUPPORTED_P   zip_array_mode_supported_p
6537
+
6538
+/* TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P(MODE) ... Define this to return
6539
+ * nonzero if libgcc provides support for the floating-point mode MODE, which is
6540
+ * known to pass TARGET_SCALAR_MODE_SUPPORTED_P.  The default version of this
6541
+ * hook returns true for all of SFmode, DFmode, XFmode, and TFmode, if such
6542
+ * modes exist.
6543
+ *
6544
+ * ZipCPU---We only support SFmode and DFmode, but for now only in emulation
6545
+ * (if we can).  Let's allow both of those and see how far we get.
6546
+ */
6547
+#undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
6548
+#define        TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P zip_libgcc_floating_mode_supported_p
6549
+
6550 202 dgisselq
+/* TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P(MODE) ... Define this to return
6551
+ * nonzero for machine modes for which the port has small register classes.  If
6552 102 dgisselq
+ * target hook returns nonzero for a given MODE, the compiler will try to
6553
+ * minimize the lifetime of registers in MODE.  The hook may be called with
6554
+ * VOIDmode as an argument.  In this case, the hook is expected to return
6555
+ * nonzero if it returns nonzero for any mode.
6556
+ *
6557
+ * The default version of this hook returns false for any mode.
6558
+ *
6559
+ * ZipCPU---Default sounds good.
6560
+ */
6561
+
6562
+/* 17.09.08 How scalar function values are returned */
6563
+
6564
+/* TARGET_FUNCTION_VALUE
6565
+ */
6566
+
6567
+/* LIBCALL_VALUE
6568
+ */
6569
+
6570
+
6571
+/* 17.09.09 How large values are returned */
6572
+
6573
+/* TARGET_RETURN_IN_MEMORY(TYP,FNTYP) ... This target hook should return a
6574
+ * nonzero value to say to return the function value in memory, just as large
6575
+ * structures are always returned.  Here type will be the data type of the value
6576
+ * and FNTYP will be the type of the function doing the returning, or NULL
6577
+ * for libcalls.
6578
+ *
6579
+ */
6580
+#undef TARGET_RETURN_IN_MEMORY
6581
+#define        TARGET_RETURN_IN_MEMORY zip_return_in_memory
6582
+
6583
+/* DEFAULT_PCC_STRUCT_RETURN
6584
+ * TARGET_STRUCT_VALUE_RTX
6585
+ * PCC_STATIC_STRUCT_RETURN
6586
+ * TARGET_GET_RAW_RESULT_MODE
6587
+ * TARGET_GET_RAW_ARG_MODE
6588
+ */
6589
+
6590
+
6591
+/* 17.09.10 Caller-Saves Register Allocation */
6592
+/* 17.09.11 Function Entry and Exit */
6593
+// TARGET_ASM_FUNCTION_PROLOGUE
6594
+// TARGET_ASM_FUNCTION_END_PROLOGUE
6595
+// TARGET_ASM_FUNCCTION_BEGIN_EPILOGUE
6596
+// TARGET_ASM_FUNCTION_EPILOGUE
6597
+/* EXIT_IGNORE_STACK ... Define this macro as a C expression that is nonzero
6598
+ * if the return instruction or the function epilogue ignores the value of the
6599
+ * stack pointer; in other words, if it is safe to delete an instruction to
6600
+ * adjust the stack pointer before a return from the function.
6601
+ *
6602
+ * The default is 0.
6603
+ *
6604
+ * Note that this macro's value is relevant only for functions for which frame
6605
+ * pointers are maintained.  It is never safe to delete a final stack adjustment
6606
+ * in a function that has no frame pointer, and the compiler knows this
6607
+ * regardless of EXIT_IGNORE_STACK.
6608
+ *
6609
+ * ZipCPU -- Thanks to the example of the m68k, and a careful selection of what
6610
+ * our options otherwise could have been, our epilogue code does not use the
6611
+ * stack register at all, but rather starts by moving the frame register into
6612
+ * the stack register.
6613 111 dgisselq
+ */
6614
+#define EXIT_IGNORE_STACK      1
6615
+// EPILOGUE_USES(regno)
6616
+// EH_USES(regno)
6617
+// TARGET_ASM_OUTPUT_MI_THUNK
6618
+// TARGET_ASM_CAN_OUTPUT_MI_THUNK
6619
+
6620
+/* 17.09.12 Generating code for profiling */
6621
+// FUNCTION_PROFILER
6622
+// PROFILE_HOOK
6623
+// NO_PROFILE_COUNTERS
6624
+// PROFILE_BEFORE_PROLOGUE
6625
+// TARGET_KEEP_LEAF_WHEN_PROFILED
6626
+
6627
+/* 17.09.13 Permitting tail calls*/
6628
+
6629
+/* TARGET_FUNCTION_OK_FOR_SIBCALL(DECL,EXP) ... True if it is OK to do sibling
6630
+ * call optimizations for the specified call expression EXP.  DECL will be the
6631
+ * called function, or NULL if this is an indirect call.
6632
+ *
6633
+ * It is not uncommon for limitations of calling conventions to prevent tail
6634
+ * calls to functions outside the current unit of translation, or during PIC
6635
+ * compilation.  The hook is used to enforce these restrictions, as the sibcall
6636
+ * md pattern can not fail, or fall over to a 'normal' call.  The criteria for
6637
+ * successful sibling call optimization may vary greatly between different
6638
+ * architectures.
6639
+ *
6640 102 dgisselq
+ * What's a sibling call?  "Sibling calls or tail calls terminate the function
6641 111 dgisselq
+ * in a nonn-standard way and thus an edge to the exit must be present.
6642
+ * EDGE_SIBCALL and EDGE_ABNORMAL are set in such case(s).  These edges only
6643
+ * exist in the RTL representation.
6644
+ *
6645
+ * So, basically, a sibling call is a function call at the end of one function.
6646
+ * Rather than setting up a new stack frame, return address, etc, it is
6647 102 dgisselq
+ * possible to just jump to this new function, leaving the return address for
6648 111 dgisselq
+ * the prior function as the (now) return address for this one.
6649
+ *
6650
+ * ZipCPU --- These are good things.  We wish to support them.  We will require,
6651
+ * though, that the sibling require no more stack space than the original.
6652
+ * We might go even stricter, requiring that the sibling require no stack space
6653
+ * at all--and only register variables.
6654
+ */
6655
+#define        TARGET_FUNCTION_OK_FOR_SIBCALL  zip_function_ok_for_sibcall
6656
+
6657
+/* TARGET_EXTRA_LIVE_ON_ENTRY(REGS) ... Add any hard registers to regs that are
6658
+ * live on entry to the function.  This hook only needs to be defined to provide
6659
+ * registers that cannot be found by examination of FUNTION_ARG_REGNO_P, the
6660 191 dgisselq
+ * ... and the ...
6661
+ *
6662
+ * ZipCPU -- the default should be good enough for us.
6663
+ */
6664
+/* TARGET_SET_UP_BY_PROLOGUE(CONTAINER) ... This hook should add additional
6665
+ * registers that are computed by the prologue to the hard register set for
6666
+ * shrink-wrapping optimization purposes.
6667
+ *
6668
+ * ??
6669
+ */
6670
+
6671
+/* TARGET_WARN_FUNC_RETURN(TREE) ... True if a function's return statements
6672
+ * should be checked for matching the function's return type.  This includes
6673
+ * checking for falling off the end of a non-void function.  Return false if
6674 111 dgisselq
+ * no such check should be made.
6675 191 dgisselq
+ *
6676 111 dgisselq
+ * ZipCPU--the default should be good enough for us.
6677 191 dgisselq
+ */
6678
+
6679
+/* 17.09.14 Stack smashing protection */
6680
+// TARGET_STACK_PROTECT_GUARD
6681
+// TARGET_STACK_PROTECT_FAIL
6682
+// TARGET_SUPPORTS_SPLIT_STACK
6683
+
6684
+/* 17.09.15 Miscellaneous register hooks */
6685
+
6686
+// TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
6687
+
6688
+/* TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
6689
+ * ZipCPU --- default is good enough for us.
6690 111 dgisselq
+ */
6691 191 dgisselq
+
6692
+/* 17.10 Implementing VARARGS MACROS */
6693
+
6694
+/* ...
6695
+ */
6696
+
6697
+/* void TARGET_SETUP_INCOMING_VARARGS(A,M,T,I,S) ... This target hook offers an
6698
+ * alternative to using __builtin_saveregs and defining the hook TARGET_EXPAND..
6699 102 dgisselq
+ * _BUILTIN_SAVEREGS.  Use it to store the anonymous register arguments into the
6700 111 dgisselq
+ * stack so that all the arguments appear to have been passed consecutively
6701
+ * on the stack.  Once this is done, you can use the standard implementation
6702
+ * of varargs that works for machines that pass all their arguments on the
6703
+ * stack.
6704 102 dgisselq
+ */
6705
+// #undef      TARGET_SETUP_INCOMING_VARARGS
6706 111 dgisselq
+// #define     TARGET_SETUP_INCOMING_VARARGS   zip_setup_incoming_varargs
6707
+
6708 102 dgisselq
+/* ...
6709
+ */
6710
+
6711
+/* 17.11 Trampolines for Nested Functions */
6712
+
6713
+/* TARGET_ASM_TRAMPOLINE_TEMPLATE ... This hook is called by
6714
+ * assemble_trampoline_template to output, on the stream f, assembler code for
6715
+ * a block of data that contains the constant parts of a trampoline.  This code
6716
+ * should not include a label--the label is taken care of automatically.
6717
+ *
6718
+ * ZipCPU -- looks like we need to do this.
6719
+ */
6720
+#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
6721
+#define        TARGET_ASM_TRAMPOLINE_TEMPLATE  zip_asm_trampoline_template
6722
+
6723
+/* TRAMPOLINE_SECTION ... Return the section into which the trampoline template
6724
+ * is to be placed.  The default value is readonly_data_section.
6725
+ *
6726
+ * ZipCPU--default should be good enough.
6727
+ */
6728
+
6729
+/* TRAMPOLINE_SIZE ... A C expression for the size (in bytes) of the trampoline
6730
+ * as an integer.
6731
+ *
6732
+ * ZipCPU--it's three instructions, or 96 bits: BREV, LDILO, and JMP
6733
+ *
6734
+ */
6735
+// #warning "May need to redefine trampoline_size in words, not bytes"
6736
+#undef TRAMPOLINE_SIZE
6737
+#define        TRAMPOLINE_SIZE 3*UNITS_PER_WORD
6738
+
6739
+/* TRAMPOLINE_ALIGNMENT ... alignment required for trampolines, in bits.
6740
+ *
6741
+ * Well that's well known in ZipCPU --- 32-bits.
6742
+ */
6743
+#undef TRAMPOLINE_ALIGNMENT
6744
+#define        TRAMPOLINE_ALIGNMENT    UNITS_PER_WORD
6745
+
6746
+/* void TARGET_TRAMPOLINE_INIT(RTX,TREE,RTX CH) ... This hook is called to
6747
+ * initialize a trampoline.  m_tramp is an RTX for the memory block for the
6748
+ * trampoline; TREE is the FUNCTION_DECL for the nested fucntion;  CH is an
6749
+ * rtx for the static chain value that should be passed to the function when
6750
+ * it is called.
6751
+ *
6752 202 dgisselq
+ * ZipCPU ... Can we get by without this?
6753 102 dgisselq
+ */
6754
+#undef TARGET_TRAMPOLINE_INIT
6755
+#define        TARGET_TRAMPOLINE_INIT  zip_trampoline_init
6756
+
6757 202 dgisselq
+/* TARGET_TRAMPOLINE_ADJUST_ADDRESS(RTX) ... This hook should perform any
6758 102 dgisselq
+ * machine-specific adjustment in the address of the trampoline.  Its argument
6759
+ * contains the address of the memory block that was passed to
6760
+ * TARGET_TRAMPOLINE_INIT.  In case the address to be used for a function call
6761
+ * should be different from the address at which the template was stored, the
6762
+ * different address should be returned; otherwise addr should be returned
6763
+ * unchanged.  If the hook is not defined, RTX (addr) will be used for function
6764 202 dgisselq
+ * calls.
6765 102 dgisselq
+ *
6766
+ * ZipCPU--works for us!
6767
+ */
6768
+
6769
+/* CLEAR_INSN_CACHE(BEG,END) ... If defined, expands to a C expression clearing
6770
+ * the instruction cache in the specified interval.  The definition of this
6771
+ * macro would typically be a series of asm statements.   Both BEG and END are
6772
+ * pointer expressions.
6773
+ *
6774
+ * ZipCPU --- Ouch!  We have no way to do this (yet)!
6775
+ */
6776
+#define        CLEAR_INSN_CACHE(BEG,END)       gcc_assert(0);
6777
+
6778
+/* TRANSFER_FROM_TRAMPOLINE ... Define this macro is trampolines need a special
6779
+ * subroutine to do their work.  The macro should expand to a series of asm
6780
+ * statements which will be compiled with GCC.  They go in a library function
6781
+ * named __transfer_from_trampoline.
6782
+ *
6783
+ * We may need to rethink trampolines on ZipCPU.
6784
+ */
6785
+
6786
+
6787
+/* 17.12 Implicit Calls to Library Routines */
6788
+
6789
+/* DECLARE_LIBRARY_RENAMES
6790
+ *
6791
+ * ZipCPU: Don't need it.
6792
+ */
6793
+
6794
+/* TARGET_INIT_LIBFUNCS(VOID) ... This hook should declare additional library
6795
+ * routines or rename existing ones, using the functions set_optab_libfunc and
6796 202 dgisselq
+ * init_one_libfunc defined in optabs.c.  init_optabs calls this macro after
6797 102 dgisselq
+ * initializing all the normal library routines.
6798
+ *
6799 111 dgisselq
+ * Most ports don't need to define this hook, so we won't either.
6800 102 dgisselq
+ */
6801
+
6802
+/* TARGET_LIBFUNC_GNU_PREFIX ... If false (the default), internal library
6803
+ * routines start with two underscores.  If set to true, these routines start
6804
+ * with __gnu_ instead.
6805
+ *
6806
+ * ZipCPU: No change necessary.
6807
+ */
6808
+
6809
+/* FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE,COMPARISON) ... This macro should return
6810
+ * true if the library routine that implements the floating point comparison
6811
+ * operator comparison in mode mode will return a boolean and false if it will
6812
+ * return a tristate.
6813
+ *
6814
+ * Most ports don't need to define this macro, so Zip CPU won't either.
6815
+ */
6816
+
6817
+/* TARGET_HAS_NO_HW_DIVIDE ... This macro should be defined if the target has no
6818
+ * hardware divide instructions.  If this macro is defined, GCC will use an
6819
+ * algorithm which makes use of simple logical and arithmetic operations for
6820
+ * 64-bit division.  If the macro is not defined, GCC will use an algorithm
6821
+ * which makes use of a 64-bit by 32-bit divide primitive.
6822
+ *
6823
+ * Zip CPU, though, doesn't have the 64-bit by 32-bit divide primitive, thus
6824
+ * we have no HW DIVIDE (for now).
6825
+ */
6826
+#define        TARGET_HAS_NO_HW_DIVIDE
6827
+
6828
+/* TARGET_EDOM ... The value of EDOM on the target machine, as a C integer
6829
+ * expression.  If you don't define this macro, GCC does not attempt to deposit
6830
+ * the value of EDOM into errno directly.  Look in /usr/include/errno.h to find
6831
+ * the value of EDOM on your system.
6832
+ *
6833
+ * EDOM is the error created when a math argument is out of the domain of the
6834
+ * function.
6835
+ *
6836
+ * ZipCPU: Don't need it---I don't think.
6837
+ */
6838
+
6839
+/* GEN_ERRNO_RTX ... Define this macro as a C exrpession to create an rtl
6840
+ * expression that refers to the global "variable" errno.  (On certain
6841
+ * systems, errno may not actually be a variable.)  If you don't define this
6842
+ * macro, a reasonable default is used.
6843
+ *
6844
+ * ZipCPU --- if a reasonable default is used, we'll use that--especially since
6845
+ * I doubt we'll be using errno for a while.
6846
+ */
6847
+
6848
+/* NEXT_OBJC_RUNTIME ... Set this macro to 1 to use the "NeXT" Objective-C
6849
+ * message sending conventions by default.  This calling convention involves
6850
+ * passing the object, the selector and the method arguments all at once to the
6851
+ * method-lookup library function.  This is the usual setting when targetting
6852
+ * Darwin/Mac OS X systems, which have the NeXT runtime installed.
6853
+ *
6854
+ * If the macro is set to 0, ...
6855
+ *
6856
+ * Doesn't look relevant (yet) for the Zip CPU--especially since we don't have
6857
+ * an O/S yet.
6858
+ */
6859
+
6860
+
6861
+
6862
+/* 17.13 Addressing Modes */
6863
+
6864
+/* C expressions that are nonzero if the machine supports pre-increment,
6865
+ * pre-decrement, post-increment, or post-decrement addressing respectively.
6866
+ */
6867
+#define        HAVE_PRE_INCREMENT      (0)
6868
+#define        HAVE_PRE_DECREMENT      (0)
6869
+#define        HAVE_POST_INCREMENT     (0)
6870
+#define        HAVE_POST_DECREMENT     (0)
6871
+
6872
+/* C expression that is nonzero if the machine supports pre- or post- address
6873
+ * side-effect generation involving constants other than the size of the memory
6874
+ * operand.
6875
+ */
6876
+#define        HAVE_PRE_MODIFY_DISP    (0)
6877
+#define        HAVE_POST_MODIFY_DISP   (0)
6878
+
6879
+/* C expression that is non-zero if the machine supports pre- or post-address
6880
+ * side-effect generation involving a register displacement.
6881
+ */
6882
+#define        HAVE_PRE_MODIFY_REG     (0)
6883
+#define        HAVE_POST_MODIFY_REG    (0)
6884
+
6885
+/* CONSTANT_ADDRESS_P(X) ... A C expression that is 1 if the RTX X is a constant
6886
+ * which is a valid address.  On most machines the default definition ... is
6887
+ * acceptable, but a few machines are more restrictive as to which constant
6888
+ * addresses are supported.
6889
+ *
6890
+ * Zip CPU is designed for offset addresses, not constant addresses.  Although
6891
+ * the CPU will support 18-bit signed constant addresses, the assembler and
6892
+ * general programming model do not.  Further, without knowing where the final
6893
+ * address will be located, this is an unusable model.  Therefore we will
6894
+ * define this as not supported.
6895
+ *
6896
+ * In hindsight, this isn't true--labels and symbols are valid addresses, and
6897
+ * they are also constant addresses.  Hence, we leave this at its default.
6898
+ */
6899
+// #undef      CONSTANT_ADDRESS_P
6900
+// #define     CONSTANT_ADDRESS_P(X)   (0)
6901
+
6902
+/* CONSTANT_P(X) ... CONSTANT_P, which is defined by target-independent code,
6903
+ * accepts integer values expressions whose values are not explicitly known,
6904
+ * such as symbol_ref, label_ref, and high expressions and const arithmetic
6905
+ * expressions, in addition to const_int and const_double expressions.
6906
+ *
6907
+ * Huh???
6908
+ */
6909
+// #define CONSTANT_P(X) ???
6910
+
6911
+/* MAX_REGS_PER_ADDRESS ... A number, the maximum number of registers that can
6912
+ * appear in a valid memory address.  Note that it is up to you to specify a
6913
+ * value equal to the maximum number that TARGET_LEGITIMATE_ADDRESS_P would
6914
+ * ever accept.
6915
+ */
6916
+#define        MAX_REGS_PER_ADDRESS    1
6917
+
6918
+/* TARGET_LEGITIMATE_ADDRESS_P(MODE,RTX,STRICT) ... A function that returns
6919
+ * whether RTX is a legitimate memory address on the target machine for a
6920
+ * memory operation of mode MODE.
6921
+ */
6922 111 dgisselq
+#undef TARGET_LEGITIMATE_ADDRESS_P
6923
+#define TARGET_LEGITIMATE_ADDRESS_P    zip_legitimate_address_p
6924
+
6925
+/* TARGET_MEM_CONSTRAINT ... A single character to be used instead of the
6926 102 dgisselq
+ * default 'm' character for general memory addresses.  This defines the
6927
+ * constraint letter which matches the memory addresses accepted by
6928
+ * TARGET_LEGITIMATE_ADDRESS_P.  Define this macro if you want to support new
6929
+ * address format in your back end without changing the semantics of the 'm'
6930
+ * constraint.  This is necessary in order to preserve functionality of inline
6931 111 dgisselq
+ * assembly constructs using the 'm' constraint.
6932
+ *
6933
+ * ZipCPU--doesn't look like we need to define this at all.
6934
+ */
6935 102 dgisselq
+
6936
+/* FIND_BASE_TERM(X) ... A C expression to determine the base term of address
6937
+ * X or to provide a simplified version of X from which alias.c can easily find
6938
+ * the base term.  This macro is used in only two places: find_base_value and
6939
+ * find_base_term in alias.c.
6940
+ *
6941
+ * It is always safe for this macro  to not be defined.  It exists so that
6942
+ * alias analysis can understand machine-dependent addresses.
6943
+ *
6944
+ * ZipCPU: We'll skip this then.
6945
+ */
6946
+
6947
+/* TARGET_LEGITIMIZE_ADDRESS(RTX,OLD,MODE) ... This hook is given an invalid
6948
+ * memory address RTX for an operand of mode MODE and should try to return a
6949
+ * valid memory address.  RTX will always be the result of a call to
6950
+ * break_out_memory_refs, and OLD will be the operand that was given to that
6951
+ * function to produce RTX.
6952
+ *
6953
+ * ZipCPU --
6954
+ */
6955
+#undef TARGET_LEGITIMIZE_ADDRESS
6956
+#define        TARGET_LEGITIMIZE_ADDRESS       zip_legitimize_address
6957
+
6958
+/* LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OP,TYPE,IND,WIN) ... A C compound statement
6959
+ * that attempts to replace X, which is an address that needs reloading, with
6960
+ * a valid memory address for an operand of mode MODE.  WIN will be a C
6961
+ * statement label elsewhere in the code.  It is not necessary to define this
6962
+ * macro, but it might be useful for performance reasons.
6963
+ *
6964
+ * ZipCPU: This is worth coming back to, according to the notes page, but it
6965
+ * may also be a difficult macro to use.  Look at other implementations before
6966
+ * we dive into this.
6967
+ */
6968
+// #undef LEGITIMIZE_RELOAD_ADDRESS
6969
+// #define LEGITIMIZE_RELOAD_ADDRESS
6970
+
6971
+/* TARGET_MODE_DEPENDENT_ADDRESS_P(ADDR,SPACE) ... This hook returns true
6972
+ * if memory address addr in address space addrspace can have different meanings
6973 111 dgisselq
+ * depending on the machine mode of the memory reference it is used for or if
6974 102 dgisselq
+ * the address is valid for some modes but not others.
6975 111 dgisselq
+ */
6976
+#undef TARGET_MODE_DEPENDENT_ADDRESS_P
6977 102 dgisselq
+#define        TARGET_MODE_DEPENDENT_ADDRESS_P         zip_mode_dependent_address_p
6978
+
6979
+/* TARGET_LEGITIMATE_CONSTANT_P(MODE,RTX) ... This hook returns true if x is a
6980
+ * legitimate constant for a MODE-mode immediate operand on the target machine.
6981
+ * You can assume the RTX satisfies CONSTANT_P, so you need not check this.
6982
+ *
6983
+ * The default definition returns true.
6984
+ */
6985
+
6986
+/* TARGET_DELIGITIMIZE_ADDRESS(RTX)
6987
+ */
6988
+
6989
+/* TARGET_CONST_NOT_OK_FOR_DEBUG_P(RTX) ... This hook should return true if RTX
6990
+ * should not be emitted into debug sections.
6991
+ */
6992
+
6993
+/* TARGET_CANNOT_FORCE_CONST_MEM(MODE,RTX) ... This hook should return true if
6994
+ * RTX is a form that cannot (or should not) be spilled to the constant pool.
6995
+ * MODE is the mode of X.  The default version returns false.
6996
+ */
6997
+// #define     TARGET_CANNOT_FORCE_CONST_MEM   hook_bool_mode_rtx_false
6998
+
6999 111 dgisselq
+/* TARGET_USE_BLOCKS_FOR_CONSTANT_P(MODE,RTX) ... This hook should return true
7000
+ * if pool entries for constant RTX can be placed in an object_block structure.
7001
+ * MODE is the mode of X.  The default version returns false for all constants.
7002
+ *
7003
+ *????
7004 102 dgisselq
+ */
7005
+// #warning "Huh?"
7006
+
7007
+/* TARGET_USE_BLOCKS_FOR_DECL_P(DECL) ... This hook should return true if pool
7008
+ * entries for DECL should be placed in an object_block structure.  The default
7009
+ * version returns true for all DECL's.
7010
+ *
7011
+ * Sounds good.
7012
+ */
7013
+
7014
+/* TARGET_BUILTIN_RECIPROCAL(TREE) ... This hook should return the DECL of a
7015
+ * function that implements the reciprocal of the machine specific builtin
7016
+ * function fndecl, or NULL_TREE if such a function is not available.
7017 111 dgisselq
+ */
7018 102 dgisselq
+
7019
+/* TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD(VOID) ... This hook should return the
7020
+ * DECL of a function f that given an address addr as an argument returns a mask
7021
+ * m that can be used to extrract from two vectors the relevant data that
7022
+ * resides in addr in case addr is not properly aligned.
7023
+ *
7024
+ * Zip CPU does not support vectorization.
7025
+ */
7026
+
7027
+/* Other vector, SIMD, and GOACC macros skipped as Zip CPU doesn't support
7028
+ * such data accesses and manipulation.
7029
+ */
7030
+
7031
+/* 17.14 Anchored Addresses */
7032
+
7033
+/* TARGET_MIN_ANCHOR_OFFSET ... The minimum offset that should be applied to
7034
+ * a section anchor.  On most targets, it should be the smallest offset that
7035
+ * can be applied to a base register while still giving a legitimate address for
7036
+ * every mode.  The default value is 0.
7037
+ *
7038
+ * On the Zip CPU, this is the minimum operand B offset to a LW or SW
7039
+ * operation, which would be a signed 14 bit number.
7040
+ */
7041
+#undef TARGET_MIN_ANCHOR_OFFSET
7042
+#define TARGET_MIN_ANCHOR_OFFSET       zip_min_anchor_offset
7043
+
7044
+/* TARGET_MAX_ANCHOR_OFFSET ... Like TARGET_MIN_ANCHOR_OFFSET, but the maximum
7045
+ * (inclusive) offset that should be applied to section anchors.  The default
7046
+ * value is 0.
7047
+ */
7048
+#undef TARGET_MAX_ANCHOR_OFFSET
7049
+#define TARGET_MAX_ANCHOR_OFFSET       zip_max_anchor_offset
7050
+
7051
+/* TARGET_ASM_OUTPUT_ANCHOR(RTX) ... Write the assembly code to define section
7052
+ * anchor RTX, which is a SYMBOL_REF for which 'SYMBOL_REF_ANCHOR_P(RTL) is
7053
+ * true.  The hook is called with the assembly output position set to the
7054
+ * beginning of SYMBOL_REF_BLOCK(X).
7055
+ *
7056
+ * If ASM_OUTPUT_DEF is available, the hook's default definition uses it to
7057
+ * define the symbol as '. + SYMBOL_REF_BLOCK_OFFSET(RTL)'.  If ASM_OUTPUT_DEF
7058 202 dgisselq
+ * is not available, the hook's default definition is NULL, which disables the
7059 102 dgisselq
+ * use of section anchors altogether.
7060
+ *
7061
+ * Section anchors would be very valuable in Zip CPU assembly, therefore we
7062
+ * must define this hook.  However ... no one else seems to ever define these
7063
+ * hooks, so I really dont have much of an example to work with
7064
+ */
7065
+// #warning "Come back to this"
7066
+// #undef      TARGET_ASM_OUTPUT_ANCHOR
7067
+// #define     TARGET_ASM_OUTPUT_ANCHOR        zip_asm_output_anchor
7068
+
7069
+/* TARGET_USE_ANCHORS_FOR_SYMBOL_P(RTX) ... Return true if GCC should attempt
7070
+ * to use anchors to access SYMBOL_REF X.  You can assume
7071
+ * SYMBOL_REF_HAS_BLOCK_INFO_P(X) and !SYMBOL_REF_ANCHOR_P(X).
7072
+ *
7073
+ * The default version is correct for most targets, but you might need to
7074
+ * intercept this hook to handle things like target specific attributes or
7075
+ * target-specific sections.
7076
+ *
7077
+ * Not knowing anything more, we'll leave the default as is for the Zip CPU.
7078
+ */
7079
+// #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
7080
+// #define TARGET_USE_ANCHORS_FOR_SYMBOL_P     zip_use_anchors_for_symbol_p
7081 202 dgisselq
+
7082
+/* 17.15 Condition Code Status */
7083
+
7084 102 dgisselq
+/* 17.15.1 Representation of condition codes using (cc0) --- that's us */
7085 202 dgisselq
+
7086 102 dgisselq
+/* CC_STATUS_MDEP ... C code for a data type which is used for declaring
7087
+ * the mdep component of cc_status.  It defaults to int.
7088
+ *
7089
+ * ZipCPU---Int is good for us.
7090 202 dgisselq
+ */
7091
+
7092 102 dgisselq
+/* CC_STATUS_MDEP_INIT ... A C expression to initialize the mdep field to
7093 202 dgisselq
+ * "empty".  The default definition does nothing, since most machines don't
7094
+ * use the field anyway.  If you want to use the field, you should probably
7095
+ * define  this macro to initialize it.
7096 102 dgisselq
+ */
7097
+
7098
+/* NOTICE_UPDATE_CC(EXP, INSN) ... A C compound statement to set the components
7099
+ * of cc_status appropriately for an insn insn whose body is exp.  It is this
7100
+ * macro's responsibility to recognize insns that set the condition code as
7101
+ * a byproduct of other activity as well as those that explicitly set (cc0).
7102
+ *
7103
+ * ZipCPU --- We need this, as not all expressions set (cc0).
7104
+ *
7105
+ * In hind sight, this is the *old* and unsupported way of doing business within
7106
+ * GCC.  To switch to the new way, all instruction definitions within our .md
7107
+ * file have been adjusted to either change or clobber the CC register.
7108
+ *
7109
+ */
7110
+#ifdef HAVE_cc0
7111
+// #define     NOTICE_UPDATE_CC(EXP, INSN)     zip_update_cc_notice(EXP, INSN)
7112
+#error "ZipCPU no longer has CC0"
7113
+#endif
7114
+
7115
+
7116
+/* 17.15.2 Representation of condition codes using registers */
7117
+/* ... which the ZipCPU doesn't have.  The ZipCPU has a CC0 register, and hence
7118
+ * this section isn't supposed to apply.
7119
+ */
7120
+
7121
+/* SELECT_CC_MODE(op, x, y) ... On many machines, the condition code may be
7122
+ * produced by other instructions than compares, for example the branch can use
7123
+ * directyl the condition code set by a subtract instruction.  However, on some
7124
+ * machines when the condition code is set this way some bits (such as the
7125 191 dgisselq
+ * overflow bit) are not set in the same way as a test instruction, so that a
7126
+ * different branch instruction must be used for some conditional branches.
7127
+ * When this happens, use the machinemode of the condition code register to
7128
+ * record different formats of the condition code register.  Modes can also be
7129 102 dgisselq
+ * used to reccord which compare instruction (e.g. a signed or an unsigned
7130 122 dgisselq
+ * comparison) produced the condition codes.
7131 191 dgisselq
+ *
7132
+ * If other modes than CCmode are required, add them to 'machine-modes.def' and
7133 122 dgisselq
+ * define SELECT_CC_MODE to choose a mode given an operand of a compare.  This
7134 102 dgisselq
+ * is needed because the modes have to be chosen not only during RTL generation
7135
+ * but also, for example, by instruction combination.  The result of
7136
+ * SELECT_CC_MODE should be consistent with the mode used in the patterns; ...
7137
+ *
7138
+ * ZipCPU ... We have only one CC Mode, so we'll use the CCmode defined in
7139
+ * machine-modes.def and should be fine with it.  Hence, this doesn't need
7140
+ * to be defined.
7141 122 dgisselq
+ */
7142
+
7143
+/* TARGET_CANONICALIZE_COMPARISON(int,rtx *, rtx *, bool) ... On some machines
7144
+ * (such as the ZipCPU) not all possible comparisons are defined, but you can
7145
+ * convert an invalid comparison into a valid one.  For example, the Alpha
7146
+ * does not have a GT comparison, but you can use an LT comparison instead and
7147
+ * swap the order of the operands.
7148
+ *
7149
+ * On such machines, implement this hook to do any required conversions:  code
7150
+ * is the initial comparison code and op0 and op1 are the left and right
7151
+ * operands of the comparison, respectively.  If op0_preserve_value is true the
7152
+ * implementation is not allowed to change the value of op0 since the value
7153
+ * might be used in RTXs which aren't comparisons.  E.g. the implementation is
7154
+ * not allowed to swap operands in that case.
7155
+ *
7156
+ * GCC will not assume that the comparison resulting from this macro is valid
7157
+ * but will see if the resulting insn matches a pattern in the 'md' file.
7158
+ *
7159
+ * You need not implement this hook if it would never change the comparison
7160
+ * code or operands.
7161 102 dgisselq
+ *
7162
+ * In the case of the ZipCPU, the ZipCPU only keeps track of 8 possible
7163
+ * comparisons, and bastardizing other comparisons into those 8 is extremely
7164
+ * painful.  Therefore, we *need* this capability to make certain we can use
7165
+ * our comparisons successfully.
7166
+ *
7167
+ * The only problem is ... this hook appears to only be called on non-CC0
7168
+ * machines.  Hence, defining it hasn't done anything for us.
7169
+ */
7170
+#define        TARGET_CANONICALIZE_COMPARISON  zip_canonicalize_comparison
7171
+
7172
+/* REVERSIBLE_CC_MODE(MODE) ... A C expression whose value is one if it is
7173
+ * always safe to reverse a comparison whose mode is MODE.  If SELECT_CC_MODE
7174
+ * can ever return MODE for a floating-point inequality comparison, than
7175
+ * REVERSIBLE_CC_MODE(MODE) must be zero.
7176
+ *
7177
+ * You need not define this macro if it would always return zero or if the
7178
+ * floating-point format is anything other than IEEE_FLOAT_FORMAT.  For example,
7179
+ * here ...
7180
+ *
7181
+ * ZipCPU -- We'll always return zero, so this need not be defined.
7182
+ */
7183
+
7184
+/* REVERSE_CONDITION(CODE,MODE) ... A C expression whose value is reversed
7185
+ * condition code of thecode for comparison done in CC_MODE MODE.  This macro
7186
+ * is used only in case REVERSIBLE_CC_MODE(MODE) is nonzero. ...
7187
+ *
7188
+ * ZipCPU ... Since REVERSIBLE_CC_MODE(MODE) will always be zero, we'll leave
7189
+ * this undefined.
7190 122 dgisselq
+ */
7191 102 dgisselq
+
7192 122 dgisselq
+/* bool TARGET_FIXED_CONDITION_CODE_REGS(int *, int *) ... On targets which do
7193
+ * not use (cc0), and which use a hard register rather than a pseudo-register
7194
+ * to hold condition codes, the regular CSE passes are often not able to
7195
+ * identify cases in which the hard register is set to a common value.  Use this
7196
+ * hook to enable a small pass which optimizes such cases.  This hook should
7197
+ * return true to enable this pass, and it should set the integers to which its
7198
+ * arguments point to the hard register numbers used for condition codes.  When
7199
+ * there is only one such register, as is true on most systems, the integer
7200
+ * pointed to by p2 should  be set to INVALID_REGNUM.
7201
+ *
7202
+ * The default version of this hook returns false.
7203
+ *
7204
+ * ZipCPU --- I like the idea of enabling optimizations.  Let's return
7205
+ * something other than false.
7206
+ */
7207
+#define        TARGET_FIXED_CONDITION_CODE_REGS        zip_fixed_condition_code_regs
7208
+
7209
+/* machine_mode TARGET_CC_MODES_COMPATIBLE(M1,M2) .. On targets which use
7210
+ * multiple condition code modes in class MODE_CC, it is sometimes the case
7211
+ * that a comparison can be validly done in more than one mode.  On such a
7212
+ * system, define this target hook to take two mode arguments and to return a
7213
+ * mode in which both comparisons may be validly done.  If there is no such
7214
+ * mode, return VOIDmode.
7215
+ *
7216
+ * The default version of this hook checks whether the modes are the same.  If
7217
+ * they are, it returns that mode.  If they are different, it returns VOIDmode.
7218
+ *
7219
+ * ZipCPU--Given that we only have the one CCmode, the default definition works
7220
+ * well enough for us.
7221
+ */
7222
+
7223
+/* unsigned int TARGET_FLAGS_REGNUM ... If the target has a dedicated flags
7224
+ * register, and it needs to use the post-reload comparison elimination pass,
7225
+ * then this value should be set appropriately.
7226
+ *
7227
+ * ZipCPU---Looks like we can set this easily enough without any problems.
7228
+ */
7229
+#undef TARGET_FLAGS_REGNUM
7230
+#define        TARGET_FLAGS_REGNUM     zip_CC
7231
+
7232
+/* 17.16 Relative costs of operations */
7233
+
7234
+
7235
+// #define     REGISTER_MOVE_COST(MODE,FROM,TO)        ((MODE==DImode)||(MODE==DFmode))?4:2
7236
+// #define     TARGET_REGISTER_MOVE_COST
7237
+// #define     MEMORY_MOVE_COST(MODE, CLASS, IN)       ((MODE==DImode)||(MODE==DFmode))?8:7
7238
+/* TARGET_REGISTER_MOVE_COST(M,FRM,TO) ... This target hook should return the
7239
+ * cost of moving data of mode M from a register in class FRM to one in class
7240
+ * TO.  The classes are expressed using the enumeration values such as
7241
+ * GENERAL_REGS.  A value of 2 is the default; other values are interpreted
7242
+ * relative to that.
7243
+ *
7244
+ * It is not required that the cost always equal 2 when FROM is the same as TO;
7245
+ * on some machines it is expensive to move between registers if they are not
7246
+ * general registers.
7247
+ *
7248
+ * If reload sees ...
7249
+ *
7250
+ * ZipCPU ... We can leave this at its default value of 2.
7251
+ */
7252 102 dgisselq
+
7253
+/* TARGET_MEMORY_MOVE_COST(MOD,CL,IN) ... This target hook should return the
7254
+ * cost of moving data of mode MOD between a register of class CL and memory.
7255
+ * IN is false if the value is to be written to memory, true if it is to be
7256
+ * read in.  This cost is relative to those in TARGET_REGISTER_MOVE_COST.
7257
+ * If moving between registers and memory is more expensive that between two
7258
+ * registers, you should add this target hook to express the relative cost.
7259
+ *
7260
+ * If you do not add this target hook, GCC uses a default cost of 4 plus the
7261
+ * cost of copying via a secondary reload register, if one is needed.  If your
7262
+ * machine requires a secondary reload register to copy between memory and a
7263
+ * register of CL but the reload mechanism is more complex than copying via
7264
+ * an intermediate, use this target hook to reflect the actual cost of the
7265
+ * move.
7266
+ *
7267
+ * ZipCPU --- Memory moves are more expensive than twice the cost of register
7268
+ * moves, so let's make certain this is defined.
7269
+ */
7270
+#define        TARGET_MEMORY_MOVE_COST zip_memory_move_cost
7271
+
7272
+// #warning "This needs to be double checked, and annotated"
7273
+#define        BRANCH_COST(SPEED,PREDICTABLE)          ((PREDICTABLE)?2:5)
7274
+
7275
+/* Define this macro as a C expression which is nonzero if accessing less than
7276
+ * a word of memory (i.e. a 'char' or a 'short') is no faster than accessing
7277
+ * a word of memory.
7278
+ */
7279
+#define        SLOW_BYTE_ACCESS        1
7280
+
7281
+/* MOVE_RATIO(SPD) ... The threshold of number of scalar memory-to-memory move
7282
+ * instructions, below which a sequence of instructions should be generated
7283
+ * instead of a string move instruction or a library call.  Increasing the
7284
+ * value will always make code faster, but eventually incurs high cost in
7285
+ * increased code size.
7286
+ */
7287
+#define        MOVE_RATIO(SPD) 5
7288
+
7289
+/* TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(SZ,ALGN,OP,SPD) ...
7290
+ */
7291
+// #undef      TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(S,A,OP,SPD)
7292
+// #define     TARGET_USE_BY_PIECES_INFRASTRUCTURE_P(S,A,OP,SPD)// needs hook
7293 111 dgisselq
+
7294 102 dgisselq
+/* CLEAR_RATIO(SPD) ... The threshold number of scalar move instructions, below
7295
+ * which a sequence of instructions should be generated to clear memory instead
7296
+ * of a string clear instruction or a library call.  Increasing the value will
7297
+ * always make the code faster, but eventually incurs high cost in increased
7298
+ * code size.
7299
+ */
7300
+#define        CLEAR_RATIO(SPD)        MOVE_RATIO(SPD)
7301
+
7302
+/* NO_FUNCTION_CSE ... Define this macro to be true if it is as good or better
7303
+ * to call a constant function address than to call an address kept in a
7304
+ * register.
7305
+ *
7306
+ * On the Zip CPU, constant function addresses--especially relative ones,
7307
+ * can be optimized into a single cycle delay.  Register jumps will always
7308
+ * stall the whole (5-stage) pipeline.
7309
+ */
7310
+#define        NO_FUNCTION_CSE true
7311
+
7312
+/* TARGET_RTX_COSTS(X,CODE,OUTER,OPNO,TOTAL,SPD) ... This target hook describes
7313
+ * the relative costs of RTL expressions.
7314
+ *
7315
+ * The cost may depend on the precise form of the expression, which is avaialble
7316
+ * for examination in X, and the fact that X appears as operand OPNO of an
7317
+ * expression with rtx code OUTER.  That is, the hook can assume that there is
7318
+ * some RTX Y such that GET_CODE(Y)==OUTER and such that either (a) XEXP(Y,OPNO)
7319
+ * == X or (b) XVEC(Y,OPNO) contains X.
7320
+ *
7321
+ * ...
7322
+ * The hook returns true when all subexpressions of x have been processed and
7323
+ * false when rtx_cost should recurse.
7324
+ */
7325
+
7326
+/* TARGET_ADDRESS_COST(ADDR,MODE,AS, SPD) ... This hook computes the cost of an
7327
+ * addressing mode that contains ADDR.  If not defined, the cost is computed
7328
+ * from the ADDR expression and the TARGET_RTX_COST hook.  In cases where more
7329
+ * than one form of an address is known, the form with the lowest cost will be
7330 202 dgisselq
+ * used.  If multiple forms have the same, lowest, cost, the one that is the
7331 102 dgisselq
+ * most complex will be used.
7332 111 dgisselq
+ *
7333
+ * ZipCPU really has only one address cost, the only type of address it
7334
+ * supports.  Sure, index addressing would cost us more, but we don't support
7335
+ * that so ... I think we're okay defining this as a constant.  Indeed, the
7336
+ * docs state that, "On RISC amchines, all instructions normally have the same
7337
+ * length and execution time.  Hence all addresses will have equal costs."
7338
+ */
7339
+#undef TARGET_ADDRESS_COST
7340
+#define        TARGET_ADDRESS_COST     zip_address_cost
7341
+
7342
+
7343
+/* TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P ... This predicate controls the use
7344 102 dgisselq
+ * of the eager delay slot filler to disallow speculatively executed
7345 111 dgisselq
+ * instructions being placed in delay slots.  Targets such as certain MIPS
7346 102 dgisselq
+ * architectures posess both branches with and without delay slots.  As the
7347
+ * eager delay slot filler can decrease performance, disabling it is beneficial
7348
+ * when ordinary branches are available.  Use of delay slot branches filled
7349
+ * using basic filler is often still desirable as the delay slot can hide a
7350
+ * pipeline bubble.
7351
+ */
7352
+// How should Zip CPU define this--we have no delay slots.
7353
+
7354
+
7355
+/* 17.17 Instruction Scheduler */
7356
+
7357
+#define        TARGET_SCHED_ISSUE_RATE zip_sched_issue_rate
7358
+
7359
+/* 17.18 Dividing the Output into Sections */
7360
+
7361
+/* Switch to the text or data segment. */
7362
+#define        TEXT_SECTION_ASM_OP     "\t.text"
7363
+#define        DATA_SECTION_ASM_OP     "\t.data"
7364
+
7365
+// #undef      TARGET_LIBGCC_SDATA_SECTION
7366
+// #define     TARGET_LIBGCC_SDATA_SECTION     ".sdata"
7367
+
7368
+
7369
+/* 17.19 Position Independent Code */
7370
+
7371
+#define        PIC_OFFSET_TABLE_REGNUM                 zip_GOT
7372
+#define        PIC_OFFSET_TABLE_REG_CALL_CLOBBERED     0
7373
+// #define LEGITIMATE_PIC_OPERAND_P(X) should evaluate to X(GOT) only
7374
+
7375
+/* 17.20 Defining the Output Assembler Language */
7376
+
7377
+/* 17.20.2 Output of Data */
7378
+
7379
+/* These hooks (above) specify assembly directives for creating certain kinds
7380
+ * of integer objects.  The TARGET_ASM_BYTE_OP directive creates a byte-sized
7381
+ * object.  The TARGET_ASMALIGNED_HI_OP one creates an aligned two-byte object
7382
+ * and so on.  Any of the hookd may be NULL, indicating that no suitable
7383
+ * directive is available.
7384
+ *
7385
+ * The compiler will print these strings at the start of a new line, followed
7386
+ * immediately by the object's initial value.  In most cases, the string should
7387
+ * contain a tab, a pseudo op, and then another tab.
7388
+ */
7389
+
7390
+#undef TARGET_ASM_ALIGNED_HI_OP
7391
+#undef TARGET_ASM_ALIGNED_SI_OP
7392
+// #undef      TARGET_ASM_ALIGNED_DI_OP
7393
+#define        TARGET_ASM_ALIGNED_HI_OP        ".short"
7394
+// The assembler is set up to call a 4-byte integer a long.  This definition of
7395
+// a long isn't consistent with the compilers definition.  For this reason,
7396
+// the ZipCPU backend for the GNU Assembler defines a long as a 64-bit number,
7397 202 dgisselq
+// and an int as a 32-bit number.
7398 146 dgisselq
+#define        TARGET_ASM_ALIGNED_SI_OP        ".int"
7399
+// #define     TARGET_ASM_ALIGNED_DI_OP        ".long"
7400
+
7401
+
7402
+/* 17.20.4 Output and Generation of Labels */
7403
+
7404
+/* ASM_OUTPUT_LABEL
7405
+ * ... A default definition of this macro is provided which is correct for
7406
+ * most systems.
7407
+ */
7408
+
7409
+/* ASM_OUTPUT_FUNCTION_LABEL
7410 202 dgisselq
+ * ... if not defined, then the function name is defined in the usual manner
7411
+ * as a label.
7412
+ */
7413
+
7414
+/* ASM_OUTPUT_INTERNAL_LABEL ... Identical to ASM_OUTPUT_LABEL, except that name
7415
+ * is known to refer to a compiler-generated label.  The default definition
7416
+ * uses assemble_name_raw, which is like assemble_name except that it is more
7417
+ * efficient.
7418
+ */
7419
+
7420
+/* SIZE_ASM_OP ... A C string containing the appropriate assembler directive
7421
+ * to specify the size of a symbol, without any arguments.  ON systems that
7422 102 dgisselq
+ * use ELF, the default is "\t.size\t"; on other systems, the default is not to
7423
+ * define this macro.
7424
+ *
7425
+ * Define this amcro only if it is correct to use the default definitions of
7426
+ * ASM_OUTPUT_SIZE_DERECTIVE and ASM_OUTPUT_MEASURED_SIZE for your system.
7427
+ * If you need your own custom definitions of those macros, or if you do not
7428
+ * need explicit symbol sizes at all, do not define this macro.
7429
+ */
7430
+
7431
+/* ASM_OUTPUT_SIZE_DIRECTIVE
7432
+ * ASM_OUTPUT_MEASURED_SIZE
7433
+ */
7434
+
7435
+/* NO_DOLLAR_IN_LABEL ... Define this macro if the assembler does not accept
7436
+ * the character '$' in label names.  By default constructors and destructors
7437
+ * in G++ have "$" in the identifiers.  If this label is defined, '.' is
7438
+ * used instead.
7439
+ */
7440
+
7441
+/* NO_DOT_IN_LABEL ... Define this macro if the assembler does not accept the
7442 209 dgisselq
+ * character '.' in label names.  By default constructors and destructors in
7443 102 dgisselq
+ * G++ have names that use '.'.  If this macro is defined, these names are
7444
+ * rewritten to avoid '.'.
7445
+ */
7446
+
7447
+/* TYPE_ASM_OP ... A C string containing the appropriate assembler directive to
7448
+ * specify the type of a symbol, without any arguments.  On systems that use
7449
+ * ELF the default in config/elfos.h is "\t.type\t"; on other systems, the default is not to define this macro.
7450
+ *
7451
+ * Define this macro only if it is correct to use the default definition of
7452
+ * ASM_OUTPUT_TYPE_DIRECTIVE forr your system.  If you need your own custom
7453
+ * definition of this macr, or if you do not need explicit symbol types at all,
7454
+ * do not define this macro.
7455
+ */
7456
+
7457
+/* TYPE OPERAND_FMD ... A
7458
+ */
7459
+
7460
+/* ASM_OUTPUT_TYPE_DIRECTIVE
7461
+ */
7462
+
7463
+/* ASM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) ...
7464
+ * if this macro is not defined, then the function name is defined in the usual
7465
+ * manner as a label (by means of ASM_OUTPUT_FUNCTION_LABEL).
7466
+ */
7467
+
7468
+/* ASM_DECLARE_FUNCTION_SIZE
7469
+ * ASM_DECLARE_COLD_FUNCTION_NAME
7470
+ * ASM_DECLARE_COLD_FUNCTION_SIZE
7471
+ * ASM_DECLARE_OBJECT_NAME
7472
+ * TARGET_ASM_DECLARE_CONSTANT_NAME
7473
+ */
7474
+/* ASM_DECLARE_REGISTER_GLOBAL(STREAM, DECL, REGNO, NAME) ... A C statement
7475
+ * (sans semicolon) to output to the stdio stream STREAM any text necessary for
7476
+ * claiming a register REGNO for a global variable DECL with name NAME.
7477
+ *
7478
+ * If you don't defin this macro, that is equivalent to defining it to do
7479
+ * nothing.
7480
+ */
7481
+
7482
+/* ASM_FINISH_DECLARE_OBJECT
7483
+ * TARGET_ASM_GLOBALIZE_LABEL
7484
+ * TARGET_ASM_GLOBALIZE_DECL_NAME
7485
+ * TARGET_ASM_ASSEMBLE_UNDEFINED_DECL
7486
+ * ASM_WEAKEN_LABEL
7487
+ * ASM_WEAKEN_DECL
7488
+ * ASM_OUTPUT_WEAKREF
7489
+ * SUPPORTS_WEAK
7490
+ * TARGET_SUPPORTS_WEAK
7491
+ * MAKE_DECL_ONE_ONLY
7492
+ * SUPPORTS_ONE_ONLY
7493
+ * TARGTE_ASM_ASSEMBLE_VISIBILITY
7494
+ * TARGET_WEAK_NOT_IN_ARCHIVE_TOC
7495
+ * ASM_OUTPUT_EXTERNAL
7496
+ * TARGET_ASM_EXTERNAL_LIBCALL
7497
+ * TARGET_ASM_MARK_DECLPRESERVED
7498 209 dgisselq
+ * ASM_OUTPUT_LABELREF
7499 102 dgisselq
+ * TARGET_MANGLE_ASSEMBLER_NAME
7500
+ * ASM_OUTPUT_SYMBOL_REF
7501
+ * ASM_OUTPUT_LABEL_REF
7502
+ * TARGET_ASM_INTERNAL_LABEL
7503
+ * ASM_OUTPUT_DEBUG_LABEL
7504
+ * ASM_GENERATE_INTERNAL_LABEL
7505
+ * ASM_FORMAT_PRIVATE_NAME
7506
+ */
7507
+
7508
+/* ASM_OUTPUT_DEF ... A C statement to output to the stdio stream STREAM
7509
+ * assembler code which defines (equates) the symbol NAME to have the value
7510
+ * VALUE.
7511
+ *
7512
+ * ZipCPU---So many other things that we need depend upon this, that we need
7513
+ * to implement a non-default version.
7514
+ */
7515
+#define        ASM_OUTPUT_DEF  zip_asm_output_def
7516
+
7517
+/* ASM_OUTPUT_DEF_FROM_DECLS
7518
+ * TARGET_DEFERRED_OUTPUT_DEFS
7519
+ * ASM_OUTPUT_WEAK_ALIAS
7520
+ * OBJ_GEN_METHOD_LABEL
7521
+ */
7522
+
7523
+
7524
+/* 17.20.7 Output of Assembler Instructions */
7525
+
7526
+#define        REGISTER_NAMES {                                        \
7527
+       "R0", "R1", "R2",  "R3",  "R4",  "R5", "R6", "R7",      \
7528
+       "R8", "R9", "R10", "R11", "R12", "SP", "CC", "PC",      \
7529
+       "uR0","uR1","uR2", "uR3", "uR4", "uR5","uR6","uR7",     \
7530
+       "uR8","uR9","uR10","uR11","uR12","uSP","uCC","uPC",     \
7531
+       "PSEUDO-AP" }
7532
+
7533
+/* REGISTER_PREFIX     (Undefined by default)
7534
+ * LOCAL_LABEL_PREFIX  (Undefined by default)
7535
+ * USER_LABEL_PREFIX   defaults to "*"
7536
+ * IMMEDIATE_PREFIX    (Undefined by default)
7537
+ *
7538
+ * If defined, C string expressions to be used for the '%R', '%L', '%U', and
7539
+ * '%I' options of asm_fprintf (see 'final.c').  These are useful when a single
7540
+ * 'md' file must support multiple assembler formats.  In that case, the various
7541
+ * 'tm.h' files can define these macros differently.
7542
+ */
7543
+// #define     USER_LABEL_PREFIX       "*"
7544
+
7545
+/* Defining memory operand address formats is in this section. */
7546 171 dgisselq
+
7547
+/* 17.20.10 Assembler Commands for Alignment */
7548
+
7549
+/* JUMP_ALIGN(label) ... The alignment (log base 2) to put in front of label,
7550
+ * which is a common destination of jumps and has no fallthru incoming
7551
+ * edge.  This macro need not be defined if you don't want any special alignment
7552 102 dgisselq
+ * to be done at such a time.  Most machine descriptions do not currently define
7553
+ * this macro.
7554
+ *
7555
+ * ZipCPU---The assembler should automatically deal with label alignment, so
7556
+ * let's not do anything about it here.
7557
+ */
7558
+
7559
+/* TARGET_ASM_JUMP_ALIGN_MAX_SKIP
7560
+ */
7561
+
7562
+/* LABEL_ALIGN_AFTER_BARRIER
7563
+ * TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP
7564
+ */
7565
+
7566
+/* LOOP_ALIGN(label)
7567
+ * TARGET_ASM_LOOP_ALIGN_MAX_SKIP
7568
+ * LABEL_ALIGN
7569
+ * TARGET_ASM_LABEL_ALIGN_MAX_SKIP
7570
+ */
7571
+
7572
+/* ASM_OUTPUT_SKIP(STREAM, NBYTES) A C statement to output to the stdio
7573
+ * stream an assembler instruction to advance the location counter by nbytes
7574
+ * bytes.
7575
+ */
7576
+
7577
+/* TARGET_ASM_LABEL_ALIGN */
7578
+/* Assembler Commands for Alignment */
7579
+#define        ASM_OUTPUT_ALIGN(STREAM,POWER)  \
7580
+       do { fprintf(STREAM, "\t.align\t%d\n", POWER); } while (0)
7581
+
7582
+
7583
+/* 17.21 Controlling Debugging Information Format */
7584
+/* 17.22 Cross Compilation and Floating Point */
7585
+
7586
+// REAL_VALUE_TYPE
7587
+// REAL_VALUES_EQUAL
7588
+// REAL_VALUES_LESS ... Tess whether x is less than y
7589
+/* REAL_VALUE_FIX ... Truncates x to an unsigned integer, rouding toward zero.
7590
+ * If x is negative, returns zero.
7591
+ */
7592
+// REAL_VALUE_ATOF
7593
+// REAL_VALUE_NEGATIVE
7594
+// REAL_VALUE_ISINF
7595
+// REAL_VALUE_ISNAN
7596
+/* REAL_ARITHMETIC(OUT,CODE,X,Y) ... (Macro) Calculates an arithmetic operation
7597
+ * on two floating point values X and Y, storing the result in OUT (which must
7598
+ * be a variable).
7599
+ *
7600 202 dgisselq
+ * The operation to be performed is specified by CODE.  Only the following
7601 102 dgisselq
+ * codes are supported: PLUS_EXPR, MINUS_EXPR, MULT_EXPR, RDIV_EXPR, MAX_EXPR,
7602
+ * MIN_EXPR.
7603
+ *
7604
+ * If REAL_ARITHMETIC is asked to evaluate division by zero and the target's
7605 111 dgisselq
+ * floating point format cannot represent infinity, it will call abort().
7606
+ * Callers shoudl check for this situation first, using MODE_HAS_INFINITIES.
7607
+ */
7608
+/* REAL_VALUE_NEGATE(X) ... [Macro] Returns the negative of the floating point
7609
+ * value X.
7610
+ */
7611
+/* REAL_VALUE_ABS(X) ... [Macro] Returns the absolute value of X.
7612
+ */
7613
+/* 17.23 Mode switching instructions */
7614
+/* 17.24 Defining target-specific uses of __attribute__ */
7615
+#undef TARGET_OPTION_OVERRIDE
7616
+#define        TARGET_OPTION_OVERRIDE  zip_override_options
7617
+
7618
+/* 17.25 Emulating TLS */
7619
+/* 17.26 Defining coprocessor specifics for MIPS targets*/
7620
+
7621
+ // ZipCPU isn't MIPS.
7622
+
7623
+/* 17.27 Parameters for Precompiled Header Validity Checking */
7624
+/* 17.28 C++ ABI parameters */
7625
+/* 17.29 Adding support for named address spaces */
7626
+/* 17.30 Miscellaneous Parameters */
7627
+
7628
+/* HAS_LONG_COND_BRANCH ... Define this boolean macro to indicate whether or
7629
+ * not your architecture has conditional branches that can span all of memory.
7630
+ * It is used in conjunction with an optimization that partitions hot and
7631
+ * cold basic blocks into separate sections of the executable.  If this macro
7632
+ * is set to false, gcc will convert any conditional branches that attempt to
7633 102 dgisselq
+ * cross between sections into unconditional branches or indirect jumps.
7634
+ *
7635
+ * ZipCPU --- The assembler renders long unconditional branch code without
7636
+ * problems, so we can pretend that such long branches exist.
7637
+ */
7638
+#define        HAS_LONG_COND_BRANCH true
7639
+
7640
+/* HAS_LONG_UNCOND_BRANCH ... Define this boolean macro to indicate whether
7641
+ * or not your architecture has unconditional branches that can span all of
7642
+ * memory.  (ZipCPU does ... via the LW (PC),PC instruction.)  It is used in
7643
+ * conjunction with an optimization that partitions hot and cold basic blocks
7644
+ * into separate sections of the executable.  If this macro is set to false,
7645
+ * gcc will convert any unconditional branches that attempt to cross between
7646
+ * sections into indirect jumps.
7647
+ *
7648
+ * ZipCPU has the LW (PC),PC instruction which can be used to implement a long
7649
+ * jump.
7650
+ */
7651
+#define        HAS_LONG_UNCOND_BRANCH  true
7652
+
7653
+/* CASE_VECTOR_MODE ... An alias for a machine mode name.  This is the machine
7654
+ * mode that elements of a jump-table should have.
7655
+ *
7656
+ */
7657
+#define        CASE_VECTOR_MODE        SImode
7658
+
7659
+/* CASE_VECTOR_SHORTEN_MODE(MIN,MAX,BODY) ... Optional: return the preferred
7660
+ * mode for an addr_diff_vec when the minimum and maximum offset are known.
7661
+ * If you define this, it enables extra code in branch shortening to deal with
7662 202 dgisselq
+ * addr_diff_vec.  To make this work, you also have to define INSN_ALIGN and
7663 102 dgisselq
+ * make the alignment for addr_diff_vec explicit.  The body argument is provided so that the offset_unsigned and scale flags can be updated.
7664
+ *
7665
+ * ZipCPU---No advantage here.
7666
+ */
7667
+
7668 202 dgisselq
+/* CASE_VECTOR_PC_RELATIVE ... Define this exrpession to indicate when
7669 102 dgisselq
+ * jump-tables should contain relative addresses.  You need not define this
7670
+ * macro if jump-tables never contain relative addresses, or jump-tables
7671
+ * should contain relative addresses only when -fPIC or -FPIC is in effect.
7672
+ *
7673
+ * ZipCPU---No advantage in PC-Relative jump tables--except in PIC relative
7674 202 dgisselq
+ * code.
7675 102 dgisselq
+ */
7676
+
7677
+/* TARGET_CASE_VALUES_THRESHOLD(VOID) ... This function returns the smallest
7678
+ * number of different values for which it is best to use a jump-table instead
7679
+ * of a tree of conditional branches.  The default is four for machines with a
7680
+ * casesi instruction and five otherwise.  This is best for most machines.
7681
+ *
7682
+ * ZipCPU---Leave at the default.
7683
+ */
7684
+
7685
+/* WORD_REGISTER_OPERATIONS ... Define this macro to 1 if operations between
7686
+ * registers with integral mode smaller than a word are always performed on the
7687
+ * entire register.  Most RISC machines have this property and most CISC
7688
+ * machines do not.
7689
+ *
7690
+ * ZipCPU---We have the property, 'cause we're fairly risc.
7691
+ */
7692
+#undef WORD_REGISTER_OPERATIONS
7693
+#define        WORD_REGISTER_OPERATIONS        1
7694
+
7695
+/* LOAD_EXTEND_OP(MEMODE) ... Define this macro to be a C expression indicating
7696
+ * when insns that read memory in MEMMODE, an integral mode narrower than a
7697
+ * word, set the bits outside of MEMMODE to be either the sign extension or
7698
+ * zero-extension of the data read.  Return SIGN_EXTEND for values of MEMMODE
7699
+ * for which the insn sign-extends, ZERO_EXTEND for which it zero-extends, and
7700
+ * UNKNOWN for other modes.
7701
+ *
7702
+ * Do not define this macro if it would always return UNKNOWN.
7703
+ *
7704
+ * ZipCPU---Our memory unit zero extends registers, so we'll zero extend here.
7705
+ */
7706
+#undef LOAD_EXTEND_OP
7707
+#define        LOAD_EXTEND_OP(MEM)     ZERO_EXTEND
7708
+
7709
+/* SHORT_IMMEDIATES_SIGN_EXTEND ... Define this macro to 1 if loading short
7710 202 dgisselq
+ * immediate values into registers sign extends.
7711 102 dgisselq
+ *
7712
+ * ZipCPU---All immediates are sign extended, so yes.
7713
+ */
7714
+#undef SHORT_IMMEDIATES_SIGN_EXTEND
7715
+#define        SHORT_IMMEDIATES_SIGN_EXTEND    1
7716
+
7717
+/* TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
7718
+ */
7719
+
7720
+/* MOVE_MAX ... The maximum number of bytes that a single instruction can move
7721
+ * quickly between memory and registers or between two memory locations.
7722
+ *
7723
+ * ZipCPU --- Although we can move 32-bits at a time, and most people would call
7724 202 dgisselq
+ * this 4-bytes, the compiler defines a byte as the minimum addressable unit.
7725 102 dgisselq
+ * Therefore, this is defined to be one.
7726
+ */
7727 202 dgisselq
+#define        MOVE_MAX        UNITS_PER_WORD
7728 102 dgisselq
+
7729 202 dgisselq
+/* MAX_MOVE_MAX ... The maximum number of bytes that a single instruction can
7730
+ * move quickly between memory and registers or between two memory ...
7731 102 dgisselq
+ *
7732
+ * ZipCPU --- this sounds just the same as MOVE_MAX, which is the default
7733
+ * definition of this.
7734
+ */
7735
+
7736
+/* SHIFT_COUNT_TRUNCATED ... A C expression that is nonzero if on this machine
7737
+ * the number of bits actually used for the count of a shift operation is equal
7738
+ * to the number of bits needed to represent the size of the object being
7739
+ * shifted.
7740
+ *
7741
+ * You need not define this macro if it would have the value of zero.
7742
+ *
7743
+ * ZipCPU---A shift of 33 (or more) in either direction will wipe out the
7744
+ * value in the register, therefore this value should be zero, the default.
7745
+ */
7746
+
7747 202 dgisselq
+/* TARGET_SHIFT_TRUNCATION_MASK(MODE) ... This function describes how the
7748 102 dgisselq
+ * standard shift patterns for MODE deal with shifts by negative amounts or by
7749
+ * more than the width of the mode.
7750
+ *
7751
+ * ZipCPU---The default is zero, since we didn't define SHIFT_COUNT_TRUNCATED.
7752
+ * This is the case for the ZipCPU as well.
7753
+ */
7754
+
7755
+/* TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) ... A C expression which is nonzero
7756
+ * if on this machine it is safe to "convert" an integer of INPREC bits to one
7757
+ * of OUTPREC bits (where OUTPREC is smaller than INPREC) by merely operating on
7758
+ * it as if it had OUTPREC bist.  On many machines, this expression can be 1.
7759
+ *
7760
+ * ZiPCPU ...
7761
+ */
7762
+#undef TRULY_NOOP_TRUNCATION
7763
+#define TRULY_NOOP_TRUNCATION(O,I)     1
7764
+
7765
+/* TARGET_MODE_REP_EXTENDED(MODE,REPMODE) ... The representation of an integral
7766
+ * mode can be such that the values are always extended to a wider integral
7767
+ * mode.  Return SIGN_EXTEND if values of MODE are represented in sign-extended
7768
+ * form to REPMODE.  Return UNKNOWN otherwise.  (Currently none of the targets
7769
+ * use zero-extended this way so unlike LOAD_EXTEND_OP, TARGET_MODE_REP_EXTENDED
7770
+ * is expected to return either SIGN_EXTEND or UNKNOWN.  Also, no target extends
7771
+ * MODE to REP_MODE so that REP_MODE is not the next widest integral mode and
7772
+ * we currently take advantage of this fact.)
7773
+ *
7774
+ * Similarly to LOAD_EXTEND_OP you may return a non_UNKNOWN value even if the
7775
+ * extension is not performed on certain hard registers as long as for the
7776
+ * REGNO_REG_CLASS of tehsse hard registers CANNOT_CHANGE_MODE_CLASS returns
7777
+ * zero.
7778
+ *
7779
+ * Not that TARGET_MODE_REP_EXTENDED and LOAD_EXTEND_OP describe two related
7780 202 dgisselq
+ * properties.  If you define TARGET_MODE_REP_EXTENDED(mode,wordmode) you
7781 102 dgisselq
+ * probably also want to define LOAD_EXTEND_OP(mode) to return the same type
7782
+ * of extension.
7783
+ *
7784
+ * In order to enforce the representation of mode, TRULY_NOOP_TRUNCATION should
7785
+ * return false when truncating to MODE.
7786
+ *
7787
+ * ZipCPU ... ???
7788
+ */
7789 202 dgisselq
+// #undef      TARGET_MODE_REP_EXTENDED
7790
+// #define     TARGET_MODE_REP_EXTENDED(R,M)   UNKNOWN
7791
+
7792
+/* STORE_FLAG_VALUE ... A C expression describing the value returned by a
7793 102 dgisselq
+ * comparison operator with an integral mode and stored by a store-flag
7794 202 dgisselq
+ * instruction (cstoremode4) when the condition is true.  This description
7795
+ * must apply to all the cstoremode4 patterns and all the comparison operators
7796
+ * whose results have MODE_INT mode.
7797
+ *
7798
+ * ZipCPU---Doesn't really have a STORE_FLAG_VALUE instruction ...
7799
+ */
7800
+
7801
+/* FLOAT_STORE_FLAG_VALUE
7802
+ *
7803
+ * ZipCPU
7804
+ */
7805
+
7806
+/* VECTOR_STORE_FLAG_VALUE ... define this macro on machines that have vector
7807
+ * comparison operations that return a vector result ...
7808 102 dgisselq
+ *
7809
+ * ZipCPU---Doesn't support vector operations.
7810 202 dgisselq
+ */
7811 102 dgisselq
+
7812
+/* CLZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
7813
+ * CTZ_DEFINED_VALUE_AT_ZERO(MODE, VAL)
7814
+ *
7815
+ * A C expression that indicates whetther the architecture defines a value for
7816
+ * clz or ctz with a zero operand.  A result of 0 indicates the value is
7817
+ * undefined.  If the value is defined for only the RTL expression, the macro
7818
+ * should evaluate to 1.  If the value also applies to the corresponding optab
7819
+ * entry, then the macro should evaluate to 2.  In cases where the value is
7820
+ * defined, value should be set to this value.
7821
+ * If this macro is not defined, the value of clz or ctz at zero is assumed to
7822
+ * be undefined.
7823
+ *
7824
+ * ZipCPU---Has neither clz nor ctz instructions, so we don't need this.
7825
+ */
7826
+
7827
+/* Pmode ... An alias for the machine mode for pointers.  On most machines,
7828
+ * define this to be the integer mode corresponding to the width of a
7829
+ * hardware pointer.  SImode on 32-bits machines, or DImode on 64-bit machines.
7830
+ * On some machines you must define this to be one of the partial
7831
+ * integer modes, such as PSImode.
7832
+ *
7833
+ * ZipCPU--the machine mode for pointers is one word (32-bits).  The one word
7834
+ * mode is the SImode, so that's what we use here.
7835
+ */
7836
+#undef Pmode
7837 202 dgisselq
+#define        Pmode   SImode
7838
+
7839 102 dgisselq
+/* FUNCTION_MODE ... An alias for the machine mode used for memory references to
7840
+ * function being called, in call RTL expressions.  On most CISC machines, where
7841
+ * an instruction can begin at any byte address, this should be QImode.  On most
7842
+ * RISC machines, where all instructions have fixed size and alignment, this
7843
+ * should be a mode with the same size and alignment as the machine instruction
7844
+ * words--typically SImode or HImode.
7845
+ *
7846
+ * ZipCPU---Definitely SImode, as with Pmode.  (All words are 32-bits, including
7847
+ * addresses on the ZipCPU.
7848
+ */
7849
+#undef FUNCTION_MODE
7850
+#define        FUNCTION_MODE   SImode
7851
+
7852 202 dgisselq
+/* STDC_0_IN_SYSTEM_HEADERS
7853
+ */
7854
+
7855 102 dgisselq
+/* TARGET_C_PREINCLUDE(V) ... Define this hook to return the name of  a header
7856
+ * file to be included at the start of all compilations, as if it had been
7857
+ * included with #include <file>.  If this hook returns NULL, or is not defined,
7858
+ * or if the header is not found, or if the user specifies -ffreestanding or
7859 202 dgisselq
+ * -nostdinc, no header is included.
7860 102 dgisselq
+ *
7861
+ * ZipCPU --- We don't have a standard library defined yet, so we'll leave this
7862
+ * as NULL.
7863
+ */
7864
+#undef TARGET_C_PREINCLUDE
7865
+#define        TARGET_C_PREINCLUDE     NULL
7866
+
7867
+/* TARGET_CXX_IMPLICIT_EXTERN_C(CONST CHAR *) ... Define this hook to add target
7868
+ * specific C++ implicit extern C functions.  If this function returns true
7869
+ * for the name of a file-scope function, that function implicitly gets extern
7870
+ * "C" linkage rather than whatever linkage the declaration would normally have.
7871
+ * An example of such function is WinMain on Win32 targets.
7872
+ *
7873
+ * ZipCPU---Not ready to deal with this yet.
7874
+ */
7875
+
7876
+/* NO_IMPLICIT_EXTERN_C ... Define this macro if the system header files
7877
+ * support C++ as well as C.  This macro inhibits the usual method of using
7878
+ * system header files in C++, which is to pretend that the file's contents
7879
+ * are enclosed in 'extern "C" {...}'.
7880
+ *
7881
+ *
7882
+ * ZipCPU --- Don't have either C or C++ headers, so let's skip this for now.
7883
+ * Eventually, though, I think ZipCPU and C++ would go very well together.
7884
+ */
7885
+
7886
+/* REGISTER_TARGET_PRAGMAS ... Define this macro if you want to implement any
7887
+ * target specific pragmas.
7888
+ *
7889
+ * ZipCPU --- let's not.
7890
+ */
7891
+
7892
+/* HANDLE_PRAGMA_PACK_WITH_EXPANSION ... Define this macro if macros should be
7893
+ * expanded in the arguments of #pragma pack().
7894
+ *
7895
+ * ZipCPU ... why?
7896
+ */
7897
+
7898
+/* TARGET_DEFAULT_PACK_STRUCT ... If your target requires a struct packing
7899
+ * default other than 0 (meaning the machine default), define this macro to
7900
+ * the necessary value (in bytes).  This must be a value that would also be
7901
+ * valid to use with #pragma pack() (that is a small power of two.
7902
+ */
7903
+
7904
+/* DOLLARS_IN_IDENTIFIERS
7905
+ * ZipCPU --- Default (not changing C)
7906
+ */
7907
+
7908
+/* INSN_SETS_ARE_DELAYED(INSN) ... Define this macro as a C expression that
7909
+ * is nonzero if it is safe for the delay slot schedule to place instructions
7910
+ * in the delay slot of INSN, even if they appear to use a resource set or
7911
+ * clobbered in INSN.  INSN is always a ...
7912
+ *
7913
+ * ZipCPU --- You need not define this macro if it would always return zero.
7914
+ */
7915
+
7916
+/* INSN_REFERENCES_ARE_DELAYED(INSN) ... Define this macro as a C expression
7917
+ * that is nonzero if it is safe for the delay slot schedule to place
7918
+ * instructions in the delay slot of INSN, even if they appear to set or clobber
7919
+ * a resource referenced in INSN.  INSN is always a jump_insn or an insn.  On
7920
+ * machines where some insn or jump_insn is really a function call and ...
7921
+ *
7922
+ * ZipCPU --- You need not define this macro if it would always return zero.
7923
+ */
7924
+
7925
+/* MULTIPLE_SYMBOL_SPACES ... Define this macro as a C expression that is
7926
+ * nonzero if, in some cases, global symbols from one translation unit may not
7927
+ * be bound to undefined symbols in another translation unit without user
7928
+ * intervention.  For instance, under Microsoft Windows symbols must be
7929
+ * explicitly imported from shared libraries (DLLs).
7930
+ *
7931
+ * ZipCPU---You need not define this macro if it would always evaluate to zero,
7932
+ * so we won't.
7933
+ */
7934
+
7935
+/* TARGET_MD_ASM_ADJUST
7936
+ */
7937
+/* MATH_LIBRARY ... Define this macro as a C constant ... you only need to
7938
+ * define this macro if the default of "m" is wrong.
7939
+ *
7940
+ * ZipCPU --- as we don't have a math library yet, building one such that "m"
7941
+ * works doesn't sound like a problem.  Let's not define this.
7942
+ */
7943
+
7944
+/* LIBRARY_PATH_ENV ... Define this as a C string constant for the environment
7945
+ * variable that specifies where the linker should look for libraries.
7946
+ *
7947
+ * Just in case we want to add libraries for ZipCPU, let's place them in
7948
+ * /usr/local/zip/lib, so as not to confuse them with our local systems
7949
+ * libraries.
7950
+ */
7951
+#define        LIBRARY_PATH_ENV        "/usr/local/zip/lib"
7952
+
7953
+/* TARGET_POSIX_IO ... Define this macro if the target supports the following
7954
+ * POSIX file fucntions: access, mkdir, and file locking with fcntl/F_SETLKW.
7955
+ *
7956
+ * ZipCPU does not.
7957
+ */
7958
+
7959
+/* MAX_CONDITIONAL_EXECUTE ... A C expression for the maximum number of
7960
+ * instructions to execute via conditional execution instructions instead of a
7961
+ * branch.  A value of BRANCH_COST+1 is the default if the machine does not use
7962
+ * cc0 and 1 if it does use cc0.
7963
+ *
7964
+ * ZipCPU---This sounds good enough for the ZipCPU as well--as long as we have
7965
+ * BRANCH_COST defined.  However, BRANCH_COST is defined as conditionally to
7966
+ * something else, so let's keep looking into this.
7967
+ */
7968
+
7969
+/* IFCVT_MODIFY_TESTS(CEINFO,TRUE,FALSE) ... Used if the target needs to
7970
+ * perform machine-dependent modifications on the conditionals used for turning
7971
+ * basic blocks into conditionally executed code.  CEINFO points to a data
7972
+ * structure, struct ce_if_block, which contains information about the currently
7973
+ * processed blocks.  TRUE and FALSE are the tests that are used for
7974
+ * converting the then-block and the else-block, respectively.  Set either TRUE
7975
+ * or FALSE to a null pointer if the tests cannot be converted.
7976
+ *
7977
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
7978
+ * execution and conditional testing capabilities.
7979
+ */
7980
+#define        IFCVT_MODIFY_TESTS(CI,TR,FL)    zip_ifcvt_modify_tests(CI,&TR,&FL)
7981
+
7982
+/* IFCVT_MODIFY_MULTIPLE_TESTS(CEINFO, BB, TRUE, FALSE) ... Like
7983
+ * IFCVT_MODIFY_TESTS, but used when converting more complicated if-statements
7984
+ * into conditions combined by and and or operations.  BB contains the basic
7985
+ * block that contains the test that is currently being processed and about to
7986
+ * be turned into a condition.
7987
+ *
7988
+ *
7989
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
7990 103 dgisselq
+ * execution and conditional testing capabilities.
7991 102 dgisselq
+ */
7992
+// #warning "Need to come back to this."
7993
+#define        IFCVT_MODIFY_MULTIPLE_TESTS(CI,BB,TR,FL) TR=NULL_RTX
7994
+
7995
+
7996
+/* IFCVT_MODIFY_INSN(CEINFO, PATTERN, INSN) ... A C expression to modify the
7997
+ * PATTERN of an INSN that is to be converted to conditional execution format.
7998
+ * CEINFO points to a data structure, struct ce_if_block, which contains
7999
+ * information about the currently processed blocks.
8000 122 dgisselq
+ *
8001 102 dgisselq
+ *
8002
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
8003
+ * execution and conditional testing capabilities.
8004
+ */
8005
+#define        IFCVT_MODIFY_INSN(CE,PATRN,INSN) zip_ifcvt_modify_insn(CE,PATRN,INSN)
8006
+
8007
+
8008
+/* IFCVT_MODIFY_FINAL(CEINFO) ... A C expression to perform any final
8009
+ * machine dependent modifications in converting code to conditional
8010
+ * execution.  The involved basic blocks can be found in struct ce_if_block
8011
+ * structure pointed to be CEINFO.
8012
+ *
8013 122 dgisselq
+ *
8014 102 dgisselq
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
8015
+ * execution and conditional testing capabilities.
8016
+ */
8017
+// #warning "Need to come back to this."
8018
+#define        IFCVT_MODIFY_FINAL(CEINFO)      zip_ifcvt_modify_final(CEINFO)
8019
+
8020
+
8021
+/* IFCVT_MODIFY_CANCEL(CEINFO) ... A C expression to cancel any machine
8022
+ * dependent modifications in converting code to conditional execution.  The
8023
+ * involved basic blocks can be found in the struct ce_if_block structure that
8024
+ * is pointed to by CEINFO.
8025 142 dgisselq
+ *
8026 102 dgisselq
+ *
8027
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
8028
+ * execution and conditional testing capabilities.
8029
+ */
8030
+// #warning "Need to come back to this."
8031
+#define        IFCVT_MODIFY_CANCEL(CEINFO)     zip_ifcvt_modify_cancel(CEINFO)
8032
+
8033
+
8034
+/* IFCVT_MACHDEP_INIT(CEINFO) ... A C expression to initialize any machine
8035
+ * specific data for if-conversion of the if-block in the CEINFO block structure
8036
+ * that is pointed by CEINFO.
8037
+ *
8038 122 dgisselq
+ *
8039 102 dgisselq
+ * ZipCPU --- I need to set this to properly take advantage of our conditional
8040
+ * execution and conditional testing capabilities.
8041
+ */
8042
+// #warning "Need to come back to this."
8043
+#define        IFCVT_MACHDEP_INIT(CEINFO)      zip_ifcvt_machdep_init(CEINFO)
8044
+
8045
+
8046
+/* TARGET_MACHINE_DEPENDENT_REORG(VOID) ... If non-null, this hook performs a
8047
+ * target specific pass over the instruction stream.  The compiler will run it
8048
+ * at all optimization levels, just before the point at which it normally does
8049
+ * delayed branch scheduling.
8050
+ *
8051 122 dgisselq
+ * You need not implement the hook if it has nothing to do.
8052 102 dgisselq
+ *
8053
+ * ZipCPU---This may be part of a later upgrade, but shouldn't be needed to
8054
+ * just get us started.
8055
+ */
8056
+
8057
+
8058
+/* TARGET_INIT_BUILTINS(VOID) ... Define this hook if you ahve any machine
8059
+ * specific builtin functions that need to be defined.  It should be a function
8060
+ * that performs the necessary setup.  Machine specific builtin functions can be
8061
+ * useful to expand special machine instructions that would otherwise not
8062
+ * normally be generated because they have no equivalent in the source language.
8063 122 dgisselq
+ *
8064 102 dgisselq
+ * To create a built in function, call the function lang_hooks.builtin_function
8065
+ * which is defined by the language front end.  You can use any type nodes
8066
+ * set up by build_common_tree_nodes; only language front ends that use those
8067
+ * two functions will call "TARGET_INIT_BUILTINS".
8068
+ *
8069
+ * ZipCPU---We need to come back to this.  We should have several built-ins
8070
+ * defined: rtu(), wait(), halt(), save_context(cstackregno), and
8071
+ * restore_context(cstackregno).
8072
+ *
8073
+ */
8074
+#undef TARGET_INIT_BUILTINS
8075
+#define        TARGET_INIT_BUILTINS    zip_init_builtins
8076
+
8077
+/* TARGET_BUILTIN_DECL(CODE,INITP) ... Define this hook if you have any
8078
+ * machine specific builtin functions that need to be defined.  It should be a
8079
+ * function that returns the builtin function declaration for the builtin
8080
+ * function code code.  If there is no such builtin and it cannot be initialized
8081
+ * at this time if INITP is true the function should return NULL_TREE.  If
8082
+ * CODE is out of range the fucntion should return error-mark_node.
8083
+ *
8084
+ * ZipCPU ... needs to be done, don't know how to do it yet.
8085
+ */
8086
+#undef TARGET_BUILTIN_DECL
8087
+#define        TARGET_BUILTIN_DECL     zip_builtin_decl
8088
+
8089
+
8090
+/* TARGET_EXPAND_BUILTIN(TREE,TGT,SUB,MODE,IGNORE) ... Expand a call to a
8091
+ * machine specific built-in function that was set up by TARGET_INIT_BUILTINS.
8092
+ * TREE is the expression for the function call; the result should go to
8093
+ * TGT if that is convenient, and have mode MODE if that is convenient.  SUB
8094
+ * may be used as the target for computing one of EXP's operands.  IGNORE is
8095
+ * non-zero if the value is to be ignored.  This function should return the
8096
+ * result of the call to the built-in function.
8097
+ *
8098
+ * ZipCPU ... needs to do it, just to get our special intrinsic functions
8099
+ */
8100
+#define        TARGET_EXPAND_BUILTIN   zip_expand_builtin
8101
+
8102
+
8103
+/* TARGET_BUILTIN_CHKP_FUNCTION(FCODE) ... Allows the target to redefine
8104
+ * builtin functions used by Pointer Bounds Checker for code instrumentation.
8105
+ *
8106
+ * ZipCPU --- not interested.
8107
+ */
8108
+/* TARGET_CHKP_BOUND_TYPE
8109
+ * TARGET_CHKP_MAKE_BOUNDS_CONSTANT
8110
+ * TARGET_CHKP_INITIALIZE_BOUNDS
8111
+ *
8112
+ * ZipCPU --- Same as last one.
8113
+ */
8114
+
8115
+
8116
+/* TARGET_RESOLVE_OVERLOADED_BUILTIN(LOC, FN, ARGS) ... Select a replacement
8117
+ * for a machine specific built-in function that was set up by
8118
+ * TARGET_INIT_BUILTINS.
8119
+ *
8120
+ * ZipCPU --- If I go to the trouble to create a builtin, why would I want
8121
+ * to then overload it?
8122
+ */
8123
+
8124
+/* TARGET_FOLD_BUILTIN(FN,NARGS,ARGP,IGNORE) ... Fold a call to a machine
8125
+ * specific built-in function that was set up by 'TARGET_INIT_BUILTINS'  FN
8126
+ * is the declaration of the built-in function.  NARGS is the number of
8127
+ * arguments passed to the function; the arguments themselves are pointed to by
8128
+ * ARGP.  The result is another tree, valid for both GIMPLE and GENERIC,
8129
+ * containing as simplified expression for the call's result.  If IGNORE is
8130
+ * true the value will be ignored.
8131
+ *
8132
+ * ZipCPU --- You know, this and the previous couple sound like something
8133
+ * whereby I might be able replace bit-reversal code with my bit reverse
8134
+ * instruction.  That would be very useful, but not necessary to get me
8135
+ * started.
8136
+ */
8137
+
8138
+/* TARGET_GIMPLE_FOLD_BUILTIN
8139
+ * TARGET_COMPARE_VERSION_PRIORITY
8140
+ * TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
8141
+ * TARGET_GENERATE_VERSION_DISPATCHER_BODY
8142
+ * TARGET_CAN_USE_DOLOOP_P
8143
+ * TARGET_INVALID_WITHIN_DOOLOOP
8144
+ * TARGET_LEGITIMATE_COMBINED_INSN
8145
+ * TARGET_CAN_FOLLOW_JUMP
8146
+ * TARGET_COMMUTATIVE_P
8147
+ */
8148
+
8149
+/* TARGET_ALLOCATE_INITIAL_VALUE(REGNO)  ... When the initial value of a hard
8150
+ * register has been copied in a pseudo register, it is often not necessary
8151
+ * ...
8152
+ */
8153
+/* TARGET_UNSPEC_MAY_TRAP_P(RTX,FLAGS)  ... This target hook returns nonzero in
8154
+ * RTX, un unspec or unspec_volatile operation, might cause a trap.  Targets
8155
+ * can use this hook to enhance precision of analysis for unspec and
8156
+ * unspec_volatile operations.  You may call may_trap_p_1 to analyze inner
8157
+ * elements of RTX in which case flags should be passed along.
8158
+ */
8159
+
8160
+/* TARGET_SET_CURRENT_FUNCTION(TREE)  The compiler invokes this hook whenever
8161
+ * it changes its current function context (CFUN).  You can define this
8162
+ * function if the back end needs to perform any initialization or reset
8163
+ * actions on a per-function basis.  For example, it may be used to implement
8164
+ * function attributes that affect register usage or code generation patterns.
8165
+ */
8166
+
8167
+/* TARGET_OBJECT_SUFFIX ... Define this macro to be a C string representing the
8168
+ * suffix for object files on your target machine.  If you do not define this
8169
+ * macro, GCC will use ".o" as the suffix for object files.
8170
+ */
8171
+#define        TARGET_OBJECT_SUFFIX    ".o"
8172
+
8173
+/* TARGET_EXECUTABLE_SUFFIX
8174
+ */
8175
+#define        TARGET_EXECUTABLE_SUFFIX        ""
8176
+
8177
+/* COLLECT_EXPORT_LIST ... If defined, collect2 will scan the individual object
8178
+ * files specified on its command line and create an export list for the linker.
8179
+ * Define this macro for systems like AIX, where the linker discards object
8180
+ * files that are not referenced from main and uses export lists.
8181
+ *
8182
+ * ZipCPU --- shoudln't need this.
8183
+ */
8184
+
8185
+/* MODIFY_JNI_METHOD_CALL(MDECL)  ... Define this macro to a C expression
8186
+ * representing a variant of the method call mdecl, if Java Native Interface
8187
+ * (JNI) methods must be invoked differently from other methods on your
8188
+ * target.  For example, on 32-bit MSWindows, JNI methods must be invoked
8189
+ * using the stdcall calling convention and this macro is then ...
8190
+ *
8191
+ * ZipCPU----Don't need this.  (yet)
8192
+ */
8193
+
8194
+
8195
+/* TARGET_CANNOT_MODIFY_JUMPS_P ... This target hook returns true past the
8196
+ * point in which a new jump instructions could be created.  On machines that
8197
+ * require a register for every jump such as the SHmedia ISA of SH5, this point
8198
+ * would typically be reload, so thiss target hook should be defined to a
8199
+ * function such as:
8200
+ *
8201
+ * ZipCPU --- I don't get what this is for.
8202
+ *     Actually, in hind sight, ZipCPU needs this.  Without this, the
8203
+ * compiler will try to reorder basic blocks, shuffling logic around and so
8204
+ * fortch, preventing our comparison optimizations from being used.  By setting
8205
+ * this function appropriately, we can prevent it from reversing conditions into
8206
+ * conditions we don't support.
8207
+ */
8208
+#define        TARGET_CANNOT_MODIFY_JUMPS_P    zip_cannot_modify_jumps_p
8209
+
8210
+/* TARGET_BRANCH_TARGET_REGISTER_CLASS ... This target hook returns a register
8211
+ * class for which branch target register optimizations should be applied.  All
8212
+ * registers in this class should be usable interchangably.  After reload,
8213
+ * registers in this class will be re-allocated and loads will be hoisted out of
8214
+ * loops and be subjected to inter-block scheduling.
8215
+ *
8216
+ * ZipCPU---GENERAL_REGS, but this should be a default already ...
8217
+ */
8218
+
8219
+
8220
+/* TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED ...  Branch target register
8221 117 dgisselq
+ * optimization will by default exclude callee-saved registers that are not
8222
+ * already live during the current function.  If this target hook returns true,
8223
+ * they will be included.  The target code must then make sure that all target
8224
+ * registers in the class returned by TARGET_BRANCH_REGISTER_CLASS that might
8225
+ * be saved are saaved.
8226
+ *
8227 102 dgisselq
+ * ZipCPU---
8228 117 dgisselq
+ */
8229 102 dgisselq
+
8230
+
8231
+/* TARGET_HAVE_CONDITIONAL_EXECUTION(VOID) ... This target hook returns true
8232
+ * if the target supports conditional execution.  This target hook is required
8233
+ * only when the target has several different modes and they have different
8234
+ * conditional execution capability, such as ARM.
8235
+ *
8236
+ * ZipCPU---Yes!  All instructions may be conditionally executed (except the
8237
+ * long version load immediate ...)
8238
+ */
8239
+#define        TARGET_HAVE_CONDITIONAL_EXECUTION       hook_bool_void_true
8240
+
8241
+/* TARGET_GEN_CCMP_FIRST(PREP,GEN,CODE,OP0,OP1) .. This function prepares to
8242
+ * emit a comparison instruction for the first compare in a sequence of
8243
+ * conditional comparisons.  It returns an appropriate comparison with CC for
8244
+ * passing to gen_ccmp_next or cbranch_optab.  The instructions to prepare the
8245
+ * compare are saved in prep_seq and the compare instructions are saved in
8246
+ * gen_seq.  They will be emitted when all the compares in the conditional
8247
+ * comparison are generated without error.  CODE is the rtx_code of the compare
8248
+ * for op0 and op1.
8249
+ *
8250
+ *
8251
+ * ZipCPU---???
8252
+ */
8253
+
8254
+/* TARGET_GEN_CCMP_NEXT(PREP,GEN,PREV,CMP,OP0,OP1,BITCODE) ... This function
8255
+ * prepares to emit a conditional comparison within a sequence of conditional
8256
+ * comparisons.  It returns an appropriate comparison with CC for passing to
8257
+ * gen_ccmp_next or cbranch_optab.  The insn to prepare the compare are saved
8258
+ * in prep_seq and the compare instructions are saved in gen_seq.  They will be
8259
+ * emitted when all the compares in the conditional comparison are generated
8260
+ * without error.  The pPREV expression is the result of a prior call to either
8261
+ * gen_ccmp_first or gen_ccmp_next.  It may return NULL if the combination of
8262
+ * PREV and this comparison is not supported, otherwise the result must be the
8263
+ * appropriate for passing to gen_ccmp_next or cbranch_optab.  CODE is the RTX
8264
+ * code of the compare for op0 and op1.  BITCODE is AND or IOR, which is the op
8265
+ * on the compares.
8266
+ *
8267
+ *
8268
+ * ZipCPU --- ???
8269
+ */
8270
+
8271
+/* TARGET_LOOP_UNROLL_ADJUST(NUNROLL, LOOP) ... This target hook returns a new
8272
+ * value for the number of times loop should be unrolled.  The parameter NUNROLL
8273
+ * is the number of times the loop is to be unrolled.  The parameter loop is a
8274
+ * pointer to the loop, which is going to be checked for unrolling.  The target
8275
+ * hook is required only when the target has special constraints like maximum number of memory accesses.
8276
+ *
8277
+ *
8278
+ * ZipCPU -- ???
8279
+ */
8280
+
8281
+
8282
+/* POWI_MAX_MULTS ... If defined, this macro is interpreted as a signed integer
8283
+ * C expression that specifies the maximum number of floating point
8284
+ * multiplications that should be emitted when expanding exponentiation by an
8285
+ * integer constant inline.  When this value is defined, exponentiation
8286
+ * requiring more than this number of multiplications is implemented by calling
8287
+ * the system library's pow, powf, or powl routines.  The default value
8288
+ places no upper bound on the multiplication count.
8289
+ *
8290
+ * ZipCPU---As we have no system library pow() routine (yet) ... we're not
8291
+ * ready for this macro.
8292
+ */
8293
+
8294
+
8295
+/* TARGET_EXTRA_INCLUDES(SYSROOT, PFX, STDINC) ... This target hook should
8296
+ * register any extra include files for the target.  The parameter stdinc
8297
+ * indicates if normal include files are present.  The parameter SYSROOT is the
8298
+ * system root directory.  The parameter PFX is the prefix for the GCC
8299
+ * directoiry.
8300
+ *
8301
+ *
8302
+ * ZipCPU---None yet.
8303
+ */
8304
+
8305
+/* TARGET_EXTRA_PRE_INCLUDES(SYSROOT, PFX, STDINC) ... This target hook should
8306
+ * register any extrra include files for the target before any standard headers.
8307
+ * The parameter stdinc indicates if normal include files are present.
8308
+ *
8309
+ * ZipCPU --- None.
8310
+ */
8311
+
8312
+/* TARGET_OPTF(PATH) ... This target hook should register special include paths
8313
+ * for the target.  The parameter path is the integer to register.  On Darwin
8314
+ * systems, this is used for Framework includes, which have semantics that are
8315
+ * different from -I.
8316
+ *
8317
+ *
8318
+ * ZipCPU --- None.
8319
+ */
8320
+
8321
+/* TARGET_USE_LOCAL_THUNK_ALIAS_P(FN) ... This target macro returns if it is
8322
+ * safe to use a local alias for a virtual function FN when constructing
8323
+ * thunks, false otherwise.  By default, the macro returns true for all
8324
+ * functions, if a target supports aliases (i.e. defines ASM_OUTPUT_DEF),
8325
+ * false otherwise.
8326
+ *
8327
+ *
8328
+ * ZipCPU --- ???
8329
+ */
8330
+// #warning "ASM_OUTPUT_DEF's definition has not been considered"
8331
+
8332
+
8333
+/* TARGET_FORMAT_TYPES ... If defined, this macro is the name of a global
8334
+ * variable containing target-specific format checking information for the
8335
+ * -Wformat option.  The default is to have no target-specific format checks.
8336
+ *
8337
+ * ZipCPU --- Default
8338
+ */
8339
+
8340
+/* TARGET_N_FORMAT_TYPES
8341
+ *
8342
+ * ZipCPU --- Default
8343
+ */
8344
+
8345
+/* TARGET_OVERRIDES_FORMAT_ATTRIBUTES ... If defined, this macro is the name of
8346
+ * a global variable containing target-specific format overrides for the
8347
+ * -Wformat option.  The default is to have no target specific format overrides.
8348
+ *
8349
+ * ZipCPU --- Default
8350
+ */
8351
+
8352
+/* TARGET_OVERRIDEES_FORMAT_ATTRIBUTES
8353
+ * TARGET_OVERRIDEES_FORMAT_ATTRIBUTES_COUNT
8354
+ *
8355
+ * If defined, the (first) macro is the name of a global variable containing
8356
+ * target-specific format overrides for the -Wformat option.
8357
+ */
8358
+/* TARGET_OVERRIDES_FORMAT_INIT ... If defined, this macro specifies the
8359
+ * optional initialization routine for target specific customizations of the
8360
+* system printf and scanf formatter settings.
8361
+ */
8362
+
8363
+/* TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN(TLIST,FN,VAL) ... If defined, this
8364
+ * macro returns the diagnostic message when it is illegal to pass an argument
8365
+ * VAL to function FN with prototype TLIST.
8366
+ *
8367
+ * ZipCPU---Default.
8368
+ */
8369
+
8370
+/* TARGET_INVALID_CONVERSION
8371
+ * TARGET_INVALID_UNARY_OP
8372
+ * TARGET_INVALID_BINARY_OP
8373
+ * TARGET_INVALID_PARAMETER_TYPE
8374
+ * TARGET_INVALID_RETURN_TYPE
8375
+ * TARGET_PROMOTED_TYPE
8376
+ * TARGET_CONVERT_TO_TYPE
8377
+ * TARGET_USE_JCR_SECTION_TYPE
8378
+ * OBJC_JBLEN
8379
+ * LIBGCC2_UNWIND_ATTRIBUTE
8380
+ * TARGET_UPDATE_STACK_BOUNDARY
8381
+ * TARGET_GET_DRAP_RTX
8382
+ * TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
8383
+ */
8384
+/* TARGET_CONST_ANCHOR ... On some architectures it can take multiple
8385
+ * instructions to synthesize a constant. If there is another constant already
8386
+ * in a register that is close enough in value then it is preferable that the
8387
+ * new constant is computed from the register using immediate addition or
8388
+ * subtraction.  We accomplish this through CSE.  Besides the value of the
8389
+ * constant we also add a lower and an upper constant anchor to the available
8390
+ * expressions.  These are then queried when encountering new constants.  The
8391
+ * anchors are computed by rounding the constant up and down to a multiple of
8392
+ * the value of TARGET_CONST_ANCHOR.  TARGET_CONST_ANCHOR should be the maximum
8393
+ * positive value accepted by immediate-add plus one.  We currently assume that
8394
+ * the value of TARGET_CONST_ANCHOR is a poewr of 2.  For example, on MIPS,
8395
+ * where add-immediate takes a 16-bit signed value, TARGET_CONST_ANCHOR is set
8396
+ * to 0x8000.  The default value is zero, which disables this optimization.
8397
+ *
8398
+ * ZipCPU---One of the great strengths of the ZipCPU ISA is its ability to
8399
+ * access registers plus immediates.  To use this, we *need* this capability.
8400
+ * So, we define it here. (to 0x20000, or 2^17 because we can handle 18-bits of
8401
+ * signed immediate offsets)
8402
+ *
8403
+ * On ZipCPU---2^17
8404
+ */
8405
+#define        TARGET_CONST_ANCHOR     zip_const_anchor
8406
+
8407
+/* TARGET_ASAN_SHADOW_OFFSET ... Return the offset bitwise ored into shifted
8408
+ * address to get corresponding Address Sanitizer shadow memory address.  NULL
8409
+ * if address Sanitizer is not supported by the target.
8410
+ */
8411
+#define        TARGET_ASAN_SHADOW_OFFSET       NULL
8412
+
8413
+/* TARGET_MEMMODEL_CHECK
8414
+ */
8415
+/* TARGET_ATOMIC_TEST_AND_SET_TRUEVAL ... This value should be set if the result
8416
+ * written by atomic test and set is not exactly 1, i.e. the bool true.
8417
+ */
8418
+/* TARGET_HAS_IFUNC_P ... It returns true if the target supports GNU indirect
8419
+ * functions.  The support includes the assembler, linker, and dynamic linker.
8420
+ * The default value of this hook is based on target's libc.
8421
+ */
8422
+#define        TARGET_HAS_IFUNC_P      hook_bool_void_true
8423
+
8424
+/* TARGET_ATOMIC_ALIGN_FOR_MODE(MODE) ... If defined, this function returns
8425
+ * an appropriate alignment in bits for an atomic object of machine mode
8426
+ * MODE.  If 0 is returned then the default alignment for the specified mode
8427
+ * is used.
8428
+ *
8429
+ * ZipCPU---Both default and 2 would be valid.  We'll stick to the default.
8430
+ */
8431
+
8432
+/* TARGET_ATOMIC_ASSIGN_EXPAND_FENV --- ISO C11 requires atomic compound
8433
+ * assignments that may raise floating-point exceptions to raise exceptions
8434
+ * corresponding to the arithmetic operation whose result was successfully
8435
+ * stored in a compare-and-exchange sequence.  This requires code equivalent to
8436
+ * calls to feholdexcept, feclearexcept and feupdateenv to be generated at
8437
+ * appropriate points in the compare-and-exchange sequence.  This hook should
8438
+ * set *hold to an expression equivalent
8439
+ *
8440
+ * ZipCPU --- ???
8441
+ */
8442
+
8443
+/* TARGET_RECORD_OFFLOAD_SYMBOL ... Used when offloaded functions are seen in
8444
+ * the compilation unit and no named sections are available.  It is called once
8445
+ * for each symbol that must be recorded in the offload function and variable
8446
+ * table.
8447
+ *
8448
+ * ZipCPU --- Offloaded functions?
8449
+ */
8450
+
8451
+/* TARGET_OFFLOAD_OPTIONS
8452
+ *
8453
+ * ZipCPU---none defined
8454
+ */
8455
+
8456
+/* TARGET_SUPPORTS_WIDE_INT ... On older ports, large integers are stored
8457
+ * in CONST_DOUBLE rtl objects.  Newer ports define TARGET_SUPPORTS_WIDE_INT
8458
+ * to be nonzero to indicate that large integers are stored in CONST_WIDE_INT
8459
+ * rtl objects.  The CONST_WIDE_INT allows very large integer constants to be
8460
+ * represented.  CONST_DOUBLE is limited to twice the size of the hosts
8461
+ * HOST_WIDE_INT representation.
8462
+ *
8463
+ * ZipCPU---We don't need these yet, so this isn't yet relevant.  (These ints
8464
+ * are wider than DImode ...)
8465
+ */
8466
+#define        TARGET_SUPPORTS_WIDE_INT        0
8467
+
8468
+
8469
+/* Now, for the prototype functions ...*/
8470
+// These have been moved to zip-protos.h
8471
+
8472
+// extern void zip_init_builtins(void);
8473
+// extern void zip_asm_output_anchor(rtx x);
8474
+// extern bool zip_legitimate_address_p(enum machine_mode mode, rtx x, bool string);
8475
+// extern void zip_asm_trampoline_template(FILE *);
8476
+// extern void zip_initial_elimination_offset(int from, int to);
8477
+// extern void zip_print_operand(FILE *stream, rtx *x, int code);
8478
+// extern void zip_print_operand_address(FILE *stream, rtx *x);
8479
+// extern void zip_asm_output_def(FILE *s, const char *n, const char *v);
8480
+// extern void zip_update_cc_notice(rtx exp, rtx_insn *insn);
8481
+// extern      int zip_address_operand(rtx op);
8482
+// extern      int zip_const_address_operand(rtx op);
8483
+// extern void zip_expand_prologue(void);
8484
+// extern void zip_expand_epilogue(void);
8485
+// extern bool zip_gen_move_rtl(rtx, rtx);
8486
+// extern bool zip_load_address_lod(rtx, rtx);
8487
+// extern bool zip_load_address_sto(rtx, rtx);
8488
+// extern void zip_print_operand(FILE *fp, rtx x, int code);
8489
+// extern void zip_print_operand_address(FILE *fp, rtx x);
8490
+extern int zip_use_return_insn(void);
8491
+
8492
+#include "insn-modes.h"
8493
+// #include "zip-protos.h"     // Cant include this here!
8494
+
8495
+#endif /* GCC_ZIP_H */
8496
+
8497
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip.md gcc-6.2.0-zip/gcc/config/zip/zip.md
8498
--- gcc-6.2.0/gcc/config/zip/zip.md     1969-12-31 19:00:00.000000000 -0500
8499
+++ gcc-6.2.0-zip/gcc/config/zip/zip.md 2018-06-07 12:51:05.802342817 -0400
8500
@@ -0,0 +1,1897 @@
8501
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8502
+;;
8503
+;; Filename:   zip.md
8504
+;;
8505
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
8506
+;;
8507
+;; Purpose:    This is the machine description of the Zip CPU as needed by the
8508
+;;             GNU compiler collection (GCC).
8509
+;;
8510 202 dgisselq
+;;
8511 102 dgisselq
+;; Creator:    Dan Gisselquist, Ph.D.
8512
+;;             Gisselquist Technology, LLC
8513 200 dgisselq
+;;
8514 102 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8515
+;;
8516
+;; Copyright (C) 2015-2018, Gisselquist Technology, LLC
8517 202 dgisselq
+;;
8518
+;; This program is free software (firmware): you can redistribute it and/or
8519 209 dgisselq
+;; modify it under the terms of  the GNU General Public License as published
8520
+;; by the Free Software Foundation, either version 3 of the License, or (at
8521 102 dgisselq
+;; your option) any later version.
8522
+;;
8523
+;; This program is distributed in the hope that it will be useful, but WITHOUT
8524
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
8525
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
8526
+;; for more details.
8527
+;;
8528
+;; License:    GPL, v3, as defined and found on www.gnu.org,
8529
+;;             http://www.gnu.org/licenses/gpl.html
8530
+;;
8531
+;;
8532
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8533
+;;
8534
+;;
8535
+;; - Immediate integer operand constraints
8536 209 dgisselq
+;;     'I'     -2^22 ... 2^22-1, or -4194304 .. 4194303        (LDI insn)
8537 102 dgisselq
+;;     'x'     -2^17 ... 2^17-1,                               (DI const)
8538
+;;     'K'     0...2^17-2                                      (ucmp offset)
8539
+;;     'M'     -2^12 ... 2^12-1, or -4096 ... 4095             (MOV offset)
8540
+;;     'N'     -2^14 ... 2^14-1, or -16384 ... 16383           (OpB offset)
8541
+;;     'O'     -2^17 ... 2^17-1, or -131072 ... 131071         (OpB Immediate)
8542
+;;     'R'     0...31                                          (Shift value)
8543
+;; - Memory constraints
8544
+;;     "Q"     Op-B capable references to memory
8545
+;;     "S"     References to constant memory
8546
+;; - Address constraints
8547
+;;     "U"     Op-B capable address that references to memory
8548
+;;     "T"     Constant memory addresses
8549
+(define_constraint "x"
8550
+  "An 17-bit signed immediate such as a CMP:DI instruction can handle"
8551
+  (and (match_code "const_wide_int")
8552
+       (match_test "(ival < 0x20000l) && (ival >= -0x20000l)")))
8553
+(define_constraint "K"
8554
+  "An 17-bit signed immediate such as a CMP:DI instruction can handle"
8555
+  (and (match_code "const_int")
8556
+       (match_test "(ival < 0x20000) && (ival >= -0x20000)")))
8557 202 dgisselq
+(define_constraint "M"
8558
+  "An 13-bit signed immediate such as a MOV instruction can handle"
8559 102 dgisselq
+  (and (match_code "const_int")
8560
+       (match_test "(ival < 0x1000) && (ival >= -0x1000)")))
8561
+(define_constraint "N"
8562
+  "An 14-bit signed immediate offset such as an Op-B register offset"
8563
+  (and (match_code "const_int")
8564 111 dgisselq
+       (match_test "(ival < 0x2000) && (ival >= -0x2000)")))
8565
+(define_constraint "O"
8566 102 dgisselq
+  "An 18-bit signed immediate such as an Op-B Immediate can handle"
8567 111 dgisselq
+  (and (match_code "const_int")
8568
+       (match_test "(ival < 0x20000) && (ival >= -0x20000)")))
8569 202 dgisselq
+(define_constraint "R"
8570
+  "Bits that a value may be shifted"
8571
+  (and (match_code "const_int")
8572
+       (match_test "(ival < 32) && (ival >= 0)")))
8573
+;;
8574
+;
8575
+;
8576
+; Our builtin functions, by identifier
8577 102 dgisselq
+;
8578
+(define_constants
8579
+       [(UNSPEC_RTU             1)
8580
+       (UNSPEC_HALT             2)
8581
+       (UNSPEC_IDLE             3)
8582
+       (UNSPEC_SYSCALL          4)
8583
+       (UNSPEC_SAVE_CONTEXT     5)
8584
+       (UNSPEC_RESTORE_CONTEXT  6)
8585
+       (UNSPEC_BITREV           7)
8586
+       (UNSPEC_GETUCC           8)
8587
+       (UNSPEC_GETCC            9)
8588
+       (UNSPEC_LDILO           10)
8589
+       ; (UNSPEC_RAW_CALL      11)
8590
+       ])
8591
+;
8592
+;
8593
+; Registers by name
8594
+(define_constants
8595
+  [(RTN_REG            0)      ; Return address register
8596
+   (RTNV_REG           1)      ; Subroutine return value register
8597
+   (AP_REG             10)     ; Hopefully never used
8598
+   (GBL_REG            11)     ; Hopefully never used, but just in case ...
8599 117 dgisselq
+   (FP_REG             12)     ; Frame pointer register
8600
+   (SP_REG             13)     ; Stack pointer register
8601
+   (CC_REG             14)     ; Condition codes register
8602
+   (PC_REG             15)     ; Program counter
8603
+  ])
8604
+;
8605
+;
8606
+;
8607
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8608
+;;
8609 127 dgisselq
+;; Mode iterator
8610 102 dgisselq
+;;
8611
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8612
+;
8613
+;
8614
+(define_mode_iterator ZI [QI HI SI])
8615
+(define_mode_attr sz [(QI "B") (HI "H") (SI "W")])
8616
+;
8617
+;
8618
+;
8619 209 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8620
+;;
8621
+;; Predicates
8622
+;;
8623 102 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8624
+;
8625
+;
8626
+;
8627 200 dgisselq
+(define_predicate "zip_const_address_operand_p"
8628
+       (match_code "symbol_ref,const,label_ref,code_label")
8629 202 dgisselq
+{
8630
+       return zip_const_address_operand(op);
8631
+})
8632
+
8633
+(define_predicate "zip_address_operand_p"
8634
+       (match_code "reg,plus")
8635
+{
8636
+       return zip_pd_opb_operand(op);
8637
+})
8638
+
8639
+(define_predicate "zip_opb_operand_p"
8640
+       (match_code "reg,plus,const_int,subreg")
8641 102 dgisselq
+{
8642 200 dgisselq
+       return zip_pd_opb_operand(op);
8643
+})
8644
+
8645
+(define_predicate "zip_opb_immv_p"
8646
+       (match_code "const_int")
8647 102 dgisselq
+{
8648
+       return (INTVAL(op)<((1<<13)-1))&&(INTVAL(op)>=-((1<<13)));
8649
+})
8650
+
8651
+(define_predicate "zip_opb_single_operand_p"
8652
+       (match_code "reg,subreg,const_int")
8653
+{
8654
+       return zip_pd_opb_operand(op);
8655
+})
8656 111 dgisselq
+
8657 102 dgisselq
+(define_predicate "zip_mov_operand_p"
8658
+       (match_code "reg,plus")
8659 111 dgisselq
+{
8660 122 dgisselq
+       return zip_pd_mov_operand(op);
8661 111 dgisselq
+})
8662
+
8663
+(define_predicate "zip_memory_operand_p"
8664
+       (match_code "mem")
8665 122 dgisselq
+{
8666
+       return zip_pd_opb_operand(XEXP(op,0));
8667
+})
8668
+
8669
+(define_predicate "zip_imm_operand_p"
8670
+       (match_code "const_int")
8671 111 dgisselq
+{
8672 122 dgisselq
+       return zip_pd_imm_operand(op);
8673 111 dgisselq
+})
8674
+
8675
+(define_predicate "zip_mvimm_operand_p"
8676
+       (match_code "const_int")
8677 102 dgisselq
+{
8678
+       return zip_pd_mvimm_operand(op);
8679
+})
8680
+
8681
+;
8682
+;
8683
+;
8684
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8685
+;;
8686 111 dgisselq
+;; Constraints
8687 102 dgisselq
+;;
8688
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8689 111 dgisselq
+;
8690
+;
8691
+;
8692
+(define_memory_constraint "S"
8693
+       "Any memory referenced by a constant address, possibly unknown at compile time"
8694
+       (and (match_code "mem")
8695
+               (match_test "zip_ct_const_address_operand(XEXP(op,0))")))
8696
+(define_memory_constraint "Q"
8697
+       "Any memory addressed suitably for a load or store instruction"
8698
+       (and (match_code "mem")
8699
+               (match_test "zip_ct_address_operand(XEXP(op,0))")))
8700
+(define_address_constraint "U"
8701 202 dgisselq
+       "An address suitable for a load or store instruction"
8702
+       (and (match_code "reg,plus")
8703 200 dgisselq
+               (match_test "zip_ct_address_operand(op)")))
8704
+(define_address_constraint "T"
8705
+       "Any constant address, to include those made by symbols unknown at compile time"
8706 102 dgisselq
+       (and (match_code "label_ref,code_label,symbol_ref,const")
8707 200 dgisselq
+               (match_test "zip_ct_const_address_operand(op)")))
8708
+;
8709 102 dgisselq
+;
8710 200 dgisselq
+;
8711
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8712 102 dgisselq
+;;
8713
+;; Attributes
8714
+;;
8715
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8716
+;
8717
+;
8718
+;
8719
+;
8720
+;
8721
+(define_attr "predicable"  "no,yes" (const_string "yes"))
8722
+(define_attr "ccresult" "set,unknown,unchanged,validzn" (const_string "set"))
8723
+;
8724
+;
8725
+;
8726
+;
8727
+;
8728
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8729
+;;
8730 200 dgisselq
+;; Instructions
8731
+;;
8732
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8733 102 dgisselq
+;
8734 200 dgisselq
+;
8735
+;
8736 102 dgisselq
+;; Instructions
8737 200 dgisselq
+;
8738
+; (define_insn
8739
+;      optional name
8740
+;      RTL template -- a vector of incomplete RTL expressions describing the
8741 102 dgisselq
+;              semantics of the instruction.  It is incomplete because it may
8742
+;              contain match_operand, match_operator, and match_dup expressions
8743
+;      The condition --- contains a C expression, may be an empty string
8744
+;      output template or output statement--fragment of C code returning a str
8745
+;      Attributes --
8746
+;      )
8747 200 dgisselq
+;
8748
+; (match_operand:m n predicate constraint)
8749
+;      Placeholder for operand #n of the instruction
8750 102 dgisselq
+;      Predicate       string that is the name of a fucntion w/ 2 arguments:
8751 200 dgisselq
+;                              (expression, machine mode)
8752
+;              we can build functions:
8753 102 dgisselq
+;                      "isregister"    to describe a register
8754 200 dgisselq
+;                      "isimmediate"   to describe an immediate
8755
+;                      "offsetreg"     to describe a register plus offset
8756
+;                      "anyregister"   to describe *ANY* register (uRx or Rx)
8757
+;              But ... functions "address_operand", "immediate_operand",
8758 102 dgisselq
+;                      "register_operand", "indirect_operand"
8759
+;              "comparison_operatot" and "ordered_comparison_operator"
8760
+;              are also available--be aware, they include more comparisons
8761
+;              than Zip CPU can do.
8762
+;
8763
+;
8764
+;
8765
+;
8766
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8767
+;;
8768
+;; Move instructions: both
8769
+;;     (arbitrary) from variables to variables, but this gets
8770
+;;             expanded into:
8771
+;;     from registers to registers
8772
+;;     from immediates to registers
8773
+;;
8774
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8775
+;
8776
+;
8777
+;
8778
+(define_expand "mov<mode>"
8779
+       [(set (match_operand:ZI 0 "nonimmediate_operand" "")
8780
+               (match_operand:ZI 1 "general_operand" ""))]
8781
+       ""
8782
+       {//; Everything except mem=const or mem=mem can be done easily
8783
+       //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
8784
+       //; fprintf(stderr, "ZIP-GEN-MOVE\n");
8785
+       //; zip_debug_rtx_pfx("FROM: ", operands[1]);
8786
+       //; zip_debug_rtx_pfx("TO  : ", operands[0]);
8787
+
8788
+       //; Need to load into a register between memory slots
8789 200 dgisselq
+       if ((MEM_P(operands[0]))&&(MEM_P(operands[1]))) {
8790
+               //; fprintf(stderr, "GEN-MOVSI: MEM -> MEM\n");
8791
+               if (can_create_pseudo_p()) {
8792
+                       rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
8793 102 dgisselq
+                       if (GET_MODE(operands[1])==QImode)
8794
+                               emit_insn(gen_movqi(tmp,operands[1]));
8795
+                       else if (GET_MODE(operands[1])==HImode)
8796
+                               emit_insn(gen_movhi(tmp,operands[1]));
8797
+                       else
8798
+                               emit_insn(gen_movsi(tmp,operands[1]));
8799 111 dgisselq
+                       operands[1] = tmp;
8800
+               }
8801 102 dgisselq
+       }}
8802 111 dgisselq
+       [(set_attr "ccresult" "unchanged")])
8803
+(define_insn "mov<mode>_raw"
8804
+       [(set (match_operand:ZI 0 "nonimmediate_operand" "=r,Q,r,r")
8805
+               (match_operand:ZI 1 "general_operand" "r,r,Q,i"))]
8806
+       ""
8807
+       "@
8808
+       MOV\t%1,%0
8809
+       S<sz>\t%1,%0
8810
+       L<sz>\t%1,%0
8811
+       LDI\t%1,%0"
8812
+       [(set_attr "ccresult" "unchanged")])
8813 202 dgisselq
+(define_insn "movsi_reg_off" ; Register to register move, used by prologue
8814
+       [(set (match_operand:SI 0 "register_operand" "=r")
8815
+               (plus:SI (match_operand:SI 1 "register_operand" "r")
8816
+                       (match_operand:SI 2 "zip_mvimm_operand_p" "M")))
8817
+               ]
8818
+       ""
8819 111 dgisselq
+       "MOV    %2(%1),%0"
8820
+       [(set_attr "ccresult" "unchanged")])
8821 202 dgisselq
+(define_insn "mov<mode>_lod"   ; Load from memory
8822 102 dgisselq
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8823 202 dgisselq
+               (match_operand:ZI 1 "zip_memory_operand_p" "Q"))]
8824
+       ""
8825
+       "L<sz>\t%1,%0"
8826
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
8827 111 dgisselq
+(define_insn "mov<mode>_lod_off" ; used by epilogue code
8828
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8829 202 dgisselq
+               (mem:ZI (plus:SI (match_operand:SI 1 "register_operand" "r")
8830
+                       (match_operand:SI 2 "zip_opb_immv_p" "N"))))]
8831 111 dgisselq
+       ""
8832
+       "L<sz>\t%2(%1),%0"
8833 202 dgisselq
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
8834
+(define_insn "mov<mode>_sto"   ; Store into memory
8835
+       [(set (match_operand:ZI 0 "zip_memory_operand_p" "=Q")
8836
+               (match_operand:ZI 1 "register_operand" "r"))]
8837 111 dgisselq
+       ""
8838 102 dgisselq
+       "S<sz>\t%1,%0"
8839
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
8840
+(define_insn "mov<mode>_sto_off" ; used by prologue code
8841 202 dgisselq
+       [(set (mem:ZI (plus:SI
8842 102 dgisselq
+                       (match_operand:SI 0 "register_operand" "r")
8843
+                       (match_operand:SI 1 "zip_opb_immv_p" "N")))
8844
+               (match_operand:ZI 2 "register_operand" "r"))]
8845 202 dgisselq
+       ""
8846 103 dgisselq
+       "S<sz>\t%2,%1(%0)"
8847 202 dgisselq
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
8848
+(define_insn "mov<mode>_ldi"   ; Load immediate
8849
+       [(set (match_operand:ZI 0 "register_operand" "=r")
8850
+               (match_operand:ZI 1 "immediate_operand" "ipU"))]
8851 124 dgisselq
+       ""
8852 202 dgisselq
+       "LDI    %1,%0"
8853 124 dgisselq
+       [(set_attr "ccresult" "unchanged")])
8854 202 dgisselq
+;
8855 102 dgisselq
+;
8856
+;
8857
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8858 202 dgisselq
+;;
8859 103 dgisselq
+;; Substitution Pattern
8860 202 dgisselq
+;;
8861
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8862 124 dgisselq
+;
8863 202 dgisselq
+;
8864
+(define_subst "cc_substitution"
8865 124 dgisselq
+       ; The pattern may not have any match_dup expressions.
8866 202 dgisselq
+       [(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
8867 124 dgisselq
+               (clobber (reg:CC CC_REG))]
8868 102 dgisselq
+       ""
8869
+       [(set (match_dup 0) (match_dup 1))
8870
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))
8871
+       ])
8872
+;
8873
+(define_subst_attr "cc_subst" "cc_substitution" "_raw" "_clobber")
8874
+;
8875
+;
8876
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8877
+;;
8878
+;; Mode conversions
8879 127 dgisselq
+;;
8880
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8881
+;
8882
+;
8883
+(define_insn "zero_extendqisi2"
8884
+       [(set (match_operand:SI 0 "register_operand" "=r")
8885
+               (zero_extend:SI
8886
+                       (match_operand:QI 1 "register_operand" "0")))
8887
+       (clobber (reg:CC CC_REG))]
8888
+       ""
8889
+       "AND\t255,%0    ; zero_extendqisi2 ... reg"
8890
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
8891
+
8892
+(define_insn "zero_extendqisi2_raw"
8893
+       [(set (match_operand:SI 0 "register_operand" "=r")
8894
+               (zero_extend:SI
8895
+                       (match_operand:QI 1 "register_operand" "0")))
8896
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8897
+       ""
8898 202 dgisselq
+       "AND\t255,%0    ; zero_extendqisi2 ... raw/set CC"
8899 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
8900
+
8901
+(define_insn "zero_extendqisi2_mem"
8902
+       [(set (match_operand:SI 0 "register_operand" "=r")
8903 202 dgisselq
+               (zero_extend:SI
8904 122 dgisselq
+                       (match_operand:QI 1 "memory_operand" "Q")))]
8905 202 dgisselq
+       ""
8906
+       "LB\t%1,%0\t; Zero-Extend:QI"
8907 127 dgisselq
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
8908
+;
8909 202 dgisselq
+;
8910
+;
8911
+;
8912
+(define_insn "zero_extendhisi2"
8913 127 dgisselq
+       [(set (match_operand:SI 0 "register_operand" "=r")
8914 202 dgisselq
+               (zero_extend:SI
8915
+                       (match_operand:HI 1 "register_operand" "0")))
8916 122 dgisselq
+       (clobber (reg:CC CC_REG))]
8917 102 dgisselq
+       ""
8918 202 dgisselq
+       "AND\t65535,%0  ; zero_extendhisi2 ... reg"
8919
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
8920
+(define_insn "zero_extendhisi2_raw"
8921
+       [(set (match_operand:SI 0 "register_operand" "=r")
8922
+               (zero_extend:SI
8923
+                       (match_operand:HI 1 "register_operand" "0")))
8924
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
8925 102 dgisselq
+       ""
8926 202 dgisselq
+       "AND\t65535,%0  ; zero_extendhisi2 ... reg"
8927
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
8928 102 dgisselq
+(define_insn "zero_extendhisi2_mem"
8929
+       [(set (match_operand:SI 0 "register_operand" "=r")
8930
+               (zero_extend:SI
8931 202 dgisselq
+                       (match_operand:HI 1 "memory_operand" "Q")))
8932
+       ]
8933
+       ""
8934
+       "LH\t%1,%0\t; Zero-Extend:HI"
8935
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "set")])
8936 127 dgisselq
+;
8937
+;
8938 202 dgisselq
+;
8939
+;
8940
+(define_insn "extendqisi2"
8941
+       [(set (match_operand:SI 0 "register_operand" "=r")
8942
+               (sign_extend:SI
8943
+                       (match_operand:QI 1 "register_operand" "0")))
8944 122 dgisselq
+       (clobber (reg:CC CC_REG))]
8945 102 dgisselq
+       ""
8946 202 dgisselq
+       "SEXTB\t%0\t; SEXTB"
8947
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8948
+(define_insn "extendhisi2"
8949
+       [(set (match_operand:SI 0 "register_operand" "=r")
8950
+               (sign_extend:SI
8951
+                       (match_operand:HI 1 "register_operand" "0")))
8952
+       (clobber (reg:CC CC_REG))]
8953 127 dgisselq
+       ""
8954 202 dgisselq
+       "SEXTH\t%0\t; SEXTH"
8955
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8956 138 dgisselq
+;
8957
+;
8958
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8959
+;;
8960 202 dgisselq
+;; General arithmetic instructions
8961 138 dgisselq
+;;
8962 202 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8963
+;
8964
+;
8965 138 dgisselq
+;
8966 202 dgisselq
+;;
8967
+;; modsi3
8968
+;; umodsi3
8969 138 dgisselq
+;;
8970 202 dgisselq
+(define_insn "uminsi3"
8971
+       [(set (match_operand:SI 0 "register_operand" "=r")
8972
+               (umin:SI (match_operand:SI 1 "register_operand" "%0")
8973 138 dgisselq
+                       (match_operand:SI 2 "register_operand" "r")))
8974 202 dgisselq
+       (clobber (reg:CC CC_REG))
8975
+       ]
8976 138 dgisselq
+       ""
8977
+       "CMP    %0,%2
8978 202 dgisselq
+       MOV.C   %2,%0"
8979
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8980
+(define_insn "umaxsi3"
8981
+       [(set (match_operand:SI 0 "register_operand" "=r")
8982
+               (umax:SI (match_operand:SI 1 "register_operand" "%0")
8983 138 dgisselq
+                       (match_operand:SI 2 "register_operand" "r")))
8984
+       (clobber (reg:CC CC_REG))
8985 202 dgisselq
+       ]
8986 102 dgisselq
+       ""
8987
+       "CMP    %2,%0
8988
+       MOV.C   %2,%0"
8989
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
8990 202 dgisselq
+(define_insn "sminsi3"
8991
+       [(set (match_operand:SI 0 "register_operand" "=r")
8992
+               (smin:SI (match_operand:SI 1 "register_operand" "%0")
8993
+                       (match_operand:SI 2 "register_operand" "r")))
8994 122 dgisselq
+       (clobber (reg:CC CC_REG))
8995 102 dgisselq
+       ]
8996
+       ""
8997
+       "CMP    %2,%0
8998
+       MOV.GE  %2,%0"
8999
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9000 202 dgisselq
+(define_insn "smaxsi3"
9001
+       [(set (match_operand:SI 0 "register_operand" "=r")
9002
+               (smax:SI (match_operand:SI 1 "register_operand" "%0")
9003
+                       (match_operand:SI 2 "register_operand" "r")))
9004 122 dgisselq
+       (clobber (reg:CC CC_REG))
9005 102 dgisselq
+       ]
9006
+       ""
9007
+       "CMP    %2,%0
9008
+       MOV.LT  %2,%0"
9009
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9010 202 dgisselq
+;
9011
+;
9012
+; AND
9013
+; iOR
9014 122 dgisselq
+; XOR
9015 102 dgisselq
+;
9016
+;
9017
+;
9018 202 dgisselq
+;(define_insn "addvsi4"
9019 102 dgisselq
+       ;[(set (match_operand:SI 0 "register_operand" "=r")
9020 202 dgisselq
+               ;(plus:SI (match_operand:SI 1 "register_operand" "%r")
9021
+                       ;(match_operand:SI 2 "general_operand" "rO")))
9022
+       ;(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
9023
+                       ;(label_ref (match_operand 3))
9024 122 dgisselq
+                       ;(pc)))]
9025 102 dgisselq
+       ;""
9026
+       ;"MOV   %1,%0
9027 202 dgisselq
+       ;ADD    %2,%0
9028 102 dgisselq
+       ;BV     %3"
9029
+       ;[(set_attr "predicable" "no") (set_attr "ccresult" "set")])
9030 127 dgisselq
+;;(define_insn "subvsi4"
9031
+;;     MOV     %1,%0
9032 200 dgisselq
+;;     SUB     %2,%0
9033
+;;     BV      %3
9034
+;;(mulvsi4)
9035
+;;(define_insn "uaddvsi4"
9036
+;;     ADD     %2,%0
9037
+;;     BC      %3
9038 202 dgisselq
+;;(define_insn "usubvsi4"
9039
+;;     MOV     %1,%0
9040
+;;     SUB     %2,%0
9041
+;;     BC      %3
9042 122 dgisselq
+;;
9043 102 dgisselq
+;; (define_insn "umulvsi4"
9044
+;;     ... ???)
9045
+;;
9046
+;
9047
+;
9048
+;
9049
+;
9050
+;
9051
+;
9052
+; Others:  NEG, TEST, POPC, NOT
9053
+;
9054
+;
9055
+(define_insn "negsi2"
9056
+       [(set (match_operand:SI 0 "register_operand" "=r")
9057
+               (neg:SI (match_operand:SI 1 "register_operand" "r")))
9058
+       (clobber (reg:CC CC_REG))]
9059
+       ""
9060
+       "NEG    %1,%0"  ;//; = MOV -1(%1),%0, XOR -1,%0
9061
+       [(set_attr "ccresult" "validzn")])
9062
+(define_insn "abssi2"
9063
+       [(set (match_operand:SI 0 "register_operand" "=r")
9064
+               (abs:SI (match_operand:SI 1 "register_operand" "0")))
9065
+       (clobber (reg:CC CC_REG))]
9066 200 dgisselq
+       ""
9067
+       "TEST\t%0\n\tNEG.LT\t%0"
9068
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9069
+(define_insn_and_split "one_cmplsi2"
9070
+       [(set (match_operand:SI 0 "register_operand" "=r")
9071 127 dgisselq
+               (not:SI (match_operand:SI 1 "register_operand" "0")))
9072 200 dgisselq
+       (clobber (reg:CC CC_REG))]
9073
+       ""
9074
+       "#"
9075 202 dgisselq
+       ""
9076
+       [(parallel [(set (match_dup 0) (xor:SI (match_dup 1) (const_int -1)))
9077
+               (clobber (reg:CC CC_REG))])]
9078 122 dgisselq
+       ""
9079 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9080 202 dgisselq
+;
9081 102 dgisselq
+;
9082 202 dgisselq
+;
9083
+;
9084
+;
9085 122 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9086 102 dgisselq
+;;
9087 202 dgisselq
+;; Comparison instructions, both compare and test
9088 102 dgisselq
+;;
9089 202 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9090
+;
9091
+;
9092
+;
9093 102 dgisselq
+;; This will only work so well, since the direction of the compare is
9094 202 dgisselq
+;; important in unsigned compares.
9095 102 dgisselq
+;;
9096 202 dgisselq
+(define_expand "cmpsi"
9097
+       [(set (reg:CC CC_REG) (compare:CC
9098
+               (match_operand:SI 0 "register_operand" "r")
9099 102 dgisselq
+               (match_operand:SI 1 "nonmemory_operand" "")))]
9100
+       ""
9101 200 dgisselq
+       {
9102
+               if (!zip_opb_operand_p(operands[1],SImode)) {
9103
+                       if (can_create_pseudo_p()) {
9104
+                               //; fprintf(stderr, "Generating pseudo register for compare\n");
9105 102 dgisselq
+                               rtx tmp = gen_reg_rtx(SImode);
9106
+                               emit_insn(gen_movsi(tmp,operands[1]));
9107
+                               operands[1] = tmp;
9108
+                       } else FAIL;
9109
+               }
9110
+       })
9111
+(define_insn "cmpsi_reg"
9112
+       [(set (reg:CC CC_REG) (compare:CC
9113
+               (match_operand:SI 0 "register_operand" "r")
9114
+               (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))]
9115
+       ""
9116 202 dgisselq
+       "CMP\t%1,%0"
9117 122 dgisselq
+       [(set_attr "ccresult" "set")])
9118 202 dgisselq
+(define_insn "cmpsi_off"
9119
+       [(set (reg:CC CC_REG) (compare:CC
9120 102 dgisselq
+               (match_operand:SI 0 "register_operand" "r")
9121 122 dgisselq
+               (plus:SI (match_operand:SI 1 "register_operand" "r")
9122
+                       (match_operand 2 "zip_opb_immv_p" "N"))))]
9123
+       ""
9124
+       "CMP\t%2+%1,%0"
9125
+       [(set_attr "ccresult" "set")])
9126
+(define_insn "testsi"
9127
+       [(set (reg:CC CC_REG) (compare:CC (and:SI (match_operand:SI 0 "register_operand" "r")
9128
+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
9129
+                       (const_int 0)))]
9130
+       ""
9131 202 dgisselq
+       "TEST   %1,%0"
9132 122 dgisselq
+       [(set_attr "ccresult" "set")])
9133 202 dgisselq
+(define_insn "testsi_off"
9134
+       [(set (reg:CC CC_REG) (compare:CC
9135 122 dgisselq
+               (and:SI (match_operand:SI 0 "register_operand" "r")
9136 102 dgisselq
+                       (plus:SI
9137
+                               (match_operand:SI 1 "register_operand" "r")
9138 202 dgisselq
+                               (match_operand:SI 2 "zip_opb_immv_p" "N")))
9139 122 dgisselq
+               (const_int 0)))]
9140 202 dgisselq
+       ""
9141
+       "TEST   %2+%1,%0"
9142 122 dgisselq
+       [(set_attr "ccresult" "set")])
9143 102 dgisselq
+(define_insn "nop"
9144
+       [(const_int 0)]
9145
+       ""
9146 202 dgisselq
+       "NOOP"
9147
+       [(set_attr "ccresult" "unchanged")])
9148
+;
9149 102 dgisselq
+;
9150
+;
9151
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9152
+;;
9153 202 dgisselq
+;; Conditional execution predicates
9154 122 dgisselq
+;;
9155 202 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9156
+;
9157
+; Sadly, these aren't complete like they should be.  Although these are all of
9158
+; the conditional execution prefixes that the Zip CPU supports, GCC looks for
9159 122 dgisselq
+; other conditions then these.  That is, (cond_exec ...) is not as well
9160 102 dgisselq
+; recognized as (if_then_else ...).  So we have to duplicate things to support
9161
+; both methods.
9162
+;
9163
+(define_cond_exec
9164
+       [(eq  (reg:CC CC_REG) (const_int 0))] "" "[Z]")
9165
+(define_cond_exec
9166
+       [(ne  (reg:CC CC_REG) (const_int 0))] "" "[NZ]")
9167
+(define_cond_exec
9168
+       [(lt  (reg:CC CC_REG) (const_int 0))] "" "[LT]")
9169
+(define_cond_exec
9170
+       [(ge  (reg:CC CC_REG) (const_int 0))] "" "[GE]")
9171
+(define_cond_exec
9172
+       [(ltu (reg:CC CC_REG) (const_int 0))] "" "[C]")
9173
+(define_cond_exec
9174
+       [(geu (reg:CC CC_REG) (const_int 0))] "" "[NC]")
9175
+;
9176
+;
9177
+;
9178
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9179
+;;
9180
+;; Conditional move instructions, since these won't accept conditional
9181
+;;     execution RTL
9182
+;;
9183
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9184 202 dgisselq
+;
9185 102 dgisselq
+; // Look for #define HAVE_conditional_move to understand how these might be
9186 202 dgisselq
+; // used.
9187 102 dgisselq
+;
9188 202 dgisselq
+; set_zero_or_one_si
9189 102 dgisselq
+; movsicc
9190 202 dgisselq
+(define_expand "movsicc"
9191 102 dgisselq
+       [(set (match_operand:SI 0 "nonimmediate_operand" "")
9192 202 dgisselq
+               (if_then_else:SI (match_operand 1 "comparison_operator")
9193 200 dgisselq
+                       (match_operand:SI 2 "general_operand" "")
9194 202 dgisselq
+                       (match_operand:SI 3 "general_operand" "")))]
9195 102 dgisselq
+       ""
9196
+       {
9197
+       //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
9198
+       //; fprintf(stderr, "MOVSICC\n");
9199
+       //; zip_debug_rtx_pfx("- DST: ", operands[0]);
9200
+       //; zip_debug_rtx_pfx("- CMP: ", operands[1]);
9201
+       //; zip_debug_rtx_pfx("- NEW: ", operands[2]);
9202
+       //; zip_debug_rtx_pfx("- DEF: ", operands[3]);
9203
+
9204
+       if (!REG_P(operands[2]))
9205
+               operands[2] = force_reg(SImode, operands[2]);
9206
+
9207
+       if ((!REG_P(operands[3]))||(REGNO(operands[0]) != REGNO(operands[3])))
9208 202 dgisselq
+               emit_insn(gen_movsi(operands[0], operands[3]));
9209
+       operands[3] = operands[0];
9210
+
9211
+
9212
+       rtx_code        ccode = GET_CODE(operands[1]);
9213
+       rtx     cmpop0 = copy_rtx(XEXP(operands[1], 0));
9214
+       rtx     cmpop1 = copy_rtx(XEXP(operands[1], 1));
9215 102 dgisselq
+
9216 202 dgisselq
+       zip_canonicalize_comparison((int *)&ccode, &cmpop0, &cmpop1, true);
9217
+       emit_insn(gen_cmpsi(cmpop0, cmpop1));
9218
+
9219
+       operands[1] = gen_rtx_fmt_ee(ccode, VOIDmode,
9220
+                       gen_rtx_REG(CCmode, 14), const0_rtx);
9221
+       })
9222
+;
9223
+;
9224
+;
9225
+(define_expand "addsicc"
9226
+       [(set (match_operand:SI 0 "register_operand" "=r")
9227
+               (if_then_else:SI (match_operand 1 "comparison_operator")
9228
+                       (plus:SI (match_operand:SI 2 "register_operand" "0")
9229
+                               (match_operand:SI 3 "zip_opb_single_operand_p" "rO"))
9230
+                       (match_dup 2)))]
9231
+       ""
9232
+       {
9233
+               //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
9234
+               //; fprintf(stderr, "ADDSICC\n");
9235
+               //; zip_debug_rtx_pfx("- DST: ", operands[0]);
9236
+               //; zip_debug_rtx_pfx("- CMP: ", operands[1]);
9237
+               //; zip_debug_rtx_pfx("- OLD: ", operands[2]);
9238
+               //; zip_debug_rtx_pfx("- INC: ", operands[3]);
9239
+
9240
+               if (!REG_P(operands[2]))
9241
+                       operands[2] = force_reg(SImode, operands[2]);
9242
+               if (REGNO(operands[0]) != REGNO(operands[2]))
9243
+                       emit_insn(gen_movsi(operands[0], operands[2]));
9244
+               operands[2] = operands[0];
9245
+
9246
+               rtx_code        ccode = GET_CODE(operands[1]);
9247
+               rtx     cmpop0 = copy_rtx(XEXP(operands[1], 0));
9248
+               rtx     cmpop1 = copy_rtx(XEXP(operands[1], 1));
9249
+
9250
+               zip_canonicalize_comparison((int *)&ccode, &cmpop0, &cmpop1, true);
9251
+               emit_insn(gen_cmpsi(cmpop0, cmpop1));
9252
+
9253
+               operands[1] = gen_rtx_fmt_ee(ccode, VOIDmode,
9254
+                       gen_rtx_REG(CCmode, 14), const0_rtx);
9255
+       }
9256
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9257
+;
9258
+;
9259
+;
9260
+(define_expand "notsicc"
9261
+       [(set (match_operand:SI 0 "register_operand" "=r")
9262
+               (if_then_else:SI (match_operand 1 "comparison_operator")
9263
+                       (xor:SI (match_operand:SI 2 "register_operand" "0")
9264
+                               (const_int -1))
9265
+                       (match_operand:SI 3 "register_operand" "0")))]
9266
+       ""
9267
+       {
9268
+               //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
9269
+               //; fprintf(stderr, "NOTSICC\n");
9270
+               //; zip_debug_rtx_pfx("- DST: ", operands[0]);
9271
+               //; zip_debug_rtx_pfx("- CMP: ", operands[1]);
9272
+               //; zip_debug_rtx_pfx("- NOT: ", operands[2]);
9273
+               //; zip_debug_rtx_pfx("- OLD: ", operands[3]);
9274
+
9275 102 dgisselq
+
9276
+               rtx_code        ccode = GET_CODE(operands[1]);
9277 202 dgisselq
+               rtx     cmpop0 = copy_rtx(XEXP(operands[1], 0));
9278
+               rtx     cmpop1 = copy_rtx(XEXP(operands[1], 1));
9279
+
9280
+               zip_canonicalize_comparison((int *)&ccode,&cmpop0,&cmpop1,true);
9281
+               emit_insn(gen_cmpsi(cmpop0, cmpop1));
9282
+
9283
+               operands[1] = gen_rtx_fmt_ee(ccode, VOIDmode,
9284
+                       gen_rtx_REG(CCmode, 14), const0_rtx);
9285 209 dgisselq
+       }
9286 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9287
+;
9288 209 dgisselq
+;
9289 202 dgisselq
+(define_expand "negsicc"
9290
+       [(set (match_operand:SI 0 "register_operand" "+r")
9291
+               (if_then_else:SI (match_operand 1 "comparison_operator")
9292
+                       (neg:SI (match_operand:SI 2 "register_operand" "0"))
9293
+                       (match_operand:SI 3 "register_operand" "0")))]
9294
+       ""
9295
+       {
9296
+               //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
9297
+               //; fprintf(stderr, "NEGSICC\n");
9298
+               //; zip_debug_rtx_pfx("- DST: ", operands[0]);
9299
+               //; zip_debug_rtx_pfx("- CMP: ", operands[1]);
9300
+               //; zip_debug_rtx_pfx("- NOT: ", operands[2]);
9301
+
9302
+               if (!REG_P(operands[2]))
9303
+                       operands[2] = force_reg(SImode, operands[2]);
9304
+               if (REGNO(operands[0]) != REGNO(operands[3]))
9305
+                       emit_insn(gen_movsi(operands[0], operands[3]));
9306
+
9307 102 dgisselq
+               rtx_code        ccode = GET_CODE(operands[1]);
9308
+               rtx     cmpop0 = copy_rtx(XEXP(operands[1], 0));
9309 202 dgisselq
+               rtx     cmpop1 = copy_rtx(XEXP(operands[1], 1));
9310
+
9311
+               zip_canonicalize_comparison((int *)&ccode,&cmpop0,&cmpop1,true);
9312
+               emit_insn(gen_cmpsi(cmpop0, cmpop1));
9313
+
9314
+               operands[1] = gen_rtx_fmt_ee(ccode, VOIDmode,
9315
+                       gen_rtx_REG(CCmode, 14), const0_rtx);
9316
+
9317
+               if (REGNO(operands[0]) != REGNO(operands[2]))
9318
+                       emit_insn(gen_movsicc(operands[0], operands[1], operands[2], operands[0]));
9319
+       }
9320
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9321
+;
9322
+;
9323
+(define_expand "cstoresi4"
9324
+       [(set (reg:CC CC_REG) (compare:CC (match_operand:SI 2 "register_operand" "r")
9325
+               (match_operand:SI 3 "zip_opb_operand_p" "rO")))
9326
+       (set (match_operand:SI 0 "register_operand" "=r")
9327
+               (if_then_else:SI
9328
+                       (match_operator 1 "ordered_comparison_operator"
9329
+                               [(reg:CC CC_REG) (const_int 0)])
9330
+                       (const_int 1) (const_int 0)))]
9331
+       ""
9332
+       {
9333
+               //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
9334
+               //; fprintf(stderr, "CSTORESI4\n");
9335
+               //; zip_debug_rtx_pfx("- DST: ", operands[0]);
9336
+               //; zip_debug_rtx_pfx("- TST: ", operands[1]);
9337
+               //; zip_debug_rtx_pfx("- A  : ", operands[2]);
9338
+               //; zip_debug_rtx_pfx("-  -B: ", operands[3]);
9339
+
9340
+               rtx_code        ccode = GET_CODE(operands[1]);
9341 102 dgisselq
+
9342 192 dgisselq
+               zip_canonicalize_comparison((int *)&ccode,&operands[2],&operands[3],true);
9343 202 dgisselq
+               emit_insn(gen_cmpsi(operands[2], operands[3]));
9344
+               emit_insn(gen_movsi(operands[0], const0_rtx));
9345
+               switch(ccode) {
9346
+               case EQ:
9347
+                       emit_insn(gen_cmov_eq(operands[0], const1_rtx));
9348
+                       break;
9349
+               case NE:
9350
+                       emit_insn(gen_cmov_ne(operands[0], const1_rtx));
9351
+                       break;
9352
+               case LT:
9353
+                       emit_insn(gen_cmov_lt(operands[0], const1_rtx));
9354
+                       break;
9355
+               case GE:
9356
+                       emit_insn(gen_cmov_ge(operands[0], const1_rtx));
9357
+                       break;
9358
+               case LTU:
9359 192 dgisselq
+                       emit_insn(gen_cmov_ltu(operands[0], const1_rtx));
9360 202 dgisselq
+                       break;
9361
+               case GEU:
9362
+                       emit_insn(gen_cmov_geu(operands[0], const1_rtx));
9363
+                       break;
9364
+               default:
9365
+                       FAIL;
9366
+               } DONE;
9367
+       }
9368
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9369
+;
9370
+;
9371
+;
9372
+;
9373
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9374
+;;
9375
+;; Control flow instructions
9376
+;;
9377
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9378
+;
9379
+;
9380
+;
9381
+(define_expand "jump"
9382
+       [(set (pc)
9383
+               (label_ref (match_operand 0 "" "")))])
9384
+(define_insn "jump_const"
9385
+       [(set (pc)
9386
+               (match_operand:SI 0 "zip_const_address_operand_p" ""))]
9387
+       ""
9388
+       "BRA    %0"
9389 192 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9390
+(define_insn "jump_label"      ; Must be modeless, VOIDmode, not SI or any othr
9391 102 dgisselq
+       [(set (pc)      ; Otherwise it won't accept jumps to labels
9392
+               (label_ref (match_operand 0 "" "")))]
9393
+       ""
9394
+       "BRA    %0"
9395
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
9396
+;
9397
+; This is really the same thing as an indirect jump ... the big difference
9398
+; is that the zip_address_operand_p checks for an "N" type condition, not an
9399
+; "M" type condition ... a bug, but one that works for now.  (The assembler
9400
+; should be able to catch and except on it ...)
9401
+;
9402
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
9403 202 dgisselq
+(define_insn "jump_variable"
9404 127 dgisselq
+       [(set (pc)
9405
+               (match_operand:SI 0 "zip_address_operand_p" ""))]
9406 102 dgisselq
+       ""
9407
+       "JMP    %0"
9408
+       [(set_attr "ccresult" "unchanged")])
9409
+;
9410
+; Indirect jumps ... both to registers, and registers plus offsets
9411
+;
9412
+(define_insn "indirect_jump"
9413
+       [(set (pc)
9414
+               (match_operand:SI 0 "register_operand" "r"))]
9415
+       ""
9416
+       "JMP    %0"
9417
+       [(set_attr "ccresult" "unchanged")])
9418
+(define_insn "indirect_jump_mem"
9419
+       [(set (pc) (match_operand:SI 0 "zip_memory_operand_p" "o"))]
9420
+       ""
9421
+       "LW     %0,PC"
9422
+       [(set_attr "ccresult" "unchanged")])
9423
+(define_insn "indirect_jump_off"
9424
+       [(set (pc)
9425
+               (plus:SI (match_operand:SI 0 "register_operand" "r")
9426
+                       (match_operand:SI 1 "const_int_operand" "M")))]
9427
+       ""
9428
+       "JMP    %1(%0)"
9429
+       [(set_attr "ccresult" "unchanged")])
9430
+;;
9431
+; cbranchsi4
9432
+;;     Op 0 = the comparison operator (le,lt,eq,ne,gt,ge,and usgn ltu,geu,etc.)
9433
+;;     Op 1&2 the operands of the compare instruction
9434
+;;     Op 3 is the jump label
9435
+;;
9436
+;;
9437
+;;
9438
+(define_expand "cbranchsi4"
9439
+       [(set (reg:CC CC_REG) (compare:CC (match_operand:SI 1 "register_operand" "r")
9440
+               (match_operand:SI 2 "zip_opb_operand_p" "rO")))
9441 202 dgisselq
+       (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator"
9442 102 dgisselq
+                       [(reg:CC CC_REG) (const_int 0)])
9443
+                       (label_ref (match_operand 3 "" ""))
9444
+                       (pc)))]
9445
+       ""
9446
+       {
9447
+               if (true) {
9448
+               //; extern void zip_debug_rtx_pfx(const char *, const_rtx);
9449
+               //; Two branches give us no end of difficulty when implementing.
9450
+               //; Let's check for these two branch codes, and swap the
9451
+               //; comparison to simplify them.
9452
+               //; fprintf(stderr, "CBRANCH\n");
9453
+               //; zip_debug_rtx_pfx("- CMP: ", operands[0]);
9454
+               //; zip_debug_rtx_pfx("- A  : ", operands[1]);
9455
+               //; zip_debug_rtx_pfx("- B  : ", operands[2]);
9456
+               //; zip_debug_rtx_pfx("- JMP: ", operands[3]);
9457
+               //; Can we do better if we reverse some compares?
9458 202 dgisselq
+               //;
9459
+               //; We have GE, LT, LTU, and GEU conditions
9460
+               //; Figure out how to create the other conditions from
9461 102 dgisselq
+               //; these.
9462 122 dgisselq
+               if (GET_CODE(operands[0])==GTU) {
9463 102 dgisselq
+                       if (REG_P(operands[2])) {
9464
+                               //; Reverse the comparison
9465
+                               emit_insn(gen_cmpsi(operands[2],operands[1]));
9466
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
9467 125 dgisselq
+                               DONE;
9468 202 dgisselq
+                       } else if ((CONST_INT_P(operands[2]))
9469 102 dgisselq
+                               &&(INTVAL(operands[2])>-(1<<17)+2)) {
9470
+                               //; A >  B
9471
+                               //; A >= B+1
9472 122 dgisselq
+                               //; Add one to the integer constant,
9473
+                               //; And use a GEU comparison
9474
+                               emit_insn(gen_cmpsi(operands[1],
9475
+                                       GEN_INT(INTVAL(operands[2])+1)));
9476
+                               emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
9477 117 dgisselq
+                               DONE;
9478 202 dgisselq
+                       } else if ((CONST_INT_P(operands[2]))
9479
+                               &&(can_create_pseudo_p())) {
9480
+                                       rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
9481
+                                       emit_insn(gen_movsi(tmp,operands[2]));
9482
+                                       emit_insn(gen_cmpsi(tmp,operands[1]));
9483
+                                       emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
9484
+
9485
+                               DONE;
9486
+
9487
+                       }
9488
+               } else if (GET_CODE(operands[0]) == LEU) {
9489
+                       if (REG_P(operands[2])) {
9490
+                               //; Reverse the comparison
9491
+                               emit_insn(gen_cmpsi(operands[2],operands[1]));
9492
+                               emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
9493
+                               DONE;
9494
+                       } else if ((CONST_INT_P(operands[2]))
9495
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
9496 200 dgisselq
+                               //; A <= B
9497 202 dgisselq
+                               //; A <  B+1
9498
+                               //; Add one to the integer constant,
9499
+                               //; And use a GTU comparison
9500
+                               emit_insn(gen_cmpsi(operands[1],
9501
+                                       GEN_INT(INTVAL(operands[2])+1)));
9502
+                               emit_jump_insn(gen_cbranch_jmp_ltu(operands[3]));
9503
+                               DONE;
9504
+                       } else if ((CONST_INT_P(operands[2]))
9505
+                               &&(can_create_pseudo_p())) {
9506
+                                       rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
9507 200 dgisselq
+                                       emit_insn(gen_movsi(tmp,operands[2]));
9508 202 dgisselq
+                                       emit_insn(gen_cmpsi(tmp,operands[1]));
9509
+                                       emit_jump_insn(gen_cbranch_jmp_geu(operands[3]));
9510
+                               DONE;
9511
+
9512
+                       }
9513
+               } else if (GET_CODE(operands[0]) == LE) {
9514
+                       if (REG_P(operands[2])) {
9515 117 dgisselq
+                               //; Reverse the comparison
9516 202 dgisselq
+                               emit_insn(gen_cmpsi(operands[2],operands[1]));
9517
+                               emit_jump_insn(gen_cbranch_jmp_gte(operands[3]));
9518
+                               DONE;
9519
+                       } else if ((CONST_INT_P(operands[2]))
9520 122 dgisselq
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
9521 202 dgisselq
+                               //; A <= B
9522
+                               //; A <  B+1
9523 122 dgisselq
+                               //; Add one to the integer constant,
9524 202 dgisselq
+                               //; And use a GTU comparison
9525
+                               emit_insn(gen_cmpsi(operands[1],
9526
+                                       GEN_INT(INTVAL(operands[2])+1)));
9527
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
9528
+                               DONE;
9529
+                       } else if ((CONST_INT_P(operands[2]))
9530 122 dgisselq
+                               &&(can_create_pseudo_p())) {
9531 202 dgisselq
+                               rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
9532
+                                       emit_insn(gen_movsi(tmp,operands[2]));
9533
+                                       emit_insn(gen_cmpsi(tmp,operands[1]));
9534
+                                       emit_jump_insn(gen_cbranch_jmp_gte(operands[3]));
9535
+                               DONE;
9536
+
9537
+                       }
9538 122 dgisselq
+               } else if (GET_CODE(operands[0]) == GT) {
9539 202 dgisselq
+                       if (REG_P(operands[2])) {
9540 200 dgisselq
+                               //; Reverse the comparison
9541 202 dgisselq
+                               emit_insn(gen_cmpsi(operands[2],operands[1]));
9542
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
9543
+                               DONE;
9544
+                       } else if ((CONST_INT_P(operands[2]))
9545 200 dgisselq
+                               &&(INTVAL(operands[2])<(1<<17)-2)) {
9546 202 dgisselq
+                               //; A >  B
9547
+                               //; A >= B+1
9548 200 dgisselq
+                               //; Add one to the integer constant,
9549 202 dgisselq
+                               //; And use a GTU comparison
9550
+                               emit_insn(gen_cmpsi(operands[1],
9551
+                                       GEN_INT(INTVAL(operands[2])+1)));
9552
+                               emit_jump_insn(gen_cbranch_jmp_gte(operands[3]));
9553
+                               DONE;
9554
+                       } else if ((CONST_INT_P(operands[2]))
9555 200 dgisselq
+                                       &&(can_create_pseudo_p())) {
9556 202 dgisselq
+                               rtx tmp = gen_reg_rtx(GET_MODE(operands[1]));
9557
+                               emit_insn(gen_movsi(tmp,operands[2]));
9558
+                               emit_insn(gen_cmpsi(tmp,operands[1]));
9559
+                               emit_jump_insn(gen_cbranch_jmp_lt(operands[3]));
9560
+
9561
+                               DONE;
9562
+                       }
9563 200 dgisselq
+               }
9564 202 dgisselq
+       }})
9565 102 dgisselq
+(define_insn "cbranch_jmp_eq"
9566 202 dgisselq
+       [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
9567
+                (label_ref (match_operand 0 "" ""))
9568
+                (pc)))]
9569
+       ""
9570 122 dgisselq
+       "BZ\t%0"
9571 202 dgisselq
+       [(set_attr "predicable" "no")
9572
+               (set_attr "ccresult" "unchanged")])
9573 122 dgisselq
+(define_insn "cbranch_jmp_neq"
9574 202 dgisselq
+       [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0))
9575
+                (label_ref (match_operand 0 "" ""))
9576
+                (pc)))]
9577
+       ""
9578
+       "BNZ\t%0"
9579
+       [(set_attr "predicable" "no")
9580
+               (set_attr "ccresult" "unchanged")])
9581 122 dgisselq
+(define_insn "cbranch_jmp_lt"
9582
+       [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
9583 202 dgisselq
+                (label_ref (match_operand 0 "" ""))
9584
+                (pc)))]
9585 102 dgisselq
+       ""
9586 122 dgisselq
+       "BLT\t%0"
9587 102 dgisselq
+       [(set_attr "predicable" "no")
9588
+               (set_attr "ccresult" "unchanged")])
9589
+(define_insn "cbranch_jmp_le"
9590
+       [(set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
9591
+                (label_ref (match_operand 0 "" ""))
9592
+                (pc)))]
9593
+       ""
9594 122 dgisselq
+       "BLT\t%0\n\tBZ\t%0"
9595 102 dgisselq
+       [(set_attr "predicable" "no")
9596
+               (set_attr "ccresult" "unchanged")])
9597
+(define_insn "cbranch_jmp_gt"
9598
+       [(set (pc) (if_then_else (gt (reg:CC CC_REG) (const_int 0))
9599
+                (label_ref (match_operand 0 "" ""))
9600
+                (pc)))]
9601
+       ""
9602 122 dgisselq
+       "BZ\t.Lgt%=\n\tBGE\t%0\n\t.Lgt%=:"
9603 102 dgisselq
+       [(set_attr "predicable" "no")
9604
+               (set_attr "ccresult" "unchanged")])
9605
+(define_insn "cbranch_jmp_gte"
9606
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
9607
+                (label_ref (match_operand 0 "" ""))
9608
+                (pc)))]
9609
+       ""
9610 122 dgisselq
+       "BGE\t%0"
9611 102 dgisselq
+       [(set_attr "predicable" "no")
9612
+               (set_attr "ccresult" "unchanged")])
9613
+(define_insn "cbranch_jmp_ltu"
9614 202 dgisselq
+       [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
9615 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9616
+                (pc)))]
9617
+       ""
9618 122 dgisselq
+       "BC\t%0"
9619 102 dgisselq
+       [(set_attr "predicable" "no")
9620
+               (set_attr "ccresult" "unchanged")])
9621
+(define_insn "cbranch_jmp_gtu"
9622 202 dgisselq
+       [(set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
9623 102 dgisselq
+                (label_ref (match_operand 0 "" ""))
9624
+                (pc)))]
9625 202 dgisselq
+       ""
9626 122 dgisselq
+       ;// We could flip the condition code, and then be able to jump.
9627 102 dgisselq
+       ;// The problem is that doing this adjusts the condition code, and
9628
+       ;// we aren't allowed to do that here.
9629 202 dgisselq
+       ;//
9630 102 dgisselq
+       ;// The problem here is the equals.  What do you do if A=B?  Our new
9631
+       ;// condition tests for A>=B, not A>B.  So ... how do you get rid of
9632
+       ;// the equals?  We do so here by branching around. (sigh)
9633
+       "BZ\t.Lgtu%=\n\tBNC\t%0\n.Lgtu%=:"
9634 122 dgisselq
+       [(set_attr "predicable" "no")
9635 102 dgisselq
+               (set_attr "ccresult" "unknown")])
9636
+(define_insn "cbranch_jmp_leu"
9637
+       [(set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
9638
+                (label_ref (match_operand 0 "" ""))
9639
+                (pc)))]
9640
+       ""      ; Need to check for both LTU (i.e. C) and Z
9641 202 dgisselq
+       "BC\t%0
9642 122 dgisselq
+       BZ\t%0"
9643 102 dgisselq
+       [(set_attr "predicable" "no")
9644 200 dgisselq
+               (set_attr "ccresult" "unchanged")])
9645 202 dgisselq
+(define_insn "cbranch_jmp_geu"
9646 200 dgisselq
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
9647
+                (label_ref (match_operand 0 "" ""))
9648
+                (pc)))]
9649
+       ""
9650
+       "BNC\t%0"
9651
+       [(set_attr "predicable" "no")
9652
+               (set_attr "ccresult" "unchanged")])
9653
+;
9654
+;
9655
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9656 102 dgisselq
+;;
9657 122 dgisselq
+;; Looping constructs
9658 102 dgisselq
+;;
9659
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9660
+;
9661
+;
9662
+;
9663
+(define_insn "decrement_and_branch_until_zero"
9664
+       [(set (pc) (if_then_else
9665 202 dgisselq
+               (ge (plus:SI (match_operand:SI 0 "register_operand" "+r,Q")
9666 122 dgisselq
+                       (const_int -1)) (const_int 0))
9667 102 dgisselq
+               (label_ref (match_operand 1 "" ""))
9668 200 dgisselq
+               (pc)))
9669 202 dgisselq
+       (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
9670 200 dgisselq
+       ;(set (reg:CC CC_REG)
9671
+               ;(compare:CC (minus:SI (match_dup 0) (const_int 1))
9672
+                       ;(const_int 0)))
9673 102 dgisselq
+       (clobber (match_scratch:SI 2 "=r,r"))
9674
+       (clobber (reg:CC CC_REG))]
9675
+       ""
9676
+       {
9677 191 dgisselq
+               if (MEM_P(operands[0])) {
9678
+                       //; We could also go searching for dead regs if
9679
+                       //; necessary
9680
+                       return "LW %0,%2"
9681
+                               "\t; decrement_and_branch_until_zero(MEM)\n"
9682
+                               "\tADD\t-1,%2\t\n"
9683
+                               "\tSW %2,%0\n"
9684 202 dgisselq
+                               "\tBLT\t.Ldec%=\n"
9685
+                               "\tBRA\t%1\n"
9686
+                               ".Ldec%=:";
9687
+               }
9688
+               return "ADD\t-1,%0\t; decrement_and_branch_until_zero (REG)\n"
9689 191 dgisselq
+                       "\tBLT\t.Ldec%=\n"
9690
+                       "\tBRA\t%1\n"
9691
+                       ".Ldec%=:";
9692
+       }
9693 202 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9694 191 dgisselq
+;
9695
+;
9696 202 dgisselq
+; Requires TARGET_CAN_USE_DOLOOP_P to be set appropriately in order to use
9697
+;
9698
+;
9699
+;(define_insn "doloop_end"
9700
+       ;[(set (pc)
9701
+               ;(if_then_else
9702
+                       ;(ne (plus:SI (match_operand:SI 0 "register_operand" "+r")
9703
+                               ;;(const_int -1)) (const_int 0))
9704
+                       ;(label_ref (match_operand 1 "" ""))
9705
+                       ;(pc)))
9706
+       ;(set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
9707
+       ;; (set (reg:CC CC_REG)
9708
+               ;; (compare:CC (minus:SI (match_dup 0) (const_int 1))
9709
+                       ;; (const_int 0)))
9710
+       ;(clobber (reg:CC CC_REG))]
9711
+       ;"(reload_completed)"
9712
+       ;"ADD\t-1,%0\t; doloop_end\n\tBZ\t.Lloop%=\n\tBRA\t%1\n.Lloop%=:"
9713 191 dgisselq
+       ;[(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9714
+;
9715
+; Since we have a doloop_end, we must also have a doloop_begin.  Since the
9716 202 dgisselq
+; ZipCPU has no special begin looping instruction, we'll simply define this
9717 191 dgisselq
+; as a null instruction.
9718 202 dgisselq
+;
9719
+; (define_expand "doloop_begin" [(const_int 0)] "(0)")
9720
+;
9721
+;
9722
+;
9723
+;
9724
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9725
+;;
9726
+;; Subroutine call
9727
+;;
9728
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9729
+;
9730
+;
9731
+; There are two types of calls: "call" and "call_value".
9732
+;
9733
+; Each of these types of calls are then expanded into one of:
9734
+;
9735 191 dgisselq
+;      _const          - A call to a constant address, such as a symbol
9736
+;                      reference or a fixed location
9737
+;
9738
+;      _label          - This should be the same as _const, except that for
9739 202 dgisselq
+;                      some reason the RTL and matching rules are separate.
9740 191 dgisselq
+;                      Hence we have a separate rule for this.
9741
+;
9742
+;      _mem            - The memory address we wish to jump to is stored in
9743 202 dgisselq
+;                      memory somewhere, and we have only a pointer.  In this
9744 191 dgisselq
+;                      case, we load that pointer straight to the PC and go.
9745
+;
9746 102 dgisselq
+;      _var            - The address to jump to is given as an offset to a
9747
+;                      register, such as X+R3.  This is an indirect jump.
9748
+;                      Although we support it, it does require different RTL
9749
+;                      code.
9750
+;
9751
+(define_expand "call"
9752
+       [(call (match_operand 0 "" "")
9753
+               (match_operand 1 "" ""))]
9754
+       ""
9755
+       {
9756
+               if (MEM_P(operands[0])) {
9757
+                       ;// extern void zip_debug_rtx(const_rtx);
9758
+                       ;//
9759
+                       ;// fprintf(stderr, "CALL: ");
9760
+                       ;// zip_debug_rtx(operands[0]);
9761
+                       ;//
9762
+                       ;//
9763
+                       ;// This should always be the case
9764
+                       rtx addr = XEXP(operands[0],0);
9765
+                       if (zip_const_address_operand_p(addr, SImode)) {
9766
+                               //; fprintf(stderr, "Generating gen_void_call_const()\n");
9767
+                               emit_call_insn(gen_void_call_const(addr,
9768
+                                               operands[1]));
9769
+                       } else if ((MEM_P(addr))&&(zip_address_operand(
9770
+                                                       XEXP(addr,0)))) {
9771
+                               fprintf(stderr, "ERR: ZIP.MD::CALL INDIRECT\n");
9772
+                               emit_call_insn(gen_void_call_mem(XEXP(addr,0),
9773
+                                                                operands[1]));
9774
+                               gcc_assert(0);
9775
+                       } else {
9776
+                               emit_call_insn(gen_void_call_var(operands[0],
9777 202 dgisselq
+                                                                operands[1]));
9778
+                       }
9779
+                       DONE;
9780
+               } else FAIL;
9781
+       })
9782
+;
9783
+(define_expand "sibcall"
9784 102 dgisselq
+       [(call (mem:SI (match_operand 0 "zip_const_address_operand_p" ""))
9785
+               (match_operand 1 "" ""))
9786 122 dgisselq
+       (use (match_operand 2 "" ""))
9787 102 dgisselq
+       (use (reg:SI RTN_REG))
9788
+       (simple_return)]
9789
+       ""
9790
+       {
9791 202 dgisselq
+               if (MEM_P(operands[0])) {
9792 102 dgisselq
+                       ;// extern void zip_debug_rtx(const_rtx);
9793
+                       ;//
9794 202 dgisselq
+                       ;// fprintf(stderr, "CALL: ");
9795 102 dgisselq
+                       ;// zip_debug_rtx(operands[0]);
9796 202 dgisselq
+                       ;//
9797 102 dgisselq
+                       ;//
9798
+                       ;// This should always be the case
9799
+                       rtx addr = XEXP(operands[0],0);
9800 202 dgisselq
+                       if (zip_const_address_operand_p(addr, SImode)) {
9801 102 dgisselq
+                               //; fprintf(stderr, "Generating gen_void_call_const()\n");
9802
+                               emit_call_insn(gen_void_sibcall_const(addr,
9803 191 dgisselq
+                                               operands[1]));
9804
+                       } else if ((MEM_P(addr))&&(zip_address_operand(
9805
+                                                       XEXP(addr,0)))) {
9806
+                               fprintf(stderr, "ERR: ZIP.MD::SIBCALL INDIRECT\n");
9807
+                               emit_call_insn(gen_void_sibcall_mem(XEXP(addr,0),
9808
+                                                                operands[1]));
9809
+                               gcc_assert(0);
9810
+                       } else {
9811
+                               emit_call_insn(gen_void_sibcall_var(operands[0],
9812 202 dgisselq
+                                                                operands[1]));
9813
+                       }
9814
+                       DONE;
9815
+               } else FAIL;
9816
+       }) ; "BAR\t%0\n"
9817
+;
9818
+(define_insn "void_sibcall_const"
9819 191 dgisselq
+       [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
9820
+                       (match_operand 1 "const_int_operand" "n"))
9821
+               (use (reg:SI RTN_REG))
9822
+               (clobber (reg:CC CC_REG))
9823
+               (simple_return)]
9824
+       ""
9825
+       "BRA\t%0"
9826 202 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9827 191 dgisselq
+(define_insn "void_sibcall_mem"
9828
+       [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
9829 202 dgisselq
+                       (match_operand 1 "const_int_operand" "n"))
9830 191 dgisselq
+               (use (reg:SI RTN_REG))
9831 202 dgisselq
+               (clobber (reg:CC CC_REG))
9832 191 dgisselq
+               (simple_return)]
9833
+       ""
9834
+       "LW\t%0,PC"
9835 202 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9836 191 dgisselq
+;
9837 102 dgisselq
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
9838 191 dgisselq
+(define_insn "void_sibcall_var"
9839
+       [(call (match_operand:SI 0 "zip_memory_operand_p" "")
9840
+                       (match_operand 1 "const_int_operand" "n"))
9841
+               (use (reg:SI RTN_REG))
9842
+               (clobber (reg:CC CC_REG))
9843
+               (simple_return)]
9844
+       ""
9845
+       "JMP\t%0"
9846
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9847
+;
9848
+(define_expand "sibcall_value"
9849
+       [(set (match_operand 0 "register_operand" "")
9850
+               (call (mem:SI
9851
+                       (match_operand 1 "zip_const_address_operand_p" ""))
9852
+               (match_operand 2 "" "")))
9853
+       (use (match_operand 3 "" ""))
9854 202 dgisselq
+       (use (reg:SI RTN_REG))
9855 191 dgisselq
+       (clobber (reg:CC CC_REG))
9856 102 dgisselq
+       (simple_return)]
9857 191 dgisselq
+       ""
9858
+       {
9859 202 dgisselq
+               if (MEM_P(operands[1])) {
9860 191 dgisselq
+                       ;// extern void zip_debug_rtx(const_rtx);
9861
+                       ;//
9862
+                       ;// fprintf(stderr, "SIBCALL/V: ");
9863
+                       ;// zip_debug_rtx(operands[1]);
9864
+                       ;//
9865
+                       ;//
9866
+                       ;// This should always be the case
9867
+                       rtx addr = XEXP(operands[1],0);
9868
+                       if (zip_const_address_operand_p(addr, SImode)) {
9869
+                               emit_call_insn(gen_reg_sibcall_const(operands[0], addr, operands[2]));
9870
+                       } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
9871
+                               fprintf(stderr, "ERR: ZIP.MD::SIBCALL-VALUE() INDIRECT\n");
9872
+                               emit_call_insn(gen_reg_sibcall_mem(operands[0], XEXP(addr,0), operands[2]));
9873
+                               gcc_assert(0);
9874
+                       } else {
9875
+                               emit_call_insn(gen_reg_sibcall_var(operands[0], operands[1], operands[2]));
9876
+                       }
9877
+                       DONE;
9878
+               } else FAIL;
9879
+       })
9880 202 dgisselq
+;
9881
+;
9882
+;
9883
+;
9884
+; How do we want to do this better?
9885
+;      Replace the RTL w/
9886
+;              return_label= gen_label_rtx();
9887 191 dgisselq
+;              emit_movsi(gen_rtx_REG(zip_R0),plus_constant(
9888
+;                      gen_rtx_REG(zip_PC),return_label));
9889 202 dgisselq
+;              emit_jump(label_rtx(
9890 191 dgisselq
+;
9891 202 dgisselq
+;              emit_label(return_label);
9892
+;
9893
+; The problem is: we can't!  GCC distinguishes between jumps and calls when
9894 191 dgisselq
+; optimizing, and it doesn't see the need to keep the label around.  Thus, the
9895 202 dgisselq
+; label gets removed and the call gets lost.  Hence we do it this way (below).
9896 191 dgisselq
+; I'll probably bastardize a means of getting a new codelabel that GCC doesn't
9897
+; recognize as such, but for now we'll use .Lcall# as our label.
9898 202 dgisselq
+;
9899 191 dgisselq
+(define_insn "void_call_const"
9900
+       [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p" ""))
9901
+                       (match_operand 1 "const_int_operand" "n"))
9902
+               (clobber (reg:SI RTN_REG))
9903
+               (clobber (reg:CC CC_REG))]
9904 102 dgisselq
+       ""
9905
+       "JSR\t%0"
9906
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9907
+(define_insn "void_call_mem"
9908
+       [(call (mem:SI (match_operand:SI 0 "zip_memory_operand_p" "Q"))
9909
+                       (match_operand 1 "const_int_operand" "n"))
9910
+               (clobber (reg:SI RTN_REG))
9911
+               (clobber (reg:CC CC_REG))]
9912
+       ""
9913
+       "MOV    .Lcall%=(PC),R0\;LW\t%0,PC\n.Lcall%=:"
9914
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9915
+;
9916
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
9917
+(define_insn "void_call_var"
9918
+       [(call (match_operand:SI 0 "zip_memory_operand_p" "")
9919
+                       (match_operand 1 "const_int_operand" "n"))
9920 122 dgisselq
+               (clobber (reg:SI RTN_REG))
9921 111 dgisselq
+               (clobber (reg:CC CC_REG))]
9922 122 dgisselq
+       ""
9923
+       {
9924 102 dgisselq
+               if (REG_P(operands[0]))
9925 202 dgisselq
+                       return "JSR\t(%0)";
9926 102 dgisselq
+               else
9927
+                       return "JSR\t%0";
9928 122 dgisselq
+       }
9929 111 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9930 122 dgisselq
+;
9931
+;
9932 102 dgisselq
+(define_expand "call_value"
9933 202 dgisselq
+       [(parallel [(set (match_operand 0 "register_operand")
9934 102 dgisselq
+               (call (match_operand:SI 1 "" "")
9935
+                       (match_operand 2 "const_int_operand" "n")))
9936
+       (clobber (reg:SI RTN_REG))
9937
+       (clobber (reg:CC CC_REG))])]
9938 202 dgisselq
+       ""
9939 111 dgisselq
+       {
9940 122 dgisselq
+               if (MEM_P(operands[1])) {
9941
+                       ;// extern void zip_debug_rtx(const_rtx);
9942 102 dgisselq
+                       ;//
9943 202 dgisselq
+                       ;// fprintf(stderr, "CALL/V: ");
9944
+                       ;// zip_debug_rtx(operands[1]);
9945
+                       ;//
9946
+                       ;//
9947
+                       //; This should always be the case
9948
+                       rtx addr = XEXP(operands[1],0);
9949 102 dgisselq
+                       if (zip_const_address_operand_p(addr, SImode)) {
9950 191 dgisselq
+                               //; fprintf(stderr, "Generating gen_reg_call_const()\n");
9951
+                               emit_call_insn(gen_reg_call_const(operands[0], addr, operands[2]));
9952 102 dgisselq
+                       } else if ((MEM_P(addr))&&(zip_address_operand(XEXP(addr,0)))) {
9953 202 dgisselq
+                               fprintf(stderr, "ERR: ZIP.MD::CALL-VALUE() INDIRECT\n");
9954 102 dgisselq
+                               emit_call_insn(gen_reg_call_mem(operands[0], XEXP(addr,0), operands[2]));
9955 111 dgisselq
+                               gcc_assert(0);
9956 202 dgisselq
+                       } else {
9957 122 dgisselq
+                               //; fprintf(stderr, "ZIP.MD::CALL-VALUE() INDIRECT\n");
9958 102 dgisselq
+                               emit_call_insn(gen_reg_call_var(operands[0], operands[1], operands[2]));
9959
+                       }
9960
+                       DONE;
9961 202 dgisselq
+               } else FAIL;
9962
+       })
9963
+(define_insn "reg_call_const"
9964
+       [(set (match_operand 0 "register_operand" "")
9965
+               (call (mem:SI (match_operand:SI 1 "zip_const_address_operand_p" ""))
9966
+                       (match_operand 2 "const_int_operand" "n")))
9967 122 dgisselq
+               (clobber (reg:SI RTN_REG))
9968 102 dgisselq
+               (clobber (reg:CC CC_REG))]
9969
+       ""
9970 122 dgisselq
+       "JSR\t%1"
9971 202 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9972 102 dgisselq
+(define_insn "reg_call_mem"
9973 202 dgisselq
+       [(set (match_operand 0 "register_operand" "")
9974
+               (call (mem:SI (match_operand:SI 1 "zip_memory_operand_p" "Q"))
9975
+                       (match_operand 2 "const_int_operand" "n")))
9976 102 dgisselq
+               (clobber (reg:SI RTN_REG))
9977 122 dgisselq
+               (clobber (reg:CC CC_REG))]
9978 202 dgisselq
+       ""
9979 102 dgisselq
+       "MOV    .Lcall%=(PC),R0\t; CALL MEM (untested)\n\tLW\t%1,PC\n.Lcall%=:"
9980
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
9981 202 dgisselq
+;
9982 102 dgisselq
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
9983
+(define_insn "reg_call_var"
9984 202 dgisselq
+       [(set (match_operand 0 "register_operand" "")
9985
+               (call (match_operand:SI 1 "zip_memory_operand_p" "")
9986
+                       (match_operand 2 "const_int_operand" "n")))
9987 122 dgisselq
+               (clobber (reg:SI RTN_REG))
9988
+               (clobber (reg:CC CC_REG))]
9989 102 dgisselq
+       ""
9990 202 dgisselq
+       {
9991 102 dgisselq
+               ;// extern void zip_debug_rtx(const_rtx);
9992
+
9993 202 dgisselq
+               ;// fprintf(stderr, "CALL-V/REG: ");
9994
+               ;// zip_debug_rtx(operands[0]);
9995
+
9996 122 dgisselq
+               if (REG_P(operands[1]))
9997
+                       return "JSR\t(%1)";
9998 102 dgisselq
+               else
9999 202 dgisselq
+                       return "JSR\t%1";
10000 102 dgisselq
+       }
10001 111 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
10002 102 dgisselq
+;
10003
+;
10004 202 dgisselq
+;
10005
+(define_insn "reg_sibcall_const"
10006
+       [(set (match_operand 0 "register_operand" "")
10007 122 dgisselq
+               (call (mem:SI (match_operand:SI 1 "zip_const_address_operand_p" ""))
10008
+                       (match_operand 2 "const_int_operand" "n")))
10009 102 dgisselq
+               (use (reg:SI RTN_REG))
10010 202 dgisselq
+               (clobber (reg:CC CC_REG))
10011
+               (simple_return)]
10012
+       ""
10013
+       "BRA\t%1"
10014
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
10015
+(define_insn "reg_sibcall_mem"
10016
+       [(set (match_operand 0 "register_operand" "")
10017
+               (call (mem:SI (match_operand:SI 1 "zip_memory_operand_p" "Q"))
10018
+                       (match_operand 2 "const_int_operand" "n")))
10019
+               (use (reg:SI RTN_REG))
10020
+               (clobber (reg:CC CC_REG))
10021 102 dgisselq
+               (simple_return)]
10022
+       ""
10023
+       "LW\t%1,PC"
10024
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
10025 191 dgisselq
+;
10026 202 dgisselq
+; #warning "This predicate is appropriate for non-moves, but not for JMPs"
10027
+(define_insn "reg_sibcall_var"
10028
+       [(set (match_operand 0 "register_operand" "")
10029 191 dgisselq
+               (call (match_operand:SI 1 "zip_memory_operand_p" "")
10030
+                       (match_operand 2 "const_int_operand" "n")))
10031
+               (use (reg:SI RTN_REG))
10032
+               (clobber (reg:CC CC_REG))
10033 202 dgisselq
+               (simple_return)]
10034 191 dgisselq
+       ""
10035
+       {
10036 202 dgisselq
+               if (REG_P(operands[1]))
10037
+                       return "JMP\t(%1); REG_SIBCALL_VAR";
10038
+               else
10039 191 dgisselq
+                       return "JMP\t%1";
10040
+       }
10041
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
10042
+;
10043 202 dgisselq
+;
10044 191 dgisselq
+;
10045
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10046
+;;
10047
+;; Frame manipulation RTX
10048 202 dgisselq
+;;
10049
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10050
+;
10051 191 dgisselq
+;
10052
+;
10053
+(define_expand "prologue"
10054
+       [(const_int 0)]
10055 202 dgisselq
+       ""
10056
+       "{ zip_expand_prologue(); DONE; }")
10057
+(define_expand "sibcall_epilogue"
10058
+       [(return)]
10059
+       ""
10060
+       "{ zip_sibcall_epilogue(); DONE; }")
10061 191 dgisselq
+(define_expand "epilogue"
10062
+       [(return)]
10063
+       ""
10064
+       "{ zip_expand_epilogue(); DONE; }")
10065 102 dgisselq
+(define_expand "return" ; In order to use the function predicate, this *must*
10066
+       [(return)]      ; be a define_expand
10067
+       "zip_use_return_insn()")
10068
+       ; "JMP  R0"
10069
+       ; [(set_attr "ccresult" "unchanged")])
10070
+(define_insn "*return" ; A "*" -- means it cannot be called from C
10071
+       [(return)]
10072
+       ""
10073
+       "RETN"
10074
+       [(set_attr "ccresult" "unchanged")])
10075
+(define_insn "simple_return"   ; A "*" -- means it cannot be called from C
10076
+       [(simple_return)]
10077 191 dgisselq
+       ""
10078
+       "RETN"
10079
+       [(set_attr "ccresult" "unchanged")])
10080
+(define_insn "return_if_eq"
10081 102 dgisselq
+       [(set (pc) (if_then_else (eq (reg:CC CC_REG) (const_int 0))
10082
+                       (return) (pc)))]
10083
+       "zip_use_return_insn()"
10084
+       "RETN.Z"
10085
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10086
+(define_insn "return_if_ne"
10087
+       [(set (pc) (if_then_else (ne (reg:CC CC_REG) (const_int 0))
10088
+                       (return) (pc)))]
10089
+       "zip_use_return_insn()"
10090
+       "RETN.NZ"
10091
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10092
+(define_insn "return_if_lt"
10093 200 dgisselq
+       [(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
10094 102 dgisselq
+                       (return) (pc)))]
10095
+       "zip_use_return_insn()"
10096
+       "RETN.LT"
10097
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10098 200 dgisselq
+(define_insn "return_if_gte"
10099 102 dgisselq
+       [(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
10100 191 dgisselq
+                       (return) (pc)))]
10101
+       "(zip_use_return_insn())"
10102
+       "RETN.GTE"
10103
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10104 200 dgisselq
+(define_insn "return_if_ltu"
10105 191 dgisselq
+       [(set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
10106
+                       (return) (pc)))]
10107
+       "zip_use_return_insn()"
10108
+       "RETN.C"
10109
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10110 200 dgisselq
+(define_insn "return_if_geu"
10111 191 dgisselq
+       [(set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
10112
+                       (return) (pc)))]
10113
+       "(zip_use_return_insn())"
10114
+       "RETN.NC"
10115
+       [(set_attr "ccresult" "unchanged") (set_attr "predicable" "no")])
10116 200 dgisselq
+;
10117 191 dgisselq
+;
10118
+;
10119
+;;;;;;;;;;;;;;;;;;;;;;;;;;
10120
+;;
10121 202 dgisselq
+;; Zip Builtin Functions
10122 200 dgisselq
+;;
10123 191 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;
10124
+;
10125
+;
10126
+;
10127
+(define_insn "zip_rtu"
10128 200 dgisselq
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_RTU)
10129 191 dgisselq
+       (clobber (reg:CC CC_REG))]
10130 200 dgisselq
+       "(!ZIP_USER)"
10131
+       "RTU"
10132
+       [(set_attr "ccresult" "unknown")])
10133 202 dgisselq
+(define_insn "zip_busy"
10134 200 dgisselq
+       [(set (pc) (minus:SI (pc) (const_int 1)))]
10135
+       ""
10136 102 dgisselq
+       "BUSY"
10137
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
10138
+(define_insn "zip_halt" ; Needs to be unspec_volatile, or optimizer will opt out
10139
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_HALT)
10140
+       (clobber (reg:CC CC_REG))]
10141
+       "(!ZIP_USER)"
10142
+       "HALT"
10143
+       [(set_attr "ccresult" "unknown")])
10144
+(define_insn "zip_idle"
10145
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_IDLE)
10146
+       (clobber (reg:CC CC_REG))]
10147
+       ""
10148
+       "WAIT"
10149 122 dgisselq
+       [(set_attr "ccresult" "unknown")])
10150 102 dgisselq
+(define_insn "zip_syscall"
10151
+       [(unspec_volatile [(reg:SI CC_REG)] UNSPEC_SYSCALL)]
10152
+       ""
10153 171 dgisselq
+       "CLR\tCC"
10154
+       [(set_attr "ccresult" "unknown")])
10155
+;
10156
+;
10157
+; Operator "save_context"
10158 102 dgisselq
+;
10159
+;      Okay, so we're not really reading and writing operand 0, %0, however
10160 122 dgisselq
+;      if we don't list it as a "+r" register, the compiler may allocate it
10161 102 dgisselq
+;      among the other registers, thus we clobber it in the middle of the
10162
+;      operation before the task is complete.
10163
+;
10164
+(define_insn "zip_save_context"
10165
+       [(unspec_volatile
10166 122 dgisselq
+                       [ (match_operand:SI 0 "register_operand" "+r") ]
10167 102 dgisselq
+                       UNSPEC_SAVE_CONTEXT)
10168
+               (clobber (match_scratch:SI 1 "=r"))
10169
+               (clobber (match_scratch:SI 2 "=r"))
10170
+               (clobber (match_scratch:SI 3 "=r"))
10171
+               (clobber (match_scratch:SI 4 "=r"))]
10172
+       "(!ZIP_USER)"
10173
+       "MOV\tuR0,%1
10174
+       MOV\tuR1,%2
10175
+       MOV\tuR2,%3
10176
+       MOV\tuR3,%4
10177
+       SW\t%1,%0
10178
+       SW\t%2,4(%0)
10179 117 dgisselq
+       SW\t%3,8(%0)
10180
+       SW\t%4,12(%0)
10181
+       MOV\tuR4,%1
10182
+       MOV\tuR5,%2
10183 102 dgisselq
+       MOV\tuR6,%3
10184
+       MOV\tuR7,%4
10185 117 dgisselq
+       SW\t%1,16(%0)
10186
+       SW\t%2,20(%0)
10187 102 dgisselq
+       SW\t%3,24(%0)
10188
+       SW\t%4,28(%0)
10189
+       MOV\tuR8,%1
10190
+       MOV\tuR9,%2
10191 117 dgisselq
+       MOV\tuR10,%3
10192 102 dgisselq
+       MOV\tuR11,%4
10193
+       SW\t%1,32(%0)
10194
+       SW\t%2,36(%0)
10195
+       SW\t%3,40(%0)
10196
+       SW\t%4,44(%0)
10197 202 dgisselq
+       MOV\tuR12,%1
10198
+       MOV\tuSP,%2
10199
+       MOV\tuCC,%3
10200
+       MOV\tuPC,%4
10201 102 dgisselq
+       SW\t%1,48(%0)
10202
+       SW\t%2,52(%0)
10203
+       SW\t%3,56(%0)
10204
+       SW\t%4,60(%0)"
10205 202 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10206
+;
10207
+; See the comment above about why operand 0, %0, *must* be a "+r" operand,
10208
+; even though we don't really read (or change) its value throughout this
10209 102 dgisselq
+; operation.
10210
+;
10211
+(define_insn "zip_restore_context"
10212
+       [(unspec_volatile [
10213 202 dgisselq
+               (match_operand:SI 0 "register_operand" "+r")] UNSPEC_RESTORE_CONTEXT)
10214
+       (clobber (match_scratch:SI 1 "=r"))
10215
+       (clobber (match_scratch:SI 2 "=r"))
10216
+       (clobber (match_scratch:SI 3 "=r"))
10217 102 dgisselq
+       (clobber (match_scratch:SI 4 "=r"))]
10218
+       "(!ZIP_USER)"
10219
+       "LW\t0(%0),%1
10220
+       LW\t4(%0),%2
10221 202 dgisselq
+       LW\t8(%0),%3
10222
+       LW\t12(%0),%4
10223
+       MOV\t%1,uR0
10224
+       MOV\t%2,uR1
10225 122 dgisselq
+       MOV\t%3,uR2
10226 117 dgisselq
+       MOV\t%4,uR3
10227
+       LW\t16(%0),%1
10228
+       LW\t20(%0),%2
10229
+       LW\t24(%0),%3
10230
+       LW\t28(%0),%4
10231 102 dgisselq
+       MOV\t%1,uR4
10232
+       MOV\t%2,uR5
10233 117 dgisselq
+       MOV\t%3,uR6
10234 102 dgisselq
+       MOV\t%4,uR7
10235
+       LW\t32(%0),%1
10236
+       LW\t36(%0),%2
10237 117 dgisselq
+       LW\t40(%0),%3
10238 102 dgisselq
+       LW\t44(%0),%4
10239 202 dgisselq
+       MOV\t%1,uR8
10240
+       MOV\t%2,uR9
10241
+       MOV\t%3,uR10
10242
+       MOV\t%4,uR11
10243 102 dgisselq
+       LW\t48(%0),%1
10244
+       LW\t52(%0),%2
10245
+       LW\t56(%0),%3
10246
+       LW\t60(%0),%4
10247 202 dgisselq
+       MOV\t%1,uR12
10248
+       MOV\t%2,uSP
10249
+       MOV\t%3,uCC
10250
+       MOV\t%4,uPC"
10251 102 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10252
+(define_insn "zip_bitrev"
10253
+       [(set (match_operand:SI 0 "register_operand" "=r")
10254
+               (unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_BITREV))
10255 202 dgisselq
+       ]
10256
+       ""
10257
+       "BREV\t%1,%0"
10258
+       [(set_attr "ccresult" "unchanged")])
10259 102 dgisselq
+(define_insn "zip_cc"
10260
+       [(set (match_operand:SI 0 "register_operand" "=r")
10261
+               (unspec:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
10262
+       ""
10263 202 dgisselq
+       "MOV\tCC,%0"
10264
+       [(set_attr "ccresult" "unchanged")])
10265
+(define_insn "zip_ucc"
10266
+       [(set (match_operand:SI 0 "register_operand" "=r")
10267 102 dgisselq
+               (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETUCC))]
10268
+       ""
10269
+       "MOV\tuCC,%0"
10270
+       [(set_attr "ccresult" "unchanged")])
10271 122 dgisselq
+(define_insn "zip_cc_sto"
10272 102 dgisselq
+       [(set (mem:SI (match_operand:SI 0 "register_operand" "r"))
10273
+               (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
10274
+       ""
10275
+       "SW\tCC,(%0)"
10276
+       [(set_attr "ccresult" "unchanged")])
10277
+(define_insn "zip_cc_sto_off"
10278 122 dgisselq
+       [(set (mem:SI (plus:SI
10279 102 dgisselq
+                       (match_operand:SI 0 "register_operand" "r")
10280
+                       (match_operand:SI 1 "const_int_operand" "N")))
10281
+               (unspec_volatile:SI [(reg:SI CC_REG)] UNSPEC_GETCC))]
10282
+       ""
10283
+       "SW\tCC,%1(%0)"
10284
+       [(set_attr "ccresult" "unchanged")])
10285 117 dgisselq
+(define_insn "ldilo"
10286
+       [(set (match_operand:SI 0 "register_operand" "=r")
10287
+               (unspec:SI [(match_operand:SI 1 "immediate_operand" "")] UNSPEC_LDILO))]
10288
+       ""
10289
+       "LDILO  %1,%0"
10290
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
10291 111 dgisselq
+
10292
+;
10293 117 dgisselq
+;
10294 111 dgisselq
+; Missing still: zip_break(idno)
10295 202 dgisselq
+; Would also be nice to have a zip_reg builtin, allowing us to read or write
10296 111 dgisselq
+; a register, as in zip_reg(5)=40;.  Not sure what this means, though, when the
10297
+; number placed into this is not constant, or how to specify that it must *only*
10298
+; be constant.  Thats actually the problem with both proposals, zip_break(id)
10299
+; and zip_reg(regno)--both depend upon a compile time constant to work.
10300
+;
10301 117 dgisselq
+;
10302 111 dgisselq
+;
10303 202 dgisselq
+;
10304 111 dgisselq
+;
10305 102 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10306
+;;
10307
+;; Trap Instruction
10308
+;;
10309
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10310
+;
10311
+;
10312
+; The ZipCPU doesn't really have a "trap" instruction per se.  The goal is that
10313
+; *nothing* should ever trap, and so we should never get here.  However, the
10314 171 dgisselq
+; compiler seems to want a trap instruction for some reason.  (It keeps us
10315
+; from calling the abort() function, if we don't define these ...)  So let's
10316
+; just grab onto the break instruction and declare it to be a trap instruction
10317
+; for our purposes.  Alternatively, we might've used a syscall, but ... this
10318
+; will work for both user and system instructions.
10319
+;
10320 102 dgisselq
+(define_insn "trap"
10321 171 dgisselq
+       [(trap_if (const_int 1) (const_int 0))]
10322
+       ""
10323
+       "BREAK"
10324
+       [(set_attr "predicable" "yes") (set_attr "ccresult" "unchanged")])
10325 102 dgisselq
+;
10326
+;
10327
+(define_expand "ctrapsi4"
10328
+       [(set (reg:CC CC_REG) (compare:CC
10329
+               (match_operand:SI 1 "register_operand" "r")
10330
+               (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
10331
+       (trap_if (match_operator 0 "ordered_comparison_operator"
10332
+                       [(reg:CC CC_REG) (const_int 0)])
10333
+                       (match_operand 3 "const_int_operand" "O"))]
10334
+       ""
10335
+       )
10336
+;
10337
+;
10338
+(define_insn "trapif"
10339
+       [(trap_if (match_operator 0 "ordered_comparison_operator"
10340
+                       [(reg:CC CC_REG) (const_int 0)])
10341
+                       (match_operand 1 "const_int_operand" "O"))]
10342
+       ""
10343
+       "BREAK\t%1"
10344
+       [(set_attr "predicable" "no")])
10345
+;
10346 209 dgisselq
+;
10347 202 dgisselq
+;
10348 122 dgisselq
+;
10349 202 dgisselq
+(include "zip-di.md")
10350
+(include "zip-ops.md")
10351 102 dgisselq
+(include "zip-float.md")
10352 122 dgisselq
+(include "zip-sync.md")
10353 102 dgisselq
+(include "zip-peephole.md")
10354
+;
10355
+;
10356 209 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10357
+;;
10358 102 dgisselq
+;; Unimplemented (or not yet implemented) RTL Codes
10359
+;;
10360 122 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10361 102 dgisselq
+;
10362
+;
10363
+;
10364
+;
10365
+;(define_insn "addvsi4"
10366
+;      )
10367
+;(define_insn "subvsi4"
10368 200 dgisselq
+;      )
10369 202 dgisselq
+;(define_insn "mulvsi4"
10370
+;      )
10371 200 dgisselq
+;(define_insn "umulvsi4"
10372
+;      )
10373
+;(define_insn "umulvsi4"
10374
+;      )
10375
+;(define_insn "negvsi3"
10376 102 dgisselq
+;      "MOV    %1,%0
10377
+;      XOR     -1,%0
10378
+;      ADD     1,%0
10379
+;      BV      %2"
10380
+;      )
10381
+;
10382
+;(define_insn "ssum_widen
10383
+;(define_insn "usum_widen
10384
+;(define_insn "udot_prod"
10385 200 dgisselq
+;(define_insn "maddsidi4"
10386
+;(define_insn "umaddsidi4"
10387
+;(define_insn "msubsidi4"
10388
+;(define_insn "umsubsidi4"
10389
+;
10390
+;
10391
+; STILL MISSING:
10392
+;      SYSCALL(ID)
10393
+;              MOV %ID,R0
10394
+;              CLR     CC
10395 102 dgisselq
+;      cmove   ... the conditional move, created from a
10396
+;      (set (match_op 0 "" "r") (if_then_else (condition) (a) (reg X))))
10397
+;      pattern
10398
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-ops.md gcc-6.2.0-zip/gcc/config/zip/zip-ops.md
10399
--- gcc-6.2.0/gcc/config/zip/zip-ops.md 1969-12-31 19:00:00.000000000 -0500
10400 200 dgisselq
+++ gcc-6.2.0-zip/gcc/config/zip/zip-ops.md     2018-03-22 18:33:11.175718614 -0400
10401 124 dgisselq
@@ -0,0 +1,2744 @@
10402 200 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10403
+;;
10404
+;; Filename:   zip-ops.md
10405
+;;
10406
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
10407
+;;
10408
+;; Purpose:    This is a computer generated machine description of the
10409
+;;             ZipCPU's operations.  It is computer generated simply for
10410
+;;     two reasons.  First, I can't seem to find a way to generate this
10411
+;;     information within GCC's current constructs.  Specifically, the
10412
+;;     CPU's instructions normally set the condition codes, unless they
10413
+;;     are conditional instructions when they don't.  Second, the ZipCPU is
10414
+;;     actually quite regular.  Almost all of the instructions have the same
10415
+;;     form.  This form turns into many, many RTL instructions.  Because the
10416
+;;     CPU doesn't match any of the others within GCC, that means either
10417
+;;     I have a *lot* of cut, copy, paste, and edit to do to create the file
10418 209 dgisselq
+;;     and upon any and every edit, or I need to build a program to generate
10419
+;;     the remaining .md constructs.  Hence, I chose the latter to minimize
10420
+;;     the amount of work I needed to do.
10421
+;;
10422
+;;
10423
+;; Creator:    Dan Gisselquist, Ph.D.
10424
+;;             Gisselquist Technology, LLC
10425
+;;
10426
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10427
+;;
10428
+;; Copyright (C) 2017, Gisselquist Technology, LLC
10429
+;;
10430
+;; This program is free software (firmware): you can redistribute it and/or
10431
+;; modify it under the terms of  the GNU General Public License as published
10432
+;; by the Free Software Foundation, either version 3 of the License, or (at
10433
+;; your option) any later version.
10434
+;;
10435
+;; This program is distributed in the hope that it will be useful, but WITHOUT
10436
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
10437
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
10438
+;; for more details.
10439
+;;
10440
+;; License:    GPL, v3, as defined and found on www.gnu.org,
10441
+;;             http://www.gnu.org/licenses/gpl.html
10442
+;;
10443
+;;
10444
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10445
+;;
10446
+;;
10447
+;
10448
+;
10449
+;
10450
+; ADD (genzipop_long)
10451
+;
10452
+;
10453
+;
10454
+(define_insn "addsi3"
10455
+       [(set (match_operand:SI 0 "register_operand" "=r")
10456
+               (plus:SI (match_operand:SI 1 "register_operand" "0")
10457
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
10458
+       (clobber (reg:CC CC_REG))]
10459
+       ""
10460
+       "ADD\t%2,%0     ; addsi3"
10461
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10462
+;
10463
+;
10464
+(define_insn "addsi3_raw"
10465
+       [(set (match_operand:SI 0 "register_operand" "=r")
10466
+               (plus:SI (match_dup 0)
10467
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
10468
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
10469
+       ""
10470
+       "ADD\t%1,%0     ; addsi3_raw"
10471
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10472
+;
10473
+;
10474
+(define_insn "addsi3_eq"
10475
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
10476
+                       (set (match_operand:SI 0 "register_operand" "=r")
10477
+               (plus:SI (match_dup 0)
10478
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10479
+       ""      ; Condition
10480
+       "ADD.Z\t%1,%0   ; genzip, conditional operator" ; Template
10481
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10482
+;
10483
+;
10484
+(define_insn "addsi3_ne"
10485
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
10486
+                       (set (match_operand:SI 0 "register_operand" "=r")
10487
+               (plus:SI (match_dup 0)
10488
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10489
+       ""      ; Condition
10490
+       "ADD.NZ\t%1,%0  ; genzip, conditional operator" ; Template
10491
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10492
+;
10493
+;
10494
+(define_insn "addsi3_lt"
10495
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
10496
+                       (set (match_operand:SI 0 "register_operand" "=r")
10497
+               (plus:SI (match_dup 0)
10498
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10499
+       ""      ; Condition
10500
+       "ADD.LT\t%1,%0  ; genzip, conditional operator" ; Template
10501
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10502
+;
10503
+;
10504
+(define_insn "addsi3_ge"
10505
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
10506
+                       (set (match_operand:SI 0 "register_operand" "=r")
10507
+               (plus:SI (match_dup 0)
10508
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10509
+       ""      ; Condition
10510
+       "ADD.GE\t%1,%0  ; genzip, conditional operator" ; Template
10511
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10512
+;
10513
+;
10514
+(define_insn "addsi3_ltu"
10515
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
10516
+                       (set (match_operand:SI 0 "register_operand" "=r")
10517
+               (plus:SI (match_dup 0)
10518
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10519
+       ""      ; Condition
10520
+       "ADD.C\t%1,%0   ; genzip, conditional operator" ; Template
10521
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10522
+;
10523
+;
10524
+(define_insn "addsi3_geu"
10525
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
10526
+                       (set (match_operand:SI 0 "register_operand" "=r")
10527
+               (plus:SI (match_dup 0)
10528
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10529
+       ""      ; Condition
10530
+       "ADD.NC\t%1,%0  ; genzip, conditional operator" ; Template
10531
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10532
+;
10533
+;
10534
+;
10535
+;
10536
+;
10537
+; ADD (genzipop_long)
10538
+;
10539
+;
10540
+;
10541
+(define_insn "addsi3_off"
10542
+       [(set (match_operand:SI 0 "register_operand" "=r")
10543
+               (plus:SI (match_operand:SI 1 "register_operand" "0")
10544
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
10545
+                               (match_operand:SI 3 "const_int_operand" "N"))))
10546
+       (clobber (reg:CC CC_REG))]
10547
+       ""
10548
+       "ADD\t%2,%0     ; addsi3_off"
10549
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10550
+;
10551
+;
10552
+(define_insn "addsi3_off_raw"
10553
+       [(set (match_operand:SI 0 "register_operand" "=r")
10554
+               (plus:SI (match_dup 0)
10555
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10556
+                               (match_operand:SI 2 "const_int_operand" "N"))))
10557
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
10558
+       ""
10559
+       "ADD\t%1,%0     ; addsi3_off_raw"
10560
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10561
+;
10562
+;
10563
+(define_insn "addsi3_off_eq"
10564
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
10565
+                       (set (match_operand:SI 0 "register_operand" "=r")
10566
+               (plus:SI (match_dup 0)
10567
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10568
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10569
+       ""      ; Condition
10570
+       "ADD.Z\t%1,%0   ; genzip, conditional operator" ; Template
10571
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10572
+;
10573
+;
10574
+(define_insn "addsi3_off_ne"
10575
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
10576
+                       (set (match_operand:SI 0 "register_operand" "=r")
10577
+               (plus:SI (match_dup 0)
10578
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10579
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10580
+       ""      ; Condition
10581
+       "ADD.NZ\t%1,%0  ; genzip, conditional operator" ; Template
10582
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10583
+;
10584
+;
10585
+(define_insn "addsi3_off_lt"
10586
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
10587
+                       (set (match_operand:SI 0 "register_operand" "=r")
10588
+               (plus:SI (match_dup 0)
10589
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10590
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10591
+       ""      ; Condition
10592
+       "ADD.LT\t%1,%0  ; genzip, conditional operator" ; Template
10593
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10594
+;
10595
+;
10596
+(define_insn "addsi3_off_ge"
10597
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
10598
+                       (set (match_operand:SI 0 "register_operand" "=r")
10599
+               (plus:SI (match_dup 0)
10600
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10601
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10602
+       ""      ; Condition
10603
+       "ADD.GE\t%1,%0  ; genzip, conditional operator" ; Template
10604
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10605
+;
10606
+;
10607
+(define_insn "addsi3_off_ltu"
10608
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
10609
+                       (set (match_operand:SI 0 "register_operand" "=r")
10610
+               (plus:SI (match_dup 0)
10611
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10612
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10613
+       ""      ; Condition
10614
+       "ADD.C\t%1,%0   ; genzip, conditional operator" ; Template
10615
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10616
+;
10617
+;
10618
+(define_insn "addsi3_off_geu"
10619
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
10620
+                       (set (match_operand:SI 0 "register_operand" "=r")
10621
+               (plus:SI (match_dup 0)
10622
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10623
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10624
+       ""      ; Condition
10625
+       "ADD.NC\t%1,%0  ; genzip, conditional operator" ; Template
10626
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10627
+;
10628
+;
10629
+;
10630
+;
10631
+;
10632
+; SUB (genzipop_long)
10633
+;
10634
+;
10635
+;
10636
+(define_insn "subsi3"
10637
+       [(set (match_operand:SI 0 "register_operand" "=r")
10638
+               (minus:SI (match_operand:SI 1 "register_operand" "0")
10639
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
10640
+       (clobber (reg:CC CC_REG))]
10641
+       ""
10642
+       "SUB\t%2,%0     ; subsi3"
10643
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10644
+;
10645
+;
10646
+(define_insn "subsi3_raw"
10647
+       [(set (match_operand:SI 0 "register_operand" "=r")
10648
+               (minus:SI (match_dup 0)
10649
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
10650
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
10651
+       ""
10652
+       "SUB\t%1,%0     ; subsi3_raw"
10653
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10654
+;
10655
+;
10656
+(define_insn "subsi3_eq"
10657
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
10658
+                       (set (match_operand:SI 0 "register_operand" "=r")
10659
+               (minus:SI (match_dup 0)
10660
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10661
+       ""      ; Condition
10662
+       "SUB.Z\t%1,%0   ; genzip, conditional operator" ; Template
10663
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10664
+;
10665
+;
10666
+(define_insn "subsi3_ne"
10667
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
10668
+                       (set (match_operand:SI 0 "register_operand" "=r")
10669
+               (minus:SI (match_dup 0)
10670
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10671
+       ""      ; Condition
10672
+       "SUB.NZ\t%1,%0  ; genzip, conditional operator" ; Template
10673
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10674
+;
10675
+;
10676
+(define_insn "subsi3_lt"
10677
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
10678
+                       (set (match_operand:SI 0 "register_operand" "=r")
10679
+               (minus:SI (match_dup 0)
10680
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10681
+       ""      ; Condition
10682
+       "SUB.LT\t%1,%0  ; genzip, conditional operator" ; Template
10683
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10684
+;
10685
+;
10686
+(define_insn "subsi3_ge"
10687
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
10688
+                       (set (match_operand:SI 0 "register_operand" "=r")
10689
+               (minus:SI (match_dup 0)
10690
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10691
+       ""      ; Condition
10692
+       "SUB.GE\t%1,%0  ; genzip, conditional operator" ; Template
10693
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10694
+;
10695
+;
10696
+(define_insn "subsi3_ltu"
10697
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
10698
+                       (set (match_operand:SI 0 "register_operand" "=r")
10699
+               (minus:SI (match_dup 0)
10700
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10701
+       ""      ; Condition
10702
+       "SUB.C\t%1,%0   ; genzip, conditional operator" ; Template
10703
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10704
+;
10705
+;
10706
+(define_insn "subsi3_geu"
10707
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
10708
+                       (set (match_operand:SI 0 "register_operand" "=r")
10709
+               (minus:SI (match_dup 0)
10710
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10711
+       ""      ; Condition
10712
+       "SUB.NC\t%1,%0  ; genzip, conditional operator" ; Template
10713
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10714
+;
10715
+;
10716
+;
10717
+;
10718
+;
10719
+; SUB (genzipop_long)
10720
+;
10721
+;
10722
+;
10723
+(define_insn "subsi3_off"
10724
+       [(set (match_operand:SI 0 "register_operand" "=r")
10725
+               (minus:SI (match_operand:SI 1 "register_operand" "0")
10726
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
10727
+                               (match_operand:SI 3 "const_int_operand" "N"))))
10728
+       (clobber (reg:CC CC_REG))]
10729
+       ""
10730
+       "SUB\t%2,%0     ; subsi3_off"
10731
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10732
+;
10733
+;
10734
+(define_insn "subsi3_off_raw"
10735
+       [(set (match_operand:SI 0 "register_operand" "=r")
10736
+               (minus:SI (match_dup 0)
10737
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10738
+                               (match_operand:SI 2 "const_int_operand" "N"))))
10739
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
10740
+       ""
10741
+       "SUB\t%1,%0     ; subsi3_off_raw"
10742
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10743
+;
10744
+;
10745
+(define_insn "subsi3_off_eq"
10746
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
10747
+                       (set (match_operand:SI 0 "register_operand" "=r")
10748
+               (minus:SI (match_dup 0)
10749
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10750
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10751
+       ""      ; Condition
10752
+       "SUB.Z\t%1,%0   ; genzip, conditional operator" ; Template
10753
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10754
+;
10755
+;
10756
+(define_insn "subsi3_off_ne"
10757
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
10758
+                       (set (match_operand:SI 0 "register_operand" "=r")
10759
+               (minus:SI (match_dup 0)
10760
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10761
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10762
+       ""      ; Condition
10763
+       "SUB.NZ\t%1,%0  ; genzip, conditional operator" ; Template
10764
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10765
+;
10766
+;
10767
+(define_insn "subsi3_off_lt"
10768
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
10769
+                       (set (match_operand:SI 0 "register_operand" "=r")
10770
+               (minus:SI (match_dup 0)
10771
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10772
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10773
+       ""      ; Condition
10774
+       "SUB.LT\t%1,%0  ; genzip, conditional operator" ; Template
10775
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10776
+;
10777
+;
10778
+(define_insn "subsi3_off_ge"
10779
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
10780
+                       (set (match_operand:SI 0 "register_operand" "=r")
10781
+               (minus:SI (match_dup 0)
10782
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10783
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10784
+       ""      ; Condition
10785
+       "SUB.GE\t%1,%0  ; genzip, conditional operator" ; Template
10786
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10787
+;
10788
+;
10789
+(define_insn "subsi3_off_ltu"
10790
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
10791
+                       (set (match_operand:SI 0 "register_operand" "=r")
10792
+               (minus:SI (match_dup 0)
10793
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10794
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10795
+       ""      ; Condition
10796
+       "SUB.C\t%1,%0   ; genzip, conditional operator" ; Template
10797
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10798
+;
10799
+;
10800
+(define_insn "subsi3_off_geu"
10801
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
10802
+                       (set (match_operand:SI 0 "register_operand" "=r")
10803
+               (minus:SI (match_dup 0)
10804
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10805
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10806
+       ""      ; Condition
10807
+       "SUB.NC\t%1,%0  ; genzip, conditional operator" ; Template
10808
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10809
+;
10810
+;
10811
+;
10812
+;
10813
+;
10814
+; MPY (genzipop_long)
10815
+;
10816
+;
10817
+;
10818
+(define_insn "mulsi3"
10819
+       [(set (match_operand:SI 0 "register_operand" "=r")
10820
+               (mult:SI (match_operand:SI 1 "register_operand" "0")
10821
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
10822
+       (clobber (reg:CC CC_REG))]
10823
+       ""
10824
+       "MPY\t%2,%0     ; mulsi3"
10825
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10826
+;
10827
+;
10828
+(define_insn "mulsi3_raw"
10829
+       [(set (match_operand:SI 0 "register_operand" "=r")
10830
+               (mult:SI (match_dup 0)
10831
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
10832
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
10833
+       ""
10834
+       "MPY\t%1,%0     ; mulsi3_raw"
10835
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10836
+;
10837
+;
10838
+(define_insn "mulsi3_eq"
10839
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
10840
+                       (set (match_operand:SI 0 "register_operand" "=r")
10841
+               (mult:SI (match_dup 0)
10842
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10843
+       ""      ; Condition
10844
+       "MPY.Z\t%1,%0   ; genzip, conditional operator" ; Template
10845
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10846
+;
10847
+;
10848
+(define_insn "mulsi3_ne"
10849
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
10850
+                       (set (match_operand:SI 0 "register_operand" "=r")
10851
+               (mult:SI (match_dup 0)
10852
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10853
+       ""      ; Condition
10854
+       "MPY.NZ\t%1,%0  ; genzip, conditional operator" ; Template
10855
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10856
+;
10857
+;
10858
+(define_insn "mulsi3_lt"
10859
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
10860
+                       (set (match_operand:SI 0 "register_operand" "=r")
10861
+               (mult:SI (match_dup 0)
10862
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10863
+       ""      ; Condition
10864
+       "MPY.LT\t%1,%0  ; genzip, conditional operator" ; Template
10865
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10866
+;
10867
+;
10868
+(define_insn "mulsi3_ge"
10869
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
10870
+                       (set (match_operand:SI 0 "register_operand" "=r")
10871
+               (mult:SI (match_dup 0)
10872
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10873
+       ""      ; Condition
10874
+       "MPY.GE\t%1,%0  ; genzip, conditional operator" ; Template
10875
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10876
+;
10877
+;
10878
+(define_insn "mulsi3_ltu"
10879
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
10880
+                       (set (match_operand:SI 0 "register_operand" "=r")
10881
+               (mult:SI (match_dup 0)
10882
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10883
+       ""      ; Condition
10884
+       "MPY.C\t%1,%0   ; genzip, conditional operator" ; Template
10885
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10886
+;
10887
+;
10888
+(define_insn "mulsi3_geu"
10889
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
10890
+                       (set (match_operand:SI 0 "register_operand" "=r")
10891
+               (mult:SI (match_dup 0)
10892
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
10893
+       ""      ; Condition
10894
+       "MPY.NC\t%1,%0  ; genzip, conditional operator" ; Template
10895
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10896
+;
10897
+;
10898
+;
10899
+;
10900
+;
10901
+; MPY (genzipop_long)
10902
+;
10903
+;
10904
+;
10905
+(define_insn "mulsi3_off"
10906
+       [(set (match_operand:SI 0 "register_operand" "=r")
10907
+               (mult:SI (match_operand:SI 1 "register_operand" "0")
10908
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
10909
+                               (match_operand:SI 3 "const_int_operand" "N"))))
10910
+       (clobber (reg:CC CC_REG))]
10911
+       ""
10912
+       "MPY\t%2,%0     ; mulsi3_off"
10913
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10914
+;
10915
+;
10916
+(define_insn "mulsi3_off_raw"
10917
+       [(set (match_operand:SI 0 "register_operand" "=r")
10918
+               (mult:SI (match_dup 0)
10919
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10920
+                               (match_operand:SI 2 "const_int_operand" "N"))))
10921
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
10922
+       ""
10923
+       "MPY\t%1,%0     ; mulsi3_off_raw"
10924
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
10925
+;
10926
+;
10927
+(define_insn "mulsi3_off_eq"
10928
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
10929
+                       (set (match_operand:SI 0 "register_operand" "=r")
10930
+               (mult:SI (match_dup 0)
10931
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10932
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10933
+       ""      ; Condition
10934
+       "MPY.Z\t%1,%0   ; genzip, conditional operator" ; Template
10935
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10936
+;
10937
+;
10938
+(define_insn "mulsi3_off_ne"
10939
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
10940
+                       (set (match_operand:SI 0 "register_operand" "=r")
10941
+               (mult:SI (match_dup 0)
10942
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10943
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10944
+       ""      ; Condition
10945
+       "MPY.NZ\t%1,%0  ; genzip, conditional operator" ; Template
10946
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10947
+;
10948
+;
10949
+(define_insn "mulsi3_off_lt"
10950
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
10951
+                       (set (match_operand:SI 0 "register_operand" "=r")
10952
+               (mult:SI (match_dup 0)
10953
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10954
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10955
+       ""      ; Condition
10956
+       "MPY.LT\t%1,%0  ; genzip, conditional operator" ; Template
10957
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10958
+;
10959
+;
10960
+(define_insn "mulsi3_off_ge"
10961
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
10962
+                       (set (match_operand:SI 0 "register_operand" "=r")
10963
+               (mult:SI (match_dup 0)
10964
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10965
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10966
+       ""      ; Condition
10967
+       "MPY.GE\t%1,%0  ; genzip, conditional operator" ; Template
10968
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10969
+;
10970
+;
10971
+(define_insn "mulsi3_off_ltu"
10972
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
10973
+                       (set (match_operand:SI 0 "register_operand" "=r")
10974
+               (mult:SI (match_dup 0)
10975
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10976
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10977
+       ""      ; Condition
10978
+       "MPY.C\t%1,%0   ; genzip, conditional operator" ; Template
10979
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10980
+;
10981
+;
10982
+(define_insn "mulsi3_off_geu"
10983
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
10984
+                       (set (match_operand:SI 0 "register_operand" "=r")
10985
+               (mult:SI (match_dup 0)
10986
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
10987
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
10988
+       ""      ; Condition
10989
+       "MPY.NC\t%1,%0  ; genzip, conditional operator" ; Template
10990
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
10991
+;
10992
+;
10993
+;
10994
+;
10995
+;
10996
+; DIVS (genzipop_long)
10997
+;
10998
+;
10999
+;
11000
+(define_insn "divsi3"
11001
+       [(set (match_operand:SI 0 "register_operand" "=r")
11002
+               (div:SI (match_operand:SI 1 "register_operand" "0")
11003
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11004
+       (clobber (reg:CC CC_REG))]
11005
+       "(ZIP_DIVIDE)"
11006
+       "DIVS\t%2,%0    ; divsi3"
11007
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11008
+;
11009
+;
11010
+(define_insn "divsi3_raw"
11011
+       [(set (match_operand:SI 0 "register_operand" "=r")
11012
+               (div:SI (match_dup 0)
11013
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
11014
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
11015
+       "(ZIP_DIVIDE)"
11016
+       "DIVS\t%1,%0    ; divsi3_raw"
11017
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11018
+;
11019
+;
11020
+(define_insn "divsi3_eq"
11021
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
11022
+                       (set (match_operand:SI 0 "register_operand" "=r")
11023
+               (div:SI (match_dup 0)
11024
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11025
+       "(ZIP_DIVIDE)"  ; Condition
11026
+       "DIVS.Z\t%1,%0  ; genzip, conditional operator" ; Template
11027
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11028
+;
11029
+;
11030
+(define_insn "divsi3_ne"
11031
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
11032
+                       (set (match_operand:SI 0 "register_operand" "=r")
11033
+               (div:SI (match_dup 0)
11034
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11035
+       "(ZIP_DIVIDE)"  ; Condition
11036
+       "DIVS.NZ\t%1,%0 ; genzip, conditional operator" ; Template
11037
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11038
+;
11039
+;
11040
+(define_insn "divsi3_lt"
11041
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
11042
+                       (set (match_operand:SI 0 "register_operand" "=r")
11043
+               (div:SI (match_dup 0)
11044
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11045
+       "(ZIP_DIVIDE)"  ; Condition
11046
+       "DIVS.LT\t%1,%0 ; genzip, conditional operator" ; Template
11047
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11048
+;
11049
+;
11050
+(define_insn "divsi3_ge"
11051
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
11052
+                       (set (match_operand:SI 0 "register_operand" "=r")
11053
+               (div:SI (match_dup 0)
11054
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11055
+       "(ZIP_DIVIDE)"  ; Condition
11056
+       "DIVS.GE\t%1,%0 ; genzip, conditional operator" ; Template
11057
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11058
+;
11059
+;
11060
+(define_insn "divsi3_ltu"
11061
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
11062
+                       (set (match_operand:SI 0 "register_operand" "=r")
11063
+               (div:SI (match_dup 0)
11064
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11065
+       "(ZIP_DIVIDE)"  ; Condition
11066
+       "DIVS.C\t%1,%0  ; genzip, conditional operator" ; Template
11067
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11068
+;
11069
+;
11070
+(define_insn "divsi3_geu"
11071
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
11072
+                       (set (match_operand:SI 0 "register_operand" "=r")
11073
+               (div:SI (match_dup 0)
11074
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11075
+       "(ZIP_DIVIDE)"  ; Condition
11076
+       "DIVS.NC\t%1,%0 ; genzip, conditional operator" ; Template
11077
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11078
+;
11079
+;
11080
+;
11081
+;
11082
+;
11083
+; DIVS (genzipop_long)
11084
+;
11085
+;
11086
+;
11087
+(define_insn "divsi3_off"
11088
+       [(set (match_operand:SI 0 "register_operand" "=r")
11089
+               (div:SI (match_operand:SI 1 "register_operand" "0")
11090
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
11091
+                               (match_operand:SI 3 "const_int_operand" "N"))))
11092
+       (clobber (reg:CC CC_REG))]
11093
+       "(ZIP_DIVIDE)"
11094
+       "DIVS\t%2,%0    ; divsi3_off"
11095
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11096
+;
11097
+;
11098
+(define_insn "divsi3_off_raw"
11099
+       [(set (match_operand:SI 0 "register_operand" "=r")
11100
+               (div:SI (match_dup 0)
11101
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11102
+                               (match_operand:SI 2 "const_int_operand" "N"))))
11103
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
11104
+       "(ZIP_DIVIDE)"
11105
+       "DIVS\t%1,%0    ; divsi3_off_raw"
11106
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11107
+;
11108
+;
11109
+(define_insn "divsi3_off_eq"
11110
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
11111
+                       (set (match_operand:SI 0 "register_operand" "=r")
11112
+               (div:SI (match_dup 0)
11113
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11114
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11115
+       "(ZIP_DIVIDE)"  ; Condition
11116
+       "DIVS.Z\t%1,%0  ; genzip, conditional operator" ; Template
11117
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11118
+;
11119
+;
11120
+(define_insn "divsi3_off_ne"
11121
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
11122
+                       (set (match_operand:SI 0 "register_operand" "=r")
11123
+               (div:SI (match_dup 0)
11124
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11125
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11126
+       "(ZIP_DIVIDE)"  ; Condition
11127
+       "DIVS.NZ\t%1,%0 ; genzip, conditional operator" ; Template
11128
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11129
+;
11130
+;
11131
+(define_insn "divsi3_off_lt"
11132
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
11133
+                       (set (match_operand:SI 0 "register_operand" "=r")
11134
+               (div:SI (match_dup 0)
11135
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11136
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11137
+       "(ZIP_DIVIDE)"  ; Condition
11138
+       "DIVS.LT\t%1,%0 ; genzip, conditional operator" ; Template
11139
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11140
+;
11141
+;
11142
+(define_insn "divsi3_off_ge"
11143
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
11144
+                       (set (match_operand:SI 0 "register_operand" "=r")
11145
+               (div:SI (match_dup 0)
11146
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11147
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11148
+       "(ZIP_DIVIDE)"  ; Condition
11149
+       "DIVS.GE\t%1,%0 ; genzip, conditional operator" ; Template
11150
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11151
+;
11152
+;
11153
+(define_insn "divsi3_off_ltu"
11154
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
11155
+                       (set (match_operand:SI 0 "register_operand" "=r")
11156
+               (div:SI (match_dup 0)
11157
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11158
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11159
+       "(ZIP_DIVIDE)"  ; Condition
11160
+       "DIVS.C\t%1,%0  ; genzip, conditional operator" ; Template
11161
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11162
+;
11163
+;
11164
+(define_insn "divsi3_off_geu"
11165
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
11166
+                       (set (match_operand:SI 0 "register_operand" "=r")
11167
+               (div:SI (match_dup 0)
11168
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11169
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11170
+       "(ZIP_DIVIDE)"  ; Condition
11171
+       "DIVS.NC\t%1,%0 ; genzip, conditional operator" ; Template
11172
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11173
+;
11174
+;
11175
+;
11176
+;
11177
+;
11178
+; DIVU (genzipop_long)
11179
+;
11180
+;
11181
+;
11182
+(define_insn "udivsi3"
11183
+       [(set (match_operand:SI 0 "register_operand" "=r")
11184
+               (udiv:SI (match_operand:SI 1 "register_operand" "0")
11185
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11186
+       (clobber (reg:CC CC_REG))]
11187
+       "(ZIP_DIVIDE)"
11188
+       "DIVU\t%2,%0    ; udivsi3"
11189
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11190
+;
11191
+;
11192
+(define_insn "udivsi3_raw"
11193
+       [(set (match_operand:SI 0 "register_operand" "=r")
11194
+               (udiv:SI (match_dup 0)
11195
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
11196
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
11197
+       "(ZIP_DIVIDE)"
11198
+       "DIVU\t%1,%0    ; udivsi3_raw"
11199
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11200
+;
11201
+;
11202
+(define_insn "udivsi3_eq"
11203
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
11204
+                       (set (match_operand:SI 0 "register_operand" "=r")
11205
+               (udiv:SI (match_dup 0)
11206
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11207
+       "(ZIP_DIVIDE)"  ; Condition
11208
+       "DIVU.Z\t%1,%0  ; genzip, conditional operator" ; Template
11209
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11210
+;
11211
+;
11212
+(define_insn "udivsi3_ne"
11213
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
11214
+                       (set (match_operand:SI 0 "register_operand" "=r")
11215
+               (udiv:SI (match_dup 0)
11216
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11217
+       "(ZIP_DIVIDE)"  ; Condition
11218
+       "DIVU.NZ\t%1,%0 ; genzip, conditional operator" ; Template
11219
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11220
+;
11221
+;
11222
+(define_insn "udivsi3_lt"
11223
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
11224
+                       (set (match_operand:SI 0 "register_operand" "=r")
11225
+               (udiv:SI (match_dup 0)
11226
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11227
+       "(ZIP_DIVIDE)"  ; Condition
11228
+       "DIVU.LT\t%1,%0 ; genzip, conditional operator" ; Template
11229
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11230
+;
11231
+;
11232
+(define_insn "udivsi3_ge"
11233
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
11234
+                       (set (match_operand:SI 0 "register_operand" "=r")
11235
+               (udiv:SI (match_dup 0)
11236
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11237
+       "(ZIP_DIVIDE)"  ; Condition
11238
+       "DIVU.GE\t%1,%0 ; genzip, conditional operator" ; Template
11239
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11240
+;
11241
+;
11242
+(define_insn "udivsi3_ltu"
11243
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
11244
+                       (set (match_operand:SI 0 "register_operand" "=r")
11245
+               (udiv:SI (match_dup 0)
11246
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11247
+       "(ZIP_DIVIDE)"  ; Condition
11248
+       "DIVU.C\t%1,%0  ; genzip, conditional operator" ; Template
11249
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11250
+;
11251
+;
11252
+(define_insn "udivsi3_geu"
11253
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
11254
+                       (set (match_operand:SI 0 "register_operand" "=r")
11255
+               (udiv:SI (match_dup 0)
11256
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11257
+       "(ZIP_DIVIDE)"  ; Condition
11258
+       "DIVU.NC\t%1,%0 ; genzip, conditional operator" ; Template
11259
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11260
+;
11261
+;
11262
+;
11263
+;
11264
+;
11265
+; DIVU (genzipop_long)
11266
+;
11267
+;
11268
+;
11269
+(define_insn "udivsi3_off"
11270
+       [(set (match_operand:SI 0 "register_operand" "=r")
11271
+               (udiv:SI (match_operand:SI 1 "register_operand" "0")
11272
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
11273
+                               (match_operand:SI 3 "const_int_operand" "N"))))
11274
+       (clobber (reg:CC CC_REG))]
11275
+       "(ZIP_DIVIDE)"
11276
+       "DIVU\t%2,%0    ; udivsi3_off"
11277
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11278
+;
11279
+;
11280
+(define_insn "udivsi3_off_raw"
11281
+       [(set (match_operand:SI 0 "register_operand" "=r")
11282
+               (udiv:SI (match_dup 0)
11283
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11284
+                               (match_operand:SI 2 "const_int_operand" "N"))))
11285
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
11286
+       "(ZIP_DIVIDE)"
11287
+       "DIVU\t%1,%0    ; udivsi3_off_raw"
11288
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11289
+;
11290
+;
11291
+(define_insn "udivsi3_off_eq"
11292
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
11293
+                       (set (match_operand:SI 0 "register_operand" "=r")
11294
+               (udiv:SI (match_dup 0)
11295
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11296
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11297
+       "(ZIP_DIVIDE)"  ; Condition
11298
+       "DIVU.Z\t%1,%0  ; genzip, conditional operator" ; Template
11299
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11300
+;
11301
+;
11302
+(define_insn "udivsi3_off_ne"
11303
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
11304
+                       (set (match_operand:SI 0 "register_operand" "=r")
11305
+               (udiv:SI (match_dup 0)
11306
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11307
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11308
+       "(ZIP_DIVIDE)"  ; Condition
11309
+       "DIVU.NZ\t%1,%0 ; genzip, conditional operator" ; Template
11310
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11311
+;
11312
+;
11313
+(define_insn "udivsi3_off_lt"
11314
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
11315
+                       (set (match_operand:SI 0 "register_operand" "=r")
11316
+               (udiv:SI (match_dup 0)
11317
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11318
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11319
+       "(ZIP_DIVIDE)"  ; Condition
11320
+       "DIVU.LT\t%1,%0 ; genzip, conditional operator" ; Template
11321
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11322
+;
11323
+;
11324
+(define_insn "udivsi3_off_ge"
11325
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
11326
+                       (set (match_operand:SI 0 "register_operand" "=r")
11327
+               (udiv:SI (match_dup 0)
11328
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11329
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11330
+       "(ZIP_DIVIDE)"  ; Condition
11331
+       "DIVU.GE\t%1,%0 ; genzip, conditional operator" ; Template
11332
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11333
+;
11334
+;
11335
+(define_insn "udivsi3_off_ltu"
11336
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
11337
+                       (set (match_operand:SI 0 "register_operand" "=r")
11338
+               (udiv:SI (match_dup 0)
11339
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11340
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11341
+       "(ZIP_DIVIDE)"  ; Condition
11342
+       "DIVU.C\t%1,%0  ; genzip, conditional operator" ; Template
11343
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11344
+;
11345
+;
11346
+(define_insn "udivsi3_off_geu"
11347
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
11348
+                       (set (match_operand:SI 0 "register_operand" "=r")
11349
+               (udiv:SI (match_dup 0)
11350
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11351
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11352
+       "(ZIP_DIVIDE)"  ; Condition
11353
+       "DIVU.NC\t%1,%0 ; genzip, conditional operator" ; Template
11354
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11355
+;
11356
+;
11357
+;
11358
+;
11359
+;
11360
+; AND (genzipop_long)
11361
+;
11362
+;
11363
+;
11364
+(define_insn "andsi3"
11365
+       [(set (match_operand:SI 0 "register_operand" "=r")
11366
+               (and:SI (match_operand:SI 1 "register_operand" "0")
11367
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11368
+       (clobber (reg:CC CC_REG))]
11369
+       ""
11370
+       "AND\t%2,%0     ; andsi3"
11371
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11372
+;
11373
+;
11374
+(define_insn "andsi3_raw"
11375
+       [(set (match_operand:SI 0 "register_operand" "=r")
11376
+               (and:SI (match_dup 0)
11377
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
11378
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
11379
+       ""
11380
+       "AND\t%1,%0     ; andsi3_raw"
11381
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11382
+;
11383
+;
11384
+(define_insn "andsi3_eq"
11385
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
11386
+                       (set (match_operand:SI 0 "register_operand" "=r")
11387
+               (and:SI (match_dup 0)
11388
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11389
+       ""      ; Condition
11390
+       "AND.Z\t%1,%0   ; genzip, conditional operator" ; Template
11391
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11392
+;
11393
+;
11394
+(define_insn "andsi3_ne"
11395
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
11396
+                       (set (match_operand:SI 0 "register_operand" "=r")
11397
+               (and:SI (match_dup 0)
11398
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11399
+       ""      ; Condition
11400
+       "AND.NZ\t%1,%0  ; genzip, conditional operator" ; Template
11401
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11402
+;
11403
+;
11404
+(define_insn "andsi3_lt"
11405
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
11406
+                       (set (match_operand:SI 0 "register_operand" "=r")
11407
+               (and:SI (match_dup 0)
11408
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11409
+       ""      ; Condition
11410
+       "AND.LT\t%1,%0  ; genzip, conditional operator" ; Template
11411
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11412
+;
11413
+;
11414
+(define_insn "andsi3_ge"
11415
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
11416
+                       (set (match_operand:SI 0 "register_operand" "=r")
11417
+               (and:SI (match_dup 0)
11418
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11419
+       ""      ; Condition
11420
+       "AND.GE\t%1,%0  ; genzip, conditional operator" ; Template
11421
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11422
+;
11423
+;
11424
+(define_insn "andsi3_ltu"
11425
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
11426
+                       (set (match_operand:SI 0 "register_operand" "=r")
11427
+               (and:SI (match_dup 0)
11428
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11429
+       ""      ; Condition
11430
+       "AND.C\t%1,%0   ; genzip, conditional operator" ; Template
11431
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11432
+;
11433
+;
11434
+(define_insn "andsi3_geu"
11435
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
11436
+                       (set (match_operand:SI 0 "register_operand" "=r")
11437
+               (and:SI (match_dup 0)
11438
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11439
+       ""      ; Condition
11440
+       "AND.NC\t%1,%0  ; genzip, conditional operator" ; Template
11441
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11442
+;
11443
+;
11444
+;
11445
+;
11446
+;
11447
+; AND (genzipop_long)
11448
+;
11449
+;
11450
+;
11451
+(define_insn "andsi3_off"
11452
+       [(set (match_operand:SI 0 "register_operand" "=r")
11453
+               (and:SI (match_operand:SI 1 "register_operand" "0")
11454
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
11455
+                               (match_operand:SI 3 "const_int_operand" "N"))))
11456
+       (clobber (reg:CC CC_REG))]
11457
+       ""
11458
+       "AND\t%2,%0     ; andsi3_off"
11459
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11460
+;
11461
+;
11462
+(define_insn "andsi3_off_raw"
11463
+       [(set (match_operand:SI 0 "register_operand" "=r")
11464
+               (and:SI (match_dup 0)
11465
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11466
+                               (match_operand:SI 2 "const_int_operand" "N"))))
11467
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
11468
+       ""
11469
+       "AND\t%1,%0     ; andsi3_off_raw"
11470
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11471
+;
11472
+;
11473
+(define_insn "andsi3_off_eq"
11474
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
11475
+                       (set (match_operand:SI 0 "register_operand" "=r")
11476
+               (and:SI (match_dup 0)
11477
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11478
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11479
+       ""      ; Condition
11480
+       "AND.Z\t%1,%0   ; genzip, conditional operator" ; Template
11481
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11482
+;
11483
+;
11484
+(define_insn "andsi3_off_ne"
11485
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
11486
+                       (set (match_operand:SI 0 "register_operand" "=r")
11487
+               (and:SI (match_dup 0)
11488
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11489
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11490
+       ""      ; Condition
11491
+       "AND.NZ\t%1,%0  ; genzip, conditional operator" ; Template
11492
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11493
+;
11494
+;
11495
+(define_insn "andsi3_off_lt"
11496
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
11497
+                       (set (match_operand:SI 0 "register_operand" "=r")
11498
+               (and:SI (match_dup 0)
11499
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11500
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11501
+       ""      ; Condition
11502
+       "AND.LT\t%1,%0  ; genzip, conditional operator" ; Template
11503
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11504
+;
11505
+;
11506
+(define_insn "andsi3_off_ge"
11507
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
11508
+                       (set (match_operand:SI 0 "register_operand" "=r")
11509
+               (and:SI (match_dup 0)
11510
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11511
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11512
+       ""      ; Condition
11513
+       "AND.GE\t%1,%0  ; genzip, conditional operator" ; Template
11514
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11515
+;
11516
+;
11517
+(define_insn "andsi3_off_ltu"
11518
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
11519
+                       (set (match_operand:SI 0 "register_operand" "=r")
11520
+               (and:SI (match_dup 0)
11521
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11522
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11523
+       ""      ; Condition
11524
+       "AND.C\t%1,%0   ; genzip, conditional operator" ; Template
11525
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11526
+;
11527
+;
11528
+(define_insn "andsi3_off_geu"
11529
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
11530
+                       (set (match_operand:SI 0 "register_operand" "=r")
11531
+               (and:SI (match_dup 0)
11532
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11533
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11534
+       ""      ; Condition
11535
+       "AND.NC\t%1,%0  ; genzip, conditional operator" ; Template
11536
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11537
+;
11538
+;
11539
+;
11540
+;
11541
+;
11542
+; OR (genzipop_long)
11543
+;
11544
+;
11545
+;
11546
+(define_insn "iorsi3"
11547
+       [(set (match_operand:SI 0 "register_operand" "=r")
11548
+               (ior:SI (match_operand:SI 1 "register_operand" "0")
11549
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11550
+       (clobber (reg:CC CC_REG))]
11551
+       ""
11552
+       "OR\t%2,%0      ; iorsi3"
11553
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11554
+;
11555
+;
11556
+(define_insn "iorsi3_raw"
11557
+       [(set (match_operand:SI 0 "register_operand" "=r")
11558
+               (ior:SI (match_dup 0)
11559
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
11560
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
11561
+       ""
11562
+       "OR\t%1,%0      ; iorsi3_raw"
11563
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11564
+;
11565
+;
11566
+(define_insn "iorsi3_eq"
11567
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
11568
+                       (set (match_operand:SI 0 "register_operand" "=r")
11569
+               (ior:SI (match_dup 0)
11570
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11571
+       ""      ; Condition
11572
+       "OR.Z\t%1,%0    ; genzip, conditional operator" ; Template
11573
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11574
+;
11575
+;
11576
+(define_insn "iorsi3_ne"
11577
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
11578
+                       (set (match_operand:SI 0 "register_operand" "=r")
11579
+               (ior:SI (match_dup 0)
11580
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11581
+       ""      ; Condition
11582
+       "OR.NZ\t%1,%0   ; genzip, conditional operator" ; Template
11583
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11584
+;
11585
+;
11586
+(define_insn "iorsi3_lt"
11587
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
11588
+                       (set (match_operand:SI 0 "register_operand" "=r")
11589
+               (ior:SI (match_dup 0)
11590
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11591
+       ""      ; Condition
11592
+       "OR.LT\t%1,%0   ; genzip, conditional operator" ; Template
11593
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11594
+;
11595
+;
11596
+(define_insn "iorsi3_ge"
11597
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
11598
+                       (set (match_operand:SI 0 "register_operand" "=r")
11599
+               (ior:SI (match_dup 0)
11600
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11601
+       ""      ; Condition
11602
+       "OR.GE\t%1,%0   ; genzip, conditional operator" ; Template
11603
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11604
+;
11605
+;
11606
+(define_insn "iorsi3_ltu"
11607
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
11608
+                       (set (match_operand:SI 0 "register_operand" "=r")
11609
+               (ior:SI (match_dup 0)
11610
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11611
+       ""      ; Condition
11612
+       "OR.C\t%1,%0    ; genzip, conditional operator" ; Template
11613
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11614
+;
11615
+;
11616
+(define_insn "iorsi3_geu"
11617
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
11618
+                       (set (match_operand:SI 0 "register_operand" "=r")
11619
+               (ior:SI (match_dup 0)
11620
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11621
+       ""      ; Condition
11622
+       "OR.NC\t%1,%0   ; genzip, conditional operator" ; Template
11623
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11624
+;
11625
+;
11626
+;
11627
+;
11628
+;
11629
+; OR (genzipop_long)
11630
+;
11631
+;
11632
+;
11633
+(define_insn "iorsi3_off"
11634
+       [(set (match_operand:SI 0 "register_operand" "=r")
11635
+               (ior:SI (match_operand:SI 1 "register_operand" "0")
11636
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
11637
+                               (match_operand:SI 3 "const_int_operand" "N"))))
11638
+       (clobber (reg:CC CC_REG))]
11639
+       ""
11640
+       "OR\t%2,%0      ; iorsi3_off"
11641
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11642
+;
11643
+;
11644
+(define_insn "iorsi3_off_raw"
11645
+       [(set (match_operand:SI 0 "register_operand" "=r")
11646
+               (ior:SI (match_dup 0)
11647
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11648
+                               (match_operand:SI 2 "const_int_operand" "N"))))
11649
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
11650
+       ""
11651
+       "OR\t%1,%0      ; iorsi3_off_raw"
11652
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11653
+;
11654
+;
11655
+(define_insn "iorsi3_off_eq"
11656
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
11657
+                       (set (match_operand:SI 0 "register_operand" "=r")
11658
+               (ior:SI (match_dup 0)
11659
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11660
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11661
+       ""      ; Condition
11662
+       "OR.Z\t%1,%0    ; genzip, conditional operator" ; Template
11663
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11664
+;
11665
+;
11666
+(define_insn "iorsi3_off_ne"
11667
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
11668
+                       (set (match_operand:SI 0 "register_operand" "=r")
11669
+               (ior:SI (match_dup 0)
11670
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11671
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11672
+       ""      ; Condition
11673
+       "OR.NZ\t%1,%0   ; genzip, conditional operator" ; Template
11674
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11675
+;
11676
+;
11677
+(define_insn "iorsi3_off_lt"
11678
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
11679
+                       (set (match_operand:SI 0 "register_operand" "=r")
11680
+               (ior:SI (match_dup 0)
11681
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11682
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11683
+       ""      ; Condition
11684
+       "OR.LT\t%1,%0   ; genzip, conditional operator" ; Template
11685
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11686
+;
11687
+;
11688
+(define_insn "iorsi3_off_ge"
11689
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
11690
+                       (set (match_operand:SI 0 "register_operand" "=r")
11691
+               (ior:SI (match_dup 0)
11692
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11693
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11694
+       ""      ; Condition
11695
+       "OR.GE\t%1,%0   ; genzip, conditional operator" ; Template
11696
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11697
+;
11698
+;
11699
+(define_insn "iorsi3_off_ltu"
11700
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
11701
+                       (set (match_operand:SI 0 "register_operand" "=r")
11702
+               (ior:SI (match_dup 0)
11703
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11704
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11705
+       ""      ; Condition
11706
+       "OR.C\t%1,%0    ; genzip, conditional operator" ; Template
11707
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11708
+;
11709
+;
11710
+(define_insn "iorsi3_off_geu"
11711
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
11712
+                       (set (match_operand:SI 0 "register_operand" "=r")
11713
+               (ior:SI (match_dup 0)
11714
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11715
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11716
+       ""      ; Condition
11717
+       "OR.NC\t%1,%0   ; genzip, conditional operator" ; Template
11718
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11719
+;
11720
+;
11721
+;
11722
+;
11723
+;
11724
+; XOR (genzipop_long)
11725
+;
11726
+;
11727
+;
11728
+(define_insn "xorsi3"
11729
+       [(set (match_operand:SI 0 "register_operand" "=r")
11730
+               (xor:SI (match_operand:SI 1 "register_operand" "0")
11731
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11732
+       (clobber (reg:CC CC_REG))]
11733
+       ""
11734
+       "XOR\t%2,%0     ; xorsi3"
11735
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11736
+;
11737
+;
11738
+(define_insn "xorsi3_raw"
11739
+       [(set (match_operand:SI 0 "register_operand" "=r")
11740
+               (xor:SI (match_dup 0)
11741
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
11742
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
11743
+       ""
11744
+       "XOR\t%1,%0     ; xorsi3_raw"
11745
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11746
+;
11747
+;
11748
+(define_insn "xorsi3_eq"
11749
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
11750
+                       (set (match_operand:SI 0 "register_operand" "=r")
11751
+               (xor:SI (match_dup 0)
11752
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11753
+       ""      ; Condition
11754
+       "XOR.Z\t%1,%0   ; genzip, conditional operator" ; Template
11755
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11756
+;
11757
+;
11758
+(define_insn "xorsi3_ne"
11759
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
11760
+                       (set (match_operand:SI 0 "register_operand" "=r")
11761
+               (xor:SI (match_dup 0)
11762
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11763
+       ""      ; Condition
11764
+       "XOR.NZ\t%1,%0  ; genzip, conditional operator" ; Template
11765
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11766
+;
11767
+;
11768
+(define_insn "xorsi3_lt"
11769
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
11770
+                       (set (match_operand:SI 0 "register_operand" "=r")
11771
+               (xor:SI (match_dup 0)
11772
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11773
+       ""      ; Condition
11774
+       "XOR.LT\t%1,%0  ; genzip, conditional operator" ; Template
11775
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11776
+;
11777
+;
11778
+(define_insn "xorsi3_ge"
11779
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
11780
+                       (set (match_operand:SI 0 "register_operand" "=r")
11781
+               (xor:SI (match_dup 0)
11782
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11783
+       ""      ; Condition
11784
+       "XOR.GE\t%1,%0  ; genzip, conditional operator" ; Template
11785
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11786
+;
11787
+;
11788
+(define_insn "xorsi3_ltu"
11789
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
11790
+                       (set (match_operand:SI 0 "register_operand" "=r")
11791
+               (xor:SI (match_dup 0)
11792
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11793
+       ""      ; Condition
11794
+       "XOR.C\t%1,%0   ; genzip, conditional operator" ; Template
11795
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11796
+;
11797
+;
11798
+(define_insn "xorsi3_geu"
11799
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
11800
+                       (set (match_operand:SI 0 "register_operand" "=r")
11801
+               (xor:SI (match_dup 0)
11802
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11803
+       ""      ; Condition
11804
+       "XOR.NC\t%1,%0  ; genzip, conditional operator" ; Template
11805
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11806
+;
11807
+;
11808
+;
11809
+;
11810
+;
11811
+; XOR (genzipop_long)
11812
+;
11813
+;
11814
+;
11815
+(define_insn "xorsi3_off"
11816
+       [(set (match_operand:SI 0 "register_operand" "=r")
11817
+               (xor:SI (match_operand:SI 1 "register_operand" "0")
11818
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
11819
+                               (match_operand:SI 3 "const_int_operand" "N"))))
11820
+       (clobber (reg:CC CC_REG))]
11821
+       ""
11822
+       "XOR\t%2,%0     ; xorsi3_off"
11823
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11824
+;
11825
+;
11826
+(define_insn "xorsi3_off_raw"
11827
+       [(set (match_operand:SI 0 "register_operand" "=r")
11828
+               (xor:SI (match_dup 0)
11829
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11830
+                               (match_operand:SI 2 "const_int_operand" "N"))))
11831
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
11832
+       ""
11833
+       "XOR\t%1,%0     ; xorsi3_off_raw"
11834
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11835
+;
11836
+;
11837
+(define_insn "xorsi3_off_eq"
11838
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
11839
+                       (set (match_operand:SI 0 "register_operand" "=r")
11840
+               (xor:SI (match_dup 0)
11841
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11842
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11843
+       ""      ; Condition
11844
+       "XOR.Z\t%1,%0   ; genzip, conditional operator" ; Template
11845
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11846
+;
11847
+;
11848
+(define_insn "xorsi3_off_ne"
11849
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
11850
+                       (set (match_operand:SI 0 "register_operand" "=r")
11851
+               (xor:SI (match_dup 0)
11852
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11853
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11854
+       ""      ; Condition
11855
+       "XOR.NZ\t%1,%0  ; genzip, conditional operator" ; Template
11856
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11857
+;
11858
+;
11859
+(define_insn "xorsi3_off_lt"
11860
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
11861
+                       (set (match_operand:SI 0 "register_operand" "=r")
11862
+               (xor:SI (match_dup 0)
11863
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11864
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11865
+       ""      ; Condition
11866
+       "XOR.LT\t%1,%0  ; genzip, conditional operator" ; Template
11867
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11868
+;
11869
+;
11870
+(define_insn "xorsi3_off_ge"
11871
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
11872
+                       (set (match_operand:SI 0 "register_operand" "=r")
11873
+               (xor:SI (match_dup 0)
11874
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11875
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11876
+       ""      ; Condition
11877
+       "XOR.GE\t%1,%0  ; genzip, conditional operator" ; Template
11878
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11879
+;
11880
+;
11881
+(define_insn "xorsi3_off_ltu"
11882
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
11883
+                       (set (match_operand:SI 0 "register_operand" "=r")
11884
+               (xor:SI (match_dup 0)
11885
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11886
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11887
+       ""      ; Condition
11888
+       "XOR.C\t%1,%0   ; genzip, conditional operator" ; Template
11889
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11890
+;
11891
+;
11892
+(define_insn "xorsi3_off_geu"
11893
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
11894
+                       (set (match_operand:SI 0 "register_operand" "=r")
11895
+               (xor:SI (match_dup 0)
11896
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
11897
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
11898
+       ""      ; Condition
11899
+       "XOR.NC\t%1,%0  ; genzip, conditional operator" ; Template
11900
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11901
+;
11902
+;
11903
+;
11904
+;
11905
+;
11906
+; ASR (genzipop_long)
11907
+;
11908
+;
11909
+;
11910
+(define_insn "ashrsi3"
11911
+       [(set (match_operand:SI 0 "register_operand" "=r")
11912
+               (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
11913
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
11914
+       (clobber (reg:CC CC_REG))]
11915
+       ""
11916
+       "ASR\t%2,%0     ; ashrsi3"
11917
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11918
+;
11919
+;
11920
+(define_insn "ashrsi3_raw"
11921
+       [(set (match_operand:SI 0 "register_operand" "=r")
11922
+               (ashiftrt:SI (match_dup 0)
11923
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
11924
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
11925
+       ""
11926
+       "ASR\t%1,%0     ; ashrsi3_raw"
11927
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
11928
+;
11929
+;
11930
+(define_insn "ashrsi3_eq"
11931
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
11932
+                       (set (match_operand:SI 0 "register_operand" "=r")
11933
+               (ashiftrt:SI (match_dup 0)
11934
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11935
+       ""      ; Condition
11936
+       "ASR.Z\t%1,%0   ; genzip, conditional operator" ; Template
11937
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11938
+;
11939
+;
11940
+(define_insn "ashrsi3_ne"
11941
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
11942
+                       (set (match_operand:SI 0 "register_operand" "=r")
11943
+               (ashiftrt:SI (match_dup 0)
11944
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11945
+       ""      ; Condition
11946
+       "ASR.NZ\t%1,%0  ; genzip, conditional operator" ; Template
11947
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11948
+;
11949
+;
11950
+(define_insn "ashrsi3_lt"
11951
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
11952
+                       (set (match_operand:SI 0 "register_operand" "=r")
11953
+               (ashiftrt:SI (match_dup 0)
11954
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11955
+       ""      ; Condition
11956
+       "ASR.LT\t%1,%0  ; genzip, conditional operator" ; Template
11957
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11958
+;
11959
+;
11960
+(define_insn "ashrsi3_ge"
11961
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
11962
+                       (set (match_operand:SI 0 "register_operand" "=r")
11963
+               (ashiftrt:SI (match_dup 0)
11964
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11965
+       ""      ; Condition
11966
+       "ASR.GE\t%1,%0  ; genzip, conditional operator" ; Template
11967
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11968
+;
11969
+;
11970
+(define_insn "ashrsi3_ltu"
11971
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
11972
+                       (set (match_operand:SI 0 "register_operand" "=r")
11973
+               (ashiftrt:SI (match_dup 0)
11974
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11975
+       ""      ; Condition
11976
+       "ASR.C\t%1,%0   ; genzip, conditional operator" ; Template
11977
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11978
+;
11979
+;
11980
+(define_insn "ashrsi3_geu"
11981
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
11982
+                       (set (match_operand:SI 0 "register_operand" "=r")
11983
+               (ashiftrt:SI (match_dup 0)
11984
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
11985
+       ""      ; Condition
11986
+       "ASR.NC\t%1,%0  ; genzip, conditional operator" ; Template
11987
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
11988
+;
11989
+;
11990
+;
11991
+;
11992
+;
11993
+; ASR (genzipop_long)
11994
+;
11995
+;
11996
+;
11997
+(define_insn "ashrsi3_off"
11998
+       [(set (match_operand:SI 0 "register_operand" "=r")
11999
+               (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
12000
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
12001
+                               (match_operand:SI 3 "const_int_operand" "N"))))
12002
+       (clobber (reg:CC CC_REG))]
12003
+       ""
12004
+       "ASR\t%2,%0     ; ashrsi3_off"
12005
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12006
+;
12007
+;
12008
+(define_insn "ashrsi3_off_raw"
12009
+       [(set (match_operand:SI 0 "register_operand" "=r")
12010
+               (ashiftrt:SI (match_dup 0)
12011
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12012
+                               (match_operand:SI 2 "const_int_operand" "N"))))
12013
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
12014
+       ""
12015
+       "ASR\t%1,%0     ; ashrsi3_off_raw"
12016
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12017
+;
12018
+;
12019
+(define_insn "ashrsi3_off_eq"
12020
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
12021
+                       (set (match_operand:SI 0 "register_operand" "=r")
12022
+               (ashiftrt:SI (match_dup 0)
12023
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12024
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12025
+       ""      ; Condition
12026
+       "ASR.Z\t%1,%0   ; genzip, conditional operator" ; Template
12027
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12028
+;
12029
+;
12030
+(define_insn "ashrsi3_off_ne"
12031
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
12032
+                       (set (match_operand:SI 0 "register_operand" "=r")
12033
+               (ashiftrt:SI (match_dup 0)
12034
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12035
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12036
+       ""      ; Condition
12037
+       "ASR.NZ\t%1,%0  ; genzip, conditional operator" ; Template
12038
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12039
+;
12040
+;
12041
+(define_insn "ashrsi3_off_lt"
12042
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
12043
+                       (set (match_operand:SI 0 "register_operand" "=r")
12044
+               (ashiftrt:SI (match_dup 0)
12045
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12046
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12047
+       ""      ; Condition
12048
+       "ASR.LT\t%1,%0  ; genzip, conditional operator" ; Template
12049
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12050
+;
12051
+;
12052
+(define_insn "ashrsi3_off_ge"
12053
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
12054
+                       (set (match_operand:SI 0 "register_operand" "=r")
12055
+               (ashiftrt:SI (match_dup 0)
12056
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12057
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12058
+       ""      ; Condition
12059
+       "ASR.GE\t%1,%0  ; genzip, conditional operator" ; Template
12060
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12061
+;
12062
+;
12063
+(define_insn "ashrsi3_off_ltu"
12064
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
12065
+                       (set (match_operand:SI 0 "register_operand" "=r")
12066
+               (ashiftrt:SI (match_dup 0)
12067
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12068
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12069
+       ""      ; Condition
12070
+       "ASR.C\t%1,%0   ; genzip, conditional operator" ; Template
12071
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12072
+;
12073
+;
12074
+(define_insn "ashrsi3_off_geu"
12075
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
12076
+                       (set (match_operand:SI 0 "register_operand" "=r")
12077
+               (ashiftrt:SI (match_dup 0)
12078
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12079
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12080
+       ""      ; Condition
12081
+       "ASR.NC\t%1,%0  ; genzip, conditional operator" ; Template
12082
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12083
+;
12084
+;
12085
+;
12086
+;
12087
+;
12088
+; LSL (genzipop_long)
12089
+;
12090
+;
12091
+;
12092
+(define_insn "ashlsi3"
12093
+       [(set (match_operand:SI 0 "register_operand" "=r")
12094
+               (ashift:SI (match_operand:SI 1 "register_operand" "0")
12095
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
12096
+       (clobber (reg:CC CC_REG))]
12097
+       ""
12098
+       "LSL\t%2,%0     ; ashlsi3"
12099
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12100
+;
12101
+;
12102
+(define_insn "ashlsi3_raw"
12103
+       [(set (match_operand:SI 0 "register_operand" "=r")
12104
+               (ashift:SI (match_dup 0)
12105
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
12106
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
12107
+       ""
12108
+       "LSL\t%1,%0     ; ashlsi3_raw"
12109
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12110
+;
12111
+;
12112
+(define_insn "ashlsi3_eq"
12113
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
12114
+                       (set (match_operand:SI 0 "register_operand" "=r")
12115
+               (ashift:SI (match_dup 0)
12116
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12117
+       ""      ; Condition
12118
+       "LSL.Z\t%1,%0   ; genzip, conditional operator" ; Template
12119
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12120
+;
12121
+;
12122
+(define_insn "ashlsi3_ne"
12123
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
12124
+                       (set (match_operand:SI 0 "register_operand" "=r")
12125
+               (ashift:SI (match_dup 0)
12126
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12127
+       ""      ; Condition
12128
+       "LSL.NZ\t%1,%0  ; genzip, conditional operator" ; Template
12129
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12130
+;
12131
+;
12132
+(define_insn "ashlsi3_lt"
12133
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
12134
+                       (set (match_operand:SI 0 "register_operand" "=r")
12135
+               (ashift:SI (match_dup 0)
12136
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12137
+       ""      ; Condition
12138
+       "LSL.LT\t%1,%0  ; genzip, conditional operator" ; Template
12139
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12140
+;
12141
+;
12142
+(define_insn "ashlsi3_ge"
12143
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
12144
+                       (set (match_operand:SI 0 "register_operand" "=r")
12145
+               (ashift:SI (match_dup 0)
12146
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12147
+       ""      ; Condition
12148
+       "LSL.GE\t%1,%0  ; genzip, conditional operator" ; Template
12149
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12150
+;
12151
+;
12152
+(define_insn "ashlsi3_ltu"
12153
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
12154
+                       (set (match_operand:SI 0 "register_operand" "=r")
12155
+               (ashift:SI (match_dup 0)
12156
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12157
+       ""      ; Condition
12158
+       "LSL.C\t%1,%0   ; genzip, conditional operator" ; Template
12159
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12160
+;
12161
+;
12162
+(define_insn "ashlsi3_geu"
12163
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
12164
+                       (set (match_operand:SI 0 "register_operand" "=r")
12165
+               (ashift:SI (match_dup 0)
12166
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12167
+       ""      ; Condition
12168
+       "LSL.NC\t%1,%0  ; genzip, conditional operator" ; Template
12169
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12170
+;
12171
+;
12172
+;
12173
+;
12174
+;
12175
+; LSL (genzipop_long)
12176
+;
12177
+;
12178
+;
12179
+(define_insn "ashlsi3_off"
12180
+       [(set (match_operand:SI 0 "register_operand" "=r")
12181
+               (ashift:SI (match_operand:SI 1 "register_operand" "0")
12182
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
12183
+                               (match_operand:SI 3 "const_int_operand" "N"))))
12184
+       (clobber (reg:CC CC_REG))]
12185
+       ""
12186
+       "LSL\t%2,%0     ; ashlsi3_off"
12187
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12188
+;
12189
+;
12190
+(define_insn "ashlsi3_off_raw"
12191
+       [(set (match_operand:SI 0 "register_operand" "=r")
12192
+               (ashift:SI (match_dup 0)
12193
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12194
+                               (match_operand:SI 2 "const_int_operand" "N"))))
12195
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
12196
+       ""
12197
+       "LSL\t%1,%0     ; ashlsi3_off_raw"
12198
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12199
+;
12200
+;
12201
+(define_insn "ashlsi3_off_eq"
12202
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
12203
+                       (set (match_operand:SI 0 "register_operand" "=r")
12204
+               (ashift:SI (match_dup 0)
12205
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12206
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12207
+       ""      ; Condition
12208
+       "LSL.Z\t%1,%0   ; genzip, conditional operator" ; Template
12209
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12210
+;
12211
+;
12212
+(define_insn "ashlsi3_off_ne"
12213
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
12214
+                       (set (match_operand:SI 0 "register_operand" "=r")
12215
+               (ashift:SI (match_dup 0)
12216
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12217
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12218
+       ""      ; Condition
12219
+       "LSL.NZ\t%1,%0  ; genzip, conditional operator" ; Template
12220
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12221
+;
12222
+;
12223
+(define_insn "ashlsi3_off_lt"
12224
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
12225
+                       (set (match_operand:SI 0 "register_operand" "=r")
12226
+               (ashift:SI (match_dup 0)
12227
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12228
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12229
+       ""      ; Condition
12230
+       "LSL.LT\t%1,%0  ; genzip, conditional operator" ; Template
12231
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12232
+;
12233
+;
12234
+(define_insn "ashlsi3_off_ge"
12235
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
12236
+                       (set (match_operand:SI 0 "register_operand" "=r")
12237
+               (ashift:SI (match_dup 0)
12238
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12239
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12240
+       ""      ; Condition
12241
+       "LSL.GE\t%1,%0  ; genzip, conditional operator" ; Template
12242
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12243
+;
12244
+;
12245
+(define_insn "ashlsi3_off_ltu"
12246
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
12247
+                       (set (match_operand:SI 0 "register_operand" "=r")
12248
+               (ashift:SI (match_dup 0)
12249
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12250
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12251
+       ""      ; Condition
12252
+       "LSL.C\t%1,%0   ; genzip, conditional operator" ; Template
12253
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12254
+;
12255
+;
12256
+(define_insn "ashlsi3_off_geu"
12257
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
12258
+                       (set (match_operand:SI 0 "register_operand" "=r")
12259
+               (ashift:SI (match_dup 0)
12260
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12261
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12262
+       ""      ; Condition
12263
+       "LSL.NC\t%1,%0  ; genzip, conditional operator" ; Template
12264
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12265
+;
12266
+;
12267
+;
12268
+;
12269
+;
12270
+; LSR (genzipop_long)
12271
+;
12272
+;
12273
+;
12274
+(define_insn "lshrsi3"
12275
+       [(set (match_operand:SI 0 "register_operand" "=r")
12276
+               (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12277
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
12278
+       (clobber (reg:CC CC_REG))]
12279
+       ""
12280
+       "LSR\t%2,%0     ; lshrsi3"
12281
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12282
+;
12283
+;
12284
+(define_insn "lshrsi3_raw"
12285
+       [(set (match_operand:SI 0 "register_operand" "=r")
12286
+               (lshiftrt:SI (match_dup 0)
12287
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
12288
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
12289
+       ""
12290
+       "LSR\t%1,%0     ; lshrsi3_raw"
12291
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12292
+;
12293
+;
12294
+(define_insn "lshrsi3_eq"
12295
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
12296
+                       (set (match_operand:SI 0 "register_operand" "=r")
12297
+               (lshiftrt:SI (match_dup 0)
12298
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12299
+       ""      ; Condition
12300
+       "LSR.Z\t%1,%0   ; genzip, conditional operator" ; Template
12301
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12302
+;
12303
+;
12304
+(define_insn "lshrsi3_ne"
12305
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
12306
+                       (set (match_operand:SI 0 "register_operand" "=r")
12307
+               (lshiftrt:SI (match_dup 0)
12308
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12309
+       ""      ; Condition
12310
+       "LSR.NZ\t%1,%0  ; genzip, conditional operator" ; Template
12311
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12312
+;
12313
+;
12314
+(define_insn "lshrsi3_lt"
12315
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
12316
+                       (set (match_operand:SI 0 "register_operand" "=r")
12317
+               (lshiftrt:SI (match_dup 0)
12318
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12319
+       ""      ; Condition
12320
+       "LSR.LT\t%1,%0  ; genzip, conditional operator" ; Template
12321
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12322
+;
12323
+;
12324
+(define_insn "lshrsi3_ge"
12325
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
12326
+                       (set (match_operand:SI 0 "register_operand" "=r")
12327
+               (lshiftrt:SI (match_dup 0)
12328
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12329
+       ""      ; Condition
12330
+       "LSR.GE\t%1,%0  ; genzip, conditional operator" ; Template
12331
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12332
+;
12333
+;
12334
+(define_insn "lshrsi3_ltu"
12335
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
12336
+                       (set (match_operand:SI 0 "register_operand" "=r")
12337
+               (lshiftrt:SI (match_dup 0)
12338
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12339
+       ""      ; Condition
12340
+       "LSR.C\t%1,%0   ; genzip, conditional operator" ; Template
12341
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12342
+;
12343
+;
12344
+(define_insn "lshrsi3_geu"
12345
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
12346
+                       (set (match_operand:SI 0 "register_operand" "=r")
12347
+               (lshiftrt:SI (match_dup 0)
12348
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))))]
12349
+       ""      ; Condition
12350
+       "LSR.NC\t%1,%0  ; genzip, conditional operator" ; Template
12351
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12352
+;
12353
+;
12354
+;
12355
+;
12356
+;
12357
+; LSR (genzipop_long)
12358
+;
12359
+;
12360
+;
12361
+(define_insn "lshrsi3_off"
12362
+       [(set (match_operand:SI 0 "register_operand" "=r")
12363
+               (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
12364
+                       (plus:SI (match_operand:SI 2 "register_operand" "r")
12365
+                               (match_operand:SI 3 "const_int_operand" "N"))))
12366
+       (clobber (reg:CC CC_REG))]
12367
+       ""
12368
+       "LSR\t%2,%0     ; lshrsi3_off"
12369
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12370
+;
12371
+;
12372
+(define_insn "lshrsi3_off_raw"
12373
+       [(set (match_operand:SI 0 "register_operand" "=r")
12374
+               (lshiftrt:SI (match_dup 0)
12375
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12376
+                               (match_operand:SI 2 "const_int_operand" "N"))))
12377
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
12378
+       ""
12379
+       "LSR\t%1,%0     ; lshrsi3_off_raw"
12380
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12381
+;
12382
+;
12383
+(define_insn "lshrsi3_off_eq"
12384
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
12385
+                       (set (match_operand:SI 0 "register_operand" "=r")
12386
+               (lshiftrt:SI (match_dup 0)
12387
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12388
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12389
+       ""      ; Condition
12390
+       "LSR.Z\t%1,%0   ; genzip, conditional operator" ; Template
12391
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12392
+;
12393
+;
12394
+(define_insn "lshrsi3_off_ne"
12395
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
12396
+                       (set (match_operand:SI 0 "register_operand" "=r")
12397
+               (lshiftrt:SI (match_dup 0)
12398
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12399
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12400
+       ""      ; Condition
12401
+       "LSR.NZ\t%1,%0  ; genzip, conditional operator" ; Template
12402
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12403
+;
12404
+;
12405
+(define_insn "lshrsi3_off_lt"
12406
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
12407
+                       (set (match_operand:SI 0 "register_operand" "=r")
12408
+               (lshiftrt:SI (match_dup 0)
12409
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12410
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12411
+       ""      ; Condition
12412
+       "LSR.LT\t%1,%0  ; genzip, conditional operator" ; Template
12413
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12414
+;
12415
+;
12416
+(define_insn "lshrsi3_off_ge"
12417
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
12418
+                       (set (match_operand:SI 0 "register_operand" "=r")
12419
+               (lshiftrt:SI (match_dup 0)
12420
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12421
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12422
+       ""      ; Condition
12423
+       "LSR.GE\t%1,%0  ; genzip, conditional operator" ; Template
12424
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12425
+;
12426
+;
12427
+(define_insn "lshrsi3_off_ltu"
12428
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
12429
+                       (set (match_operand:SI 0 "register_operand" "=r")
12430
+               (lshiftrt:SI (match_dup 0)
12431
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12432
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12433
+       ""      ; Condition
12434
+       "LSR.C\t%1,%0   ; genzip, conditional operator" ; Template
12435
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12436
+;
12437
+;
12438
+(define_insn "lshrsi3_off_geu"
12439
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
12440
+                       (set (match_operand:SI 0 "register_operand" "=r")
12441
+               (lshiftrt:SI (match_dup 0)
12442
+                       (plus:SI (match_operand:SI 1 "register_operand" "r")
12443
+                               (match_operand:SI 2 "const_int_operand" "N")))))]
12444
+       ""      ; Condition
12445
+       "LSR.NC\t%1,%0  ; genzip, conditional operator" ; Template
12446
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12447
+;
12448
+;
12449
+;
12450
+;
12451
+;
12452
+; MPYSHI (genzipop_long)
12453
+;
12454
+;
12455
+;
12456
+(define_insn "smulsi_highpart"
12457
+       [(set (match_operand:SI 0 "register_operand" "=r")
12458
+               (truncate:SI (ashiftrt:DI (mult:DI
12459
+                       (sign_extend:DI (match_operand:SI 1 "register_operand" "0"))
12460
+                       (sign_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO")))
12461
+                       (const_int 32))))
12462
+       (clobber (reg:CC CC_REG))]
12463
+       "(ZIP_HAS_DI)"
12464
+       "MPYSHI\t%2,%0  ; smulsi_highpart"
12465
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12466
+;
12467
+;
12468
+(define_insn "smulsi_highpart_raw"
12469
+       [(set (match_operand:SI 0 "register_operand" "=r")
12470
+               (truncate:SI (ashiftrt:DI (mult:DI
12471
+                       (sign_extend:DI (match_dup 0))
12472
+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12473
+                       (const_int 32))))
12474
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
12475
+       "(ZIP_HAS_DI)"
12476
+       "MPYSHI\t%1,%0  ; smulsi_highpart_raw"
12477
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12478
+;
12479
+;
12480
+(define_insn "smulsi_highpart_eq"
12481
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
12482
+                       (set (match_operand:SI 0 "register_operand" "=r")
12483
+               (truncate:SI (ashiftrt:DI (mult:DI
12484
+                       (sign_extend:DI (match_dup 0))
12485
+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12486
+                       (const_int 32)))))]
12487
+       "(ZIP_HAS_DI)"  ; Condition
12488
+       "MPYSHI.Z\t%1,%0        ; genzip, conditional operator" ; Template
12489
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12490
+;
12491
+;
12492
+(define_insn "smulsi_highpart_ne"
12493
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
12494
+                       (set (match_operand:SI 0 "register_operand" "=r")
12495
+               (truncate:SI (ashiftrt:DI (mult:DI
12496
+                       (sign_extend:DI (match_dup 0))
12497
+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12498
+                       (const_int 32)))))]
12499
+       "(ZIP_HAS_DI)"  ; Condition
12500
+       "MPYSHI.NZ\t%1,%0       ; genzip, conditional operator" ; Template
12501
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12502
+;
12503
+;
12504
+(define_insn "smulsi_highpart_lt"
12505
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
12506
+                       (set (match_operand:SI 0 "register_operand" "=r")
12507
+               (truncate:SI (ashiftrt:DI (mult:DI
12508
+                       (sign_extend:DI (match_dup 0))
12509
+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12510
+                       (const_int 32)))))]
12511
+       "(ZIP_HAS_DI)"  ; Condition
12512
+       "MPYSHI.LT\t%1,%0       ; genzip, conditional operator" ; Template
12513
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12514
+;
12515
+;
12516
+(define_insn "smulsi_highpart_ge"
12517
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
12518
+                       (set (match_operand:SI 0 "register_operand" "=r")
12519
+               (truncate:SI (ashiftrt:DI (mult:DI
12520
+                       (sign_extend:DI (match_dup 0))
12521
+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12522
+                       (const_int 32)))))]
12523
+       "(ZIP_HAS_DI)"  ; Condition
12524
+       "MPYSHI.GE\t%1,%0       ; genzip, conditional operator" ; Template
12525
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12526
+;
12527
+;
12528
+(define_insn "smulsi_highpart_ltu"
12529
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
12530
+                       (set (match_operand:SI 0 "register_operand" "=r")
12531
+               (truncate:SI (ashiftrt:DI (mult:DI
12532
+                       (sign_extend:DI (match_dup 0))
12533
+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12534
+                       (const_int 32)))))]
12535
+       "(ZIP_HAS_DI)"  ; Condition
12536
+       "MPYSHI.C\t%1,%0        ; genzip, conditional operator" ; Template
12537
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12538
+;
12539
+;
12540
+(define_insn "smulsi_highpart_geu"
12541
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
12542
+                       (set (match_operand:SI 0 "register_operand" "=r")
12543
+               (truncate:SI (ashiftrt:DI (mult:DI
12544
+                       (sign_extend:DI (match_dup 0))
12545
+                       (sign_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12546
+                       (const_int 32)))))]
12547
+       "(ZIP_HAS_DI)"  ; Condition
12548
+       "MPYSHI.NC\t%1,%0       ; genzip, conditional operator" ; Template
12549
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12550
+;
12551
+;
12552
+;
12553
+;
12554
+;
12555
+; MPYUHI (genzipop_long)
12556
+;
12557
+;
12558
+;
12559
+(define_insn "umulsi_highpart"
12560
+       [(set (match_operand:SI 0 "register_operand" "=r")
12561
+               (truncate:SI (ashiftrt:DI (mult:DI
12562
+                       (zero_extend:DI (match_operand:SI 1 "register_operand" "0"))
12563
+                       (zero_extend:DI (match_operand:SI 2 "zip_opb_operand_p" "rO")))
12564
+                       (const_int 32))))
12565
+       (clobber (reg:CC CC_REG))]
12566
+       "(ZIP_HAS_DI)"
12567
+       "MPYUHI\t%2,%0  ; umulsi_highpart"
12568
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12569
+;
12570
+;
12571
+(define_insn "umulsi_highpart_raw"
12572
+       [(set (match_operand:SI 0 "register_operand" "=r")
12573
+               (truncate:SI (ashiftrt:DI (mult:DI
12574
+                       (zero_extend:DI (match_dup 0))
12575
+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12576
+                       (const_int 32))))
12577
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
12578
+       "(ZIP_HAS_DI)"
12579
+       "MPYUHI\t%1,%0  ; umulsi_highpart_raw"
12580
+       [(set_attr "predicable" "no") (set_attr "ccresult" "set")])
12581
+;
12582
+;
12583
+(define_insn "umulsi_highpart_eq"
12584
+       [(cond_exec (eq (reg:CC CC_REG) (const_int 0))
12585
+                       (set (match_operand:SI 0 "register_operand" "=r")
12586
+               (truncate:SI (ashiftrt:DI (mult:DI
12587
+                       (zero_extend:DI (match_dup 0))
12588
+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12589
+                       (const_int 32)))))]
12590
+       "(ZIP_HAS_DI)"  ; Condition
12591
+       "MPYUHI.Z\t%1,%0        ; genzip, conditional operator" ; Template
12592
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12593
+;
12594
+;
12595
+(define_insn "umulsi_highpart_ne"
12596
+       [(cond_exec (ne (reg:CC CC_REG) (const_int 0))
12597
+                       (set (match_operand:SI 0 "register_operand" "=r")
12598
+               (truncate:SI (ashiftrt:DI (mult:DI
12599
+                       (zero_extend:DI (match_dup 0))
12600
+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12601
+                       (const_int 32)))))]
12602
+       "(ZIP_HAS_DI)"  ; Condition
12603
+       "MPYUHI.NZ\t%1,%0       ; genzip, conditional operator" ; Template
12604
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12605
+;
12606
+;
12607
+(define_insn "umulsi_highpart_lt"
12608
+       [(cond_exec (lt (reg:CC CC_REG) (const_int 0))
12609
+                       (set (match_operand:SI 0 "register_operand" "=r")
12610
+               (truncate:SI (ashiftrt:DI (mult:DI
12611
+                       (zero_extend:DI (match_dup 0))
12612
+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12613
+                       (const_int 32)))))]
12614
+       "(ZIP_HAS_DI)"  ; Condition
12615
+       "MPYUHI.LT\t%1,%0       ; genzip, conditional operator" ; Template
12616
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12617
+;
12618
+;
12619
+(define_insn "umulsi_highpart_ge"
12620
+       [(cond_exec (ge (reg:CC CC_REG) (const_int 0))
12621
+                       (set (match_operand:SI 0 "register_operand" "=r")
12622
+               (truncate:SI (ashiftrt:DI (mult:DI
12623
+                       (zero_extend:DI (match_dup 0))
12624
+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12625
+                       (const_int 32)))))]
12626
+       "(ZIP_HAS_DI)"  ; Condition
12627
+       "MPYUHI.GE\t%1,%0       ; genzip, conditional operator" ; Template
12628
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12629
+;
12630
+;
12631
+(define_insn "umulsi_highpart_ltu"
12632
+       [(cond_exec (ltu (reg:CC CC_REG) (const_int 0))
12633
+                       (set (match_operand:SI 0 "register_operand" "=r")
12634
+               (truncate:SI (ashiftrt:DI (mult:DI
12635
+                       (zero_extend:DI (match_dup 0))
12636
+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12637
+                       (const_int 32)))))]
12638
+       "(ZIP_HAS_DI)"  ; Condition
12639
+       "MPYUHI.C\t%1,%0        ; genzip, conditional operator" ; Template
12640
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12641
+;
12642
+;
12643
+(define_insn "umulsi_highpart_geu"
12644
+       [(cond_exec (geu (reg:CC CC_REG) (const_int 0))
12645
+                       (set (match_operand:SI 0 "register_operand" "=r")
12646
+               (truncate:SI (ashiftrt:DI (mult:DI
12647
+                       (zero_extend:DI (match_dup 0))
12648
+                       (zero_extend:DI (match_operand:SI 1 "zip_opb_operand_p" "rO")))
12649
+                       (const_int 32)))))]
12650
+       "(ZIP_HAS_DI)"  ; Condition
12651
+       "MPYUHI.NC\t%1,%0       ; genzip, conditional operator" ; Template
12652
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12653
+;
12654
+;
12655
+;
12656
+;
12657
+; Conditional move instructions
12658
+;
12659
+;
12660
+;
12661
+;
12662
+(define_insn "cmov_eq"
12663
+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")
12664
+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))
12665
+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")
12666
+                       (match_dup 0)))]
12667
+       ""
12668
+       "@
12669
+       MOV.Z   %1,%0   ; cmov
12670
+       LW.Z    %1,%0   ; cmov
12671
+       LDI.Z   %1,%0   ; cmov
12672
+       SW.Z    %1,%0   ; cmov"
12673
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12674
+;
12675
+;
12676
+(define_insn "cmov_ne"
12677
+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")
12678
+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))
12679
+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")
12680
+                       (match_dup 0)))]
12681
+       ""
12682
+       "@
12683
+       MOV.NZ  %1,%0   ; cmov
12684
+       LW.NZ   %1,%0   ; cmov
12685
+       LDI.NZ  %1,%0   ; cmov
12686
+       SW.NZ   %1,%0   ; cmov"
12687
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12688
+;
12689
+;
12690
+(define_insn "cmov_lt"
12691
+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")
12692
+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))
12693
+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")
12694
+                       (match_dup 0)))]
12695
+       ""
12696
+       "@
12697
+       MOV.LT  %1,%0   ; cmov
12698
+       LW.LT   %1,%0   ; cmov
12699
+       LDI.LT  %1,%0   ; cmov
12700
+       SW.LT   %1,%0   ; cmov"
12701
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12702
+;
12703
+;
12704
+(define_insn "cmov_ge"
12705
+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")
12706
+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))
12707
+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")
12708
+                       (match_dup 0)))]
12709
+       ""
12710
+       "@
12711
+       MOV.GE  %1,%0   ; cmov
12712
+       LW.GE   %1,%0   ; cmov
12713
+       LDI.GE  %1,%0   ; cmov
12714
+       SW.GE   %1,%0   ; cmov"
12715
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12716
+;
12717
+;
12718
+(define_insn "cmov_ltu"
12719
+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")
12720
+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))
12721
+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")
12722
+                       (match_dup 0)))]
12723
+       ""
12724
+       "@
12725
+       MOV.C   %1,%0   ; cmov
12726
+       LW.C    %1,%0   ; cmov
12727
+       LDI.C   %1,%0   ; cmov
12728
+       SW.C    %1,%0   ; cmov"
12729
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12730
+;
12731
+;
12732
+(define_insn "cmov_geu"
12733
+       [(set (match_operand:SI 0 "register_operand" "=r,r,r,Q")
12734
+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))
12735
+                       (match_operand:SI 1 "general_operand" "r,Q,i,r")
12736
+                       (match_dup 0)))]
12737
+       ""
12738
+       "@
12739
+       MOV.NC  %1,%0   ; cmov
12740
+       LW.NC   %1,%0   ; cmov
12741
+       LDI.NC  %1,%0   ; cmov
12742
+       SW.NC   %1,%0   ; cmov"
12743
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12744
+;
12745
+;
12746
+; Conditional add instructions
12747
+;
12748
+;
12749
+;
12750
+;
12751
+(define_insn "cadd_eq"
12752
+       [(set (match_operand:SI 0 "register_operand" "=r")
12753
+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))
12754
+                       (plus:SI (match_dup 0)
12755
+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
12756
+                       (match_dup 0)))]
12757
+       ""
12758
+       "ADD.Z  %1,%0   ; cadd"
12759
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12760
+;
12761
+;
12762
+(define_insn "cadd_ne"
12763
+       [(set (match_operand:SI 0 "register_operand" "=r")
12764
+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))
12765
+                       (plus:SI (match_dup 0)
12766
+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
12767
+                       (match_dup 0)))]
12768
+       ""
12769
+       "ADD.NZ %1,%0   ; cadd"
12770
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12771
+;
12772
+;
12773
+(define_insn "cadd_lt"
12774
+       [(set (match_operand:SI 0 "register_operand" "=r")
12775
+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))
12776
+                       (plus:SI (match_dup 0)
12777
+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
12778
+                       (match_dup 0)))]
12779
+       ""
12780
+       "ADD.LT %1,%0   ; cadd"
12781
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12782
+;
12783
+;
12784
+(define_insn "cadd_ge"
12785
+       [(set (match_operand:SI 0 "register_operand" "=r")
12786
+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))
12787
+                       (plus:SI (match_dup 0)
12788
+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
12789
+                       (match_dup 0)))]
12790
+       ""
12791
+       "ADD.GE %1,%0   ; cadd"
12792
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12793
+;
12794
+;
12795
+(define_insn "cadd_ltu"
12796
+       [(set (match_operand:SI 0 "register_operand" "=r")
12797
+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))
12798
+                       (plus:SI (match_dup 0)
12799
+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
12800
+                       (match_dup 0)))]
12801
+       ""
12802
+       "ADD.C  %1,%0   ; cadd"
12803
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12804
+;
12805
+;
12806
+(define_insn "cadd_geu"
12807
+       [(set (match_operand:SI 0 "register_operand" "=r")
12808
+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))
12809
+                       (plus:SI (match_dup 0)
12810
+                               (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
12811
+                       (match_dup 0)))]
12812
+       ""
12813
+       "ADD.NC %1,%0   ; cadd"
12814
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12815
+;
12816
+;
12817
+; Conditional negate instructions
12818
+;
12819
+;
12820
+;
12821
+;
12822
+(define_insn "cneg_eq"
12823
+       [(set (match_operand:SI 0 "register_operand" "+r")
12824
+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))
12825
+                       (neg:SI (match_dup 0))
12826
+                       (match_dup 0)))]
12827
+       ""
12828
+       "NEG.Z  %0      ; cneg"
12829
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12830
+;
12831
+;
12832
+(define_insn "cneg_ne"
12833
+       [(set (match_operand:SI 0 "register_operand" "+r")
12834
+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))
12835
+                       (neg:SI (match_dup 0))
12836
+                       (match_dup 0)))]
12837
+       ""
12838
+       "NEG.NZ %0      ; cneg"
12839
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12840
+;
12841
+;
12842
+(define_insn "cneg_lt"
12843
+       [(set (match_operand:SI 0 "register_operand" "+r")
12844
+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))
12845
+                       (neg:SI (match_dup 0))
12846
+                       (match_dup 0)))]
12847
+       ""
12848
+       "NEG.LT %0      ; cneg"
12849
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12850
+;
12851
+;
12852
+(define_insn "cneg_ge"
12853
+       [(set (match_operand:SI 0 "register_operand" "+r")
12854
+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))
12855
+                       (neg:SI (match_dup 0))
12856
+                       (match_dup 0)))]
12857
+       ""
12858
+       "NEG.GE %0      ; cneg"
12859
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12860
+;
12861
+;
12862
+(define_insn "cneg_ltu"
12863
+       [(set (match_operand:SI 0 "register_operand" "+r")
12864
+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))
12865
+                       (neg:SI (match_dup 0))
12866
+                       (match_dup 0)))]
12867
+       ""
12868
+       "NEG.C  %0      ; cneg"
12869
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12870
+;
12871
+;
12872
+(define_insn "cneg_geu"
12873
+       [(set (match_operand:SI 0 "register_operand" "+r")
12874
+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))
12875
+                       (neg:SI (match_dup 0))
12876
+                       (match_dup 0)))]
12877
+       ""
12878
+       "NEG.NC %0      ; cneg"
12879
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12880
+;
12881
+;
12882
+; Conditional not instructions
12883
+;
12884
+;
12885
+;
12886
+;
12887
+(define_insn "cnot_eq"
12888
+       [(set (match_operand:SI 0 "register_operand" "=r")
12889
+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))
12890
+                       (xor:SI (match_dup 0)
12891
+                               (const_int -1))
12892
+                       (match_dup 0)))]
12893
+       ""
12894
+       "NOT.Z  %0      ; cnot"
12895
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12896
+;
12897
+;
12898
+(define_insn "cnot_ne"
12899
+       [(set (match_operand:SI 0 "register_operand" "=r")
12900
+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))
12901
+                       (xor:SI (match_dup 0)
12902
+                               (const_int -1))
12903
+                       (match_dup 0)))]
12904
+       ""
12905
+       "NOT.NZ %0      ; cnot"
12906
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12907
+;
12908
+;
12909
+(define_insn "cnot_lt"
12910
+       [(set (match_operand:SI 0 "register_operand" "=r")
12911
+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))
12912
+                       (xor:SI (match_dup 0)
12913
+                               (const_int -1))
12914
+                       (match_dup 0)))]
12915
+       ""
12916
+       "NOT.LT %0      ; cnot"
12917
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12918
+;
12919
+;
12920
+(define_insn "cnot_ge"
12921
+       [(set (match_operand:SI 0 "register_operand" "=r")
12922
+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))
12923
+                       (xor:SI (match_dup 0)
12924
+                               (const_int -1))
12925
+                       (match_dup 0)))]
12926
+       ""
12927
+       "NOT.GE %0      ; cnot"
12928
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12929
+;
12930
+;
12931
+(define_insn "cnot_ltu"
12932
+       [(set (match_operand:SI 0 "register_operand" "=r")
12933
+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))
12934
+                       (xor:SI (match_dup 0)
12935
+                               (const_int -1))
12936
+                       (match_dup 0)))]
12937
+       ""
12938
+       "NOT.C  %0      ; cnot"
12939
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12940
+;
12941
+;
12942
+(define_insn "cnot_geu"
12943
+       [(set (match_operand:SI 0 "register_operand" "=r")
12944
+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))
12945
+                       (xor:SI (match_dup 0)
12946
+                               (const_int -1))
12947
+                       (match_dup 0)))]
12948
+       ""
12949
+       "NOT.NC %0      ; cnot"
12950
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12951
+;
12952
+;
12953
+; Conditional and instructions
12954
+;
12955
+;
12956
+;
12957
+;
12958
+(define_insn "cand_eq"
12959
+       [(set (match_operand:SI 0 "register_operand" "+r")
12960
+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))
12961
+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
12962
+                       (match_dup 0)))]
12963
+       ""
12964
+       "AND.Z  %1,%0   ; cand"
12965
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12966
+;
12967
+;
12968
+(define_insn "cand_ne"
12969
+       [(set (match_operand:SI 0 "register_operand" "+r")
12970
+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))
12971
+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
12972
+                       (match_dup 0)))]
12973
+       ""
12974
+       "AND.NZ %1,%0   ; cand"
12975
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12976
+;
12977
+;
12978
+(define_insn "cand_lt"
12979
+       [(set (match_operand:SI 0 "register_operand" "+r")
12980
+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))
12981
+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
12982
+                       (match_dup 0)))]
12983
+       ""
12984
+       "AND.LT %1,%0   ; cand"
12985
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12986
+;
12987
+;
12988
+(define_insn "cand_ge"
12989
+       [(set (match_operand:SI 0 "register_operand" "+r")
12990
+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))
12991
+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
12992
+                       (match_dup 0)))]
12993
+       ""
12994
+       "AND.GE %1,%0   ; cand"
12995
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
12996
+;
12997
+;
12998
+(define_insn "cand_ltu"
12999
+       [(set (match_operand:SI 0 "register_operand" "+r")
13000
+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))
13001
+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13002
+                       (match_dup 0)))]
13003
+       ""
13004
+       "AND.C  %1,%0   ; cand"
13005
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13006
+;
13007
+;
13008
+(define_insn "cand_geu"
13009
+       [(set (match_operand:SI 0 "register_operand" "+r")
13010
+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))
13011
+                       (and:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13012
+                       (match_dup 0)))]
13013
+       ""
13014
+       "AND.NC %1,%0   ; cand"
13015
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13016
+;
13017
+;
13018
+; Conditional ior instructions
13019
+;
13020
+;
13021
+;
13022
+;
13023
+(define_insn "cior_eq"
13024
+       [(set (match_operand:SI 0 "register_operand" "+r")
13025
+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))
13026
+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13027
+                       (match_dup 0)))]
13028
+       ""
13029
+       "OR.Z   %1,%0   ; cior"
13030
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13031
+;
13032
+;
13033
+(define_insn "cior_ne"
13034
+       [(set (match_operand:SI 0 "register_operand" "+r")
13035
+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))
13036
+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13037
+                       (match_dup 0)))]
13038
+       ""
13039
+       "OR.NZ  %1,%0   ; cior"
13040
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13041
+;
13042
+;
13043
+(define_insn "cior_lt"
13044
+       [(set (match_operand:SI 0 "register_operand" "+r")
13045
+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))
13046
+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13047
+                       (match_dup 0)))]
13048
+       ""
13049
+       "OR.LT  %1,%0   ; cior"
13050
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13051
+;
13052
+;
13053
+(define_insn "cior_ge"
13054
+       [(set (match_operand:SI 0 "register_operand" "+r")
13055
+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))
13056
+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13057
+                       (match_dup 0)))]
13058
+       ""
13059
+       "OR.GE  %1,%0   ; cior"
13060
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13061
+;
13062
+;
13063
+(define_insn "cior_ltu"
13064
+       [(set (match_operand:SI 0 "register_operand" "+r")
13065
+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))
13066
+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13067
+                       (match_dup 0)))]
13068
+       ""
13069
+       "OR.C   %1,%0   ; cior"
13070
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13071
+;
13072
+;
13073
+(define_insn "cior_geu"
13074
+       [(set (match_operand:SI 0 "register_operand" "+r")
13075
+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))
13076
+                       (ior:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13077
+                       (match_dup 0)))]
13078
+       ""
13079
+       "OR.NC  %1,%0   ; cior"
13080
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13081
+;
13082
+;
13083
+; Conditional xor instructions
13084
+;
13085
+;
13086
+;
13087
+;
13088
+(define_insn "cxor_eq"
13089
+       [(set (match_operand:SI 0 "register_operand" "+r")
13090
+               (if_then_else:SI (eq (reg:CC CC_REG) (const_int 0))
13091
+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13092
+                       (match_dup 0)))]
13093
+       ""
13094
+       "XOR.Z  %1,%0   ; cxor"
13095
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13096
+;
13097
+;
13098
+(define_insn "cxor_ne"
13099
+       [(set (match_operand:SI 0 "register_operand" "+r")
13100
+               (if_then_else:SI (ne (reg:CC CC_REG) (const_int 0))
13101
+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13102
+                       (match_dup 0)))]
13103
+       ""
13104
+       "XOR.NZ %1,%0   ; cxor"
13105
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13106
+;
13107
+;
13108
+(define_insn "cxor_lt"
13109
+       [(set (match_operand:SI 0 "register_operand" "+r")
13110
+               (if_then_else:SI (lt (reg:CC CC_REG) (const_int 0))
13111
+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13112
+                       (match_dup 0)))]
13113
+       ""
13114
+       "XOR.LT %1,%0   ; cxor"
13115
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13116
+;
13117
+;
13118
+(define_insn "cxor_ge"
13119
+       [(set (match_operand:SI 0 "register_operand" "+r")
13120
+               (if_then_else:SI (ge (reg:CC CC_REG) (const_int 0))
13121
+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13122
+                       (match_dup 0)))]
13123
+       ""
13124
+       "XOR.GE %1,%0   ; cxor"
13125
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13126
+;
13127
+;
13128
+(define_insn "cxor_ltu"
13129
+       [(set (match_operand:SI 0 "register_operand" "+r")
13130
+               (if_then_else:SI (ltu (reg:CC CC_REG) (const_int 0))
13131
+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13132
+                       (match_dup 0)))]
13133
+       ""
13134
+       "XOR.C  %1,%0   ; cxor"
13135
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13136
+;
13137
+;
13138
+(define_insn "cxor_geu"
13139
+       [(set (match_operand:SI 0 "register_operand" "+r")
13140
+               (if_then_else:SI (geu (reg:CC CC_REG) (const_int 0))
13141
+                       (xor:SI (match_dup 0) (match_operand:SI 1 "zip_opb_single_operand_p" "rO"))
13142
+                       (match_dup 0)))]
13143
+       ""
13144
+       "XOR.NC %1,%0   ; cxor"
13145
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
13146
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-peephole.md gcc-6.2.0-zip/gcc/config/zip/zip-peephole.md
13147
--- gcc-6.2.0/gcc/config/zip/zip-peephole.md    1969-12-31 19:00:00.000000000 -0500
13148
+++ gcc-6.2.0-zip/gcc/config/zip/zip-peephole.md        2017-03-01 15:46:02.440221158 -0500
13149
@@ -0,0 +1,768 @@
13150
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13151
+;;
13152
+;; Filename:   zip-peephole.md
13153
+;;
13154
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
13155
+;;
13156
+;; Purpose:    This is a machine description of a variety of peephole
13157
+;;             optimizations which can be applied to the ZipCPU RTL
13158
+;;     representation.
13159
+;;
13160
+;;
13161
+;; Creator:    Dan Gisselquist, Ph.D.
13162
+;;             Gisselquist Technology, LLC
13163
+;;
13164
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13165
+;;
13166 202 dgisselq
+;; Copyright (C) 2015,2017, Gisselquist Technology, LLC
13167
+;;
13168
+;; This program is free software (firmware): you can redistribute it and/or
13169
+;; modify it under the terms of  the GNU General Public License as published
13170 200 dgisselq
+;; by the Free Software Foundation, either version 3 of the License, or (at
13171
+;; your option) any later version.
13172
+;;
13173
+;; This program is distributed in the hope that it will be useful, but WITHOUT
13174
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
13175
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13176
+;; for more details.
13177
+;;
13178
+;; License:    GPL, v3, as defined and found on www.gnu.org,
13179
+;;             http://www.gnu.org/licenses/gpl.html
13180
+;;
13181
+;;
13182
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13183
+;;
13184
+;
13185
+;
13186 202 dgisselq
+;
13187 200 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13188
+;;
13189
+;; Peephole optimizations
13190
+;;
13191
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
13192
+;
13193
+;
13194
+;
13195
+;
13196
+;
13197
+; Match:
13198
+;      CMP     R1,R0
13199
+;      BGTU    lbl
13200
+; Transform to:
13201
+;      CMP     R0,R1
13202
+;      BC      lbl
13203
+;
13204
+(define_peephole2
13205
+       [(set (reg:CC CC_REG) (compare:CC
13206
+               (match_operand:SI 0 "register_operand")
13207
+               (match_operand:SI 1 "register_operand")))
13208
+       (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
13209
+                       (label_ref (match_operand 2 ""))
13210
+                       (pc)))]
13211
+       "(ZIP_PEEPHOLE)"
13212
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 1) (match_dup 0)))
13213
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
13214
+                       (label_ref (match_dup 2))
13215
+                       (pc)))]
13216
+       "")
13217 124 dgisselq
+(define_peephole2
13218
+       [(match_scratch:SI 3 "=r")
13219
+       (set (reg:CC CC_REG) (compare:CC
13220
+               (match_operand:SI 0 "register_operand")
13221
+               (match_operand 1 "const_int_operand")))
13222
+       (match_dup 3)
13223
+       (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
13224 117 dgisselq
+                       (label_ref (match_operand 2 ""))
13225 122 dgisselq
+                       (pc)))]
13226
+       "(ZIP_PEEPHOLE)"
13227
+       [(set (match_dup 3) (match_dup 1))
13228
+       (set (reg:CC CC_REG) (compare:CC (match_dup 3) (match_dup 0)))
13229
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
13230 117 dgisselq
+                       (label_ref (match_dup 2))
13231 127 dgisselq
+                       (pc)))]
13232 122 dgisselq
+       "")
13233
+;(define_peephole2
13234 117 dgisselq
+;      [(set (reg:CC CC_REG) (compare:CC
13235
+;              (match_operand:SI 0 "register_operand")
13236
+;              (match_operand 1 "const_int_operand")))
13237 127 dgisselq
+;      (set (pc) (if_then_else (gtu (reg:CC CC_REG) (const_int 0))
13238
+;                      (label_ref (match_operand 2 ""))
13239
+;                      (pc)))]
13240
+;      ""
13241
+;      [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
13242
+;      (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
13243
+;                      (label_ref (match_dup 2))
13244
+;                      (pc)))]
13245
+;      "operands[1] = GEN_INT(INTVAL(operands[1])-1);")
13246
+;
13247
+;
13248
+; Match:
13249
+;      CMP     R1,R0
13250
+;      BGEU    lbl
13251
+; Transform to:
13252
+;      CMP     1(R0),R1
13253
+;      BC      lbl
13254
+;
13255
+(define_peephole2
13256
+       [(set (reg:CC CC_REG) (compare:CC
13257
+               (match_operand:SI 0 "register_operand")
13258
+               (match_operand:SI 1 "register_operand")))
13259
+       (set (pc) (if_then_else (geu (reg:CC CC_REG) (const_int 0))
13260
+                       (label_ref (match_operand 2 ""))
13261
+                       (pc)))]
13262
+       "(ZIP_PEEPHOLE)"
13263
+       [(set (reg:CC CC_REG) (compare:CC
13264
+               (match_dup 1) (plus:SI (match_dup 0) (const_int 1))))
13265
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
13266 124 dgisselq
+                       (label_ref (match_dup 2))
13267
+                       (pc)))]
13268
+       "")
13269
+;
13270
+;
13271
+; Match:
13272
+;      CMP     R1,R0
13273
+;      BGE     lbl
13274
+; Transform to:
13275 117 dgisselq
+;      CMP     1(R0),R1
13276 122 dgisselq
+;      BLT     lbl
13277
+; ... why?  when we support a BGE instruction?
13278
+;(define_peephole2
13279
+       ;[(set (reg:CC CC_REG) (compare:CC
13280
+               ;(match_operand:SI 0 "register_operand")
13281 117 dgisselq
+               ;(match_operand:SI 1 "register_operand")))
13282 127 dgisselq
+       ;(set (pc) (if_then_else (ge (reg:CC CC_REG) (const_int 0))
13283 122 dgisselq
+                       ;(label_ref (match_operand 2 ""))
13284 146 dgisselq
+                       ;(pc)))]
13285 122 dgisselq
+       ;"(ZIP_PEEPHOLE)"
13286 117 dgisselq
+       ;[(set (reg:CC CC_REG) (compare:CC (match_dup 1)
13287
+                       ;(plus:SI (match_dup 0) (const_int 1))))
13288
+       ;(set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
13289 124 dgisselq
+                       ;(label_ref (match_dup 2))
13290
+                       ;(pc)))]
13291
+       ;"")
13292
+;
13293
+;
13294
+; Match:
13295
+;      CMP     R1,R0
13296
+;      BLEU    lbl
13297 142 dgisselq
+; Transform to:
13298
+;      CMP     1(R1),R0
13299
+;      BC      lbl
13300
+;
13301
+(define_peephole2
13302
+       [(set (reg:CC CC_REG) (compare:CC
13303
+               (match_operand:SI 0 "register_operand" "")
13304
+               (match_operand:SI 1 "register_operand" "")))
13305
+       (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
13306
+                       (label_ref (match_operand 2 "" ""))
13307
+                       (pc)))]
13308
+       "(ZIP_PEEPHOLE)"
13309
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
13310
+                       (plus:SI (match_dup 1) (const_int 1))))
13311
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
13312 124 dgisselq
+                       (label_ref (match_dup 2))
13313
+                       (pc)))]
13314
+       "")
13315
+;
13316
+;
13317
+;
13318
+; Match:
13319 142 dgisselq
+;      CMP     R1,R0
13320 124 dgisselq
+;      BLE     lbl
13321 117 dgisselq
+; Transform to:
13322 122 dgisselq
+;      CMP     1(R1),R0
13323
+;      BLT     lbl
13324 117 dgisselq
+;
13325 122 dgisselq
+(define_peephole2
13326 117 dgisselq
+       [(set (reg:CC CC_REG)
13327
+               (compare:CC (match_operand:SI 0 "register_operand" "")
13328 127 dgisselq
+                       (match_operand:SI 1 "const_int_operand" "")))
13329 122 dgisselq
+       (set (pc) (if_then_else (le (reg:CC CC_REG) (const_int 0))
13330 146 dgisselq
+                       (label_ref (match_operand 2 "" ""))
13331 122 dgisselq
+                       (pc)))]
13332 117 dgisselq
+       "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))"
13333
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
13334
+       (set (pc) (if_then_else (lt (reg:CC CC_REG) (const_int 0))
13335
+                       (label_ref (match_dup 2))
13336 142 dgisselq
+                       (pc)))]
13337
+       "operands[1] = GEN_INT(INTVAL(operands[1])+1);")
13338
+;
13339
+; Match:
13340
+;      CMP     R1,R0
13341
+;      BLEU    lbl
13342
+; Transform to:
13343
+;      CMP     1(R1),R0
13344
+;      BC(LTU) lbl
13345 127 dgisselq
+;
13346
+(define_peephole2
13347
+       [(set (reg:CC CC_REG)
13348
+               (compare:CC (match_operand:SI 0 "register_operand" "")
13349
+                       (match_operand:SI 1 "const_int_operand" "")))
13350
+       (set (pc) (if_then_else (leu (reg:CC CC_REG) (const_int 0))
13351
+                       (label_ref (match_operand 2 "" ""))
13352
+                       (pc)))]
13353
+       "(ZIP_PEEPHOLE)&&(INTVAL(operands[1])<((1<<17)-2))"
13354
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0) (match_dup 1)))
13355
+       (set (pc) (if_then_else (ltu (reg:CC CC_REG) (const_int 0))
13356
+                       (label_ref (match_dup 2))
13357
+                       (pc)))]
13358 142 dgisselq
+       "operands[1] = GEN_INT(INTVAL(operands[1])+1);")
13359
+;
13360
+;
13361
+;
13362
+;
13363
+; Match:
13364
+;      (parallel [(set () ()) (clobber (CC))])
13365
+;      (compare () ())
13366 127 dgisselq
+; Transform to:
13367
+;      (parallel [(set () ()) (set (CC) (0))]
13368
+;      (compare () ())
13369
+;
13370
+(define_peephole2
13371
+       [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 ""))
13372
+               (clobber (reg:CC CC_REG))])
13373
+       (set (reg:CC CC_REG) (compare:CC (match_operand:SI 2 "")
13374
+                       (match_operand:SI 3 "")))]
13375 142 dgisselq
+       "(ZIP_PEEPHOLE)&&zip_insn_sets_cc(insn)"
13376 127 dgisselq
+       [(parallel [(set (match_dup 0) (match_dup 1))
13377
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13378
+       (set (reg:CC CC_REG) (compare:CC (match_dup 2) (match_dup 3)))]
13379 102 dgisselq
+       "")
13380 117 dgisselq
+;
13381
+;
13382
+;
13383 127 dgisselq
+; Match:
13384
+;      (parallel [(set () ()) (clobber (CC))])
13385
+;      (set () ())
13386
+;      (compare () ())
13387
+; Transform to:
13388
+;      (parallel [(set () ()) (set (CC) (0))]
13389 117 dgisselq
+;      (set () ())
13390 127 dgisselq
+;      (compare () ())
13391
+;
13392
+(define_peephole2
13393
+       [(parallel [(set (match_operand:SI 0 "") (match_operand:SI 1 ""))
13394
+               (clobber (reg:CC CC_REG))])
13395
+       (set (match_operand 2 "") (match_operand 3 ""))
13396
+       (set (reg:CC CC_REG) (compare:CC (match_operand:SI 4 "")
13397
+                       (match_operand:SI 5 "")))]
13398
+       "(ZIP_PEEPHOLE)&&(zip_insn_sets_cc(insn))&&((!REG_P(operands[2]))||(REGNO(operands[2])!=CC_REG))"
13399
+       [(parallel [(set (match_dup 0) (match_dup 1))
13400
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13401
+       (set (match_dup 2) (match_dup 3))
13402
+       (set (reg:CC CC_REG) (compare:CC (match_dup 4) (match_dup 5)))]
13403 122 dgisselq
+       "")
13404 127 dgisselq
+;
13405
+;
13406
+;
13407
+; Match:
13408
+;      MOV A(R1),R3
13409
+;      CMP R3,R0
13410
+;      (R3 is dead)
13411
+; Transform to:
13412
+;      CMP A(R1),R0
13413
+;
13414
+(define_peephole2
13415
+       [(set (match_operand:SI 3 "register_operand")
13416
+               (plus:SI (match_operand:SI 1 "register_operand")
13417
+                       (match_operand:SI 2 "zip_mvimm_operand_p")))
13418
+       (set (reg:CC CC_REG)
13419
+               (compare:CC (match_operand:SI 0 "register_operand")
13420
+                       (match_dup 3)))]
13421
+       "(ZIP_PEEPHOLE)&&peep2_regno_dead_p(2, REGNO(operands[3]))"
13422
+       [(set (reg:CC CC_REG) (compare:CC (match_dup 0)
13423
+               (plus:SI (match_dup 1) (match_dup 2))))]
13424
+       "")
13425
+;
13426
+;
13427
+; Match:
13428 122 dgisselq
+;      ALU OpB,R0
13429
+;      CMP 0,R0
13430
+; Transform to:
13431
+;      ALU OpB,R0
13432
+;
13433
+(define_peephole2
13434
+       [(parallel [(set (match_operand:SI 0 "register_operand")
13435
+                       (match_operand:SI 1 ""))
13436
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13437
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
13438
+       "(ZIP_PEEPHOLE)"
13439
+       [(parallel [(set (match_dup 0) (match_dup 1))
13440
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13441 127 dgisselq
+       ])
13442 122 dgisselq
+;
13443
+;
13444
+; Match:
13445
+;      ALU OpB,R0
13446
+;      MOV R1,R2       // Can be LDI, LOD, STO, etc.
13447
+;      CMP 0,R0
13448
+; Transform to:
13449
+;      ALU OpB,R0
13450
+;      MOV R0,R1
13451
+;
13452
+(define_peephole2
13453
+       [(parallel [(set (match_operand:SI 0 "register_operand")
13454 124 dgisselq
+                       (match_operand:SI 1 ""))
13455
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13456 122 dgisselq
+       (set (match_operand:SI 2 "nonimmediate_operand") (match_operand:SI 3 ""))
13457
+       (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))]
13458 127 dgisselq
+       "(ZIP_PEEPHOLE)&&((!REG_P(operands[2]))||((REGNO(operands[2])!=REGNO(operands[0]))&&((REGNO(operands[2])>=FIRST_PSEUDO_REGISTER)||(REGNO(operands[2])<CC_REG))))"
13459 122 dgisselq
+       [(parallel [(set (match_dup 0) (match_dup 1))
13460
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13461
+       (set (match_dup 2) (match_dup 3))
13462
+       ])
13463
+;
13464
+;
13465
+; Match:
13466
+;      ALU OpB,R0
13467 127 dgisselq
+;      MOV R0,R1
13468 122 dgisselq
+;      CMP 0,R1
13469
+; Transform to:
13470
+;      ALU OpB,R0
13471
+;      MOV R0,R1
13472
+;
13473 124 dgisselq
+(define_peephole2
13474
+       [(parallel [(set (match_operand:SI 0 "register_operand")
13475 122 dgisselq
+                       (match_operand:SI 1 ""))
13476 124 dgisselq
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13477 122 dgisselq
+       (set (match_operand:SI 2 "register_operand") (match_dup 0))
13478 127 dgisselq
+       (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))]
13479 122 dgisselq
+       "(ZIP_PEEPHOLE)"
13480
+       [(parallel [(set (match_dup 0) (match_dup 1))
13481
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13482
+       (set (match_dup 2) (match_dup 3))
13483
+       ])
13484
+;
13485
+;
13486
+; Match:
13487
+;      MOV R1,R0
13488
+;      ADD $x,R0
13489
+;      (CCREG is dead, and x is within range ...)
13490
+; Transform to:
13491
+;      MOV $x(R1),R0
13492
+(define_peephole2
13493
+       [(set (match_operand:SI 0 "register_operand")
13494 124 dgisselq
+               (match_operand:SI 1 "register_operand"))
13495
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0)
13496 122 dgisselq
+                               (match_operand 2 "zip_mvimm_operand_p")))
13497 124 dgisselq
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13498 122 dgisselq
+       ]
13499 127 dgisselq
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))"
13500 122 dgisselq
+       [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
13501
+;
13502
+; Match:
13503
+;      MOV A(R0),R0
13504
+;      ADD $x,R1
13505 124 dgisselq
+;      (CCREG is dead, and (A+x) is within range ...)
13506
+; Transform to:
13507
+;      MOV $x(R1),R0
13508
+;
13509
+(define_peephole2
13510
+       [(set (match_operand:SI 0 "register_operand")
13511 127 dgisselq
+               (plus:SI (match_operand:SI 1 "register_operand")
13512 124 dgisselq
+                       (match_operand 2 "zip_mvimm_operand_p")))
13513
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0)
13514
+                               (match_operand 3 "zip_mvimm_operand_p")))
13515
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13516
+       ]
13517
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))
13518
+               &&(INTVAL(operands[2])+INTVAL(operands[3])<((1<<17)))
13519 127 dgisselq
+               &&(INTVAL(operands[2])+INTVAL(operands[3])>=-(1<<17))"
13520 124 dgisselq
+       [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
13521
+       "operands[2]=GEN_INT(INTVAL(operands[2])+INTVAL(operands[3]));")
13522 127 dgisselq
+;
13523
+;
13524
+;
13525
+; Match:
13526
+;      ADD $x,R0
13527
+;      MOV R0,R1
13528 124 dgisselq
+;      (CCREG is dead, and R0 is dead)
13529 127 dgisselq
+; Transform to:
13530
+;      MOV (A+$x)(R0),R1
13531
+; ... again, how do I build this plus?
13532
+;
13533
+(define_peephole2
13534
+       [(parallel [(set (match_operand:SI 0 "register_operand")
13535
+                       (plus:SI (match_dup 0)
13536
+                               (match_operand 1 "zip_mvimm_operand_p")))
13537
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13538
+       (set (match_operand:SI 2 "register_operand") (match_dup 0))]
13539
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2, REGNO(operands[0])))&&(peep2_regno_dead_p(2,CC_REG))"
13540
+       [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))])
13541
+;
13542 124 dgisselq
+;
13543 127 dgisselq
+;
13544
+; Match:
13545 124 dgisselq
+;      ADD $x,R0
13546
+;      MOV A(R0),R1
13547
+;      (CCREG is dead, and R0 is dead)
13548
+; Transform to:
13549
+;      MOV (A+$x)(R0),R1
13550
+;
13551
+(define_peephole2
13552
+       [(parallel [
13553
+               (set (match_operand:SI 0 "register_operand")
13554
+                       (plus:SI (match_dup 0)
13555
+                               (match_operand 1 "zip_mvimm_operand_p")))
13556
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13557
+       (set (match_operand:SI 2 "register_operand")
13558
+               (plus:SI (match_dup 0)
13559 127 dgisselq
+                       (match_operand 3 "zip_mvimm_operand_p")))
13560 124 dgisselq
+       ]
13561
+       "(ZIP_PEEPHOLE)&&(peep2_regno_dead_p(2,CC_REG))
13562
+               &&(peep2_regno_dead_p(1,REGNO(operands[0])))
13563 127 dgisselq
+               &&(INTVAL(operands[1])+INTVAL(operands[3])<((1<<17)))
13564 124 dgisselq
+               &&(INTVAL(operands[1])+INTVAL(operands[3])>=-(1<<17))"
13565 127 dgisselq
+       [(set (match_dup 0) (plus:SI (match_dup 2) (match_dup 3)))]
13566
+       "operands[3]=GEN_INT(INTVAL(operands[1])+INTVAL(operands[3]));")
13567
+;
13568
+;
13569
+;
13570
+; Match:
13571
+;      ADD     $x,R0
13572
+;      ADD     R0,Rn
13573
+;      (R0 is dead, if R0 is not Rn)
13574
+; Transform to:
13575
+;      ADD     $x(R0),Rn
13576
+;
13577
+(define_peephole2
13578
+       [(parallel [(set (match_operand:SI 0 "register_operand")
13579
+                       (plus:SI (match_dup 0)
13580
+                               (match_operand 1 "zip_opb_immv_p")))
13581
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13582
+       (parallel [(set (match_operand:SI 2 "register_operand")
13583
+                       (plus:SI (match_dup 2) (match_dup 0)))
13584
+               (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
13585
+       ]
13586
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[2]))&&(peep2_regno_dead_p(2, REGNO(operands[0])))"
13587
+       [(parallel [(set (match_dup 2)
13588
+                       (plus:SI (match_dup 2)
13589
+                               (plus:SI (match_dup 0)
13590
+                                       (match_dup 1))))
13591 124 dgisselq
+               (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0)))])
13592
+       ])
13593
+;
13594
+; Match:
13595
+;      ADD     $x,R0
13596
+;      LOD     -x(R0),R1
13597
+; Transform to:
13598
+;      LOD     (R0),R1
13599
+;      ADD     $x,R0
13600
+;
13601
+(define_peephole2
13602
+       [(parallel [(set (match_operand:SI 0 "register_operand")
13603
+                       (plus:SI (match_dup 0)
13604
+                               (match_operand 1 "zip_opb_immv_p")))
13605
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13606 127 dgisselq
+       (set (match_operand:SI 3 "register_operand")
13607 124 dgisselq
+               (mem:SI (plus:SI (match_dup 0)
13608
+                       (match_operand 2 "zip_opb_immv_p"))))
13609
+       ]
13610
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
13611
+       [(set (match_dup 3) (mem:SI (match_dup 0)))
13612
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
13613
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13614
+       ])
13615
+(define_peephole2
13616
+       [(parallel [(set (match_operand:SI 0 "register_operand")
13617
+                       (plus:SI (match_dup 0)
13618
+                               (match_operand 1 "zip_opb_immv_p")))
13619
+               (clobber (reg:CC CC_REG))])
13620
+       (set (match_operand:SI 3 "register_operand")
13621
+               (mem:SI (plus:SI (match_dup 0)
13622
+                       (match_operand 2 "zip_opb_immv_p"))))
13623
+       ]
13624
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
13625
+       [(set (match_dup 3) (mem:SI (match_dup 0)))
13626
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
13627
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13628
+       ])
13629
+;
13630 127 dgisselq
+;
13631 124 dgisselq
+;
13632
+; Match:
13633
+;      ADD     $x,R0
13634
+;      STO     R1,-x(R0)
13635 127 dgisselq
+; Transform to:
13636
+;      STO     R1,(R0)
13637
+;      ADD     $x,R0
13638
+;
13639
+(define_peephole2
13640
+       [(parallel [(set (match_operand:SI 0 "register_operand")
13641
+                       (plus:SI (match_dup 0)
13642
+                               (match_operand 1 "zip_opb_immv_p")))
13643
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13644
+       (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p")))
13645
+               (match_operand:SI 3 "register_operand"))
13646
+       ]
13647
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
13648
+       [(set (mem:SI (match_dup 0)) (match_dup 3))
13649 124 dgisselq
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
13650
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13651
+       ])
13652
+(define_peephole2
13653
+       [(parallel [(set (match_operand:SI 0 "register_operand")
13654
+                       (plus:SI (match_dup 0)
13655
+                               (match_operand 1 "zip_opb_immv_p")))
13656
+               (clobber (reg:CC CC_REG))])
13657
+       (set (mem:SI (plus:SI (match_dup 0) (match_operand 2 "zip_opb_immv_p")))
13658
+               (match_operand:SI 3 "register_operand"))
13659
+       ]
13660
+       "(ZIP_PEEPHOLE)&&(REGNO(operands[0])!=REGNO(operands[1]))&&(INTVAL(operands[1])==-INTVAL(operands[2]))"
13661
+       [(set (mem:SI (match_dup 0)) (match_dup 3))
13662
+       (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
13663
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13664
+       ])
13665
+;
13666
+;
13667 127 dgisselq
+; Match:
13668 124 dgisselq
+;      ADD     $x,R0
13669
+;      ANY     R1,R2 (destination is not R0, source does not reference R0)
13670
+;      ADD     R0,Rn (could be 1 or 2, not 0)
13671
+;      (R0 is dead)
13672 127 dgisselq
+; Transform to:
13673
+;      ANY     R1,R2
13674
+;      ADD     $x(R0),Rn
13675
+;
13676
+;
13677
+;
13678
+; Match:
13679
+;      MOV     R1,R0
13680
+;      AND     #/R2,R0
13681
+;      (Ry dead ...)
13682
+; Transform to:
13683
+;      TEST    #/Rz,Rx
13684
+;
13685 124 dgisselq
+(define_peephole2
13686
+       [(set (match_operand:SI 0 "register_operand")
13687
+               (match_operand:SI 1 "register_operand"))
13688
+       (parallel [(set (match_operand:SI 3 "register_operand")
13689
+                       (and:SI (match_dup 0)
13690
+                               (match_operand:SI 2 "zip_opb_single_operand_p")))
13691
+               (set (reg:CC CC_REG) (compare:CC (match_dup 0) (const_int 0)))])
13692
+       ]
13693
+       "((1)||(ZIP_PEEPHOLE))&&(peep2_regno_dead_p(2, REGNO(operands[0])))&&(peep2_regno_dead_p(2, REGNO(operands[3])))"
13694
+       [(set (reg:CC CC_REG) (compare:CC (and:SI (match_dup 1) (match_dup 2))
13695
+                       (const_int 0)))])
13696
+;
13697
+;
13698 127 dgisselq
+; Match:
13699
+;      LB OpB,Rx
13700
+;      AND 255,Rx      (in form of zero_extend)
13701
+; Transform to:
13702
+;      LB OpB,Rx
13703
+;
13704 124 dgisselq
+;
13705 127 dgisselq
+(define_peephole2
13706
+       [(set (match_operand:QI 0 "register_operand")
13707
+               (match_operand:QI 1 "memory_operand"))
13708 202 dgisselq
+       (parallel [(set (match_operand:SI 2 "register_operand")
13709 127 dgisselq
+                       (zero_extend:SI (match_dup 0)))
13710
+               (clobber (reg:CC CC_REG))])]
13711
+       "((1)||(ZIP_PEEPHOLE))"
13712
+       [(parallel [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
13713 202 dgisselq
+               (clobber (reg:CC CC_REG))])])
13714
+;
13715 127 dgisselq
+;
13716
+;
13717 202 dgisselq
+; Match:
13718 127 dgisselq
+;      LW OpB,Rx
13719 202 dgisselq
+;      AND 65535,Rx
13720
+; Transform to:
13721
+;      LW OpB,Rx
13722
+;
13723
+;
13724
+(define_peephole2
13725
+       [(set (match_operand:HI 0 "register_operand")
13726
+               (match_operand:HI 1 "memory_operand"))
13727
+       (parallel [(set (match_operand:SI 2 "register_operand")
13728
+                       (zero_extend:SI (match_dup 0)))
13729
+               (clobber (reg:CC CC_REG))])]
13730
+       "((1)||(ZIP_PEEPHOLE))
13731
+               &&(REG_P(operands[0]))
13732
+               &&(REG_P(operands[2]))
13733
+               &&(REGNO(operands[0])==REGNO(operands[2]))"
13734
+       [(parallel [(set (match_dup 2) (zero_extend:SI (match_dup 1)))
13735
+               (clobber (reg:CC CC_REG))])])
13736
+;
13737
+;
13738
+;
13739
+; Match:
13740
+;      LDI 0,Rx
13741
+;      LDI.y #,Rx
13742
+;      Add Rx,Ry
13743
+; Transform to:
13744
+;      Add.y #,Ry
13745
+;
13746
+;
13747
+(define_peephole2
13748
+       [(set (match_operand:SI 0 "register_operand") (const_int 0))
13749
+       (set (match_dup 0)
13750
+               (if_then_else:SI
13751
+                       (match_operator 1 "ordered_comparison_operator"
13752
+                               [(reg:CC CC_REG) (const_int 0)])
13753
+                       (match_operand:SI 2 "zip_opb_single_operand_p") (match_dup 0)))
13754
+       (parallel [
13755
+               (set (match_operand:SI 3 "register_operand")
13756
+                       (plus:SI (match_dup 3) (match_dup 0)))
13757
+               (clobber (reg:CC CC_REG))
13758
+               ])]
13759
+       "((1)||(ZIP_PEEPHOLE))
13760
+               &&(peep2_regno_dead_p(3, REGNO(operands[0])))"
13761
+       [(set (match_dup 3)
13762
+               (if_then_else:SI
13763
+                       (match_op_dup 1 [(reg:CC CC_REG) (const_int 0)])
13764
+                       (plus:SI (match_dup 3) (match_dup 2))
13765
+                       (match_dup 3)))])
13766
+;
13767
+;
13768
+; Match:
13769
+;      LDI     0,Rx
13770
+;      LDI.y   #,Rx
13771
+;      XOR     Rx,Rc
13772
+; Transform to:
13773
+;      XOR.y #,Ry
13774
+;
13775
+;
13776
+(define_peephole2
13777
+       [(set (match_operand:SI 0 "register_operand") (const_int 0))
13778
+       (set (match_dup 0)
13779
+               (if_then_else:SI
13780
+                       (match_operator 1 "ordered_comparison_operator"
13781
+                               [(reg:CC CC_REG) (const_int 0)])
13782
+                       (match_operand:SI 2 "zip_opb_single_operand_p") (match_dup 0)))
13783
+       (parallel [
13784
+               (set (match_operand:SI 3 "register_operand")
13785
+                       (xor:SI (match_dup 3) (match_dup 0)))
13786
+               (clobber (reg:CC CC_REG))
13787
+               ])]
13788
+       "((1)||(ZIP_PEEPHOLE))
13789
+               &&(peep2_regno_dead_p(3, REGNO(operands[0])))"
13790
+       [(set (match_dup 3)
13791
+               (if_then_else:SI
13792
+                       (match_op_dup 1 [(reg:CC CC_REG) (const_int 0)])
13793
+                       (xor:SI (match_dup 3) (match_dup 2))
13794
+                       (match_dup 3)))])
13795
+;
13796
+;
13797
+;
13798
+;
13799
+;
13800
+; Match:
13801
+;      LDI     0,Rx
13802
+;      LDI.y   #,Rx
13803
+;      OR      Rx,Rc
13804
+; Transform to:
13805
+;      OR.y #,Ry
13806
+;
13807
+;
13808
+;
13809
+(define_peephole2
13810
+       [(set (match_operand:SI 0 "register_operand") (const_int 0))
13811
+       (set (match_dup 0)
13812
+               (if_then_else:SI (match_operator 1 "ordered_comparison_operator"
13813
+                               [(reg:CC CC_REG) (const_int 0)])
13814
+                       (match_operand:SI 2 "zip_opb_single_operand_p") (match_dup 0)))
13815
+       (parallel [(set (match_operand:SI 3 "register_operand")
13816
+                       (ior:SI (match_dup 3) (match_dup 0)))
13817
+               (clobber (reg:CC CC_REG))])]
13818
+       "((1)||(ZIP_PEEPHOLE))
13819
+               &&(peep2_regno_dead_p(3, REGNO(operands[0])))"
13820
+       [(set (match_dup 3)
13821
+               (if_then_else:SI
13822
+                       (match_op_dup 1 [(reg:CC CC_REG) (const_int 0)])
13823
+                       (ior:SI (match_dup 3) (match_dup 2))
13824
+                       (match_dup 3)))])
13825
+;
13826
+;
13827
+;
13828
+; Match:
13829
+;      AND 255,Rx
13830
+;      SB OpB,Rx
13831
+;      (AND Rx is DEAD)
13832
+; Transform to:
13833
+;      SB OpB,Rx
13834
+;
13835
+;
13836
+;(define_peephole2
13837
+       ;[(set (match_operand:SI 2 "register_operand")
13838
+               ;(zero_extend:SI (match_operand:SI 0)))
13839
+       ;[(set (match_operand:QI 0 "memory_operand")
13840
+               ;(match_operand:QI 1 "memory_operand"))
13841
+       ;"((1)||(ZIP_PEEPHOLE))"
13842
+       ;[(set (match_dup 2) (zero_extend:SI (match_dup 1)))])
13843
+;
13844
+;
13845
+;
13846
+;
13847
+;
13848
+; Match:
13849
+;      (call ...
13850
+;      (set (pc) (label))
13851
+;  or (in asm)
13852
+;      MOV     .Lcallx(PC),R0
13853
+;      BRA     (somewhere)
13854
+; .Lcallx
13855
+;      BRA     (somewhere-else)
13856
+; Transform to:
13857
+;
13858
+;      (sequence [(call ...
13859
+;              (set (pc) (label))])
13860
+;   or (in asm)
13861
+;      "LDI    (somewhere-else),R0
13862
+;      BRA     subroutine"
13863
+;
13864
+; While the following looks good, it doesnt work.  My guess is that the reason
13865
+; why it doesnt work is that the jump at the end crosses basic block boundaries.
13866
+;
13867
+;(define_insn "void_call_mem_unspec"
13868
+;      [(call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p" ""))] UNSPEC_RAW_CALL)
13869 127 dgisselq
+;                      (match_operand 1 "const_int_operand" "n"))
13870
+;              (clobber (reg:SI RTN_REG))
13871
+;              (clobber (reg:CC CC_REG))]
13872
+;      ""
13873
+;      "BRA\t%0,PC"
13874
+;      [(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
13875
+;(define_peephole2
13876
+;      [(parallel [(call (mem:SI (match_operand:VOID 0 "zip_const_address_operand_p"))
13877
+;                      (match_operand 1 "const_int_operand"))
13878
+;              (clobber (reg:SI RTN_REG))
13879
+;              (clobber (reg:CC CC_REG))])
13880
+;      ; The match operand for the (set (pc) ...) cannot have anything but
13881
+;      ; VOIDmode, or it wont match.
13882
+;      (set (pc) (match_operand:VOID 2 "zip_const_address_operand_p"))]
13883
+;      ""
13884
+;      [(set (reg:SI RTN_REG) (match_dup 2))
13885
+;      (call (unspec:SI [(mem:SI (match_operand:VOID 0 "zip_const_address_operand_p"))] UNSPEC_RAW_CALL)
13886
+;                      (match_operand 1 "const_int_operand"))
13887
+;              (use (reg:SI RTN_REG))
13888
+;              (clobber (reg:SI RTN_REG))
13889
+;              (clobber (reg:CC CC_REG))]
13890
+;      "fprintf(stderr, \"CALL-JUMP Matched\");")
13891
+;
13892
+;
13893
+;
13894
+; So, the following *should* have worked as well.  However, this falls apart
13895
+; because the 'final' routine can't tell if we are calling a subroutine in this
13896
+; function or not.
13897
+;
13898
+;(define_peephole
13899
+       ;[(parallel [(call (mem:SI (match_operand:SI 0 "zip_const_address_operand_p"))
13900
+                       ;(match_operand 1 "const_int_operand"))
13901
+               ;(clobber (reg:SI RTN_REG))
13902
+               ;(clobber (reg:CC CC_REG))])
13903
+       ;(set (pc) (label_ref (match_operand 2 "")))]
13904
+       ;""
13905
+       ;"LDI\t%2,R0\;BRA\t%0"
13906
+       ;[(set_attr "predicable" "no") (set_attr "ccresult" "unknown")])
13907
+;
13908
+; and for
13909
+;      BRA target
13910
+;      BRA target ; two branches to the same identical target in a row ...
13911
+;
13912
+;
13913
+;
13914
+; STILL MISSING:
13915
+;
13916
+;
13917
+;
13918
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-protos.h gcc-6.2.0-zip/gcc/config/zip/zip-protos.h
13919
--- gcc-6.2.0/gcc/config/zip/zip-protos.h       1969-12-31 19:00:00.000000000 -0500
13920
+++ gcc-6.2.0-zip/gcc/config/zip/zip-protos.h   2017-02-17 16:45:53.264117439 -0500
13921
@@ -0,0 +1,82 @@
13922
+////////////////////////////////////////////////////////////////////////////////
13923
+//
13924
+// Filename:   zip-protos.h
13925
+//
13926
+// Project:    Zip CPU backend for the GNU Compiler Collection
13927
+//
13928 124 dgisselq
+// Purpose:
13929
+//
13930
+// Creator:    Dan Gisselquist, Ph.D.
13931
+//             Gisselquist Technology, LLC
13932
+//
13933
+////////////////////////////////////////////////////////////////////////////////
13934 102 dgisselq
+//
13935 200 dgisselq
+// Copyright (C) 2016, Gisselquist Technology, LLC
13936
+//
13937
+// This program is free software (firmware): you can redistribute it and/or
13938 202 dgisselq
+// modify it under the terms of  the GNU General Public License as published
13939
+// by the Free Software Foundation, either version 3 of the License, or (at
13940
+// your option) any later version.
13941
+//
13942 102 dgisselq
+// This program is distributed in the hope that it will be useful, but WITHOUT
13943
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
13944
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13945
+// for more details.
13946
+//
13947
+// You should have received a copy of the GNU General Public License along
13948
+// with this program.  (It's in the $(ROOT)/doc directory, run make with no
13949
+// target there if the PDF file isn't present.)  If not, see
13950
+// <http://www.gnu.org/licenses/> for a copy.
13951
+//
13952
+// License:    GPL, v3, as defined and found on www.gnu.org,
13953
+//             http://www.gnu.org/licenses/gpl.html
13954
+//
13955
+//
13956
+////////////////////////////////////////////////////////////////////////////////
13957
+#ifndef        ZIP_PROTOS_H
13958
+#define        ZIP_PROTOS_H
13959
+
13960
+extern int     zip_supported_condition(int c);
13961
+extern void    zip_expand_prologue(void);
13962
+extern void    zip_expand_epilogue(void);
13963
+extern void    zip_sibcall_epilogue(void);
13964
+extern int     zip_expand_movdi(rtx,rtx);
13965
+extern int     zip_expand_movsicc(rtx,rtx,rtx,rtx);
13966
+extern int     zip_initial_elimination_offset(int, int);
13967
+extern void    zip_print_operand(FILE *, rtx, int);
13968
+extern void    zip_print_operand_address(FILE *, rtx);
13969
+extern enum    reg_class       zip_reg_class(int);
13970
+extern rtx     zip_return_addr_rtx(int, rtx);
13971
+extern int     zip_num_arg_regs(enum machine_mode, tree);
13972
+
13973
+extern void    zip_asm_output_def(FILE *s, const char *n, const char *v);
13974
+
13975
+extern void    zip_canonicalize_comparison(int *, rtx *, rtx *, bool);
13976
+extern bool    zip_function_ok_for_sibcall(tree, tree);
13977
+extern int     zip_address_operand(rtx op);
13978
+extern int     zip_const_address_operand(rtx op);
13979
+extern int     zip_use_return_insn(void);
13980 200 dgisselq
+extern const char *zip_set_zero_or_one(rtx, rtx);
13981 102 dgisselq
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
13982
+
13983 191 dgisselq
+extern int     zip_insn_sets_cc(rtx_insn *insn);
13984 202 dgisselq
+extern int     zip_is_conditional(rtx_insn *insn);
13985 200 dgisselq
+extern int     zip_ct_address_operand(rtx op);
13986 102 dgisselq
+extern int     zip_pd_opb_operand(rtx op);
13987
+extern int     zip_pd_mov_operand(rtx op);
13988
+extern int     zip_pd_imm_operand(rtx op);
13989
+extern int     zip_pd_mvimm_operand(rtx op);
13990
+extern int     zip_ct_const_address_operand(rtx op);
13991
+extern int     zip_pd_const_address_operand(rtx op);
13992
+extern const char *zip_movsicc(rtx, rtx, rtx, rtx);
13993
+extern const char *zip_addqics(rtx, rtx, rtx, rtx);
13994 122 dgisselq
+extern const char *zip_cbranchdi(rtx, rtx, rtx, rtx);
13995
+
13996 191 dgisselq
+extern void    zip_ifcvt_machdep_init(struct ce_if_block *ceinfo);
13997 102 dgisselq
+extern void    zip_ifcvt_modify_cancel(struct ce_if_block *ceinfo);
13998
+extern void    zip_ifcvt_modify_final(struct ce_if_block *ceinfo);
13999 200 dgisselq
+extern void    zip_ifcvt_modify_tests(struct ce_if_block *ceinfo, rtx *true_expr, rtx *false_expr);
14000 102 dgisselq
+extern void    zip_ifcvt_modify_insn(struct ce_if_block *ceinfo, rtx pattern, rtx_insn *insn);
14001
+
14002
+#endif
14003 127 dgisselq
+
14004
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config/zip/zip-sync.md gcc-6.2.0-zip/gcc/config/zip/zip-sync.md
14005 102 dgisselq
--- gcc-6.2.0/gcc/config/zip/zip-sync.md        1969-12-31 19:00:00.000000000 -0500
14006 111 dgisselq
+++ gcc-6.2.0-zip/gcc/config/zip/zip-sync.md    2017-02-22 18:03:26.740198685 -0500
14007 102 dgisselq
@@ -0,0 +1,415 @@
14008 111 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14009
+;;
14010 102 dgisselq
+;; Filename:   zip-sync.md
14011
+;;
14012
+;; Project:    Zip CPU -- a small, lightweight, RISC CPU soft core
14013 202 dgisselq
+;;
14014
+;; Purpose:    This is that portion of the machine description of the Zip CPU
14015 102 dgisselq
+;;             which is focused on atomic operations.
14016 122 dgisselq
+;;
14017
+;;
14018
+;; Creator:    Dan Gisselquist, Ph.D.
14019
+;;             Gisselquist Technology, LLC
14020 142 dgisselq
+;;
14021 122 dgisselq
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14022 102 dgisselq
+;;
14023
+;; Copyright (C) 2015,2017, Gisselquist Technology, LLC
14024 202 dgisselq
+;;
14025
+;; This program is free software (firmware): you can redistribute it and/or
14026
+;; modify it under the terms of  the GNU General Public License as published
14027
+;; by the Free Software Foundation, either version 3 of the License, or (at
14028 200 dgisselq
+;; your option) any later version.
14029
+;;
14030
+;; This program is distributed in the hope that it will be useful, but WITHOUT
14031
+;; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
14032
+;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14033
+;; for more details.
14034
+;;
14035
+;; License:    GPL, v3, as defined and found on www.gnu.org,
14036
+;;             http://www.gnu.org/licenses/gpl.html
14037
+;;
14038
+;;
14039
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14040
+;;
14041
+;;
14042
+;
14043 202 dgisselq
+;
14044 200 dgisselq
+;
14045
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14046
+;;
14047
+;; Atomic access Op-codes
14048
+;;
14049
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
14050
+;
14051
+;
14052
+;
14053
+; First, the basic atomic_ operators, add, sub, ior, and, and xor
14054
+;
14055
+(define_insn "atomic_addsi"
14056
+       [(set (match_operand:SI 0 "memory_operand" "+Q")
14057
+               (plus:SI (match_dup 0)
14058
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
14059
+       (match_operand 2 "const_int_operand" "")        ; Memory model used
14060
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
14061
+       (clobber (reg:CC CC_REG))]
14062
+       "(ZIP_ATOMIC)"
14063
+       "LOCK\n\tLW %0,%3\n\tADD %1,%3\n\tSW %3,%0"
14064
+       [(set_attr "predicable" "no")])
14065
+(define_insn "atomic_subsi"
14066
+       [(set (match_operand:SI 0 "memory_operand" "+Q")
14067
+               (minus:SI (match_dup 0)
14068
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
14069
+       (match_operand 2 "const_int_operand" "")        ; Memory model used
14070
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
14071
+       (clobber (reg:CC CC_REG))]
14072
+       "(ZIP_ATOMIC)"
14073
+       "LOCK\n\tLW %0,%3\n\tSUB %1,%3\n\tSW %3,%0"
14074
+       [(set_attr "predicable" "no")])
14075
+(define_insn "atomic_iorsi"
14076 202 dgisselq
+       [(set (match_operand:SI 0 "memory_operand" "+Q")
14077 200 dgisselq
+               (ior:SI (match_dup 0)
14078
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
14079 202 dgisselq
+       (match_operand 2 "const_int_operand" "")        ; Memory model used
14080 200 dgisselq
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
14081
+       (clobber (reg:CC CC_REG))]
14082
+       "(ZIP_ATOMIC)"
14083 202 dgisselq
+       "LOCK\n\tLW %0,%3\n\tOR %1,%3\n\tSW %3,%0"
14084 200 dgisselq
+       [(set_attr "predicable" "no")])
14085
+(define_expand "atomic_andsi"
14086 202 dgisselq
+       [(match_operand:SI 0 "memory_operand" "+Q")
14087 200 dgisselq
+       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")
14088
+       (match_operand 2 "" "")                 ; Memory model used
14089 202 dgisselq
+       (clobber (reg:CC CC_REG))]
14090 200 dgisselq
+       "(ZIP_ATOMIC)"
14091
+       {
14092
+               emit_insn(gen_reissue_atomic_andsi(operands[0], operands[1]));
14093 202 dgisselq
+               DONE;
14094 200 dgisselq
+       })
14095
+(define_insn "reissue_atomic_andsi"
14096 202 dgisselq
+       [(set (match_operand:SI 0 "memory_operand" "+Q")
14097 200 dgisselq
+               (and:SI (match_dup 0)
14098
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
14099 202 dgisselq
+       (clobber (match_scratch:SI 2 "=r"))     ; Scratch register
14100 200 dgisselq
+       (clobber (reg:CC CC_REG))]
14101
+       "(ZIP_ATOMIC)"
14102
+       "LOCK\n\tLW %0,%2\n\tAND %1,%2\n\tSW %2,%0"
14103 202 dgisselq
+       [(set_attr "predicable" "no")])
14104 200 dgisselq
+(define_expand "atomic_xorsi"
14105 202 dgisselq
+       [(match_operand:SI 0 "memory_operand" "+Q")
14106
+       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")
14107
+       (match_operand 2 "" "")                 ; Memory model used
14108
+       (clobber (reg:CC CC_REG))]
14109
+       "(ZIP_ATOMIC)"
14110
+       {
14111
+               emit_insn(gen_reissue_atomic_xorsi(operands[0], operands[1]));
14112
+               DONE;
14113
+       })
14114
+(define_insn "reissue_atomic_xorsi"
14115
+       [(set (match_operand:SI 0 "memory_operand" "+Q")
14116
+               (xor:SI (match_dup 0)
14117 200 dgisselq
+                       (match_operand:SI 1 "zip_opb_single_operand_p" "rO")))
14118
+       (clobber (match_scratch:SI 2 "=r"))     ; Scratch register
14119 202 dgisselq
+       (clobber (reg:CC CC_REG))]
14120 200 dgisselq
+       "(ZIP_ATOMIC)"
14121
+       "LOCK\n\tLW %0,%2\n\tXOR %1,%2\n\tSW %2,%0"
14122 202 dgisselq
+       [(set_attr "predicable" "no")])
14123 200 dgisselq
+;
14124 202 dgisselq
+;
14125
+; Given how the ZipCPU is put together, all SI LODs and STOs are atomic.  DI
14126
+; loads and stores need the LOCK command, to keep from breaking within them.
14127
+; Further, GCC expects that anything <= the word size can use a normal load
14128
+; or store instruction.  Hence we don't need anything but the DI load and
14129
+; stores.
14130
+;
14131
+(define_insn "atomic_loaddi"
14132
+       [(set (match_operand:DI 0 "register_operand" "=r")
14133
+               (match_operand:DI 1 "memory_operand" "Q"))
14134
+       (match_operand 2 "const_int_operand" "")]
14135
+       "(ZIP_HAS_DI)&&(ZIP_ATOMIC)"
14136 200 dgisselq
+       "LOCK\n\tLW %1,%H0\t; Atomic Load:DI\n\tLW 4+%1,%L0"
14137
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
14138 202 dgisselq
+;
14139 200 dgisselq
+(define_insn "atomic_storedi"
14140
+       [(set (match_operand:DI 0 "memory_operand" "=Q")
14141 202 dgisselq
+               (match_operand:DI 1 "register_operand" "r"))
14142 200 dgisselq
+       (match_operand 2 "const_int_operand" "")]
14143
+       "(ZIP_HAS_DI)&&(ZIP_ATOMIC)"
14144
+       "LOCK\n\tSW %H1,%0\t; Atomic Store:DI\n\tSW %L1,4+%0"
14145 202 dgisselq
+       [(set_attr "predicable" "no") (set_attr "ccresult" "unchanged")])
14146
+;
14147
+;
14148
+;
14149
+;
14150 200 dgisselq
+(define_insn "atomic_exchangesi"
14151 202 dgisselq
+       [(set (match_operand:SI 0 "register_operand" "=r")
14152
+                       (match_operand:SI 1 "memory_operand" "+Q"))
14153
+               (set (match_dup 1) (match_operand:SI 2 "register_operand" "r"))
14154
+       (match_operand 3 "const_int_operand" "")]
14155
+       "(ZIP_ATOMIC)"
14156
+       "LOCK\n\tLW %1,%0\n\tSW %2,%1"
14157
+       [(set_attr "predicable" "no")])
14158 200 dgisselq
+;
14159 202 dgisselq
+;
14160
+;
14161
+; Here's another set of the atomic operators, this time those that leave their
14162
+; result in operand zero.
14163
+;
14164
+(define_expand "atomic_add_fetchsi"
14165
+       [(match_operand:SI 0 "register_operand" "=r")
14166 200 dgisselq
+       (match_operand:SI 1 "memory_operand" "+Q")
14167
+       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
14168
+       (match_operand 3 "const_int_operand" "")        ;// Memory model used
14169 202 dgisselq
+       (clobber (reg:CC CC_REG))]
14170 200 dgisselq
+       "(ZIP_ATOMIC)"
14171
+       {
14172 202 dgisselq
+               emit_insn(gen_reissue_atomic_add_fetchsi(operands[0],
14173
+                       operands[1], operands[2]));
14174
+               DONE;
14175 200 dgisselq
+       })
14176 202 dgisselq
+(define_insn "reissue_atomic_add_fetchsi"
14177 200 dgisselq
+       [(set (match_operand:SI 0 "register_operand" "=r")
14178
+               (plus:SI (match_operand:SI 1 "memory_operand" "+Q")
14179
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
14180
+       (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))
14181
+       (clobber (reg:CC CC_REG))]
14182
+       "(ZIP_ATOMIC)"
14183
+       "LOCK\n\tLW %1,%0\n\tADD %2,%0\n\tSW %0,%1"
14184 202 dgisselq
+       [(set_attr "predicable" "no")])
14185
+(define_expand "atomic_sub_fetchsi"
14186
+       [(match_operand:SI 0 "register_operand" "=r")
14187
+       (match_operand:SI 1 "memory_operand" "+Q")
14188
+       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
14189
+       (match_operand 3 "const_int_operand" "")
14190
+       (clobber (reg:CC CC_REG))]
14191
+       "(ZIP_ATOMIC)"
14192
+       {
14193
+               emit_insn(gen_reissue_atomic_sub_fetchsi(
14194
+                       operands[0], operands[1], operands[2]));
14195
+               DONE;
14196
+       })
14197 200 dgisselq
+(define_insn "reissue_atomic_sub_fetchsi"
14198 202 dgisselq
+       [(set (match_operand:SI 0 "register_operand" "=r")
14199 200 dgisselq
+               (minus:SI (match_operand:SI 1 "memory_operand" "+Q")
14200
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
14201
+       (set (match_dup 1) (minus:SI (match_dup 1) (match_dup 2)))
14202
+       (clobber (reg:CC CC_REG))]
14203 202 dgisselq
+       "(ZIP_ATOMIC)"
14204 200 dgisselq
+       "LOCK\n\tLW %1,%0\n\tSUB %2,%0\n\tSW %0,%1"
14205 202 dgisselq
+       [(set_attr "predicable" "no")])
14206
+(define_expand "atomic_or_fetchsi"
14207
+       [(match_operand:SI 0 "register_operand" "=r")
14208
+       (match_operand:SI 1 "memory_operand" "+Q")
14209
+       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
14210
+       (match_operand 3 "const_int_operand" "")
14211
+       (clobber (reg:CC CC_REG))]
14212
+       "(ZIP_ATOMIC)"
14213
+       {
14214
+               emit_insn(gen_reissue_atomic_or_fetchsi(
14215
+                       operands[0], operands[1], operands[2]));
14216
+               DONE;
14217
+       })
14218 200 dgisselq
+(define_insn "reissue_atomic_or_fetchsi"
14219 202 dgisselq
+       [(set (match_operand:SI 0 "register_operand" "=r")
14220 200 dgisselq
+               (ior:SI (match_operand:SI 1 "memory_operand" "+Q")
14221
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
14222
+       (set (match_dup 1) (ior:SI (match_dup 1) (match_dup 2)))
14223
+       (clobber (reg:CC CC_REG))]
14224 202 dgisselq
+       "(ZIP_ATOMIC)"
14225 200 dgisselq
+       "LOCK\n\tLW %1,%0\n\tOR %2,%0\n\tSW %0,%1"
14226 202 dgisselq
+       [(set_attr "predicable" "no")])
14227
+(define_expand "atomic_and_fetchsi"
14228
+       [(match_operand:SI 0 "register_operand" "=r")
14229
+       (match_operand:SI 1 "memory_operand" "+Q")
14230
+       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
14231
+       (match_operand 3 "const_int_operand" "")
14232
+       (clobber (reg:CC CC_REG))]
14233
+       "(ZIP_ATOMIC)"
14234
+       {
14235
+               emit_insn(gen_reissue_atomic_and_fetchsi(
14236
+                       operands[0], operands[1], operands[2]));
14237
+               DONE;
14238
+       })
14239 200 dgisselq
+(define_insn "reissue_atomic_and_fetchsi"
14240 202 dgisselq
+       [(set (match_operand:SI 0 "register_operand" "=r")
14241 200 dgisselq
+               (and:SI (match_operand:SI 1 "memory_operand" "+Q")
14242
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
14243
+       (set (match_dup 1) (and:SI (match_dup 1) (match_dup 2)))
14244
+       (clobber (reg:CC CC_REG))]
14245 202 dgisselq
+       "(ZIP_ATOMIC)"
14246 200 dgisselq
+       "LOCK\n\tLW %1,%0\n\tAND %2,%0\n\tSW %0,%1"
14247 202 dgisselq
+       [(set_attr "predicable" "no")])
14248
+(define_expand "atomic_xor_fetchsi"
14249
+       [(match_operand:SI 0 "register_operand" "=r")
14250
+       (match_operand:SI 1 "memory_operand" "+Q")
14251
+       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
14252
+       (match_operand 3 "const_int_operand" "")                        ;// Memory model
14253
+       (clobber (reg:CC CC_REG))]
14254
+       "(ZIP_ATOMIC)"
14255
+       {
14256
+               emit_insn(gen_reissue_atomic_xor_fetchsi(
14257
+                       operands[0], operands[1], operands[2]));
14258
+               DONE;
14259
+       })
14260 200 dgisselq
+(define_insn "reissue_atomic_xor_fetchsi"
14261 202 dgisselq
+       [(set (match_operand:SI 0 "register_operand" "=r")
14262 200 dgisselq
+               (xor:SI (match_operand:SI 1 "memory_operand" "+Q")
14263
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
14264
+       (set (match_dup 1) (xor:SI (match_dup 1) (match_dup 2)))
14265
+       (clobber (reg:CC CC_REG))]
14266 202 dgisselq
+       "(ZIP_ATOMIC)"
14267 200 dgisselq
+       "LOCK\n\tLW %1,%0\n\tXOR %2,%0\n\tSW %0,%1"
14268 202 dgisselq
+       [(set_attr "predicable" "no")])
14269
+;
14270
+;
14271
+;
14272
+;
14273
+(define_expand "atomic_fetch_addsi"
14274
+       [(set (match_operand:SI 1 "memory_operand" "+Q")
14275
+               (plus:SI (match_dup 1)
14276
+                       (match_operand:SI 2 "register_operand" "=r")))
14277
+       (set (match_operand:SI 0 "register_operand" "=r")
14278
+               (match_dup 1))
14279
+       (set (match_dup 2) (plus:SI (match_dup 1) (match_dup 2)))
14280
+       (match_operand 3 "const_int_operand" "")                                ; Memory model used
14281 200 dgisselq
+       (clobber (reg:CC CC_REG))]
14282 202 dgisselq
+       "(ZIP_ATOMIC)"
14283 200 dgisselq
+       {
14284
+               emit_insn(gen_reissue_atomic_fetch_addsi(
14285
+                       operands[0], operands[1], operands[2]));
14286
+               DONE;
14287 202 dgisselq
+       })
14288 200 dgisselq
+(define_insn "reissue_atomic_fetch_addsi"
14289
+       [(set (match_operand:SI 1 "memory_operand" "+Q")
14290
+               (plus:SI (match_dup 1)
14291
+                       (match_operand:SI 2 "register_operand" "=r")))
14292
+       (set (match_operand:SI 0 "register_operand" "=r")
14293 202 dgisselq
+               (match_dup 1))
14294
+       (set (match_dup 2) (plus:SI (match_dup 1) (match_dup 2)))
14295 200 dgisselq
+       (clobber (reg:CC CC_REG))]
14296
+       "(ZIP_ATOMIC)"
14297
+       "LOCK\n\tLW %1,%0\n\tADD %0,%2\n\tSW %2,%1"
14298
+       [(set_attr "predicable" "no")])
14299
+(define_expand "atomic_fetch_subsi"
14300 202 dgisselq
+       [(match_operand:SI 0 "register_operand" "=r")
14301 200 dgisselq
+       (match_operand:SI 1 "memory_operand" "+Q")
14302
+       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")
14303 202 dgisselq
+       (clobber (reg:CC CC_REG))]
14304
+       "(ZIP_ATOMIC)"
14305
+       {
14306
+               emit_insn(gen_reissue_atomic_fetch_subsi(
14307
+                       operands[0], operands[1], operands[2]));
14308
+               DONE;
14309
+       })
14310
+(define_insn "reissue_atomic_fetch_subsi"
14311
+       [(set (match_operand:SI 0 "register_operand" "=r")
14312
+               (minus:SI (match_operand:SI 1 "memory_operand" "+Q")
14313
+                       (match_operand:SI 2 "zip_opb_single_operand_p" "rO")))
14314
+       (set (match_dup 1) (minus:SI (match_dup 1) (match_dup 2)))
14315
+       (clobber (match_scratch:SI 3 "=r"))     ; Scratch register
14316
+       (clobber (reg:CC CC_REG))]
14317
+       "(ZIP_ATOMIC)"
14318 200 dgisselq
+       "NEG %2,%3\n\tLOCK\n\tLW %1,%0\n\tADD %0,%3\n\tSW %3,%1"
14319 202 dgisselq
+       [(set_attr "predicable" "no")])
14320
+(define_insn "atomic_fetch_orsi"
14321
+       [(set (match_operand:SI 1 "memory_operand" "+Q")
14322
+               (ior:SI (match_dup 1)
14323
+                       (match_operand:SI 2 "register_operand" "=r")))
14324
+       (set (match_operand:SI 0 "register_operand" "=r")
14325
+               (match_dup 1))
14326
+       (set (match_dup 2) (ior:SI (match_dup 1) (match_dup 2)))
14327
+       (match_operand 3 "const_int_operand" "")        ; Memory model used
14328
+       (clobber (reg:CC CC_REG))]
14329
+       "(ZIP_ATOMIC)"
14330
+       "LOCK\n\tLW %1,%0\n\tOR %0,%2\n\tSW %2,%1"
14331
+       [(set_attr "predicable" "no")])
14332
+(define_insn "atomic_fetch_andsi"
14333
+       [(set (match_operand:SI 1 "memory_operand" "+Q")
14334
+               (and:SI (match_dup 1)
14335
+                       (match_operand:SI 2 "register_operand" "=r")))
14336
+       (set (match_operand:SI 0 "register_operand" "=r")
14337
+               (match_dup 1))
14338
+       (set (match_dup 2) (and:SI (match_dup 1) (match_dup 2)))
14339
+       (match_operand 3 "const_int_operand" "")        ; Memory model used
14340 200 dgisselq
+       (clobber (reg:CC CC_REG))]
14341 202 dgisselq
+       "(ZIP_ATOMIC)"
14342 200 dgisselq
+       "LOCK\n\tLW %1,%0\n\tAND %0,%2\n\tSW %2,%1"
14343
+       [(set_attr "predicable" "no")])
14344
+(define_insn "atomic_fetch_xorsi"
14345
+       [(set (match_operand:SI 1 "memory_operand" "+Q")
14346
+               (xor:SI (match_dup 1)
14347 202 dgisselq
+                       (match_operand:SI 2 "register_operand" "=r")))
14348 200 dgisselq
+       (set (match_operand:SI 0 "register_operand" "=r")
14349
+               (match_dup 1))
14350 202 dgisselq
+       (set (match_dup 2) (xor:SI (match_dup 1) (match_dup 2)))
14351 200 dgisselq
+       (match_operand 3 "const_int_operand" "")        ; Memory model used
14352
+       (clobber (reg:CC CC_REG))]
14353 202 dgisselq
+       "(ZIP_ATOMIC)"
14354 200 dgisselq
+       "LOCK\n\tLW %1,%0\n\tXOR %0,%2\n\tSW %2,%1"
14355
+       [(set_attr "predicable" "no")])
14356
+;
14357
+;
14358
+;
14359 202 dgisselq
+;
14360 200 dgisselq
+(define_insn "atomic_test_and_set"
14361
+       [(set (match_operand:SI 0 "register_operand" "=r")
14362 202 dgisselq
+               (zero_extend:SI
14363 200 dgisselq
+                       (match_operand:QI 1 "memory_operand" "+Q")))
14364
+       (set (match_dup 1) (const_int 1))
14365 202 dgisselq
+       (match_operand 2 "const_int_operand" "")        ; Memory model used
14366 200 dgisselq
+       (clobber (match_scratch:SI 3 "=r"))]    ; Scratch register
14367
+       "(ZIP_ATOMIC)"
14368
+       "LDI    1,%3
14369
+       LOCK
14370
+       LB      %1,%0
14371 202 dgisselq
+       SB      %3,%1"
14372 200 dgisselq
+       [(set_attr "predicable" "no")])
14373
+;
14374 202 dgisselq
+;
14375 200 dgisselq
+;
14376
+(define_expand "atomic_compare_and_swapsi"
14377
+       [(match_operand:SI 0 "register_operand" "=r")   ;; bool output
14378
+       (match_operand:SI 1 "register_operand" "=r")    ;; val output
14379
+       (match_operand:SI 2 "memory_operand" "+Q")      ;; memory
14380
+       (match_operand:SI 3 "zip_opb_single_operand_p" "rO") ;; Expected
14381
+       (match_operand:SI 4 "register_operand" "r")     ;; Desired
14382 202 dgisselq
+       (match_operand 5 "const_int_operand" "")        ; is_weak
14383
+       (match_operand 6 "const_int_operand" "")        ; mem model on success
14384
+       (match_operand 7 "const_int_operand" "")        ; mem model on failure
14385
+       ]
14386
+       "(ZIP_ATOMIC)"
14387 200 dgisselq
+       {
14388
+               emit_insn(gen_reissue_atomic_compare_and_swapsi(
14389
 
14390 202 dgisselq
+                       operands[2], operands[3],
14391
+                       operands[4]));
14392 200 dgisselq
+               DONE;
14393
+       })
14394
+
14395
+(define_insn "reissue_atomic_compare_and_swapsi"
14396 202 dgisselq
+       [(set (match_operand:SI 0 "register_operand" "=r")
14397
+               (if_then_else
14398
+                       (eq (match_operand:SI 2 "memory_operand" "+Q")
14399
+                               (match_operand:SI 3 "zip_opb_single_operand_p" "rO"))
14400
+                       (const_int 1)
14401
+                       (const_int 0)))
14402
+       (set (match_operand:SI 1 "register_operand" "=r") (match_dup 2))
14403
+       (set (match_dup 2) (if_then_else
14404
+                       (eq (match_dup 2) (match_dup 3))
14405
+                               (match_operand:SI 4 "register_operand" "r")
14406
+                               (match_dup 0)))]
14407
+       "(ZIP_ATOMIC)"
14408
+       "CLR %0
14409
 
14410
+       LW %2,%1
14411
+       CMP %3,%1
14412
+       SW %4,%1
14413
+       LDI.Z 1,%0"
14414
+       [(set_attr "predicable" "no")])
14415
+;
14416 200 dgisselq
+;
14417
+;
14418 202 dgisselq
+;
14419 200 dgisselq
+; STILL MISSING:
14420
+;
14421
+;      deprecated sync_* atomic functions
14422
+;
14423
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/config.gcc gcc-6.2.0-zip/gcc/config.gcc
14424
--- gcc-6.2.0/gcc/config.gcc    2016-06-08 09:34:25.000000000 -0400
14425
+++ gcc-6.2.0-zip/gcc/config.gcc        2016-12-31 16:41:06.258602919 -0500
14426
@@ -493,6 +493,10 @@
14427
 tilepro*-*-*)
14428
        cpu_type=tilepro
14429
        ;;
14430 202 dgisselq
+zip*)
14431 200 dgisselq
+       cpu_type=zip
14432 202 dgisselq
+       tmake_file=zip/t-zip
14433 200 dgisselq
+       ;;
14434
 esac
14435
 
14436
 tm_file=${cpu_type}/${cpu_type}.h
14437
@@ -3042,6 +3046,11 @@
14438
        c_target_objs="m32c-pragma.o"
14439
        cxx_target_objs="m32c-pragma.o"
14440
 
14441
 
14442
+       target_has_targetm_common=yes
14443 202 dgisselq
+       tm_file="elfos.h newlib-stdint.h ${tm_file}"
14444
+       tmake_file="${tmake_file} zip/t-zip"
14445
+       ;;
14446
 *)
14447 102 dgisselq
        echo "*** Configuration ${target} not supported" 1>&2
14448
        exit 1
14449
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/cse.c gcc-6.2.0-zip/gcc/cse.c
14450
--- gcc-6.2.0/gcc/cse.c 2016-02-04 04:56:13.000000000 -0500
14451
 
14452
@@ -42,6 +42,16 @@
14453
 #include "dbgcnt.h"
14454
 #include "rtl-iter.h"
14455
 
14456
+
14457 202 dgisselq
+// #define     DO_ZIP_DEBUGS
14458 102 dgisselq
+#ifdef DO_ZIP_DEBUGS
14459
 
14460
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
14461
+extern void    zip_debug_rtx(const_rtx);
14462
+#else
14463
+#define        ZIP_DEBUG_LINE(STR,RTX)
14464
+#endif
14465
+
14466
 #ifndef LOAD_EXTEND_OP
14467
 #define LOAD_EXTEND_OP(M) UNKNOWN
14468
 #endif
14469 202 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/defaults.h gcc-6.2.0-zip/gcc/defaults.h
14470
--- gcc-6.2.0/gcc/defaults.h    2016-01-04 09:30:50.000000000 -0500
14471 209 dgisselq
+++ gcc-6.2.0-zip/gcc/defaults.h        2016-12-31 16:42:29.094087738 -0500
14472 202 dgisselq
@@ -495,6 +495,8 @@
14473 138 dgisselq
 #define LOG2_BITS_PER_UNIT 3
14474
 #elif BITS_PER_UNIT == 16
14475
 #define LOG2_BITS_PER_UNIT 4
14476
+#elif BITS_PER_UNIT == 32
14477 111 dgisselq
+#define LOG2_BITS_PER_UNIT 5
14478 102 dgisselq
 
14479
 #error Unknown BITS_PER_UNIT
14480 202 dgisselq
 #endif
14481 138 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/df-scan.c gcc-6.2.0-zip/gcc/df-scan.c
14482 102 dgisselq
--- gcc-6.2.0/gcc/df-scan.c     2016-01-04 09:30:50.000000000 -0500
14483
+++ gcc-6.2.0-zip/gcc/df-scan.c 2016-12-31 16:43:04.557867015 -0500
14484
@@ -35,6 +35,14 @@
14485
 #include "dumpfile.h"
14486 202 dgisselq
 
14487
 
14488
+#ifdef DO_ZIP_DEBUGS
14489
+#include <stdio.h>
14490
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
14491
+extern void    zip_debug_rtx(const_rtx);
14492
+#else
14493 102 dgisselq
 
14494
+#endif
14495
 
14496
 /* The set of hard registers in eliminables[i].from. */
14497
 
14498
 static HARD_REG_SET elim_reg_set;
14499
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/emit-rtl.c gcc-6.2.0-zip/gcc/emit-rtl.c
14500
 
14501 202 dgisselq
+++ gcc-6.2.0-zip/gcc/emit-rtl.c        2016-12-31 16:43:35.065677060 -0500
14502
@@ -59,6 +59,15 @@
14503
 #include "stor-layout.h"
14504
 #include "opts.h"
14505
 
14506 127 dgisselq
+
14507
+#ifdef DO_ZIP_DEBUGS
14508
+#include <stdio.h>
14509 202 dgisselq
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
14510
+extern void    zip_debug_rtx(const_rtx);
14511 127 dgisselq
+#else
14512
 
14513
+#endif
14514
+
14515
 struct target_rtl default_target_rtl;
14516 202 dgisselq
 #if SWITCHABLE_TARGET
14517 127 dgisselq
 struct target_rtl *this_target_rtl = &default_target_rtl;
14518 202 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/final.c gcc-6.2.0-zip/gcc/final.c
14519
 
14520
+++ gcc-6.2.0-zip/gcc/final.c   2017-02-06 15:35:15.410085646 -0500
14521
@@ -79,6 +79,16 @@
14522
 #include "rtl-iter.h"
14523
 #include "print-rtl.h"
14524
 
14525
+
14526 102 dgisselq
+// #define     DO_ZIP_DEBUGS
14527 202 dgisselq
+#ifdef DO_ZIP_DEBUGS
14528 117 dgisselq
+#include <stdio.h>
14529 202 dgisselq
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
14530 117 dgisselq
+extern void    zip_debug_rtx(const_rtx);
14531
+#else
14532
+#define        ZIP_DEBUG_LINE(STR,RTX)
14533
+#endif
14534
+
14535
 #ifdef XCOFF_DEBUGGING_INFO
14536
 #include "xcoffout.h"          /* Needed for external data declarations.  */
14537
 #endif
14538 202 dgisselq
 
14539
 
14540
        current_output_insn = debug_insn = insn;
14541
 
14542
+ZIP_DEBUG_LINE("FINAL-INSN", insn);
14543
+
14544 117 dgisselq
        /* Find the proper template for this insn.  */
14545
        templ = get_insn_template (insn_code_number, insn);
14546 122 dgisselq
 
14547 111 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/fold-const.c gcc-6.2.0-zip/gcc/fold-const.c
14548 202 dgisselq
--- gcc-6.2.0/gcc/fold-const.c  2016-07-08 16:20:23.000000000 -0400
14549
+++ gcc-6.2.0-zip/gcc/fold-const.c      2016-12-31 16:47:49.000093249 -0500
14550
 
14551 111 dgisselq
            wide_int w2 = arg2;
14552
            f2.data.high = w2.elt (1);
14553
            f2.data.low = w2.elt (0);
14554
-           f2.mode = SImode;
14555
+           f2.mode = word_mode;
14556 202 dgisselq
          }
14557
          break;
14558
 
14559 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/jump.c gcc-6.2.0-zip/gcc/jump.c
14560 202 dgisselq
--- gcc-6.2.0/gcc/jump.c        2016-01-04 09:30:50.000000000 -0500
14561 102 dgisselq
+++ gcc-6.2.0-zip/gcc/jump.c    2016-12-31 16:49:10.675582836 -0500
14562 202 dgisselq
 
14563
 #include "cfgrtl.h"
14564
 #include "rtl-iter.h"
14565
 
14566 102 dgisselq
+
14567 202 dgisselq
 
14568
+#include <stdio.h>
14569
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
14570
+extern void    zip_debug_rtx(const_rtx);
14571
+#else
14572
+#define        ZIP_DEBUG_LINE(STR,RTX)
14573
+#endif
14574
+
14575
 
14576
    Don't know if it is worth bothering with.  */
14577
 /* Optimize two cases of conditional jump to conditional jump?
14578 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/loop-doloop.c gcc-6.2.0-zip/gcc/loop-doloop.c
14579 202 dgisselq
--- gcc-6.2.0/gcc/loop-doloop.c 2016-01-14 18:12:53.000000000 -0500
14580
+++ gcc-6.2.0-zip/gcc/loop-doloop.c     2016-12-31 16:50:27.099104820 -0500
14581
@@ -37,6 +37,15 @@
14582
 #include "regs.h"
14583
 #include "df.h"
14584 117 dgisselq
 
14585
+
14586 202 dgisselq
+#ifdef DO_ZIP_DEBUGS
14587 117 dgisselq
+#include <stdio.h>
14588
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s;%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
14589 202 dgisselq
+extern void    zip_debug_rtx(const_rtx);
14590
+#else
14591 117 dgisselq
+#define        ZIP_DEBUG_LINE(STR,RTX)
14592
+#endif
14593
+
14594 202 dgisselq
 /* This module is used to modify loops with a determinable number of
14595 117 dgisselq
    iterations to use special low-overhead looping instructions.
14596
 
14597
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/loop-iv.c gcc-6.2.0-zip/gcc/loop-iv.c
14598 202 dgisselq
--- gcc-6.2.0/gcc/loop-iv.c     2016-01-04 09:30:50.000000000 -0500
14599
+++ gcc-6.2.0-zip/gcc/loop-iv.c 2016-12-31 16:52:42.034259845 -0500
14600
@@ -1715,8 +1715,8 @@
14601
   if (op0 != XEXP (cond, 0)
14602
       || op1 != XEXP (cond, 1)
14603
       || code != GET_CODE (cond)
14604 117 dgisselq
-      || GET_MODE (cond) != SImode)
14605
-    cond = gen_rtx_fmt_ee (code, SImode, op0, op1);
14606 191 dgisselq
+      || GET_MODE (cond) != word_mode)
14607 202 dgisselq
+    cond = gen_rtx_fmt_ee (code, word_mode, op0, op1);
14608
 
14609 191 dgisselq
   return cond;
14610
 }
14611
@@ -2083,9 +2083,9 @@
14612
   rtx mmin, mmax, cond_over, cond_under;
14613 202 dgisselq
 
14614 191 dgisselq
   get_mode_bounds (mode, signed_p, iv->extend_mode, &mmin, &mmax);
14615
-  cond_under = simplify_gen_relational (LT, SImode, iv->extend_mode,
14616
+  cond_under = simplify_gen_relational (LT, word_mode, iv->extend_mode,
14617 202 dgisselq
                                        iv->base, mmin);
14618
-  cond_over = simplify_gen_relational (GT, SImode, iv->extend_mode,
14619
+  cond_over = simplify_gen_relational (GT, word_mode, iv->extend_mode,
14620
                                       iv->base, mmax);
14621
 
14622
   switch (cond)
14623
@@ -2464,7 +2464,7 @@
14624
        if (iv0.step == const0_rtx)
14625
          {
14626
            tmp = lowpart_subreg (mode, iv0.base, comp_mode);
14627
-           assumption = simplify_gen_relational (EQ, SImode, mode, tmp,
14628 191 dgisselq
+           assumption = simplify_gen_relational (EQ, word_mode, mode, tmp,
14629 202 dgisselq
                                                  mode_mmax);
14630
            if (assumption == const_true_rtx)
14631
 
14632
@@ -2474,7 +2474,7 @@
14633 191 dgisselq
        else
14634 202 dgisselq
          {
14635
            tmp = lowpart_subreg (mode, iv1.base, comp_mode);
14636
-           assumption = simplify_gen_relational (EQ, SImode, mode, tmp,
14637
 
14638
                                                  mode_mmin);
14639
            if (assumption == const_true_rtx)
14640
              goto zero_iter_simplify;
14641 191 dgisselq
@@ -2561,10 +2561,10 @@
14642 202 dgisselq
              bound = simplify_gen_binary (MINUS, comp_mode, bound, delta);
14643
              bound = lowpart_subreg (mode, bound, comp_mode);
14644
              tmp = lowpart_subreg (mode, iv0.base, comp_mode);
14645
-             may_xform = simplify_gen_relational (cond, SImode, mode,
14646
 
14647
                                                   bound, tmp);
14648
              may_not_xform = simplify_gen_relational (reverse_condition (cond),
14649
-                                                      SImode, mode,
14650
+                                                      word_mode, mode,
14651
                                                       bound, tmp);
14652
            }
14653
          else
14654
@@ -2573,10 +2573,10 @@
14655
              bound = simplify_gen_binary (PLUS, comp_mode, bound, delta);
14656
              bound = lowpart_subreg (mode, bound, comp_mode);
14657
              tmp = lowpart_subreg (mode, iv1.base, comp_mode);
14658
-             may_xform = simplify_gen_relational (cond, SImode, mode,
14659
+             may_xform = simplify_gen_relational (cond, word_mode, mode,
14660
                                                   tmp, bound);
14661
              may_not_xform = simplify_gen_relational (reverse_condition (cond),
14662
-                                                      SImode, mode,
14663
+                                                      word_mode, mode,
14664
                                                       tmp, bound);
14665
            }
14666
        }
14667
@@ -2629,7 +2629,7 @@
14668
          tmp0 = lowpart_subreg (mode, iv0.base, comp_mode);
14669
 
14670
          assumption = simplify_gen_relational (reverse_condition (cond),
14671
-                                               SImode, mode, tmp0, tmp1);
14672
+                                               word_mode, mode, tmp0, tmp1);
14673
          if (assumption == const_true_rtx)
14674
            goto zero_iter_simplify;
14675
          else if (assumption != const0_rtx)
14676
@@ -2671,7 +2671,7 @@
14677
 
14678
       tmp1 = lowpart_subreg (mode, iv1.base, comp_mode);
14679
 
14680
-      assumption = simplify_gen_relational (NE, SImode, mode, tmp, const0_rtx);
14681
+      assumption = simplify_gen_relational (NE, word_mode, mode, tmp, const0_rtx);
14682
       desc->infinite = alloc_EXPR_LIST (0, assumption, desc->infinite);
14683
 
14684
       tmp = simplify_gen_binary (UDIV, mode, tmp1, gen_int_mode (d, mode));
14685
@@ -2703,19 +2703,19 @@
14686
              /* If s is power of 2, we know that the loop is infinite if
14687
                 a % s <= b % s and b + s overflows.  */
14688
              assumption = simplify_gen_relational (reverse_condition (cond),
14689
-                                                   SImode, mode,
14690
+                                                   word_mode, mode,
14691
                                                    tmp1, bound);
14692
 
14693
              t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step);
14694
              t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step);
14695
-             tmp = simplify_gen_relational (cond, SImode, mode, t0, t1);
14696
-             assumption = simplify_gen_binary (AND, SImode, assumption, tmp);
14697 191 dgisselq
+             tmp = simplify_gen_relational (cond, word_mode, mode, t0, t1);
14698 202 dgisselq
+             assumption = simplify_gen_binary (AND, word_mode, assumption, tmp);
14699
              desc->infinite =
14700
                      alloc_EXPR_LIST (0, assumption, desc->infinite);
14701
            }
14702
          else
14703 191 dgisselq
            {
14704 202 dgisselq
-             assumption = simplify_gen_relational (cond, SImode, mode,
14705
+             assumption = simplify_gen_relational (cond, word_mode, mode,
14706
                                                    tmp1, bound);
14707
              desc->assumptions =
14708
                      alloc_EXPR_LIST (0, assumption, desc->assumptions);
14709
@@ -2724,7 +2724,7 @@
14710
          tmp = simplify_gen_binary (PLUS, comp_mode, iv1.base, iv0.step);
14711
 
14712 191 dgisselq
          assumption = simplify_gen_relational (reverse_condition (cond),
14713 202 dgisselq
-                                               SImode, mode, tmp0, tmp);
14714
+                                               word_mode, mode, tmp0, tmp);
14715
 
14716
          delta = simplify_gen_binary (PLUS, mode, tmp1, step);
14717
          delta = simplify_gen_binary (MINUS, mode, delta, tmp0);
14718
@@ -2747,19 +2747,19 @@
14719
              /* If s is power of 2, we know that the loop is infinite if
14720
                 a % s <= b % s and a - s overflows.  */
14721
              assumption = simplify_gen_relational (reverse_condition (cond),
14722
-                                                   SImode, mode,
14723
+                                                   word_mode, mode,
14724
                                                    bound, tmp0);
14725
 
14726
              t0 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp0), step);
14727
              t1 = simplify_gen_binary (UMOD, mode, copy_rtx (tmp1), step);
14728
-             tmp = simplify_gen_relational (cond, SImode, mode, t0, t1);
14729
-             assumption = simplify_gen_binary (AND, SImode, assumption, tmp);
14730
+             tmp = simplify_gen_relational (cond, word_mode, mode, t0, t1);
14731
+             assumption = simplify_gen_binary (AND, word_mode, assumption, tmp);
14732
              desc->infinite =
14733
                      alloc_EXPR_LIST (0, assumption, desc->infinite);
14734
            }
14735 191 dgisselq
          else
14736 202 dgisselq
            {
14737
-             assumption = simplify_gen_relational (cond, SImode, mode,
14738
+             assumption = simplify_gen_relational (cond, word_mode, mode,
14739
                                                    bound, tmp0);
14740
              desc->assumptions =
14741
                      alloc_EXPR_LIST (0, assumption, desc->assumptions);
14742
@@ -2768,7 +2768,7 @@
14743
          tmp = simplify_gen_binary (PLUS, comp_mode, iv0.base, iv1.step);
14744
          tmp = lowpart_subreg (mode, tmp, comp_mode);
14745 191 dgisselq
          assumption = simplify_gen_relational (reverse_condition (cond),
14746 202 dgisselq
-                                               SImode, mode,
14747
+                                               word_mode, mode,
14748
 
14749
          delta = simplify_gen_binary (MINUS, mode, tmp0, step);
14750
          delta = simplify_gen_binary (MINUS, mode, tmp1, delta);
14751
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/optabs.c gcc-6.2.0-zip/gcc/optabs.c
14752
--- gcc-6.2.0/gcc/optabs.c      2016-02-16 10:15:40.000000000 -0500
14753
+++ gcc-6.2.0-zip/gcc/optabs.c  2018-03-23 07:13:51.664427524 -0400
14754
@@ -43,6 +43,17 @@
14755
 #include "optabs-tree.h"
14756
 #include "libfuncs.h"
14757
 
14758
+
14759
+// #define     DO_ZIP_DEBUGS
14760
+#ifdef DO_ZIP_DEBUGS
14761
+#include <stdio.h>
14762
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
14763
+extern void    zip_debug_rtx(const_rtx);
14764
+extern void    zip_debug_rtx_pfx(const char *,const_rtx);
14765
+#else
14766
+#define        ZIP_DEBUG_LINE(STR,RTX)
14767
+#endif
14768
 
14769
 static void prepare_float_lib_cmp (rtx, rtx, enum rtx_code, rtx *,
14770
                                   machine_mode *);
14771
 static rtx expand_unop_direct (machine_mode, optab, rtx, rtx, int);
14772
@@ -6985,6 +6996,15 @@
14773 209 dgisselq
 maybe_gen_insn (enum insn_code icode, unsigned int nops,
14774 202 dgisselq
                struct expand_operand *ops)
14775
 {
14776
+#ifdef DO_ZIP_DEBUGS
14777 102 dgisselq
+fprintf(stderr, "ICODE = %d\n", icode);
14778 111 dgisselq
+fprintf(stderr, "NOPS  = %d\n", nops);
14779
+for(unsigned i=0; i<nops; i++) {
14780 102 dgisselq
+       char    str[10];
14781 202 dgisselq
+       sprintf(str, "Op %d: ", i);
14782
+       zip_debug_rtx_pfx(str, ops[i].value);
14783
+}
14784
+#endif
14785 102 dgisselq
   gcc_assert (nops == (unsigned int) insn_data[(int) icode].n_generator_args);
14786
   if (!maybe_legitimize_operands (icode, 0, nops, ops))
14787
 
14788
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/recog.c gcc-6.2.0-zip/gcc/recog.c
14789 202 dgisselq
--- gcc-6.2.0/gcc/recog.c       2016-01-29 13:47:17.000000000 -0500
14790
+++ gcc-6.2.0-zip/gcc/recog.c   2017-02-06 15:47:48.493946049 -0500
14791
@@ -40,6 +40,16 @@
14792
 #include "reload.h"
14793
 #include "tree-pass.h"
14794
 
14795
+
14796
+// #define     DO_ZIP_DEBUGS
14797
+#ifdef DO_ZIP_DEBUGS
14798
+#include <stdio.h>
14799 209 dgisselq
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
14800 202 dgisselq
+extern void    zip_debug_rtx(const_rtx);
14801
+#else
14802
+#define        ZIP_DEBUG_LINE(STR,RTX)
14803
+#endif
14804
+
14805
 #ifndef STACK_POP_CODE
14806
 
14807
 #define STACK_POP_CODE POST_INC
14808
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/reload1.c gcc-6.2.0-zip/gcc/reload1.c
14809
--- gcc-6.2.0/gcc/reload1.c     2016-03-18 04:25:57.000000000 -0400
14810
+++ gcc-6.2.0-zip/gcc/reload1.c 2017-02-06 15:54:21.067740343 -0500
14811
@@ -42,6 +42,15 @@
14812
 #include "dumpfile.h"
14813
 #include "rtl-iter.h"
14814 102 dgisselq
 
14815
+#ifdef DO_ZIP_DEBUGS
14816 117 dgisselq
+#include <stdio.h>
14817
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
14818 202 dgisselq
 
14819
+#else
14820 117 dgisselq
+#define        ZIP_DEBUG_LINE(STR,RTX)
14821
+#endif
14822
+
14823
+
14824
 /* This file contains the reload pass of the compiler, which is
14825 202 dgisselq
    run after register allocation has been done.  It checks that
14826
    each insn is valid (operands required to be in registers really
14827
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/reload.c gcc-6.2.0-zip/gcc/reload.c
14828
--- gcc-6.2.0/gcc/reload.c      2016-02-13 20:37:40.000000000 -0500
14829
+++ gcc-6.2.0-zip/gcc/reload.c  2017-03-01 15:46:26.784221658 -0500
14830
@@ -106,6 +106,15 @@
14831
 #include "addresses.h"
14832 117 dgisselq
 #include "params.h"
14833
 
14834
+// #define     DO_ZIP_DEBUGS
14835
+#ifdef DO_ZIP_DEBUGS
14836 202 dgisselq
+#include <stdio.h>
14837
+#define        ZIP_DEBUG_LINE(STR,RTX) do{fprintf(stderr,"%s:%d/%s\n",__FILE__,__LINE__,STR); zip_debug_rtx(RTX);} while(0)
14838 117 dgisselq
+extern void    zip_debug_rtx(const_rtx);
14839
+#else
14840
+#define        ZIP_DEBUG_LINE(STR,RTX)
14841
+#endif
14842
+
14843 202 dgisselq
 /* True if X is a constant that can be forced into the constant pool.
14844 117 dgisselq
    MODE is the mode of the operand, or VOIDmode if not known.  */
14845
 #define CONST_POOL_OK_P(MODE, X)               \
14846
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/testsuite/lib/target-supports.exp gcc-6.2.0-zip/gcc/testsuite/lib/target-supports.exp
14847 202 dgisselq
--- gcc-6.2.0/gcc/testsuite/lib/target-supports.exp     2016-07-05 13:54:02.000000000 -0400
14848
+++ gcc-6.2.0-zip/gcc/testsuite/lib/target-supports.exp 2016-12-31 16:59:52.719091392 -0500
14849
@@ -545,6 +545,11 @@
14850
        return 0
14851
 
14852
 
14853 117 dgisselq
+    # ZipCPU doesnt support profiling (yet).
14854 122 dgisselq
+    if { [istarget zip*] } {
14855
+       return 0
14856 202 dgisselq
+    }
14857
+
14858
     # cygwin does not support -p.
14859 122 dgisselq
     if { [istarget *-*-cygwin*] && $test_what == "-p" } {
14860
        return 0
14861
@@ -1090,6 +1095,12 @@
14862
        }]
14863
     }
14864
 
14865
+    # No real hardware FPU support for ZipCPU yet --- even though the
14866 202 dgisselq
+    # instruction set supports it, the CPU just isn't ready (yet).
14867
+    if { [istarget zip*] } {
14868
+        return 0
14869
+    }
14870 102 dgisselq
+
14871
     # This proc is actually checking the availabilty of FPU
14872
     # support for doubles, so on the RX we must fail if the
14873 202 dgisselq
     # 64-bit double multilib has been selected.
14874
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/tree-ssa-math-opts.c gcc-6.2.0-zip/gcc/tree-ssa-math-opts.c
14875
 
14876 102 dgisselq
+++ gcc-6.2.0-zip/gcc/tree-ssa-math-opts.c      2016-12-31 17:02:24.405602214 -0500
14877
@@ -983,7 +983,7 @@
14878 202 dgisselq
 
14879
       if (val & 1)
14880 102 dgisselq
        {
14881 202 dgisselq
-         digit = val & ((1 << POWI_WINDOW_SIZE) - 1);
14882 102 dgisselq
 
14883
          result += powi_lookup_cost (digit, cache)
14884
                    + POWI_WINDOW_SIZE + 1;
14885 202 dgisselq
          val >>= POWI_WINDOW_SIZE;
14886
@@ -1023,7 +1023,7 @@
14887
     }
14888 102 dgisselq
   else if (n & 1)
14889
     {
14890
-      digit = n & ((1 << POWI_WINDOW_SIZE) - 1);
14891
+      digit = n & ((1l << POWI_WINDOW_SIZE) - 1);
14892
       op0 = powi_as_mults_1 (gsi, loc, type, n - digit, cache);
14893
       op1 = powi_as_mults_1 (gsi, loc, type, digit, cache);
14894 202 dgisselq
     }
14895
@@ -1957,7 +1957,7 @@
14896
 };
14897
 
14898 102 dgisselq
 #define BITS_PER_MARKER 8
14899
-#define MARKER_MASK ((1 << BITS_PER_MARKER) - 1)
14900
+#define MARKER_MASK ((1l << BITS_PER_MARKER) - 1)
14901
 #define MARKER_BYTE_UNKNOWN MARKER_MASK
14902
 #define HEAD_MARKER(n, size) \
14903
   ((n) & ((uint64_t) MARKER_MASK << (((size) - 1) * BITS_PER_MARKER)))
14904
@@ -1993,7 +1993,7 @@
14905
   /* Zero out the extra bits of N in order to avoid them being shifted
14906 202 dgisselq
      into the significant bits.  */
14907 102 dgisselq
 
14908
-    n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
14909
+    n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
14910
 
14911
   switch (code)
14912
     {
14913
@@ -2020,7 +2020,7 @@
14914
 
14915 202 dgisselq
   /* Zero unused bits for size.  */
14916 102 dgisselq
   if (size < 64 / BITS_PER_MARKER)
14917
-    n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
14918
+    n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
14919
 
14920
 }
14921
 
14922
@@ -2067,7 +2067,7 @@
14923
   n->n = CMPNOP;
14924 202 dgisselq
 
14925 102 dgisselq
   if (size < 64 / BITS_PER_MARKER)
14926
-    n->n &= ((uint64_t) 1 << (size * BITS_PER_MARKER)) - 1;
14927
+    n->n &= ((uint64_t) 1l << (size * BITS_PER_MARKER)) - 1;
14928
 
14929
   return true;
14930
 }
14931
@@ -2372,7 +2372,7 @@
14932
              {
14933 202 dgisselq
                /* If STMT casts to a smaller type mask out the bits not
14934 102 dgisselq
                   belonging to the target type.  */
14935
-               n->n &= ((uint64_t) 1 << (type_size * BITS_PER_MARKER)) - 1;
14936
+               n->n &= ((uint64_t) 1l << (type_size * BITS_PER_MARKER)) - 1;
14937
              }
14938
            n->type = type;
14939
            if (!n->base_addr)
14940
@@ -2489,7 +2489,7 @@
14941
     {
14942 202 dgisselq
       uint64_t mask;
14943 102 dgisselq
 
14944
-      mask = ((uint64_t) 1 << (n->range * BITS_PER_MARKER)) - 1;
14945
+      mask = ((uint64_t) 1l << (n->range * BITS_PER_MARKER)) - 1;
14946
       cmpxchg >>= (64 / BITS_PER_MARKER - n->range) * BITS_PER_MARKER;
14947
       cmpnop &= mask;
14948
     }
14949
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/ubsan.c gcc-6.2.0-zip/gcc/ubsan.c
14950
--- gcc-6.2.0/gcc/ubsan.c       2016-08-12 15:57:35.000000000 -0400
14951 202 dgisselq
+++ gcc-6.2.0-zip/gcc/ubsan.c   2017-08-23 09:29:11.196719450 -0400
14952 102 dgisselq
@@ -1469,7 +1469,7 @@
14953
 
14954
   expanded_location xloc = expand_location (loc);
14955
   if (xloc.file == NULL || strncmp (xloc.file, "\1", 2) == 0
14956
-      || xloc.file == '\0' || xloc.file[0] == '\xff'
14957
+      || xloc.file[0] == '\0' || xloc.file[0] == '\xff'
14958
       || xloc.file[1] == '\xff')
14959
     return false;
14960 202 dgisselq
 
14961 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/gcc/varasm.c gcc-6.2.0-zip/gcc/varasm.c
14962
--- gcc-6.2.0/gcc/varasm.c      2016-03-31 11:30:33.000000000 -0400
14963
+++ gcc-6.2.0-zip/gcc/varasm.c  2016-12-31 17:03:08.629193673 -0500
14964
@@ -2771,7 +2771,7 @@
14965
 
14966
   /* Put out the first word with the specified alignment.  */
14967
   if (reverse)
14968
-    elt = flip_storage_order (SImode, gen_int_mode (data[nelts - 1], SImode));
14969 209 dgisselq
+    elt = flip_storage_order (word_mode, gen_int_mode (data[nelts - 1], SImode));
14970
   else
14971
     elt = GEN_INT (data[0]);
14972
   assemble_integer (elt, MIN (nunits, units_per), align, 1);
14973
@@ -2783,7 +2783,7 @@
14974
   for (int i = 1; i < nelts; i++)
14975
     {
14976
       if (reverse)
14977
-       elt = flip_storage_order (SImode,
14978
+       elt = flip_storage_order (word_mode,
14979
                                  gen_int_mode (data[nelts - 1 - i], SImode));
14980
       else
14981 202 dgisselq
        elt = GEN_INT (data[i]);
14982
diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/config/zip/sfp-machine.h gcc-6.2.0-zip/libgcc/config/zip/sfp-machine.h
14983
--- gcc-6.2.0/libgcc/config/zip/sfp-machine.h   1969-12-31 19:00:00.000000000 -0500
14984
+++ gcc-6.2.0-zip/libgcc/config/zip/sfp-machine.h       2018-03-23 07:16:33.779338866 -0400
14985 102 dgisselq
@@ -0,0 +1,55 @@
14986 202 dgisselq
+#ifndef        ZIP_SFP_MACHINE_H
14987
+#define        ZIP_SFP_MACHINE_H
14988
+
14989
+#define        __BIG_ENDIAN    4321
14990
+#define        __BYTE_ORDER    __BIG_ENDIAN
14991
+
14992
+#include "fp-bit.h"
14993
+
14994
+#define        _FP_W_TYPE_SIZE 32
14995
+#define        _FP_W_TYPE      unsigned int
14996
+#define        _FP_WS_TYPE     signed int
14997
+#define        _FP_I_TYPE      long
14998
+
14999
+#define        _FP_MUL_MEAT_S(R,X,Y) _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
15000
+#define        _FP_MUL_MEAT_D(R,X,Y) _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
15001
+
15002
+#define        _FP_DIV_MEAT_S(R,X,Y)   _FP_DIV_MEAT_1_loop(S,R,X,Y)
15003
+#define        _FP_DIV_MEAT_D(R,X,Y)   _FP_DIV_MEAT_2_udiv(D,R,X,Y)
15004 209 dgisselq
+
15005
+#define        _FP_NANFRAC_S   ((_FP_QNANBIT_S<<1)-1)
15006 202 dgisselq
 
15007
+
15008
+#define        _FP_QNANNEGATEDP        0
15009
+#define        _FP_NANSIGN_S           0
15010
+#define        _FP_NANSIGN_D           0
15011
+#define        _FP_KEEPNANFRACP        1
15012 209 dgisselq
+
15013
+/* Someone please check this.  --- copied from one of many other places  */
15014 202 dgisselq
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)                      \
15015
+  do {                                                          \
15016
+    if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)          \
15017
+        && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs))     \
15018
+      {                                                         \
15019
+        R##_s = Y##_s;                                          \
15020
+        _FP_FRAC_COPY_##wc(R,Y);                                \
15021
+      }                                                         \
15022
+    else                                                        \
15023
+      {                                                         \
15024
+        R##_s = X##_s;                                          \
15025
+        _FP_FRAC_COPY_##wc(R,X);                                \
15026
+      }                                                         \
15027
+    R##_c = FP_CLS_NAN;                                         \
15028
+  } while (0)
15029
+
15030
+/* Not checked.  */
15031
+#define _FP_TININESS_AFTER_ROUNDING 0
15032
+
15033
+#ifndef        __BYTE_ORDER
15034
+#define        __BYTE_ORDER    __BIG_ENDIAN
15035
+#endif
15036
+
15037
+#define        strong_alias(name, aliasname) _stong_alias(name, aliasname)
15038
+#define        _strong_alias(name, aliasname)  \
15039
+       extern __typeof(name) aliasname __attribute__ ((alias (#name)));
15040
+#endif
15041
diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/config.host gcc-6.2.0-zip/libgcc/config.host
15042
 
15043
+++ gcc-6.2.0-zip/libgcc/config.host    2018-03-23 07:31:08.573591955 -0400
15044
@@ -197,6 +197,9 @@
15045
 tic6x-*-*)
15046
        cpu_type=c6x
15047
        ;;
15048
+zip*)
15049
+       cpu_type=zip
15050
+       ;;
15051
 esac
15052
 
15053
 # Common parts for widely ported systems.
15054
 
15055 102 dgisselq
        tmake_file="$tmake_file nvptx/t-nvptx"
15056 202 dgisselq
        extra_parts="crt0.o"
15057
        ;;
15058
+zip*)
15059
+       tmake_file="$tmake_file t-softfp-sfdf t-softfp t-fdpbit"
15060
+       # extra_parts="crt0.o"
15061
+       ;;
15062
 *)
15063 209 dgisselq
        echo "*** Configuration ${host} not supported" 1>&2
15064 202 dgisselq
        exit 1
15065 102 dgisselq
diff -Naur '--exclude=*.swp' gcc-6.2.0/libgcc/configure gcc-6.2.0-zip/libgcc/configure
15066
--- gcc-6.2.0/libgcc/configure  2016-04-11 15:45:35.000000000 -0400
15067
+++ gcc-6.2.0-zip/libgcc/configure      2017-01-27 15:53:43.141531475 -0500
15068
@@ -3805,13 +3805,13 @@
15069
   CFLAGS=$ac_save_CFLAGS
15070
 elif test $ac_cv_prog_cc_g = yes; then
15071
 
15072
-    CFLAGS="-g -O2"
15073
+    CFLAGS="-O3"

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