URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

# Subversion Repositorieszipcpu

## [/] [zipcpu/] [trunk/] [sw/] [lib/] [divs.S] - Blame information for rev 69

Line No. Rev Author Line
1 45 dgisselq
``;``
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``;       DIVS``
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``;``
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``;       Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 for signed R0,R1.``
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``;       We'll call R0 (input) x, R1(input) y, result is such that``
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``;       R0 * y + R1 = x.  Now let's work through our signs with an example``
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``;       where x = +/- 22, and y = +/- 4:``
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``;``
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``;       x y``
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``;       + +     No change, just call divu``
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``;       - +     (x=-22,y= 4,R0=-5,R1=-2)``
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``;       + -     (x= 22,y=-4,R0=-5,R1= 2)``
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``;       - -     (x=-22,y=-4,R0= 5,R1=-2)``
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``;``
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``;``
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``;``
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``lib_divs: ; Given R0,R1, computer R0 = R0/R1 and R1 = R0%R1 for signed R0,R1``
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``        SUB     2,SP``
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``        STO     R2,(SP)``
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``        STO     R3,2(SP)``
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``        ;``
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``        CLR     R3              ; Keep track of resulting sign in R2``
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``        TST     -1,R0           ; Is R0 negative?``
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``        MOV     ret_div32s(PC),R2``
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``        LLO.LT  3,R3            ; If so, resulting sign will be negative, and``
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``        NEG.LT  R0              ; then we negate R0 (R0 = ABS(R0))``
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``        MOV.LT  divu_divs_return(PC),R2``
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``        TST     -1,R1           ; Is R1 negative?``
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``        XOR.LT  1,R3            ; If so, result will be opposite sign of before``
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``        NEG.LT  R1              ; Now we get R1=ABS(R1)``
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``        MOV.LT  divu_divs_return(PC),R2``
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``        BRA     lib_divu        ; Do our unsigned multiply``
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``        ; JSR   divu            ; Do our unsigned multiply``
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``divu_divs_return:``
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``        TST     1,R3            ; Check resulting sign``
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``        NEG.NE  R0              ; Need to flip the sign of our result``
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``        TST     2,R3            ; Now, if R1 was originally negative``
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``        NEG.NE  R1              ; Then negate R1``
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``ret_div32s:``
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``        LOD     (SP),R2``
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``        LOD     2(SP),R3``
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``        ADD     2,SP``
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``        JMP     R2``
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`` ``