Subversion Repositories zipcpu

; We could build mul32s (32-bit signed multiply) as

mpy32s:

        PUSH    R2

        CLR     R2              ; Keep track of resulting sign in R2

        TST     R0              ; Is R0 negative?

        XOR.LT  #1,R2           ; If so, resulting sign will be negative, and

        NEG.NZ  R0              ; then we negate R0 (R0 = ABS(R0))

        TST     R1              ; Is R1 negative?

        XOR.LT  #1,R2           ; If so, result will be opposite sign of before

        TST     R1              ; Need to retest since xor modified flags

        NEG.LT  R1              ; Now we get R1=ABS(R1)

        JSR     mpy32u          ; Do our unsigned multiply

        CMP     R2              ; Check resulting sign

        BZ      ret_mul32s      ; If positive, do nothing more

        NOT     R0              ; If negative, negate the result

        NOT     R1

        ADD     $1,R1

        ADD.C   $1,R0

ret_mul32s:

        POP     R2

        RET