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1 2 dgisselq
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Filename:     test.S
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;
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; Project:      Zip CPU -- a small, lightweight, RISC CPU soft core
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;
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; Purpose:      A disorganized test, just showing some initial operation of
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;               the CPU.  As a disorganized test, it doesn't prove anything
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;               beyond the generic operation of the CPU.
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;
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; Status:       As of July, 2015, the assembler isn't sophisticated enough
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;               to handle the address resolution needed to assemble this file.
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;
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; Creator:      Dan Gisselquist, Ph.D.
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;               Gisselquist Tecnology, LLC
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Copyright (C) 2015, Gisselquist Technology, LLC
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;
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; This program is free software (firmware): you can redistribute it and/or
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; modify it under the terms of  the GNU General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or (at
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; your option) any later version.
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;
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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; for more details.
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;
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; License:      GPL, v3, as defined and found on www.gnu.org,
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;               http://www.gnu.org/licenses/gpl.html
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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test:
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        clr     r0
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        mov     r0,r1
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        mov     $1+r0,r2
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        mov     $2+r0,r3
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        mov     $22h+r0,r4
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        mov     $377h+r0,ur5
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        noop
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        nop
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        add     r2,r0
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        add     $32,r0
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        add     $-33,r0
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        not.z   r0
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        clrf    r0
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        ldi     $5,r1
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        cmp     $0+r0,r1
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        not.lt  r0
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        not.ge  r1
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        lod     $-7+pc,r2
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        ldihi   $deadh,r3
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        ldihi   $beefh,r3
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testbench:
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        // Let's build a software test bench.
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        clr     r12     ; R12 will point to our peripherals
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        ldihi   $c000h,r12
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        mov     r12,ur12
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        mov     test_start,upc
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        ldihi   $8001,r0
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        ldilo   $-1,r0
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        sto     r0,$1+r12
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        rtu
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        lod     r12,r0
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        cmp     $0,r0
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        bnz     $1
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        halt
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        busy
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; Now for a series of tests.  If the test fails, call the trap
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; interrupt with the test number that failed.  Upon completion,
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; call the trap with #0.
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; Now for a series of tests.  If the test fails, call the trap
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; interrupt with the test number that failed.  Upon completion,
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; call the trap with #0.
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; Test LDI to PC
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; Some data registers
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        .dat    __here__+5
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test_start:
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        ldi     $2,r11
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        lod     $-3+pc,pc
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        clr     r11
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        noop
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        cmp     $0,r11
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        sto.z   r11,(r12)
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        add     $1,r0
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        add     $1,r0
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// Let's test whether overflow works
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        ldi     $3,r11
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        ldi     $-1,r0
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        lsr     $1,r0
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        add     $1,r0
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        bv      $1
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        sto     r11,(r12)
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// Overflow set from subtraction
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        ldi     $4,r11
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        ldi     $1,r0
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        .dat    0x5000001f              ; rol $31,r0
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        sub     $1,r0
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        bv      $1
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        sto     r11,(r12)
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// Overflow set from LSR
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        ldi     $5,r11
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        ldi     $1,r0
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        .dat    0x5000001f              ; rol $31,r0
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        lsr     $1,r0
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        bv      $1
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        sto     r11,(r12)
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// Overflow set from LSL
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        ldi     $6,r11
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        ldi     $1,r0
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        .dat    0x5000001e
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        lsl     $1,r0
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        bv      $1
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        sto     r11,(r12)
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// Overflow set from LSL, negative to positive
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        ldi     $7,r11
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        ldi     $1,r0
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        .dat    0x5000001f; //  E: ROL $30,R0
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        lsl     $1,r0
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        bv      $1
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        sto     r11,(r12)
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// Test carry
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        ldi     $0x010,r11
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        ldi     $-1,r0
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        add     $1,r0
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        tst     $2,cc
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        sto.z   r11,(r12)
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// and carry from subtraction
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        ldi     $17,r11
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        sub     $1,r0
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        tst     $2,cc
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        sto.z   r11,(r12)
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// Let's try a loop: for i=0; i<5; i++)
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//      We'll use R0=i, Immediates for 5
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for_loop:
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        ldi     $18,r11
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        clr     r0
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        noop
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        add     $1,r0
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        cmp     $5,r0
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        blt     for_loop
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//
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// Let's try a reverse loop.  Such loops are usually cheaper to
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// implement, and this one is no different: 2 loop instructions
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// (minus setup instructions) vs 3 from before.
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// R0 = 5; (from before)
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// do {
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// } while (R0 > 0);
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bgt_loop:
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        ldi     $19,r11
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        noop
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        sub     $1,r0
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        bgt     bgt_loop
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// How about the same thing with a >= comparison?
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// R1 = 5; // Need to do this explicitly
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// do {
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// } while(R1 >= 0);
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        ldi     $20,r00
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        ldi     $5,r1
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bge_loop:
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        noop
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        sub     $1,r1
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        bge     bge_loop
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// Let's try the reverse loop again, only this time we'll store our
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// loop variable in memory.
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// R0 = 5; (from before)
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// do {
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// } while (R0 > 0);
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        ldi     $21,r11
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        bra     $1
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loop_var:
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        .dat    0
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mem_loop:
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        mov     $-2+pc,r1
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        clr     r2
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        ldi     $5,r0
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        sto     r1,(r0)
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        add     $1,r2
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        add     $14,r0
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        lod     (r1),r0
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        sub     $1,r0
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        bgt     $-6
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        cmp     $5,r2
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        sto.ne  r11,(r12)
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// Return success / Test the trap interrupt
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        clr     r11
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        sto     r11,(r12)
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        noop
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        noop
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// Go into an infinite loop if the trap fails
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// Permanent loop instruction -- a busy halt if you will
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        busy
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// And, in case we miss a halt ...
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        halt

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