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[/] [zipcpu/] [trunk/] [sw/] [zipdbg/] [zipdbg.cpp] - Blame information for rev 69

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1 19 dgisselq
///////////////////////////////////////////////////////////////////////////////
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//
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// Filename:    zipdbg.cpp
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//
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// Project:     Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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// Purpose:     Provide a simple debugger for the Zip CPU.  This allows you
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//              to halt the CPU, examine the registers, and even single step
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//      the CPU.  It's not fully functional yet, as I would like to implement
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//      breakpoints and the ability to modify registers, but it's a good
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//      start.
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//
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//      Commands while in the debugger are:
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//      'r'     - RESET the CPU
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//      'g'     - Go.  Release the CPU and exit the debugger.
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//      'q'     - Quit.  Leave the debugger, while leaving the CPU halted.
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//      's'     - Single Step.  Allows the CPU to advance by one instruction.
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//
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//
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//
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// Creator:     Dan Gisselquist, Ph.D.
22 69 dgisselq
//              Gisselquist Tecnhology, LLC
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of  the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// License:     GPL, v3, as defined and found on www.gnu.org,
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//              http://www.gnu.org/licenses/gpl.html
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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#include <stdlib.h>
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#include <signal.h>
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#include <time.h>
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#include <unistd.h>
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#include <ctype.h>
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#include <ncurses.h>
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// #include "twoc.h"
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// #include "qspiflashsim.h"
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#include "zopcodes.h"
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#include "zparser.h"
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#include "devbus.h"
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#include "regdefs.h"
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// #include "port.h"
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// No particular "parameters" need definition or redefinition here.
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class   ZIPPY : public DEVBUS {
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        typedef DEVBUS::BUSW    BUSW;
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        DEVBUS  *m_fpga;
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public:
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        ZIPPY(DEVBUS *fpga) : m_fpga(fpga) {}
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        void    kill(void) { m_fpga->kill(); }
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        void    close(void) { m_fpga->close(); }
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        void    writeio(const BUSW a, const BUSW v) { m_fpga->writeio(a, v); }
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        BUSW    readio(const BUSW a) { return m_fpga->readio(a); }
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        void    readi(const BUSW a, const int len, BUSW *buf) {
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                return m_fpga->readi(a, len, buf); }
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        void    readz(const BUSW a, const int len, BUSW *buf) {
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                return m_fpga->readz(a, len, buf); }
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        void    writei(const BUSW a, const int len, const BUSW *buf) {
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                return m_fpga->writei(a, len, buf); }
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        void    writez(const BUSW a, const int len, const BUSW *buf) {
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                return m_fpga->writez(a, len, buf); }
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        bool    poll(void) { return m_fpga->poll(); }
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        void    usleep(unsigned ms) { m_fpga->usleep(ms); }
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        void    wait(void) { m_fpga->wait(); }
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        bool    bus_err(void) const { return m_fpga->bus_err(); }
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        void    reset_err(void) { m_fpga->reset_err(); }
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        void    clear(void) { m_fpga->clear(); }
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        void    reset(void) { writeio(R_ZIPCTRL, CPU_RESET|CPU_HALT); }
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        void    step(void) { writeio(R_ZIPCTRL, CPU_STEP); }
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        void    go(void) { writeio(R_ZIPCTRL, CPU_GO); }
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        void    halt(void) {    writeio(R_ZIPCTRL, CPU_HALT); }
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        bool    stalled(void) { return ((readio(R_ZIPCTRL)&CPU_STALL)==0); }
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        void    showval(int y, int x, const char *lbl, unsigned int v) {
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                mvprintw(y,x, "%s: 0x%08x", lbl, v);
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        }
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        void    dispreg(int y, int x, const char *n, unsigned int v) {
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                // 4,4,8,1 = 17 of 20, +3 = 19
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                mvprintw(y, x, "%s: 0x%08x", n, v);
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        }
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        void    showins(int y, const char *lbl,
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                        const int gie, const unsigned int pc) {
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                char    line[80];
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                unsigned int    v;
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                mvprintw(y, 0, "%s: 0x%08x", lbl, pc);
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                if (gie) attroff(A_BOLD);
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                else    attron(A_BOLD);
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                line[0] = '\0';
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                try {
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                        v= readio(pc);
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                        zipi_to_string(v, line);
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                        printw(" 0x%08x", v);
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                        printw("  %-24s", &line[1]);
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                } catch(BUSERR b) {
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                        printw(" 0x%08x  %-24s", b.addr, "(Bus Error)");
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                }
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                attroff(A_BOLD);
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        }
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        unsigned int    cmd_read(unsigned int a) {
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                writeio(R_ZIPCTRL, CPU_HALT|(a&0x3f));
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                while((readio(R_ZIPCTRL) & CPU_STALL) == 0)
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                        ;
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                return readio(R_ZIPDATA);
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        }
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131
        void    read_state(void) {
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                int     ln= 0;
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                bool    gie;
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                mvprintw(ln,0, "Peripherals");
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                mvprintw(ln,40, "CPU State: ");
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                {
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                        unsigned int v = readio(R_ZIPDATA);
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                        if (v & 0x010000)
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                                printw("EXT-INT ");
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                        if (v & 0x002000)
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                                printw("Supervisor Mod ");
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                        if (v & 0x001000)
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                                printw("Sleeping ");
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                        if (v & 0x008000)
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                                printw("Break-Enabled ");
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                }
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                ln++;
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                showval(ln, 1, "PIC ", cmd_read(32+ 0));
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                showval(ln,21, "WDT ", cmd_read(32+ 1));
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                showval(ln,41, "CACH", cmd_read(32+ 2));
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                showval(ln,61, "PIC2", cmd_read(32+ 3));
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                ln++;
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                showval(ln, 1, "TMRA", cmd_read(32+ 4));
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                showval(ln,21, "TMRB", cmd_read(32+ 5));
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                showval(ln,41, "TMRC", cmd_read(32+ 6));
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                showval(ln,61, "JIF ", cmd_read(32+ 7));
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                ln++;
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                showval(ln, 1, "UTSK", cmd_read(32+12));
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                showval(ln,21, "UMST", cmd_read(32+13));
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                showval(ln,41, "UPST", cmd_read(32+14));
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                showval(ln,61, "UAST", cmd_read(32+15));
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                ln++;
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                ln++;
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                unsigned int cc = cmd_read(14);
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                gie = (cc & 0x020);
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                if (gie)
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                        attroff(A_BOLD);
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                else
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                        attron(A_BOLD);
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                mvprintw(ln, 0, "Supervisor Registers");
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                ln++;
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                dispreg(ln, 1, "sR0 ", cmd_read(0));
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                dispreg(ln,21, "sR1 ", cmd_read(1));
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                dispreg(ln,41, "sR2 ", cmd_read(2));
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                dispreg(ln,61, "sR3 ", cmd_read(3)); ln++;
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                dispreg(ln, 1, "sR4 ", cmd_read(4));
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                dispreg(ln,21, "sR5 ", cmd_read(5));
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                dispreg(ln,41, "sR6 ", cmd_read(6));
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                dispreg(ln,61, "sR7 ", cmd_read(7)); ln++;
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                dispreg(ln, 1, "sR8 ", cmd_read( 8));
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                dispreg(ln,21, "sR9 ", cmd_read( 9));
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                dispreg(ln,41, "sR10", cmd_read(10));
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                dispreg(ln,61, "sR11", cmd_read(11)); ln++;
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                dispreg(ln, 1, "sR12", cmd_read(12));
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                dispreg(ln,21, "sSP ", cmd_read(13));
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                mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
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                        (cc & 0x040)?"STP":"   ",
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                        (cc & 0x020)?"GIE":"   ",
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                        (cc & 0x010)?"SLP":"   ",
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                        (cc&8)?"V":" ",
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                        (cc&4)?"N":" ",
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                        (cc&2)?"C":" ",
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                        (cc&1)?"Z":" ");
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                mvprintw(ln,61, "sPC : 0x%08x", cmd_read(15));
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                ln++;
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                if (gie)
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                        attron(A_BOLD);
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                else
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                        attroff(A_BOLD);
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                mvprintw(ln, 0, "User Registers"); ln++;
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                dispreg(ln, 1, "uR0 ", cmd_read(16));
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                dispreg(ln,21, "uR1 ", cmd_read(17));
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                dispreg(ln,41, "uR2 ", cmd_read(18));
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                dispreg(ln,61, "uR3 ", cmd_read(19)); ln++;
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                dispreg(ln, 1, "uR4 ", cmd_read(20));
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                dispreg(ln,21, "uR5 ", cmd_read(21));
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                dispreg(ln,41, "uR6 ", cmd_read(22));
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                dispreg(ln,61, "uR7 ", cmd_read(23)); ln++;
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                dispreg(ln, 1, "uR8 ", cmd_read(24));
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                dispreg(ln,21, "uR9 ", cmd_read(25));
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                dispreg(ln,41, "uR10", cmd_read(26));
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                dispreg(ln,61, "uR11", cmd_read(27)); ln++;
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                dispreg(ln, 1, "uR12", cmd_read(28));
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                dispreg(ln,21, "uSP ", cmd_read(29));
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                cc = cmd_read(30);
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                mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
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                        (cc&0x040)?"STP":"   ",
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                        (cc&0x020)?"GIE":"   ",
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                        (cc&0x010)?"SLP":"   ",
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                        (cc&8)?"V":" ",
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                        (cc&4)?"N":" ",
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                        (cc&2)?"C":" ",
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                        (cc&1)?"Z":" ");
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                mvprintw(ln,61, "uPC : 0x%08x", cmd_read(31));
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                attroff(A_BOLD);
239
                ln+=2;
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241
                ln+=3;
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                BUSW pc = cmd_read((gie)?31:15);
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                showins(ln, "I ", gie, pc+2); ln++;
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                showins(ln, "Dc", gie, pc+1); ln++;
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                showins(ln, "Op", gie, pc  ); ln++;
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                showins(ln, "Al", gie, pc-1); ln++;
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        }
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};
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DEVBUS  *m_fpga;
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252
int     main(int argc, char **argv) {
253
//      FPGAOPEN(m_fpga);
254
        ZIPPY   *zip = new ZIPPY(m_fpga);
255
 
256
        initscr();
257
        raw();
258
        noecho();
259
        keypad(stdscr, true);
260
 
261
        int     chv;
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        bool    done = false;
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264
        zip->halt();
265
        for(int i=0; (i<5)&&(zip->stalled()); i++)
266
                ;
267
        if (!zip->stalled())
268
                zip->read_state();
269
        while(!done) {
270
                chv = getch();
271
                switch(chv) {
272
                case 'g': case 'G':
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                        m_fpga->writeio(R_ZIPCTRL, CPU_GO);
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                        // We just released the CPU, so we're now done.
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                        done = true;
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                        break;
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                case 'q': case 'Q':
278
                        done = true;
279
                        break;
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                case 'r': case 'R':
281
                        zip->reset();
282
                        erase();
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                        break;
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                case 's': case 'S':
285
                        zip->step();
286
                        break;
287
                case ERR:
288
                default:
289
                        ;
290
                }
291
 
292
                if (zip->stalled())
293
                        erase();
294
                else
295
                        zip->read_state();
296
        }
297
 
298
        endwin();
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}
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