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[/] [zx_ula/] [branches/] [xilinx/] [spectrum_48k_spartan3a_for_gameduino_mod_vga_timex_hicolor_ulaplus/] [master_clock.v] - Blame information for rev 29

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1 29 mcleod_ide
////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
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////////////////////////////////////////////////////////////////////////////////
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//   ____  ____ 
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//  /   /\/   / 
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// /___/  \  /    Vendor: Xilinx 
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// \   \   \/     Version : 12.4
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//  \   \         Application : xaw2verilog
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//  /   /         Filename : master_clock.v
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// /___/   /\     Timestamp : 04/21/2012 19:26:35
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// \   \  /  \ 
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//  \___\/\___\ 
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//
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//Command: xaw2verilog -st C:\\proyectos_xilinx\ulaplus\ipcore_dir\.\master_clock.xaw C:\\proyectos_xilinx\ulaplus\ipcore_dir\.\master_clock
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//Design Name: master_clock
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//Device: xc3s1000-ft256-4
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//
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// Module master_clock
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// Generated by Xilinx Architecture Wizard
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// Written for synthesis tool: XST
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// Period Jitter (unit interval) for block DCM_INST = 0.05 UI
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// Period Jitter (Peak-to-Peak) for block DCM_INST = 1.92 ns
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`timescale 1ns / 1ps
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module master_clock(CLKIN_IN,
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                     CLKFX_OUT,
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                     CLKIN_IBUFG_OUT,
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                     CLK0_OUT);
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    input CLKIN_IN;
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   output CLKFX_OUT;
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   output CLKIN_IBUFG_OUT;
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   output CLK0_OUT;
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   wire CLKFB_IN;
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   wire CLKFX_BUF;
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   wire CLKIN_IBUFG;
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   wire CLK0_BUF;
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   wire GND_BIT;
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   assign GND_BIT = 0;
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   assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
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   assign CLK0_OUT = CLKFB_IN;
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   BUFG  CLKFX_BUFG_INST (.I(CLKFX_BUF),
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                         .O(CLKFX_OUT));
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   IBUFG  CLKIN_IBUFG_INST (.I(CLKIN_IN),
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                           .O(CLKIN_IBUFG));
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   BUFG  CLK0_BUFG_INST (.I(CLK0_BUF),
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                        .O(CLKFB_IN));
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   DCM #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(8),
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         .CLKFX_MULTIPLY(18), .CLKIN_DIVIDE_BY_2("FALSE"),
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         .CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
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         .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
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         .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
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         .FACTORY_JF(16'h8080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
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         DCM_INST (.CLKFB(CLKFB_IN),
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                 .CLKIN(CLKIN_IBUFG),
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                 .DSSEN(GND_BIT),
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                 .PSCLK(GND_BIT),
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                 .PSEN(GND_BIT),
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                 .PSINCDEC(GND_BIT),
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                 .RST(GND_BIT),
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                 .CLKDV(),
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                 .CLKFX(CLKFX_BUF),
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                 .CLKFX180(),
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                 .CLK0(CLK0_BUF),
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                 .CLK2X(),
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                 .CLK2X180(),
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                 .CLK90(),
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                 .CLK180(),
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                 .CLK270(),
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                 .LOCKED(),
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                 .PSDONE(),
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                 .STATUS());
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endmodule

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