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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:10:16 04/04/2012 
// Design Name: 
// Module Name:    rgbdtoa 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module rgbdtoa(
    input clk,  // 56MHz (or more) clock
         input reset,
    input select, // 0=ULA, 1=ULA+
    input ri, //
    input gi, // digital IRGB
    input bi, // inputs from standar ULA
    input hi, //
    input [7:0] rgbulap, // 8-bit input from ULA+
    output r, //
    output g, // sigma-delta encoded analog RGB signals
    output b  //
    );
 
         reg [2:0] dacr;
         reg [2:0] dacg;
         reg [2:0] dacb;
 
         always @(*) begin
                if (!select) begin
                        case ({hi,ri})
                                2'b00 : dacr = 3'b000;
                                2'b01 : dacr = 3'b101;
                                2'b10 : dacr = 3'b000;
                                2'b11 : dacr = 3'b111;
                        endcase
                end
                else
                        dacr = rgbulap[4:2];
        end
 
         always @(*) begin
                if (!select) begin
                        case ({hi,gi})
                                2'b00 : dacg = 3'b000;
                                2'b01 : dacg = 3'b101;
                                2'b10 : dacg = 3'b000;
                                2'b11 : dacg = 3'b111;
                        endcase
                end
                else
                        dacg = rgbulap[7:5];
        end
 
         always @(*) begin
                if (!select) begin
                        case ({hi,bi})
                                2'b00 : dacb = 3'b000;
                                2'b01 : dacb = 3'b101;
                                2'b10 : dacb = 3'b000;
                                2'b11 : dacb = 3'b111;
                        endcase
                end
                else
                        dacb = {rgbulap[1:0],rgbulap[1]};
        end
 
        dac3bit dtoarojo (
                .DACout(r),
                .DACin(dacr),
                .Clk(clk),
                .Reset(reset)
        );
 
        dac3bit dtoaverde (
                .DACout(g),
                .DACin(dacg),
                .Clk(clk),
                .Reset(reset)
        );
 
        dac3bit dtoaazul (
                .DACout(b),
                .DACin(dacb),
                .Clk(clk),
                .Reset(reset)
        );
 
endmodule
 
`define MSBI 2 // Most significant Bit of DAC input
//This is a Delta-Sigma Digital to Analog Converter
module dac3bit (DACout, DACin, Clk, Reset);
        output DACout; // This is the average output that feeds low pass filter
        input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
        input Clk;
        input Reset;
 
        reg DACout; // for optimum performance, ensure that this ff is in IOB
        reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
        reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
        reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
        reg [`MSBI+2:0] DeltaB; // B input of Delta adder
 
        always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
        always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
        always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
        always @(posedge Clk or posedge Reset)
        begin
                if(Reset)
                begin
                        SigmaLatch <= #1 1'b1 << (`MSBI+1);
                        DACout <= #1 1'b0;
                end
                else
                begin
                        SigmaLatch <= #1 SigmaAdder;
                        DACout <= #1 SigmaLatch[`MSBI+2];
                end
        end
endmodule
 

Line No.	Rev	Author	Line
1	29	mcleod_ide	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company:`
4			`// Engineer:`
5			`//`
6			`// Create Date: 11:10:16 04/04/2012`
7			`// Design Name:`
8			`// Module Name: rgbdtoa`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 0.01 - File Created`
18			`// Additional Comments:`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`module rgbdtoa(`
22			`input clk, // 56MHz (or more) clock`
23			`input reset,`
24			`input select, // 0=ULA, 1=ULA+`
25			`input ri, //`
26			`input gi, // digital IRGB`
27			`input bi, // inputs from standar ULA`
28			`input hi, //`
29			`input [7:0] rgbulap, // 8-bit input from ULA+`
30			`output r, //`
31			`output g, // sigma-delta encoded analog RGB signals`
32			`output b //`
33			`);`
34
35			`reg [2:0] dacr;`
36			`reg [2:0] dacg;`
37			`reg [2:0] dacb;`
38
39			`always @(*) begin`
40			`if (!select) begin`
41			`case ({hi,ri})`
42			`2'b00 : dacr = 3'b000;`
43			`2'b01 : dacr = 3'b101;`
44			`2'b10 : dacr = 3'b000;`
45			`2'b11 : dacr = 3'b111;`
46			`endcase`
47			`end`
48			`else`
49			`dacr = rgbulap[4:2];`
50			`end`
51
52			`always @(*) begin`
53			`if (!select) begin`
54			`case ({hi,gi})`
55			`2'b00 : dacg = 3'b000;`
56			`2'b01 : dacg = 3'b101;`
57			`2'b10 : dacg = 3'b000;`
58			`2'b11 : dacg = 3'b111;`
59			`endcase`
60			`end`
61			`else`
62			`dacg = rgbulap[7:5];`
63			`end`
64
65			`always @(*) begin`
66			`if (!select) begin`
67			`case ({hi,bi})`
68			`2'b00 : dacb = 3'b000;`
69			`2'b01 : dacb = 3'b101;`
70			`2'b10 : dacb = 3'b000;`
71			`2'b11 : dacb = 3'b111;`
72			`endcase`
73			`end`
74			`else`
75			`dacb = {rgbulap[1:0],rgbulap[1]};`
76			`end`
77
78			`dac3bit dtoarojo (`
79			`.DACout(r),`
80			`.DACin(dacr),`
81			`.Clk(clk),`
82			`.Reset(reset)`
83			`);`
84
85			`dac3bit dtoaverde (`
86			`.DACout(g),`
87			`.DACin(dacg),`
88			`.Clk(clk),`
89			`.Reset(reset)`
90			`);`
91
92			`dac3bit dtoaazul (`
93			`.DACout(b),`
94			`.DACin(dacb),`
95			`.Clk(clk),`
96			`.Reset(reset)`
97			`);`
98
99			`endmodule`
100
101			`define MSBI 2 // Most significant Bit of DAC input
102			`//This is a Delta-Sigma Digital to Analog Converter`
103			`module dac3bit (DACout, DACin, Clk, Reset);`
104			`output DACout; // This is the average output that feeds low pass filter`
105			input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
106			`input Clk;`
107			`input Reset;`
108
109			`reg DACout; // for optimum performance, ensure that this ff is in IOB`
110			reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
111			reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
112			reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
113			reg [`MSBI+2:0] DeltaB; // B input of Delta adder
114
115			always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
116			`always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;`
117			`always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;`
118			`always @(posedge Clk or posedge Reset)`
119			`begin`
120			`if(Reset)`
121			`begin`
122			SigmaLatch <= #1 1'b1 << (`MSBI+1);
123			`DACout <= #1 1'b0;`
124			`end`
125			`else`
126			`begin`
127			`SigmaLatch <= #1 SigmaAdder;`
128			DACout <= #1 SigmaLatch[`MSBI+2];
129			`end`
130			`end`
131			`endmodule`
132

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[/] [zx_ula/] [branches/] [xilinx/] [spectrum_48k_spartan3a_for_gameduino_mod_vga_timex_hicolor_ulaplus/] [rgbdtoa.v] - Blame information for rev 29