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1 29 mcleod_ide
//
2
// TV80 8-Bit Microprocessor Core
3
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
4
//
5
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
6
//
7
// Permission is hereby granted, free of charge, to any person obtaining a 
8
// copy of this software and associated documentation files (the "Software"), 
9
// to deal in the Software without restriction, including without limitation 
10
// the rights to use, copy, modify, merge, publish, distribute, sublicense, 
11
// and/or sell copies of the Software, and to permit persons to whom the 
12
// Software is furnished to do so, subject to the following conditions:
13
//
14
// The above copyright notice and this permission notice shall be included 
15
// in all copies or substantial portions of the Software.
16
//
17
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
18
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
19
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 
20
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 
21
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
22
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
23
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24
 
25
module tv80_core (/*AUTOARG*/
26
  // Outputs
27
  m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc,
28
  ts, intcycle_n, IntE, stop,
29
  // Inputs
30
  reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di
31
  );
32
  // Beginning of automatic inputs (from unused autoinst inputs)
33
  // End of automatics
34
 
35
  parameter Mode = 1;   // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
36
  parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
37
  parameter Flag_C = 0;
38
  parameter Flag_N = 1;
39
  parameter Flag_P = 2;
40
  parameter Flag_X = 3;
41
  parameter Flag_H = 4;
42
  parameter Flag_Y = 5;
43
  parameter Flag_Z = 6;
44
  parameter Flag_S = 7;
45
 
46
  input     reset_n;
47
  input     clk;
48
  input     cen;
49
  input     wait_n;
50
  input     int_n;
51
  input     nmi_n;
52
  input     busrq_n;
53
  output    m1_n;
54
  output    iorq;
55
  output    no_read;
56
  output    write;
57
  output    rfsh_n;
58
  output    halt_n;
59
  output    busak_n;
60
  output [15:0] A;
61
  input [7:0]   dinst;
62
  input [7:0]   di;
63
  output [7:0]  dout;
64
  output [6:0]  mc;
65
  output [6:0]  ts;
66
  output        intcycle_n;
67
  output        IntE;
68
  output        stop;
69
 
70
  reg    m1_n;
71
  reg    iorq;
72
`ifdef TV80_REFRESH
73
  reg    rfsh_n;
74
`endif
75
  reg    halt_n;
76
  reg    busak_n;
77
  reg [15:0] A;
78
  reg [7:0]  dout;
79
  reg [6:0]  mc;
80
  reg [6:0]  ts;
81
  reg   intcycle_n;
82
  reg   IntE;
83
  reg   stop;
84
 
85
  parameter     aNone    = 3'b111;
86
  parameter     aBC      = 3'b000;
87
  parameter     aDE      = 3'b001;
88
  parameter     aXY      = 3'b010;
89
  parameter     aIOA     = 3'b100;
90
  parameter     aSP      = 3'b101;
91
  parameter     aZI      = 3'b110;
92
 
93
  // Registers
94
  reg [7:0]     ACC, F;
95
  reg [7:0]     Ap, Fp;
96
  reg [7:0]     I;
97
`ifdef TV80_REFRESH
98
  reg [7:0]     R;
99
`endif
100
  reg [15:0]    SP, PC;
101
  reg [7:0]     RegDIH;
102
  reg [7:0]     RegDIL;
103
  wire [15:0]   RegBusA;
104
  wire [15:0]   RegBusB;
105
  wire [15:0]   RegBusC;
106
  reg [2:0]     RegAddrA_r;
107
  reg [2:0]     RegAddrA;
108
  reg [2:0]     RegAddrB_r;
109
  reg [2:0]     RegAddrB;
110
  reg [2:0]     RegAddrC;
111
  reg           RegWEH;
112
  reg           RegWEL;
113
  reg           Alternate;
114
 
115
  // Help Registers
116
  reg [15:0]    TmpAddr;        // Temporary address register
117
  reg [7:0]     IR;             // Instruction register
118
  reg [1:0]     ISet;           // Instruction set selector
119
  reg [15:0]    RegBusA_r;
120
 
121
  reg [15:0]    ID16;
122
  reg [7:0]     Save_Mux;
123
 
124
  reg [6:0]     tstate;
125
  reg [6:0]     mcycle;
126
  reg           last_mcycle, last_tstate;
127
  reg           IntE_FF1;
128
  reg           IntE_FF2;
129
  reg           Halt_FF;
130
  reg           BusReq_s;
131
  reg           BusAck;
132
  reg           ClkEn;
133
  reg           NMI_s;
134
  reg           INT_s;
135
  reg [1:0]     IStatus;
136
 
137
  reg [7:0]     DI_Reg;
138
  reg           T_Res;
139
  reg [1:0]     XY_State;
140
  reg [2:0]     Pre_XY_F_M;
141
  reg           NextIs_XY_Fetch;
142
  reg           XY_Ind;
143
  reg           No_BTR;
144
  reg           BTR_r;
145
  reg           Auto_Wait;
146
  reg           Auto_Wait_t1;
147
  reg           Auto_Wait_t2;
148
  reg           IncDecZ;
149
 
150
  // ALU signals
151
  reg [7:0]     BusB;
152
  reg [7:0]     BusA;
153
  wire [7:0]    ALU_Q;
154
  wire [7:0]    F_Out;
155
 
156
  // Registered micro code outputs
157
  reg [4:0]     Read_To_Reg_r;
158
  reg           Arith16_r;
159
  reg           Z16_r;
160
  reg [3:0]     ALU_Op_r;
161
  reg           Save_ALU_r;
162
  reg           PreserveC_r;
163
  reg [2:0]     mcycles;
164
 
165
  // Micro code outputs
166
  wire [2:0]    mcycles_d;
167
  wire [2:0]    tstates;
168
  reg           IntCycle;
169
  reg           NMICycle;
170
  wire          Inc_PC;
171
  wire          Inc_WZ;
172
  wire [3:0]    IncDec_16;
173
  wire [1:0]    Prefix;
174
  wire          Read_To_Acc;
175
  wire          Read_To_Reg;
176
  wire [3:0]     Set_BusB_To;
177
  wire [3:0]     Set_BusA_To;
178
  wire [3:0]     ALU_Op;
179
  wire           Save_ALU;
180
  wire           PreserveC;
181
  wire           Arith16;
182
  wire [2:0]     Set_Addr_To;
183
  wire           Jump;
184
  wire           JumpE;
185
  wire           JumpXY;
186
  wire           Call;
187
  wire           RstP;
188
  wire           LDZ;
189
  wire           LDW;
190
  wire           LDSPHL;
191
  wire           iorq_i;
192
  wire [2:0]     Special_LD;
193
  wire           ExchangeDH;
194
  wire           ExchangeRp;
195
  wire           ExchangeAF;
196
  wire           ExchangeRS;
197
  wire           I_DJNZ;
198
  wire           I_CPL;
199
  wire           I_CCF;
200
  wire           I_SCF;
201
  wire           I_RETN;
202
  wire           I_BT;
203
  wire           I_BC;
204
  wire           I_BTR;
205
  wire           I_RLD;
206
  wire           I_RRD;
207
  wire           I_INRC;
208
  wire           SetDI;
209
  wire           SetEI;
210
  wire [1:0]     IMode;
211
  wire           Halt;
212
 
213
  reg [15:0]     PC16;
214
  reg [15:0]     PC16_B;
215
  reg [15:0]     SP16, SP16_A, SP16_B;
216
  reg [15:0]     ID16_B;
217
  reg            Oldnmi_n;
218
 
219
  tv80_mcode #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_mcode
220
    (
221
     .IR                   (IR),
222
     .ISet                 (ISet),
223
     .MCycle               (mcycle),
224
     .F                    (F),
225
     .NMICycle             (NMICycle),
226
     .IntCycle             (IntCycle),
227
     .MCycles              (mcycles_d),
228
     .TStates              (tstates),
229
     .Prefix               (Prefix),
230
     .Inc_PC               (Inc_PC),
231
     .Inc_WZ               (Inc_WZ),
232
     .IncDec_16            (IncDec_16),
233
     .Read_To_Acc          (Read_To_Acc),
234
     .Read_To_Reg          (Read_To_Reg),
235
     .Set_BusB_To          (Set_BusB_To),
236
     .Set_BusA_To          (Set_BusA_To),
237
     .ALU_Op               (ALU_Op),
238
     .Save_ALU             (Save_ALU),
239
     .PreserveC            (PreserveC),
240
     .Arith16              (Arith16),
241
     .Set_Addr_To          (Set_Addr_To),
242
     .IORQ                 (iorq_i),
243
     .Jump                 (Jump),
244
     .JumpE                (JumpE),
245
     .JumpXY               (JumpXY),
246
     .Call                 (Call),
247
     .RstP                 (RstP),
248
     .LDZ                  (LDZ),
249
     .LDW                  (LDW),
250
     .LDSPHL               (LDSPHL),
251
     .Special_LD           (Special_LD),
252
     .ExchangeDH           (ExchangeDH),
253
     .ExchangeRp           (ExchangeRp),
254
     .ExchangeAF           (ExchangeAF),
255
     .ExchangeRS           (ExchangeRS),
256
     .I_DJNZ               (I_DJNZ),
257
     .I_CPL                (I_CPL),
258
     .I_CCF                (I_CCF),
259
     .I_SCF                (I_SCF),
260
     .I_RETN               (I_RETN),
261
     .I_BT                 (I_BT),
262
     .I_BC                 (I_BC),
263
     .I_BTR                (I_BTR),
264
     .I_RLD                (I_RLD),
265
     .I_RRD                (I_RRD),
266
     .I_INRC               (I_INRC),
267
     .SetDI                (SetDI),
268
     .SetEI                (SetEI),
269
     .IMode                (IMode),
270
     .Halt                 (Halt),
271
     .NoRead               (no_read),
272
     .Write                (write)
273
     );
274
 
275
  tv80_alu #(Mode, Flag_C, Flag_N, Flag_P, Flag_X, Flag_H, Flag_Y, Flag_Z, Flag_S) i_alu
276
    (
277
     .Arith16              (Arith16_r),
278
     .Z16                  (Z16_r),
279
     .ALU_Op               (ALU_Op_r),
280
     .IR                   (IR[5:0]),
281
     .ISet                 (ISet),
282
     .BusA                 (BusA),
283
     .BusB                 (BusB),
284
     .F_In                 (F),
285
     .Q                    (ALU_Q),
286
     .F_Out                (F_Out)
287
     );
288
 
289
  function [6:0] number_to_bitvec;
290
    input [2:0] num;
291
    begin
292
      case (num)
293
        1 : number_to_bitvec = 7'b0000001;
294
        2 : number_to_bitvec = 7'b0000010;
295
        3 : number_to_bitvec = 7'b0000100;
296
        4 : number_to_bitvec = 7'b0001000;
297
        5 : number_to_bitvec = 7'b0010000;
298
        6 : number_to_bitvec = 7'b0100000;
299
        7 : number_to_bitvec = 7'b1000000;
300
        default : number_to_bitvec = 7'bx;
301
      endcase // case(num)
302
    end
303
  endfunction // number_to_bitvec
304
 
305
  function [2:0] mcyc_to_number;
306
    input [6:0] mcyc;
307
    begin
308
      casez (mcyc)
309
        7'b1zzzzzz : mcyc_to_number = 3'h7;
310
        7'b01zzzzz : mcyc_to_number = 3'h6;
311
        7'b001zzzz : mcyc_to_number = 3'h5;
312
        7'b0001zzz : mcyc_to_number = 3'h4;
313
        7'b00001zz : mcyc_to_number = 3'h3;
314
        7'b000001z : mcyc_to_number = 3'h2;
315
        7'b0000001 : mcyc_to_number = 3'h1;
316
        default : mcyc_to_number = 3'h1;
317
      endcase
318
    end
319
  endfunction
320
 
321
  always @(/*AUTOSENSE*/mcycle or mcycles or tstate or tstates)
322
    begin
323
      case (mcycles)
324
        1 : last_mcycle = mcycle[0];
325
        2 : last_mcycle = mcycle[1];
326
        3 : last_mcycle = mcycle[2];
327
        4 : last_mcycle = mcycle[3];
328
        5 : last_mcycle = mcycle[4];
329
        6 : last_mcycle = mcycle[5];
330
        7 : last_mcycle = mcycle[6];
331
        default : last_mcycle = 1'bx;
332
      endcase // case(mcycles)
333
 
334
      case (tstates)
335
 
336
        1 : last_tstate = tstate[1];
337
        2 : last_tstate = tstate[2];
338
        3 : last_tstate = tstate[3];
339
        4 : last_tstate = tstate[4];
340
        5 : last_tstate = tstate[5];
341
        6 : last_tstate = tstate[6];
342
        default : last_tstate = 1'bx;
343
      endcase
344
    end // always @ (...
345
 
346
 
347
  always @(/*AUTOSENSE*/ALU_Q or BusAck or BusB or DI_Reg
348
           or ExchangeRp or IR or Save_ALU_r or Set_Addr_To or XY_Ind
349
           or XY_State or cen or last_tstate or mcycle)
350
    begin
351
      ClkEn = cen && ~ BusAck;
352
 
353
      if (last_tstate)
354
        T_Res = 1'b1;
355
      else T_Res = 1'b0;
356
 
357
      if (XY_State != 2'b00 && XY_Ind == 1'b0 &&
358
          ((Set_Addr_To == aXY) ||
359
           (mcycle[0] && IR == 8'b11001011) ||
360
           (mcycle[0] && IR == 8'b00110110)))
361
        NextIs_XY_Fetch = 1'b1;
362
      else
363
        NextIs_XY_Fetch = 1'b0;
364
 
365
      if (ExchangeRp)
366
        Save_Mux = BusB;
367
      else if (!Save_ALU_r)
368
        Save_Mux = DI_Reg;
369
      else
370
        Save_Mux = ALU_Q;
371
    end // always @ *
372
 
373
  always @ (posedge clk or negedge reset_n)
374
    begin
375
      if (reset_n == 1'b0 )
376
        begin
377
          PC <= #1 0;  // Program Counter
378
          A <= #1 0;
379
          TmpAddr <= #1 0;
380
          IR <= #1 8'b00000000;
381
          ISet <= #1 2'b00;
382
          XY_State <= #1 2'b00;
383
          IStatus <= #1 2'b00;
384
          mcycles <= #1 3'b000;
385
          dout <= #1 8'b00000000;
386
 
387
          ACC <= #1 8'hFF;
388
          F <= #1 8'hFF;
389
          Ap <= #1 8'hFF;
390
          Fp <= #1 8'hFF;
391
          I <= #1 0;
392
          `ifdef TV80_REFRESH
393
          R <= #1 0;
394
          `endif
395
          SP <= #1 16'hFFFF;
396
          Alternate <= #1 1'b0;
397
 
398
          Read_To_Reg_r <= #1 5'b00000;
399
          Arith16_r <= #1 1'b0;
400
          BTR_r <= #1 1'b0;
401
          Z16_r <= #1 1'b0;
402
          ALU_Op_r <= #1 4'b0000;
403
          Save_ALU_r <= #1 1'b0;
404
          PreserveC_r <= #1 1'b0;
405
          XY_Ind <= #1 1'b0;
406
        end
407
      else
408
        begin
409
 
410
          if (ClkEn == 1'b1 )
411
            begin
412
 
413
              ALU_Op_r <= #1 4'b0000;
414
              Save_ALU_r <= #1 1'b0;
415
              Read_To_Reg_r <= #1 5'b00000;
416
 
417
              mcycles <= #1 mcycles_d;
418
 
419
              if (IMode != 2'b11 )
420
                begin
421
                  IStatus <= #1 IMode;
422
                end
423
 
424
              Arith16_r <= #1 Arith16;
425
              PreserveC_r <= #1 PreserveC;
426
              if (ISet == 2'b10 && ALU_Op[2] == 1'b0 && ALU_Op[0] == 1'b1 && mcycle[2] )
427
                begin
428
                  Z16_r <= #1 1'b1;
429
                end
430
              else
431
                begin
432
                  Z16_r <= #1 1'b0;
433
                end
434
 
435
              if (mcycle[0] && (tstate[1] | tstate[2] | tstate[3] ))
436
                begin
437
                  // mcycle == 1 && tstate == 1, 2, || 3
438
                  if (tstate[2] && wait_n == 1'b1 )
439
                    begin
440
                      `ifdef TV80_REFRESH
441
                      if (Mode < 2 )
442
                        begin
443
                          A[7:0] <= #1 R;
444
                          A[15:8] <= #1 I;
445
                          R[6:0] <= #1 R[6:0] + 1;
446
                        end
447
                      `endif
448
                      if (Jump == 1'b0 && Call == 1'b0 && NMICycle == 1'b0 && IntCycle == 1'b0 && ~ (Halt_FF == 1'b1 || Halt == 1'b1) )
449
                        begin
450
                          PC <= #1 PC16;
451
                        end
452
 
453
                      if (IntCycle == 1'b1 && IStatus == 2'b01 )
454
                        begin
455
                          IR <= #1 8'b11111111;
456
                        end
457
                      else if (Halt_FF == 1'b1 || (IntCycle == 1'b1 && IStatus == 2'b10) || NMICycle == 1'b1 )
458
                        begin
459
                          IR <= #1 8'b00000000;
460
                          TmpAddr[7:0] <= #1 dinst; // Special M1 vector fetch
461
                        end
462
                      else
463
                        begin
464
                          IR <= #1 dinst;
465
                        end
466
 
467
                      ISet <= #1 2'b00;
468
                      if (Prefix != 2'b00 )
469
                        begin
470
                          if (Prefix == 2'b11 )
471
                            begin
472
                              if (IR[5] == 1'b1 )
473
                                begin
474
                                  XY_State <= #1 2'b10;
475
                                end
476
                              else
477
                                begin
478
                                  XY_State <= #1 2'b01;
479
                                end
480
                            end
481
                          else
482
                            begin
483
                              if (Prefix == 2'b10 )
484
                                begin
485
                                  XY_State <= #1 2'b00;
486
                                  XY_Ind <= #1 1'b0;
487
                                end
488
                              ISet <= #1 Prefix;
489
                            end
490
                        end
491
                      else
492
                        begin
493
                          XY_State <= #1 2'b00;
494
                          XY_Ind <= #1 1'b0;
495
                        end
496
                    end // if (tstate == 2 && wait_n == 1'b1 )
497
 
498
 
499
                end
500
              else
501
                begin
502
                  // either (mcycle > 1) OR (mcycle == 1 AND tstate > 3)
503
 
504
                  if (mcycle[5] )
505
                    begin
506
                      XY_Ind <= #1 1'b1;
507
                      if (Prefix == 2'b01 )
508
                        begin
509
                          ISet <= #1 2'b01;
510
                        end
511
                    end
512
 
513
                  if (T_Res == 1'b1 )
514
                    begin
515
                      BTR_r <= #1 (I_BT || I_BC || I_BTR) && ~ No_BTR;
516
                      if (Jump == 1'b1 )
517
                        begin
518
                          A[15:8] <= #1 DI_Reg;
519
                          A[7:0] <= #1 TmpAddr[7:0];
520
                          PC[15:8] <= #1 DI_Reg;
521
                          PC[7:0] <= #1 TmpAddr[7:0];
522
                        end
523
                      else if (JumpXY == 1'b1 )
524
                        begin
525
                          A <= #1 RegBusC;
526
                          PC <= #1 RegBusC;
527
                        end else if (Call == 1'b1 || RstP == 1'b1 )
528
                          begin
529
                            A <= #1 TmpAddr;
530
                            PC <= #1 TmpAddr;
531
                          end
532
                        else if (last_mcycle && NMICycle == 1'b1 )
533
                          begin
534
                            A <= #1 16'b0000000001100110;
535
                            PC <= #1 16'b0000000001100110;
536
                          end
537
                        else if (mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
538
                          begin
539
                            A[15:8] <= #1 I;
540
                            A[7:0] <= #1 TmpAddr[7:0];
541
                            PC[15:8] <= #1 I;
542
                            PC[7:0] <= #1 TmpAddr[7:0];
543
                          end
544
                        else
545
                          begin
546
                            case (Set_Addr_To)
547
                              aXY :
548
                                begin
549
                                  if (XY_State == 2'b00 )
550
                                    begin
551
                                      A <= #1 RegBusC;
552
                                    end
553
                                  else
554
                                    begin
555
                                      if (NextIs_XY_Fetch == 1'b1 )
556
                                        begin
557
                                          A <= #1 PC;
558
                                        end
559
                                      else
560
                                        begin
561
                                          A <= #1 TmpAddr;
562
                                        end
563
                                    end // else: !if(XY_State == 2'b00 )
564
                                end // case: aXY
565
 
566
                              aIOA :
567
                                begin
568
                                  if (Mode == 3 )
569
                                    begin
570
                                      // Memory map I/O on GBZ80
571
                                      A[15:8] <= #1 8'hFF;
572
                                    end
573
                                  else if (Mode == 2 )
574
                                    begin
575
                                      // Duplicate I/O address on 8080
576
                                      A[15:8] <= #1 DI_Reg;
577
                                    end
578
                                  else
579
                                    begin
580
                                      A[15:8] <= #1 ACC;
581
                                    end
582
                                  A[7:0] <= #1 DI_Reg;
583
                                end // case: aIOA
584
 
585
 
586
                              aSP :
587
                                begin
588
                                  A <= #1 SP;
589
                                end
590
 
591
                              aBC :
592
                                begin
593
                                  if (Mode == 3 && iorq_i == 1'b1 )
594
                                    begin
595
                                      // Memory map I/O on GBZ80
596
                                      A[15:8] <= #1 8'hFF;
597
                                      A[7:0] <= #1 RegBusC[7:0];
598
                                    end
599
                                  else
600
                                    begin
601
                                      A <= #1 RegBusC;
602
                                    end
603
                                end // case: aBC
604
 
605
                              aDE :
606
                                begin
607
                                  A <= #1 RegBusC;
608
                                end
609
 
610
                              aZI :
611
                                begin
612
                                  if (Inc_WZ == 1'b1 )
613
                                    begin
614
                                      A <= #1 TmpAddr + 1;
615
                                    end
616
                                  else
617
                                    begin
618
                                      A[15:8] <= #1 DI_Reg;
619
                                      A[7:0] <= #1 TmpAddr[7:0];
620
                                    end
621
                                end // case: aZI
622
 
623
                              default   :
624
                                begin
625
                                  A <= #1 PC;
626
                                end
627
                            endcase // case(Set_Addr_To)
628
 
629
                          end // else: !if(mcycle[2] && IntCycle == 1'b1 && IStatus == 2'b10 )
630
 
631
 
632
                      Save_ALU_r <= #1 Save_ALU;
633
                      ALU_Op_r <= #1 ALU_Op;
634
 
635
                      if (I_CPL == 1'b1 )
636
                        begin
637
                          // CPL
638
                          ACC <= #1 ~ ACC;
639
                          F[Flag_Y] <= #1 ~ ACC[5];
640
                          F[Flag_H] <= #1 1'b1;
641
                          F[Flag_X] <= #1 ~ ACC[3];
642
                          F[Flag_N] <= #1 1'b1;
643
                        end
644
                      if (I_CCF == 1'b1 )
645
                        begin
646
                          // CCF
647
                          F[Flag_C] <= #1 ~ F[Flag_C];
648
                          F[Flag_Y] <= #1 ACC[5];
649
                          F[Flag_H] <= #1 F[Flag_C];
650
                          F[Flag_X] <= #1 ACC[3];
651
                          F[Flag_N] <= #1 1'b0;
652
                        end
653
                      if (I_SCF == 1'b1 )
654
                        begin
655
                          // SCF
656
                          F[Flag_C] <= #1 1'b1;
657
                          F[Flag_Y] <= #1 ACC[5];
658
                          F[Flag_H] <= #1 1'b0;
659
                          F[Flag_X] <= #1 ACC[3];
660
                          F[Flag_N] <= #1 1'b0;
661
                        end
662
                    end // if (T_Res == 1'b1 )
663
 
664
 
665
                  if (tstate[2] && wait_n == 1'b1 )
666
                    begin
667
                      if (ISet == 2'b01 && mcycle[6] )
668
                        begin
669
                          IR <= #1 dinst;
670
                        end
671
                      if (JumpE == 1'b1 )
672
                        begin
673
                          PC <= #1 PC16;
674
                        end
675
                      else if (Inc_PC == 1'b1 )
676
                        begin
677
                          //PC <= #1 PC + 1;
678
                          PC <= #1 PC16;
679
                        end
680
                      if (BTR_r == 1'b1 )
681
                        begin
682
                          //PC <= #1 PC - 2;
683
                          PC <= #1 PC16;
684
                        end
685
                      if (RstP == 1'b1 )
686
                        begin
687
                          TmpAddr <= #1 { 10'h0, IR[5:3], 3'h0 };
688
                          //TmpAddr <= #1 (others =>1'b0);
689
                          //TmpAddr[5:3] <= #1 IR[5:3];
690
                        end
691
                    end
692
                  if (tstate[3] && mcycle[5] )
693
                    begin
694
                      TmpAddr <= #1 SP16;
695
                    end
696
 
697
                  if ((tstate[2] && wait_n == 1'b1) || (tstate[4] && mcycle[0]) )
698
                    begin
699
                      if (IncDec_16[2:0] == 3'b111 )
700
                        begin
701
                          SP <= #1 SP16;
702
                        end
703
                    end
704
 
705
                  if (LDSPHL == 1'b1 )
706
                    begin
707
                      SP <= #1 RegBusC;
708
                    end
709
                  if (ExchangeAF == 1'b1 )
710
                    begin
711
                      Ap <= #1 ACC;
712
                      ACC <= #1 Ap;
713
                      Fp <= #1 F;
714
                      F <= #1 Fp;
715
                    end
716
                  if (ExchangeRS == 1'b1 )
717
                    begin
718
                      Alternate <= #1 ~ Alternate;
719
                    end
720
                end // else: !if(mcycle  == 3'b001 && tstate(2) == 1'b0 )
721
 
722
 
723
              if (tstate[3] )
724
                begin
725
                  if (LDZ == 1'b1 )
726
                    begin
727
                      TmpAddr[7:0] <= #1 DI_Reg;
728
                    end
729
                  if (LDW == 1'b1 )
730
                    begin
731
                      TmpAddr[15:8] <= #1 DI_Reg;
732
                    end
733
 
734
                  if (Special_LD[2] == 1'b1 )
735
                    begin
736
                      case (Special_LD[1:0])
737
                        2'b00 :
738
                          begin
739
                            ACC <= #1 I;
740
                            F[Flag_P] <= #1 IntE_FF2;
741
                            F[Flag_Z] <= (I == 0);
742
                            F[Flag_S] <= I[7];
743
                            F[Flag_H] <= 0;
744
                            F[Flag_N] <= 0;
745
                          end
746
 
747
                        2'b01 :
748
                          begin
749
                            `ifdef TV80_REFRESH
750
                            ACC <= #1 R;
751
                            `else
752
                            ACC <= #1 0;
753
                            `endif
754
                            F[Flag_P] <= #1 IntE_FF2;
755
                            F[Flag_Z] <= (I == 0);
756
                            F[Flag_S] <= I[7];
757
                            F[Flag_H] <= 0;
758
                            F[Flag_N] <= 0;
759
                          end
760
 
761
                        2'b10 :
762
                          I <= #1 ACC;
763
 
764
                        `ifdef TV80_REFRESH
765
                        default :
766
                          R <= #1 ACC;
767
                        `else
768
                        default : ;
769
                        `endif
770
                      endcase
771
                    end
772
                end // if (tstate == 3 )
773
 
774
 
775
              if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
776
                begin
777
                  if (Mode == 3 )
778
                    begin
779
                      F[6] <= #1 F_Out[6];
780
                      F[5] <= #1 F_Out[5];
781
                      F[7] <= #1 F_Out[7];
782
                      if (PreserveC_r == 1'b0 )
783
                        begin
784
                          F[4] <= #1 F_Out[4];
785
                        end
786
                    end
787
                  else
788
                    begin
789
                      F[7:1] <= #1 F_Out[7:1];
790
                      if (PreserveC_r == 1'b0 )
791
                        begin
792
                          F[Flag_C] <= #1 F_Out[0];
793
                        end
794
                    end
795
                end // if ((I_DJNZ == 1'b0 && Save_ALU_r == 1'b1) || ALU_Op_r == 4'b1001 )
796
 
797
              if (T_Res == 1'b1 && I_INRC == 1'b1 )
798
                begin
799
                  F[Flag_H] <= #1 1'b0;
800
                  F[Flag_N] <= #1 1'b0;
801
                  if (DI_Reg[7:0] == 8'b00000000 )
802
                    begin
803
                      F[Flag_Z] <= #1 1'b1;
804
                    end
805
                  else
806
                    begin
807
                      F[Flag_Z] <= #1 1'b0;
808
                    end
809
                  F[Flag_S] <= #1 DI_Reg[7];
810
                  F[Flag_P] <= #1 ~ (^DI_Reg[7:0]);
811
                end // if (T_Res == 1'b1 && I_INRC == 1'b1 )
812
 
813
 
814
              if (tstate[1] && Auto_Wait_t1 == 1'b0 )
815
                begin
816
                  dout <= #1 BusB;
817
                  if (I_RLD == 1'b1 )
818
                    begin
819
                      dout[3:0] <= #1 BusA[3:0];
820
                      dout[7:4] <= #1 BusB[3:0];
821
                    end
822
                  if (I_RRD == 1'b1 )
823
                    begin
824
                      dout[3:0] <= #1 BusB[7:4];
825
                      dout[7:4] <= #1 BusA[3:0];
826
                    end
827
                end
828
 
829
              if (T_Res == 1'b1 )
830
                begin
831
                  Read_To_Reg_r[3:0] <= #1 Set_BusA_To;
832
                  Read_To_Reg_r[4] <= #1 Read_To_Reg;
833
                  if (Read_To_Acc == 1'b1 )
834
                    begin
835
                      Read_To_Reg_r[3:0] <= #1 4'b0111;
836
                      Read_To_Reg_r[4] <= #1 1'b1;
837
                    end
838
                end
839
 
840
              if (tstate[1] && I_BT == 1'b1 )
841
                begin
842
                  F[Flag_X] <= #1 ALU_Q[3];
843
                  F[Flag_Y] <= #1 ALU_Q[1];
844
                  F[Flag_H] <= #1 1'b0;
845
                  F[Flag_N] <= #1 1'b0;
846
                end
847
              if (I_BC == 1'b1 || I_BT == 1'b1 )
848
                begin
849
                  F[Flag_P] <= #1 IncDecZ;
850
                end
851
 
852
              if ((tstate[1] && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||
853
                  (Save_ALU_r == 1'b1 && ALU_Op_r != 4'b0111) )
854
                begin
855
                  case (Read_To_Reg_r)
856
                    5'b10111 :
857
                      ACC <= #1 Save_Mux;
858
                    5'b10110 :
859
                      dout <= #1 Save_Mux;
860
                    5'b11000 :
861
                      SP[7:0] <= #1 Save_Mux;
862
                    5'b11001 :
863
                      SP[15:8] <= #1 Save_Mux;
864
                    5'b11011 :
865
                      F <= #1 Save_Mux;
866
                    default : ;
867
                  endcase
868
                end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...              
869
            end // if (ClkEn == 1'b1 )         
870
        end // else: !if(reset_n == 1'b0 )
871
    end
872
 
873
 
874
  //-------------------------------------------------------------------------
875
  //
876
  // BC('), DE('), HL('), IX && IY
877
  //
878
  //-------------------------------------------------------------------------
879
  always @ (posedge clk)
880
    begin
881
      if (ClkEn == 1'b1 )
882
        begin
883
          // Bus A / Write
884
          RegAddrA_r <= #1  { Alternate, Set_BusA_To[2:1] };
885
          if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusA_To[2:1] == 2'b10 )
886
            begin
887
              RegAddrA_r <= #1 { XY_State[1],  2'b11 };
888
            end
889
 
890
          // Bus B
891
          RegAddrB_r <= #1 { Alternate, Set_BusB_To[2:1] };
892
          if (XY_Ind == 1'b0 && XY_State != 2'b00 && Set_BusB_To[2:1] == 2'b10 )
893
            begin
894
              RegAddrB_r <= #1 { XY_State[1],  2'b11 };
895
            end
896
 
897
          // Address from register
898
          RegAddrC <= #1 { Alternate,  Set_Addr_To[1:0] };
899
          // Jump (HL), LD SP,HL
900
          if ((JumpXY == 1'b1 || LDSPHL == 1'b1) )
901
            begin
902
              RegAddrC <= #1 { Alternate, 2'b10 };
903
            end
904
          if (((JumpXY == 1'b1 || LDSPHL == 1'b1) && XY_State != 2'b00) || (mcycle[5]) )
905
            begin
906
              RegAddrC <= #1 { XY_State[1],  2'b11 };
907
            end
908
 
909
          if (I_DJNZ == 1'b1 && Save_ALU_r == 1'b1 && Mode < 2 )
910
            begin
911
              IncDecZ <= #1 F_Out[Flag_Z];
912
            end
913
          if ((tstate[2] || (tstate[3] && mcycle[0])) && IncDec_16[2:0] == 3'b100 )
914
            begin
915
              if (ID16 == 0 )
916
                begin
917
                  IncDecZ <= #1 1'b0;
918
                end
919
              else
920
                begin
921
                  IncDecZ <= #1 1'b1;
922
                end
923
            end
924
 
925
          RegBusA_r <= #1 RegBusA;
926
        end
927
 
928
    end // always @ (posedge clk)
929
 
930
 
931
  always @(/*AUTOSENSE*/Alternate or ExchangeDH or IncDec_16
932
           or RegAddrA_r or RegAddrB_r or XY_State or mcycle or tstate)
933
    begin
934
      if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && XY_State == 2'b00)
935
        RegAddrA = { Alternate, IncDec_16[1:0] };
936
      else if ((tstate[2] || (tstate[3] && mcycle[0] && IncDec_16[2] == 1'b1)) && IncDec_16[1:0] == 2'b10)
937
        RegAddrA = { XY_State[1], 2'b11 };
938
      else if (ExchangeDH == 1'b1 && tstate[3])
939
        RegAddrA = { Alternate, 2'b10 };
940
      else if (ExchangeDH == 1'b1 && tstate[4])
941
        RegAddrA = { Alternate, 2'b01 };
942
      else
943
        RegAddrA = RegAddrA_r;
944
 
945
      if (ExchangeDH == 1'b1 && tstate[3])
946
        RegAddrB = { Alternate, 2'b01 };
947
      else
948
        RegAddrB = RegAddrB_r;
949
    end // always @ *
950
 
951
 
952
  always @(/*AUTOSENSE*/ALU_Op_r or Auto_Wait_t1 or ExchangeDH
953
           or IncDec_16 or Read_To_Reg_r or Save_ALU_r or mcycle
954
           or tstate or wait_n)
955
    begin
956
      RegWEH = 1'b0;
957
      RegWEL = 1'b0;
958
      if ((tstate[1] && ~Save_ALU_r && ~Auto_Wait_t1) ||
959
          (Save_ALU_r && (ALU_Op_r != 4'b0111)) )
960
        begin
961
          case (Read_To_Reg_r)
962
            5'b10000 , 5'b10001 , 5'b10010 , 5'b10011 , 5'b10100 , 5'b10101 :
963
              begin
964
                RegWEH = ~ Read_To_Reg_r[0];
965
                RegWEL = Read_To_Reg_r[0];
966
              end // UNMATCHED !!
967
            default : ;
968
          endcase // case(Read_To_Reg_r)
969
 
970
        end // if ((tstate == 1 && Save_ALU_r == 1'b0 && Auto_Wait_t1 == 1'b0) ||...
971
 
972
 
973
      if (ExchangeDH && (tstate[3] || tstate[4]) )
974
        begin
975
          RegWEH = 1'b1;
976
          RegWEL = 1'b1;
977
        end
978
 
979
      if (IncDec_16[2] && ((tstate[2] && wait_n && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
980
        begin
981
          case (IncDec_16[1:0])
982
            2'b00 , 2'b01 , 2'b10 :
983
              begin
984
                RegWEH = 1'b1;
985
                RegWEL = 1'b1;
986
              end // UNMATCHED !!
987
            default : ;
988
          endcase
989
        end
990
    end // always @ *
991
 
992
 
993
  always @(/*AUTOSENSE*/ExchangeDH or ID16 or IncDec_16 or RegBusA_r
994
           or RegBusB or Save_Mux or mcycle or tstate)
995
    begin
996
      RegDIH = Save_Mux;
997
      RegDIL = Save_Mux;
998
 
999
      if (ExchangeDH == 1'b1 && tstate[3] )
1000
        begin
1001
          RegDIH = RegBusB[15:8];
1002
          RegDIL = RegBusB[7:0];
1003
        end
1004
      else if (ExchangeDH == 1'b1 && tstate[4] )
1005
        begin
1006
          RegDIH = RegBusA_r[15:8];
1007
          RegDIL = RegBusA_r[7:0];
1008
        end
1009
      else if (IncDec_16[2] == 1'b1 && ((tstate[2] && ~mcycle[0]) || (tstate[3] && mcycle[0])) )
1010
        begin
1011
          RegDIH = ID16[15:8];
1012
          RegDIL = ID16[7:0];
1013
        end
1014
    end
1015
 
1016
  tv80_reg i_reg
1017
    (
1018
     .clk                  (clk),
1019
     .CEN                  (ClkEn),
1020
     .WEH                  (RegWEH),
1021
     .WEL                  (RegWEL),
1022
     .AddrA                (RegAddrA),
1023
     .AddrB                (RegAddrB),
1024
     .AddrC                (RegAddrC),
1025
     .DIH                  (RegDIH),
1026
     .DIL                  (RegDIL),
1027
     .DOAH                 (RegBusA[15:8]),
1028
     .DOAL                 (RegBusA[7:0]),
1029
     .DOBH                 (RegBusB[15:8]),
1030
     .DOBL                 (RegBusB[7:0]),
1031
     .DOCH                 (RegBusC[15:8]),
1032
     .DOCL                 (RegBusC[7:0])
1033
     );
1034
 
1035
  //-------------------------------------------------------------------------
1036
  //
1037
  // Buses
1038
  //
1039
  //-------------------------------------------------------------------------
1040
 
1041
  always @ (posedge clk)
1042
    begin
1043
      if (ClkEn == 1'b1 )
1044
        begin
1045
          case (Set_BusB_To)
1046
            4'b0111 :
1047
              BusB <= #1 ACC;
1048
            4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
1049
              begin
1050
                if (Set_BusB_To[0] == 1'b1 )
1051
                  begin
1052
                    BusB <= #1 RegBusB[7:0];
1053
                  end
1054
                else
1055
                  begin
1056
                    BusB <= #1 RegBusB[15:8];
1057
                  end
1058
              end
1059
            4'b0110 :
1060
              BusB <= #1 DI_Reg;
1061
            4'b1000 :
1062
              BusB <= #1 SP[7:0];
1063
            4'b1001 :
1064
              BusB <= #1 SP[15:8];
1065
            4'b1010 :
1066
              BusB <= #1 8'b00000001;
1067
            4'b1011 :
1068
              BusB <= #1 F;
1069
            4'b1100 :
1070
              BusB <= #1 PC[7:0];
1071
            4'b1101 :
1072
              BusB <= #1 PC[15:8];
1073
            4'b1110 :
1074
              BusB <= #1 8'b00000000;
1075
            default :
1076
              BusB <= #1 8'h0;
1077
          endcase
1078
 
1079
          case (Set_BusA_To)
1080
            4'b0111 :
1081
              BusA <= #1 ACC;
1082
            4'b0000 , 4'b0001 , 4'b0010 , 4'b0011 , 4'b0100 , 4'b0101 :
1083
              begin
1084
                if (Set_BusA_To[0] == 1'b1 )
1085
                  begin
1086
                    BusA <= #1 RegBusA[7:0];
1087
                  end
1088
                else
1089
                  begin
1090
                    BusA <= #1 RegBusA[15:8];
1091
                  end
1092
              end
1093
            4'b0110 :
1094
              BusA <= #1 DI_Reg;
1095
            4'b1000 :
1096
              BusA <= #1 SP[7:0];
1097
            4'b1001 :
1098
              BusA <= #1 SP[15:8];
1099
            4'b1010 :
1100
              BusA <= #1 8'b00000000;
1101
            default :
1102
              BusA <= #1  8'h0;
1103
          endcase
1104
        end
1105
    end
1106
 
1107
  //-------------------------------------------------------------------------
1108
  //
1109
  // Generate external control signals
1110
  //
1111
  //-------------------------------------------------------------------------
1112
`ifdef TV80_REFRESH
1113
  always @ (posedge clk or negedge reset_n)
1114
    begin
1115
      if (reset_n == 1'b0 )
1116
        begin
1117
          rfsh_n <= #1 1'b1;
1118
        end
1119
      else
1120
        begin
1121
          if (cen == 1'b1 )
1122
            begin
1123
              if (mcycle[0] && ((tstate[2]  && wait_n == 1'b1) || tstate[3]) )
1124
                begin
1125
                  rfsh_n <= #1 1'b0;
1126
                end
1127
              else
1128
                begin
1129
                  rfsh_n <= #1 1'b1;
1130
                end
1131
            end
1132
        end
1133
    end // always @ (posedge clk or negedge reset_n)
1134
`else // !`ifdef TV80_REFRESH
1135
  assign rfsh_n = 1'b1;
1136
`endif
1137
 
1138
  always @(/*AUTOSENSE*/BusAck or Halt_FF or I_DJNZ or IntCycle
1139
           or IntE_FF1 or di or iorq_i or mcycle or tstate)
1140
    begin
1141
      mc = mcycle;
1142
      ts = tstate;
1143
      DI_Reg = di;
1144
      halt_n = ~ Halt_FF;
1145
      busak_n = ~ BusAck;
1146
      intcycle_n = ~ IntCycle;
1147
      IntE = IntE_FF1;
1148
      iorq = iorq_i;
1149
      stop = I_DJNZ;
1150
    end
1151
 
1152
  //-----------------------------------------------------------------------
1153
  //
1154
  // Syncronise inputs
1155
  //
1156
  //-----------------------------------------------------------------------
1157
 
1158
  always @ (posedge clk or negedge reset_n)
1159
    begin : sync_inputs
1160
      if (~reset_n)
1161
        begin
1162
          BusReq_s <= #1 1'b0;
1163
          INT_s <= #1 1'b0;
1164
          NMI_s <= #1 1'b0;
1165
          Oldnmi_n <= #1 1'b0;
1166
        end
1167
      else
1168
        begin
1169
          if (cen == 1'b1 )
1170
            begin
1171
              BusReq_s <= #1 ~ busrq_n;
1172
              INT_s <= #1 ~ int_n;
1173
              if (NMICycle == 1'b1 )
1174
                begin
1175
                  NMI_s <= #1 1'b0;
1176
                end
1177
              else if (nmi_n == 1'b0 && Oldnmi_n == 1'b1 )
1178
                begin
1179
                  NMI_s <= #1 1'b1;
1180
                end
1181
              Oldnmi_n <= #1 nmi_n;
1182
            end
1183
        end
1184
    end
1185
 
1186
  //-----------------------------------------------------------------------
1187
  //
1188
  // Main state machine
1189
  //
1190
  //-----------------------------------------------------------------------
1191
 
1192
  always @ (posedge clk or negedge reset_n)
1193
    begin
1194
      if (reset_n == 1'b0 )
1195
        begin
1196
          mcycle <= #1 7'b0000001;
1197
          tstate <= #1 7'b0000001;
1198
          Pre_XY_F_M <= #1 3'b000;
1199
          Halt_FF <= #1 1'b0;
1200
          BusAck <= #1 1'b0;
1201
          NMICycle <= #1 1'b0;
1202
          IntCycle <= #1 1'b0;
1203
          IntE_FF1 <= #1 1'b0;
1204
          IntE_FF2 <= #1 1'b0;
1205
          No_BTR <= #1 1'b0;
1206
          Auto_Wait_t1 <= #1 1'b0;
1207
          Auto_Wait_t2 <= #1 1'b0;
1208
          m1_n <= #1 1'b1;
1209
        end
1210
      else
1211
        begin
1212
          if (cen == 1'b1 )
1213
            begin
1214
              if (T_Res == 1'b1 )
1215
                begin
1216
                  Auto_Wait_t1 <= #1 1'b0;
1217
                end
1218
              else
1219
                begin
1220
                  Auto_Wait_t1 <= #1 Auto_Wait || (iorq_i & ~Auto_Wait_t2);
1221
                end
1222
              Auto_Wait_t2 <= #1 Auto_Wait_t1 & !T_Res;
1223
              No_BTR <= #1 (I_BT && (~ IR[4] || ~ F[Flag_P])) ||
1224
                        (I_BC && (~ IR[4] || F[Flag_Z] || ~ F[Flag_P])) ||
1225
                        (I_BTR && (~ IR[4] || F[Flag_Z]));
1226
              if (tstate[2] )
1227
                begin
1228
                  if (SetEI == 1'b1 )
1229
                    begin
1230
                      if (!NMICycle)
1231
                        IntE_FF1 <= #1 1'b1;
1232
                      IntE_FF2 <= #1 1'b1;
1233
                    end
1234
                  if (I_RETN == 1'b1 )
1235
                    begin
1236
                      IntE_FF1 <= #1 IntE_FF2;
1237
                    end
1238
                end
1239
              if (tstate[3] )
1240
                begin
1241
                  if (SetDI == 1'b1 )
1242
                    begin
1243
                      IntE_FF1 <= #1 1'b0;
1244
                      IntE_FF2 <= #1 1'b0;
1245
                    end
1246
                end
1247
              if (IntCycle == 1'b1 || NMICycle == 1'b1 )
1248
                begin
1249
                  Halt_FF <= #1 1'b0;
1250
                end
1251
              if (mcycle[0] && tstate[2] && wait_n == 1'b1 )
1252
                begin
1253
                  m1_n <= #1 1'b1;
1254
                end
1255
              if (BusReq_s == 1'b1 && BusAck == 1'b1 )
1256
                begin
1257
                end
1258
              else
1259
                begin
1260
                  BusAck <= #1 1'b0;
1261
                  if (tstate[2] && wait_n == 1'b0 )
1262
                    begin
1263
                    end
1264
                  else if (T_Res == 1'b1 )
1265
                    begin
1266
                      if (Halt == 1'b1 )
1267
                        begin
1268
                          Halt_FF <= #1 1'b1;
1269
                        end
1270
                      if (BusReq_s == 1'b1 )
1271
                        begin
1272
                          BusAck <= #1 1'b1;
1273
                        end
1274
                      else
1275
                        begin
1276
                          tstate <= #1 7'b0000010;
1277
                          if (NextIs_XY_Fetch == 1'b1 )
1278
                            begin
1279
                              mcycle <= #1 7'b0100000;
1280
                              Pre_XY_F_M <= #1 mcyc_to_number(mcycle);
1281
                              if (IR == 8'b00110110 && Mode == 0 )
1282
                                begin
1283
                                  Pre_XY_F_M <= #1 3'b010;
1284
                                end
1285
                            end
1286
                          else if ((mcycle[6]) || (mcycle[5] && Mode == 1 && ISet != 2'b01) )
1287
                            begin
1288
                              mcycle <= #1 number_to_bitvec(Pre_XY_F_M + 1);
1289
                            end
1290
                          else if ((last_mcycle) ||
1291
                                   No_BTR == 1'b1 ||
1292
                                   (mcycle[1] && I_DJNZ == 1'b1 && IncDecZ == 1'b1) )
1293
                            begin
1294
                              m1_n <= #1 1'b0;
1295
                              mcycle <= #1 7'b0000001;
1296
                              IntCycle <= #1 1'b0;
1297
                              NMICycle <= #1 1'b0;
1298
                              if (NMI_s == 1'b1 && Prefix == 2'b00 )
1299
                                begin
1300
                                  NMICycle <= #1 1'b1;
1301
                                  IntE_FF1 <= #1 1'b0;
1302
                                end
1303
                              else if ((IntE_FF1 == 1'b1 && INT_s == 1'b1) && Prefix == 2'b00 && SetEI == 1'b0 )
1304
                                begin
1305
                                  IntCycle <= #1 1'b1;
1306
                                  IntE_FF1 <= #1 1'b0;
1307
                                  IntE_FF2 <= #1 1'b0;
1308
                                end
1309
                            end
1310
                          else
1311
                            begin
1312
                              mcycle <= #1 { mcycle[5:0], mcycle[6] };
1313
                            end
1314
                        end
1315
                    end
1316
                  else
1317
                    begin   // verilog has no "nor" operator
1318
                      if ( ~(Auto_Wait == 1'b1 && Auto_Wait_t2 == 1'b0) &&
1319
                           ~(IOWait == 1 && iorq_i == 1'b1 && Auto_Wait_t1 == 1'b0) )
1320
                        begin
1321
                          tstate <= #1 { tstate[5:0], tstate[6] };
1322
                        end
1323
                    end
1324
                end
1325
              if (tstate[0])
1326
                begin
1327
                  m1_n <= #1 1'b0;
1328
                end
1329
            end
1330
        end
1331
    end
1332
 
1333
  always @(/*AUTOSENSE*/BTR_r or DI_Reg or IncDec_16 or JumpE or PC
1334
           or RegBusA or RegBusC or SP or tstate)
1335
    begin
1336
      if (JumpE == 1'b1 )
1337
        begin
1338
          PC16_B = { {8{DI_Reg[7]}}, DI_Reg };
1339
        end
1340
      else if (BTR_r == 1'b1 )
1341
        begin
1342
          PC16_B = -2;
1343
        end
1344
      else
1345
        begin
1346
          PC16_B = 1;
1347
        end
1348
 
1349
      if (tstate[3])
1350
        begin
1351
          SP16_A = RegBusC;
1352
          SP16_B = { {8{DI_Reg[7]}}, DI_Reg };
1353
        end
1354
      else
1355
        begin
1356
          // suspect that ID16 and SP16 could be shared
1357
          SP16_A = SP;
1358
 
1359
          if (IncDec_16[3] == 1'b1)
1360
            SP16_B = -1;
1361
          else
1362
            SP16_B = 1;
1363
        end
1364
 
1365
      if (IncDec_16[3])
1366
        ID16_B = -1;
1367
      else
1368
        ID16_B = 1;
1369
 
1370
      ID16 = RegBusA + ID16_B;
1371
      PC16 = PC + PC16_B;
1372
      SP16 = SP16_A + SP16_B;
1373
    end // always @ *
1374
 
1375
 
1376
  always @(/*AUTOSENSE*/IntCycle or NMICycle or mcycle)
1377
    begin
1378
      Auto_Wait = 1'b0;
1379
      if (IntCycle == 1'b1 || NMICycle == 1'b1 )
1380
        begin
1381
          if (mcycle[0] )
1382
            begin
1383
              Auto_Wait = 1'b1;
1384
            end
1385
        end
1386
    end // always @ *
1387
 
1388
endmodule // T80
1389
 

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