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[/] [zx_ula/] [branches/] [xilinx/] [ulaplus_replacement-upgrade_for_sp16-48k/] [rtl_ulaplus/] [ulaplus_tld.v] - Blame information for rev 29

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:        Dept. Architecture and Computing Technology. University of Seville
// Engineer:       Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es
// 
// Create Date:    19:13:39 4-Apr-2012 
// Design Name:    ULAplus replacement
// Module Name:    ulaplus_tld
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 1.00 - File Created
// Additional Comments: GPL License policies apply to the contents of this file.
//
//////////////////////////////////////////////////////////////////////////////////
module ulaplus_tld(
         // Clock and reset
    input clk50,
         input reset,
 
         // CPU interface
         input a15,
         input a14,
         input a7,
         input a6,
         input a2,
         input mreq_n,
         input ioreq_n,
         input iorq_n,
         input rd_n,
         input wr_n,
         inout [7:0] d,
         output int_n,
         output cpuclk_n,
 
         // DRAM interface
         output [6:0] va,
         output ras_n,
         output cas_n,
         output dramwe_n,
 
         // ROM interface
         output romcs_n,
 
         // Keyboard & audio interface
         input [4:0] kbd,
    output audio_out,
         input ear,
 
         // RGB video interface
         output [2:0] r,
         output [2:0] g,
         output [2:0] b,
         output csync
    );
 
        wire clk28;
        master_ula_clock clock28mhz (
    .CLKIN_IN(clk50),
    .CLKFX_OUT(clk28),
    .CLKIN_IBUFG_OUT(),
    .CLK0_OUT()
    );
 
   /////////////////////////////////////
   // The ULA
   /////////////////////////////////////        
        wire ula_r,ula_g,ula_b,ula_i,ulaplus_enabled;
        wire mic,spk;
        wire [7:0] rgbulaplus;
 
        ula the_ula (
                .clk28(clk28),
                .reset_n(reset_n),
                .a15(a15),
                .a14(a14),
                .a7(a7),
                .a6(a6),
                .a2(a2),
                .d(d),
                .mreq_n(mreq_n),
                .ioreq_n(ioreq_n),
                .iorq_n(iorq_n),
                .rd_n(rd_n),
                .wr_n(wr_n),
                .clkcpu(cpuclk_n),
                .int_n(int_n),
                .va(va),
                .ras_n(ras_n),
                .cas_n(cas_n),
                .dramwe_n(dramwe_n),
                .ear(ear),
                .mic(mic),
                .spk(spk),
                .kbd(kbd),
                .r(ula_r),
                .g(ula_g),
                .b(ula_b),
                .i(ula_i),
                .rgbulaplus(rgbulaplus),
                .ulaplus_enabled(ulaplus_enabled),
                .csync(csync)
        );
 
   /////////////////////////////////////
   // ULA/ULA+ video selector and enconding
   /////////////////////////////////////        
   rgb_builder video_final_stage (
                .select(ulaplus_enabled),
                .ri(ula_r),
                .gi(ula_g),
                .bi(ula_b),
                .hi(ula_i),
                .rgbulap(rgbulaplus),
                .r(r),
                .g(g),
                .b(b)
    );
 
   /////////////////////////////////////
   // Audio mixer
   /////////////////////////////////////        
        mixer audio_mix (
                .clkdac(clk28),
                .reset_n(reset_n),
                .ear(ear),
                .mic(mic),
                .spk(spk),
                .audio(audio_out)
        );
endmodule

Line No.	Rev	Author	Line
1	26	mcleod_ide	`timescale 1ns / 1ps
2			`//////////////////////////////////////////////////////////////////////////////////`
3			`// Company: Dept. Architecture and Computing Technology. University of Seville`
4			`// Engineer: Miguel Angel Rodriguez Jodar. rodriguj@atc.us.es`
5			`//`
6			`// Create Date: 19:13:39 4-Apr-2012`
7			`// Design Name: ULAplus replacement`
8			`// Module Name: ulaplus_tld`
9			`// Project Name:`
10			`// Target Devices:`
11			`// Tool versions:`
12			`// Description:`
13			`//`
14			`// Dependencies:`
15			`//`
16			`// Revision:`
17			`// Revision 1.00 - File Created`
18			`// Additional Comments: GPL License policies apply to the contents of this file.`
19			`//`
20			`//////////////////////////////////////////////////////////////////////////////////`
21			`module ulaplus_tld(`
22			`// Clock and reset`
23			`input clk50,`
24			`input reset,`
25
26			`// CPU interface`
27			`input a15,`
28			`input a14,`
29			`input a7,`
30			`input a6,`
31			`input a2,`
32			`input mreq_n,`
33			`input ioreq_n,`
34			`input iorq_n,`
35			`input rd_n,`
36			`input wr_n,`
37			`inout [7:0] d,`
38			`output int_n,`
39			`output cpuclk_n,`
40
41			`// DRAM interface`
42			`output [6:0] va,`
43			`output ras_n,`
44			`output cas_n,`
45			`output dramwe_n,`
46
47			`// ROM interface`
48			`output romcs_n,`
49
50			`// Keyboard & audio interface`
51			`input [4:0] kbd,`
52			`output audio_out,`
53			`input ear,`
54
55			`// RGB video interface`
56			`output [2:0] r,`
57			`output [2:0] g,`
58			`output [2:0] b,`
59			`output csync`
60			`);`
61
62	29	mcleod_ide	`wire clk28;`
63			`master_ula_clock clock28mhz (`
64	26	mcleod_ide	`.CLKIN_IN(clk50),`
65	29	mcleod_ide	`.CLKFX_OUT(clk28),`
66	26	mcleod_ide	`.CLKIN_IBUFG_OUT(),`
67			`.CLK0_OUT()`
68			`);`
69
70			`/////////////////////////////////////`
71			`// The ULA`
72			`/////////////////////////////////////`
73			`wire ula_r,ula_g,ula_b,ula_i,ulaplus_enabled;`
74			`wire mic,spk;`
75			`wire [7:0] rgbulaplus;`
76
77			`ula the_ula (`
78	29	mcleod_ide	`.clk28(clk28),`
79	26	mcleod_ide	`.reset_n(reset_n),`
80			`.a15(a15),`
81			`.a14(a14),`
82			`.a7(a7),`
83			`.a6(a6),`
84			`.a2(a2),`
85	29	mcleod_ide	`.d(d),`
86	26	mcleod_ide	`.mreq_n(mreq_n),`
87			`.ioreq_n(ioreq_n),`
88			`.iorq_n(iorq_n),`
89			`.rd_n(rd_n),`
90			`.wr_n(wr_n),`
91			`.clkcpu(cpuclk_n),`
92			`.int_n(int_n),`
93	29	mcleod_ide	`.va(va),`
94			`.ras_n(ras_n),`
95			`.cas_n(cas_n),`
96			`.dramwe_n(dramwe_n),`
97	26	mcleod_ide	`.ear(ear),`
98			`.mic(mic),`
99			`.spk(spk),`
100			`.kbd(kbd),`
101			`.r(ula_r),`
102			`.g(ula_g),`
103			`.b(ula_b),`
104			`.i(ula_i),`
105			`.rgbulaplus(rgbulaplus),`
106			`.ulaplus_enabled(ulaplus_enabled),`
107			`.csync(csync)`
108			`);`
109
110			`/////////////////////////////////////`
111			`// ULA/ULA+ video selector and enconding`
112			`/////////////////////////////////////`
113			`rgb_builder video_final_stage (`
114			`.select(ulaplus_enabled),`
115			`.ri(ula_r),`
116			`.gi(ula_g),`
117			`.bi(ula_b),`
118			`.hi(ula_i),`
119			`.rgbulap(rgbulaplus),`
120			`.r(r),`
121			`.g(g),`
122			`.b(b)`
123			`);`
124
125			`/////////////////////////////////////`
126			`// Audio mixer`
127			`/////////////////////////////////////`
128			`mixer audio_mix (`
129	29	mcleod_ide	`.clkdac(clk28),`
130	26	mcleod_ide	`.reset_n(reset_n),`
131			`.ear(ear),`
132			`.mic(mic),`
133			`.spk(spk),`
134			`.audio(audio_out)`
135			`);`
136			`endmodule`

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[/] [zx_ula/] [branches/] [xilinx/] [ulaplus_replacement-upgrade_for_sp16-48k/] [rtl_ulaplus/] [ulaplus_tld.v] - Blame information for rev 29