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Rev 27 → Rev 174

/frv400/v2_0/cdl/hal_frv_frv400.cdl
0,0 → 1,372
# ====================================================================
#
# hal_frv_frv400.cdl
#
# FRV400 board HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): bartv
# Original data: gthomas
# Contributors:
# Date: 2001-09-07
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_FRV_FRV400 {
display "FUJITSU MB93091 (FR-V 400) evaluation board"
parent CYGPKG_HAL_FRV
 
define_header hal_frv_frv400.h
include_dir cyg/hal
hardware
description "
The frv400 HAL package provides the support needed to run
eCos on a FUJITSU MB93091 (FR-V 400) eval board."
 
compile hal_diag.c frv400_misc.c
 
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGINT_HAL_FRV_ARCH_FR400
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_frv.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_frv_frv400.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLF_DEFS_H <cyg/hal/frv400.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_IO_H <cyg/hal/plf_io.h>"
puts $::cdl_header "#define HAL_PLATFORM_CPU \"Fujitsu FR400\""
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MB93091-CB10 evaluation board\""
puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
default_value {"RAM"}
legal_values {"RAM" "ROM" "ROMRAM" }
no_define
define -file system.h CYG_HAL_STARTUP
description "
When targetting the MB93091 (FR-V 400) eval board it is possible to build
the system for either RAM bootstrap or ROM bootstrap(s). Select
'ram' when building programs to load into RAM using onboard
debug software such as Angel or eCos GDB stubs. Select 'rom'
when building a stand-alone application which will be put
into ROM. For the ROMRAM startup type, code will behave as
if in ROM, but will be copied to static RAM on the board before
execution."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of communication channels on the board"
flavor data
calculated 2
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
The FRV400 board has two serial ports. This option
chooses which port will be used to connect to a host
running GDB."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
display "Default console channel."
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
calculated 0
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Diagnostic serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
description "
The FRV400 board has two serial ports. This option
chooses which port will be used for diagnostic output."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
display "Diagnostic serial port baud rate"
flavor data
legal_values 9600 19200 38400 115200
default_value 38400
description "
This option selects the baud rate used for the diagnostic port.
Note: this should match the value chosen for the GDB port if the
diagnostic and GDB port are the same."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
display "GDB serial port baud rate"
flavor data
legal_values 9600 19200 38400 115200
default_value 38400
description "
This option selects the baud rate used for the diagnostic port.
Note: this should match the value chosen for the GDB port if the
diagnostic and GDB port are the same."
}
 
cdl_option CYGSEM_HAL_DIAG_USES_LEDS {
display "Use LED bank for feedback on serial port use"
flavor bool
default_value 1
description "
Enable this option to display information in the motherboard
LED array about serial I/O. Indications will be made while
data is being sent and received over the diagnostic serial ports.
This can be useful when the board is talking with GDB, etc."
}
 
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants"
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
# Internal clock set up to run at 1MHz
calculated { (1000000/CYGNUM_HAL_RTC_DENOMINATOR) }
}
}
 
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
 
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "frv-elf" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
default_value { "-mcpu=fr400 -fPIC -G0 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
options which override these global flags."
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
default_value { "-mcpu=fr400 -fPIC -G0 -Wl,--gc-sections -Wl,-static -g -nostdlib" }
description "
This option controls the global linker flags. Individual
packages may define options which override these global flags."
}
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
display "Build GDB stub ROM image"
default_value 0
requires { CYG_HAL_STARTUP == "ROM" }
requires CYGSEM_HAL_ROM_MONITOR
requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
requires ! CYGBLD_BUILD_COMMON_GDB_STUBS
requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
no_define
description "
This option enables the building of the GDB stubs for the
board. This is a bit convoluted as it involves prepending
the image with a special header used by the FRV400 firmware
to keep track of multiple ROM images. This header includes
a checksum making it necessary to build twice."
 
make -priority 320 {
<PREFIX>/bin/gdb_module.bin : <PACKAGE>/src/gdb_module.c
@sh -c "mkdir -p src $(dir $@)"
# First build version with no checksum.
$(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o src/gdb_module_ncs.o $<
$(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o src/gdb_module_ncs.tmp src/gdb_module_ncs.o
$(OBJCOPY) --strip-debug --change-addresses=0xFBFF4000 src/gdb_module_ncs.tmp src/gdb_module_ncs.img
$(OBJCOPY) -O binary src/gdb_module_ncs.img src/gdb_module_ncs.bin
@rm src/gdb_module_ncs.tmp src/gdb_module_ncs.img
# Prepare dependency file
@echo $@ ": \\" > $(notdir $@).deps
@echo $(wildcard $(PREFIX)/lib/*) " \\" >> $(notdir $@).deps
@tail +2 deps.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm deps.tmp
# Then build version with checksum from previously built image.
$(CC) -c -DCHECKSUM=`$(dir $<)flash_cksum.tcl src/gdb_module_ncs.bin` $(INCLUDE_PATH) -I$(dir $<) $(CFLAGS) -o src/gdb_module.o $<
$(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o src/gdb_module.tmp src/gdb_module.o
$(OBJCOPY) --strip-debug --change-addresses=0xFBFF4000 src/gdb_module.tmp $(@:.bin=.img)
$(OBJCOPY) -O binary $(@:.bin=.img) src/gdb_module.bin
uuencode src/gdb_module.bin gdb_module.bin | tr '`' ' ' > $(@:.bin=.img.UU)
@rm src/gdb_module.tmp src/gdb_module_ncs.bin
@mv src/gdb_module.bin $@
}
}
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { (CYG_HAL_STARTUP == "RAM") ? "frv_frv400_ram" : \
(CYG_HAL_STARTUP == "ROM") ? "frv_frv400_rom" : \
(CYG_HAL_STARTUP == "ROMRAM") ? "frv_frv400_romram" : \
"frv_frv400C_UNKNOWN" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_frv_frv400_ram.ldi>" : \
(CYG_HAL_STARTUP == "ROM") ? "<pkgconf/mlt_frv_frv400_rom.ldi>" : \
(CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_frv_frv400_romram.ldi>" : \
"<pkgconf/mlt_frv_frv400C_UNKNOWN.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_frv_frv400_ram.h>" : \
(CYG_HAL_STARTUP == "ROM") ? "<pkgconf/mlt_frv_frv400_rom.h>" : \
(CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_frv_frv400_romram.h>" : \
"<pkgconf/mlt_frv_frv400C_UNKNOWN.h>" }
}
}
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
description "
Enable this option if this program is to be used as a ROM monitor,
i.e. applications will be loaded into RAM on the board, and this
ROM monitor may process exceptions or interrupts generated from the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
}
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
display "Work with a ROM monitor"
flavor booldata
legal_values { "Generic" "GDB_stubs" }
default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "RAM" }
description "
Support can be enabled for different varieties of ROM monitor.
This support changes various eCos semantics such as the encoding
of diagnostic output, or the overriding of hardware interrupt
vectors.
Firstly there is \"Generic\" support which prevents the HAL
from overriding the hardware vectors that it does not use, to
instead allow an installed ROM monitor to handle them. This is
the most basic support which is likely to be common to most
implementations of ROM monitor.
\"GDB_stubs\" provides support when GDB stubs are included in
the ROM monitor or boot ROM."
}
 
cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
display "Redboot HAL options"
flavor none
no_define
parent CYGPKG_REDBOOT
active_if CYGPKG_REDBOOT
description "
This option lists the target's requirements for a valid Redboot
configuration."
 
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
display "Build Redboot ROM binary image"
active_if CYGBLD_BUILD_REDBOOT
default_value 1
no_define
description "This option enables the conversion of the Redboot ELF
image to a binary image suitable for ROM programming."
 
# compile -library=libextras.a redboot_cmds.c
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
$(OBJCOPY) --strip-debug $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
}
}
 
}
/frv400/v2_0/include/plf_ints.h
0,0 → 1,108
#ifndef CYGONCE_PLF_INTS_H
#define CYGONCE_PLF_INTS_H
//==========================================================================
//
// plf_ints.h
//
// HAL extended support for platform specific interrupts
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas
// Date: 2001-02-24
// Purpose: Define Interrupt support
// Description: The interrupt details for the MB93091 (FRV400) are defined here.
// Usage:
// #include <cyg/hal/plf_ints.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
// Define here extended support for this particular platform
 
// Interrupts are mapped onto "channels" by the interrupt controller
// The channel in turn is presented to the CPU as a "level" which can
// be masked. The eCos interrupt names below are for the default mapping
// of interrupt sources to channels.
 
#define CYGNUM_HAL_INTERRUPT_TIMER0 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_14
#define CYGNUM_HAL_INTERRUPT_TIMER1 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_13
#define CYGNUM_HAL_INTERRUPT_TIMER2 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_12
#define CYGNUM_HAL_INTERRUPT_DMA0 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_11
#define CYGNUM_HAL_INTERRUPT_DMA1 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_10
#define CYGNUM_HAL_INTERRUPT_DMA2 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_9
#define CYGNUM_HAL_INTERRUPT_DMA3 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_8
#define CYGNUM_HAL_INTERRUPT_UART0 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_2
#define CYGNUM_HAL_INTERRUPT_UART1 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1
#define CYGNUM_HAL_INTERRUPT_EXT0 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_7
#define CYGNUM_HAL_INTERRUPT_EXT1 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_6
#define CYGNUM_HAL_INTERRUPT_EXT2 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_5
#define CYGNUM_HAL_INTERRUPT_EXT3 CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_4
 
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER1
#define CYGNUM_HAL_INTERRUPT_SERIALA CYGNUM_HAL_INTERRUPT_UART0
#define CYGNUM_HAL_INTERRUPT_SERIALB CYGNUM_HAL_INTERRUPT_UART1
#define CYGNUM_HAL_INTERRUPT_LAN CYGNUM_HAL_INTERRUPT_EXT2
#define CYGNUM_HAL_INTERRUPT_PCIINTA CYGNUM_HAL_INTERRUPT_EXT1
#define CYGNUM_HAL_INTERRUPT_PCIINTB CYGNUM_HAL_INTERRUPT_EXT0
#define CYGNUM_HAL_INTERRUPT_PCIINTC CYGNUM_HAL_INTERRUPT_EXT1
#define CYGNUM_HAL_INTERRUPT_PCIINTD CYGNUM_HAL_INTERRUPT_EXT0
 
 
//----------------------------------------------------------------------------
// Reset.
#define HAL_PLATFORM_RESET() \
CYG_MACRO_START \
cyg_uint32 ctrl; \
\
/* By disabling interupts we will just hang in the loop below */ \
/* if for some reason the software reset fails. */ \
HAL_DISABLE_INTERRUPTS(ctrl); \
\
/* Software reset. */ \
HAL_WRITE_UINT32(_FRV400_HW_RESET, _FRV400_HW_RESET_HR); \
\
for(;;); /* hang here forever if reset fails */ \
CYG_MACRO_END
 
#define HAL_PLATFORM_RESET_ENTRY 0xFF000000
 
#endif // CYGONCE_PLF_INTS_H
/frv400/v2_0/include/plf_stub.h
0,0 → 1,114
#ifndef CYGONCE_HAL_PLF_STUB_H
#define CYGONCE_HAL_PLF_STUB_H
 
//=============================================================================
//
// plf_stub.h
//
// Platform header for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors:jskov
// Date: 2001-09-14
// Purpose: Platform HAL stub support for Fujitsu FRV-400
// Usage: #include <cyg/hal/plf_stub.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
 
//#include <cyg/hal/hal_io.h> // IO macros
//#include <cyg/hal/hal_intr.h> // Interrupt macros
#include <cyg/hal/frv_stub.h> // architecture stub support
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
//----------------------------------------------------------------------------
// Define some platform specific communication details. This is mostly
// handled by hal_if now, but we need to make sure the comms tables are
// properly initialized.
 
externC void cyg_hal_plf_comms_init(void);
 
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
 
//----------------------------------------------------------------------------
// Stub initializer.
#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
 
// ---------------------------------------------------------------------------
// Hardware breakpoint/watchpoint support
extern int cyg_hal_plf_hw_breakpoint(int setflag, void *addr, int len);
extern int cyg_hal_plf_hw_watchpoint(int setflag, void *addr, int len, int type);
extern int cyg_hal_plf_is_stopped_by_hardware(void **paddr);
 
#define HAL_STUB_HW_BREAKPOINT_LIST_SIZE 4
#define HAL_STUB_HW_WATCHPOINT_LIST_SIZE 2
 
#define HAL_STUB_HW_BREAKPOINT(f,a,l) cyg_hal_plf_hw_breakpoint((f),(a),(l))
#define HAL_STUB_HW_WATCHPOINT(f,a,l,t) cyg_hal_plf_hw_watchpoint((f),(a),(l),(t))
#define HAL_STUB_IS_STOPPED_BY_HARDWARE(p) cyg_hal_plf_is_stopped_by_hardware(&(p))
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
// ------------------------------------------------------------------------
// Horrid stuff to enter and exit debug mode
 
#define HAL_FRV_ENTER_DEBUG_MODE() asm volatile ("break" : : : "lr")
 
#define HAL_FRV_EXIT_DEBUG_MODE() \
asm volatile ( \
"\t call 10f \n" \
"10:\t movsg lr, gr6 \n" /* get local addr */ \
"\t addi gr6, #16, gr6 \n" /* skip past rett */ \
"\t movgs gr6, bpcsr \n" /* Break PC save reg */ \
"\t rett #1 \n" \
: \
: \
: "gr6","lr" /* clobber list */ \
)
 
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PLF_STUB_H
// End of plf_stub.h
/frv400/v2_0/include/frv400.h
0,0 → 1,306
//==========================================================================
//
// frv400.h
//
// HAL misc board support definitions for Fujitsu MB93091 (FR-V 400)
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas
// Date: 2001-09-07
// Purpose: Platform register definitions
// Description:
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#ifndef __HAL_FRV400_H__
#define __HAL_FRV400_H__ 1
 
// Common
 
// Processor status register
#define _PSR_PIVL_SHIFT 3
#define _PSR_PIVL_MASK (0xF<<(_PSR_PIVL_SHIFT)) // Interrupt mask level
#define _PSR_S (1<<2) // Supervisor state
#define _PSR_PS (1<<1) // Previous supervisor state
#define _PSR_ET (1<<0) // Enable interrupts
 
// Hardware status register
#define _HSR0_ICE (1<<31) // Instruction cache enable
#define _HSR0_DCE (1<<30) // Data cache enable
#define _HSR0_IMMU (1<<26) // Instruction MMU enable
#define _HSR0_DMMU (1<<25) // Data MMU enable
 
// Debug Control Register
#define _DCR_EBE (1 << 30) // Exception break enable bit
#define _DCR_SE (1 << 29) // Single-step break enable bit
#define _DCR_IBM (1 << 28) // Instruction Break Mask (disable bit)
#define _DCR_DRBE0 (1 << 19) // READ dbar0
#define _DCR_DWBE0 (1 << 18) // WRITE dbar0
#define _DCR_DDBE0 (1 << 17) // Data-match for access to dbar0
#define _DCR_DBASE0 (1 << 17) // offset
#define _DCR_DRBE1 (1 << 16)
#define _DCR_DWBE1 (1 << 15)
#define _DCR_DDBE1 (1 << 14)
#define _DCR_DBASE1 (1 << 14)
//#define _DCR_DRBE2 (1 << 13) // 2 and 3 not supported in real hardware
//#define _DCR_DWBE2 (1 << 12)
//#define _DCR_DDBE2 (1 << 11)
//#define _DCR_DRBE3 (1 << 10)
//#define _DCR_DWBE3 (1 << 9)
//#define _DCR_DDBE3 (1 << 8)
#define _DCR_IBE0 (1 << 7)
#define _DCR_IBCE0 (1 << 6)
#define _DCR_IBE1 (1 << 5)
#define _DCR_IBCE1 (1 << 4)
#define _DCR_IBE2 (1 << 3)
#define _DCR_IBCE2 (1 << 2)
#define _DCR_IBE3 (1 << 1)
#define _DCR_IBCE3 (1 << 0)
 
// Break PSR Save Register
#define _BPSR_BS (1 << 12)
#define _BPSR_BET (1 << 0)
 
// Break Request Register
#define _BRR_EB (1 << 30)
#define _BRR_CB (1 << 29)
#define _BRR_TB (1 << 28)
#define _BRR_DB0 (1 << 11)
#define _BRR_DB1 (1 << 10)
#define _BRR_IB0 (1 << 7)
#define _BRR_IB1 (1 << 6)
#define _BRR_IB2 (1 << 5)
#define _BRR_IB3 (1 << 4)
#define _BRR_CBB (1 << 3)
#define _BRR_BB (1 << 2)
#define _BRR_SB (1 << 1)
#define _BRR_ST (1 << 0)
 
 
// Platform specifics
 
// SDRAM Controller
#define _FRV400_SDRAM_CP 0xFE000400 // Controller protect
#define _FRV400_SDRAM_CFG 0xFE000410 // Configuration
#define _FRV400_SDRAM_CTL 0xFE000418 // Control
#define _FRV400_SDRAM_MS 0xFE000420 // Mode select
#define _FRV400_SDRAM_STS 0xFE000428 // Status
#define _FRV400_SDRAM_RCN 0xFE000430 // Refresh control
#define _FRV400_SDRAM_ART 0xFE000438 // Auto-refresh timer
#define _FRV400_SDRAM_AN0 0xFE000500 // Address #0
#define _FRV400_SDRAM_AN1 0xFE000508 // Address #1
#define _FRV400_SDRAM_BR0 0xFE000E00 // Base register #0
#define _FRV400_SDRAM_BR1 0xFE000E08 // Base register #1
#define _FRV400_SDRAM_AM0 0xFE000F00 // Address mask #0
#define _FRV400_SDRAM_AM1 0xFE000F08 // Address mask #1
 
// Local bus control
#define _FRV400_LBUS_CP 0xFE000000 // Controller protect
#define _FRV400_LBUS_EST 0xFE000020 // Error status
#define _FRV400_LBUS_EAD 0xFE000028 // Error address
#define _FRV400_LBUS_CR0 0xFE000100 // Configuration - space #0
#define _FRV400_LBUS_CR1 0xFE000108 // Configuration - space #1
#define _FRV400_LBUS_CR2 0xFE000110 // Configuration - space #2
#define _FRV400_LBUS_CR3 0xFE000118 // Configuration - space #3
#define _FRV400_LBUS_BR0 0xFE000C00 // Slave - base address #0
#define _FRV400_LBUS_BR1 0xFE000C08 // Slave - base address #1
#define _FRV400_LBUS_BR2 0xFE000C10 // Slave - base address #2
#define _FRV400_LBUS_BR3 0xFE000C18 // Slave - base address #3
#define _FRV400_LBUS_AM0 0xFE000D00 // Slave - address mask #0
#define _FRV400_LBUS_AM1 0xFE000D08 // Slave - address mask #1
#define _FRV400_LBUS_AM2 0xFE000D10 // Slave - address mask #2
#define _FRV400_LBUS_AM3 0xFE000D18 // Slave - address mask #3
 
// PCI Bridge (on motherboard)
#define _FRV400_PCI_SLBUS_CONFIG 0x10000000
#define _FRV400_PCI_ECS0_CONFIG 0x10000008
#define _FRV400_PCI_ECS1_CONFIG 0x10000010
#define _FRV400_PCI_ECS2_CONFIG 0x10000018
#define _FRV400_PCI_ECS0_RANGE 0x10000020
#define _FRV400_PCI_ECS0_ADDR 0x10000028
#define _FRV400_PCI_ECS1_RANGE 0x10000030
#define _FRV400_PCI_ECS1_ADDR 0x10000038
#define _FRV400_PCI_ECS2_RANGE 0x10000040
#define _FRV400_PCI_ECS2_ADDR 0x10000048
#define _FRV400_PCI_PCIIO_RANGE 0x10000050
#define _FRV400_PCI_PCIIO_ADDR 0x10000058
#define _FRV400_PCI_PCIMEM_RANGE 0x10000060
#define _FRV400_PCI_PCIMEM_ADDR 0x10000068
#define _FRV400_PCI_PCIIO_PCI_ADDR 0x10000070
#define _FRV400_PCI_PCIMEM_PCI_ADDR 0x10000078
#define _FRV400_PCI_CONFIG_ADDR 0x10000080
#define _FRV400_PCI_CONFIG_DATA 0x10000088
 
#define _FRV400_PCI_SL_TO_PCI_MBX0 0x10000500
#define _FRV400_PCI_SL_TO_PCI_MBX1 0x10000508
#define _FRV400_PCI_SL_TO_PCI_MBX2 0x10000510
#define _FRV400_PCI_SL_TO_PCI_MBX3 0x10000518
#define _FRV400_PCI_SL_TO_PCI_MBX4 0x10000520
#define _FRV400_PCI_SL_TO_PCI_MBX5 0x10000528
#define _FRV400_PCI_SL_TO_PCI_MBX6 0x10000530
#define _FRV400_PCI_SL_TO_PCI_MBX7 0x10000538
#define _FRV400_PCI_PCI_TO_SL_MBX0 0x10000540
#define _FRV400_PCI_PCI_TO_SL_MBX1 0x10000548
#define _FRV400_PCI_PCI_TO_SL_MBX2 0x10000550
#define _FRV400_PCI_PCI_TO_SL_MBX3 0x10000558
#define _FRV400_PCI_PCI_TO_SL_MBX4 0x10000560
#define _FRV400_PCI_PCI_TO_SL_MBX5 0x10000568
#define _FRV400_PCI_PCI_TO_SL_MBX6 0x10000570
#define _FRV400_PCI_PCI_TO_SL_MBX7 0x10000578
#define _FRV400_PCI_MBX_STATUS 0x10000580
#define _FRV400_PCI_MBX_CONTROL 0x10000588
#define _FRV400_PCI_SL_TO_PCI_DOORBELL 0x10000590
#define _FRV400_PCI_PCI_TO_SL_DOORBELL 0x10000598
#define _FRV400_PCI_SL_INT_STATUS 0x100005A0
#define _FRV400_PCI_SL_INT_STATUS_MASTER_ABORT (1<<26)
#define _FRV400_PCI_PCI_INT_STATUS 0x100005A8
#define _FRV400_PCI_SL_INT_ENABLE 0x100005B0
#define _FRV400_PCI_PCI_INT_ENABLE 0x100005B8
 
#define _FRV400_PCI_CONFIG 0x10000800
#define _FRV400_PCI_DEVICE_VENDOR 0x10000800
#define _FRV400_PCI_STAT_CMD 0x10000808
#define _FRV400_PCI_STAT_ERROR_MASK 0xF000
#define _FRV400_PCI_CLASS_REV 0x10000810
#define _FRV400_PCI_BIST 0x10000818
#define _FRV400_PCI_PCI_IO_MAPPED 0x10000820
#define _FRV400_PCI_PCI_MEM_MAP_LO 0x10000828
#define _FRV400_PCI_PCI_ECS0_LO 0x10000838
#define _FRV400_PCI_PCI_ECS1_LO 0x10000840
#define _FRV400_PCI_PCI_ECS2_LO 0x10000848
#define _FRV400_PCI_MAX_LAT 0x10000878
#define _FRV400_PCI_TMO_RETRY 0x10000880
#define _FRV400_PCI_SERR_ENABLE 0x10000888
#define _FRV400_PCI_RESET 0x10000890
#define _FRV400_PCI_RESET_SRST 0x00000001 // Assert soft reset
#define _FRV400_PCI_PCI_MEM_MAP_HI 0x10000898
#define _FRV400_PCI_PCI_ECS0_HI 0x100008A8
#define _FRV400_PCI_PCI_ECS1_HI 0x100008B0
#define _FRV400_PCI_PCI_ECS2_HI 0x100008B8
 
// Motherboard resources
#define _FRV400_MB_SWGP 0x21200000 // General purpose switches
#define _FRV400_MB_LEDS 0x21200004 // LED array - 16 bits 0->on
#define _FRV400_MB_LCD 0x21200008 // LCD panel
#define _FRV400_MB_BOOT_MODE 0x21300004 // Boot mode register
#define _FRV400_MB_H_RESET 0x21300008 // Hardware reset
#define _FRV400_MB_CLKSW 0x2130000C // Clock settings
#define _FRV400_MB_PCI_ARBITER 0x21300014 // Enable PCI arbiter mode
 
// Serial ports - 16550 compatible
#define _FRV400_UART0 0xFEFF9C00
#define _FRV400_UART1 0xFEFF9C40
 
// Programmable timers
#define _FRV400_TCSR0 0xFEFF9400 // Timer 0 control/status
#define _FRV400_TCSR1 0xFEFF9408 // Timer 1 control/status
#define _FRV400_TCSR2 0xFEFF9410 // Timer 2 control/status
#define _FRV400_TCxSR_TOUT 0x80 // Status - TOUT signal
#define _FRV400_TCTR 0xFEFF9418 // Timer control
#define _FRV400_TCTR_SEL0 (0<<6) // Select timer 0
#define _FRV400_TCTR_SEL1 (1<<6) // Select timer 1
#define _FRV400_TCTR_SEL2 (2<<6) // Select timer 2
#define _FRV400_TCTR_RB (3<<6) // Timer read back
#define _FRV400_TCTR_RB_NCOUNT (1<<5) // Count data suppress
#define _FRV400_TCTR_RB_NSTATUS (1<<4) // Status data suppress
#define _FRV400_TCTR_RB_CTR2 (1<<3) // Read data for counter #2
#define _FRV400_TCTR_RB_CTR1 (1<<2) // Read data for counter #1
#define _FRV400_TCTR_RB_CTR0 (1<<1) // Read data for counter #0
#define _FRV400_TCTR_LATCH (0<<4) // Counter latch command
#define _FRV400_TCTR_R8LO (1<<4) // Read low 8 bits
#define _FRV400_TCTR_R8HI (2<<4) // Read high 8 bits
#define _FRV400_TCTR_RLOHI (3<<4) // Read/write 8 lo then 8 hi
#define _FRV400_TCTR_MODE0 (0<<1) // Mode 0 - terminal interrupt count
#define _FRV400_TCTR_MODE2 (2<<1) // Mode 2 - rate generator
#define _FRV400_TCTR_MODE4 (4<<1) // Mode 4 - software trigger strobe
#define _FRV400_TCTR_MODE5 (5<<1) // Mode 5 - hardware trigger strobe
#define _FRV400_TPRV 0xFEFF9420 // Timer prescale
#define _FRV400_TPRCKSL 0xFEFF9428 // Prescale clock
#define _FRV400_TCKSL0 0xFEFF9430 // Timer 0 clock select
#define _FRV400_TCKSL1 0xFEFF9438 // Timer 1 clock select
#define _FRV400_TCKSL2 0xFEFF9440 // Timer 2 clock select
 
// Interrupt & clock control
#define _FRV400_CLK_CTRL 0xFEFF9A00 // Clock control
#define _FRV400_IRC_TM0 0xFEFF9800 // Trigger mode 0 register (unused)
#define _FRV400_IRC_TM1 0xFEFF9808 // Trigger mode 1 register
#define _FRV400_IRC_RS 0xFEFF9810 // Request sense
#define _FRV400_IRC_RC 0xFEFF9818 // Request clear
#define _FRV400_IRC_MASK 0xFEFF9820 // Mask
#define _FRV400_IRC_IRL 0xFEFF9828 // Interrupt level read (encoded)
#define _FRV400_IRC_IRR0 0xFEFF9840 // Interrupt routing #0 (unused)
#define _FRV400_IRC_IRR1 0xFEFF9848 // Interrupt routing #1 (unused)
#define _FRV400_IRC_IRR2 0xFEFF9850 // Interrupt routing #2 (unused)
#define _FRV400_IRC_IRR3 0xFEFF9858 // Interrupt routing #3
#define _FRV400_IRC_IRR4 0xFEFF9860 // Interrupt routing #4
#define _FRV400_IRC_IRR5 0xFEFF9868 // Interrupt routing #5
#define _FRV400_IRC_IRR6 0xFEFF9870 // Interrupt routing #6
#define _FRV400_IRC_IRR7 0xFEFF9878 // Interrupt routing #7
#define _FRV400_IRC_ITM0 0xFEFF9880 // Internal trigger mode #0
#define _FRV400_IRC_ITM1 0xFEFF9888 // Internal trigger mode #1
 
// Some GPIO magic
#define _FRV400_GPIO_SIR 0xFEFF0410 // Special input signals
#define _FRV400_GPIO_SOR 0xFEFF0418 // Special output signals
 
// Reset register
#define _FRV400_HW_RESET 0xFEFF0500 // Hardware reset
#define _FRV400_HW_RESET_STAT_P (1<<10) // Last reset was power-on
#define _FRV400_HW_RESET_STAT_H (1<<9) // Last reset was hard reset
#define _FRV400_HW_RESET_STAT_S (1<<8) // Last reset was soft reset
#define _FRV400_HW_RESET_HR (1<<1) // Force hard reset
#define _FRV400_HW_RESET_SR (1<<0) // Force soft reset
 
// On-board FPGA
#define _FRV400_FPGA_CONTROL 0xFFC00000 // Access control for FPGA resources
#define _FRV400_FPGA_CONTROL_IRQ (1<<2) // Set to enable IRQ registers
#define _FRV400_FPGA_CONTROL_CS4 (1<<1) // Set to enable CS4 control regs
#define _FRV400_FPGA_CONTROL_CS5 (1<<0) // Set to enable CS5 control regs
#define _FRV400_FPGA_IRQ_MASK 0xFFC00004 // Set bits to 0 to allow interrupt
#define _FRV400_FPGA_IRQ_LEVELS 0xFFC00008 // 0=>active low, 1=>active high
#define _FRV400_FPGA_IRQ_REQUEST 0xFFC0000C // read: 1=>asserted, write: 0=>clears
#define _FRV400_FPGA_IRQ_LAN (1<<12) // Onboard LAN controller
#define _FRV400_FPGA_IRQ_INTA (1<<6) // PCI bus INTA
#define _FRV400_FPGA_IRQ_INTB (1<<5) // PCI bus INTA
#define _FRV400_FPGA_IRQ_INTC (1<<4) // PCI bus INTA
#define _FRV400_FPGA_IRQ_INTD (1<<3) // PCI bus INTA
 
#endif /* __HAL_FRV400_H__ */
/frv400/v2_0/include/pkgconf/mlt_frv_frv400_ram.h
0,0 → 1,17
// eCos memory layout - Fri Oct 20 05:56:24 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0)
#define CYGMEM_REGION_ram_SIZE (0x03E00000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x03E000000 - (size_t) CYG_LABEL_NAME (__heap1))
/frv400/v2_0/include/pkgconf/mlt_frv_frv400_ram.ldi
0,0 → 1,29
// eCos memory layout - Fri Oct 20 05:56:24 2000
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
// Space for PCI window, RedBoot
 
MEMORY
{
ram : ORIGIN = 0x0000, LENGTH = 0x03E00000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_fixed_vectors (ram, 0x1000, LMA_EQ_VMA)
SECTION_rom_vectors (ram, 0x20000, LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x1000);
SECTIONS_END
}
/frv400/v2_0/include/pkgconf/mlt_frv_frv400_rom.h
0,0 → 1,17
// eCos memory layout - Fri Oct 20 05:56:24 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0)
#define CYGMEM_REGION_ram_SIZE (0x03F00000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x03F00000 - (size_t) CYG_LABEL_NAME (__heap1))
/frv400/v2_0/include/pkgconf/mlt_frv_frv400_romram.h
0,0 → 1,17
// eCos memory layout - Fri Oct 20 05:56:24 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0)
#define CYGMEM_REGION_ram_SIZE (0x03E00000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x03E00000 - (size_t) CYG_LABEL_NAME (__heap1))
/frv400/v2_0/include/pkgconf/mlt_frv_frv400_rom.ldi
0,0 → 1,28
// eCos memory layout - Fri Oct 20 05:56:24 2000
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x0000, LENGTH = 0x03F00000
rom : ORIGIN = 0xff000000, LENGTH = 0x00200000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (rom, 0xFF000000, LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x1000, LMA_EQ_VMA)
SECTION_data (ram, 0x2000, FOLLOWING (.gcc_except_table))
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x1000);
SECTIONS_END
}
/frv400/v2_0/include/pkgconf/mlt_frv_frv400_romram.ldi
0,0 → 1,30
// eCos memory layout - Fri Oct 20 05:56:24 2000
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
// Leave room for PCI window at 0x03F00000
 
MEMORY
{
ram : ORIGIN = 0x0000, LENGTH = 0x03E00000
rom : ORIGIN = 0x03E00000, LENGTH = 0x00100000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (rom, 0x03E00000, LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x1000, LMA_EQ_VMA)
SECTION_data (ram, 0x2000, FOLLOWING (.gcc_except_table))
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x1000);
SECTIONS_END
}
/frv400/v2_0/include/plf_cache.h
0,0 → 1,77
#ifndef CYGONCE_PLF_CACHE_H
#define CYGONCE_PLF_CACHE_H
 
//=============================================================================
//
// plf_cache.h
//
// HAL cache control API - Platform specifics
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors:hmt
// Date: 2001-09-13
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/hal_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
//-----------------------------------------------------------------------------
// Cache dimensions
 
#define HAL_ICACHE_SIZE (8*1024)
#define HAL_ICACHE_LINE_SIZE 32
#define HAL_ICACHE_WAYS 2
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
#define HAL_DCACHE_SIZE (8*1024)
#define HAL_DCACHE_LINE_SIZE 32
#define HAL_DCACHE_WAYS 2
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 
// No memory mapping on this platform
#define hal_virt_to_phys_address(virt) (virt)
 
#endif // CYGONCE_PLF_CACHE_H
/frv400/v2_0/include/platform.inc
0,0 → 1,172
#ifndef _CYGONCE_PLATFORM_INC_H_
#define _CYGONCE_PLATFORM_INC_H_
// #========================================================================
// #
// # platform.inc
// #
// # Fujitsu platform specific setups (assembler macros)
// #
// #========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
// #========================================================================
// ######DESCRIPTIONBEGIN####
// #
// # Author(s): gthomas
// # Contributors: gthomas
// # Date: 2001-09-16
// # Purpose: Fujitsu (FRV400) platform specific setups
// # Description: This file defines various macros used by the generic
// # HAL startup code.
// #
// #####DESCRIPTIONEND####
// #
// #========================================================================
 
// Display a value in the system LEDs
.macro LED n
sethi #(_FRV400_MB_LEDS>>16),gr15
setlo #(_FRV400_MB_LEDS&0xFFFF),gr15
setlos #\n,gr14
not gr14,gr14
sti gr14,@(gr15,0)
.endm
 
// Platform initialization - only the necessary bits required to get the
// board started from a cold reset.
.macro platform_init
li 0x7FFF,gr4 // First, a good long spin
05: nop
subi gr4,1,gr4
cmp gr4,gr0,icc0
bne icc0,0,05b
call 10f // position independent way to get @_platform_tab
_platform_tab:
//
// SDRAM setups
//
.long _FRV400_SDRAM_BR0,0x00000000 // SDRAM 0x0XXXXXXX
.long _FRV400_SDRAM_AM0,0x0FF00000
//
// LOCAL bus setups
//
.long _FRV400_LBUS_CR0,0x03010D01 // ROM/FLASH 0xFF000000..0xFFFFFFFF
// 16 bits wide, 13 wait states, 1 idle
 
.long _FRV400_LBUS_BR1,0x10000000 // PCI bridge 0x10000000..0x100FFFFF
.long _FRV400_LBUS_AM1,0x000FFFFF
.long _FRV400_LBUS_CR1,0x00000000
 
.long _FRV400_LBUS_BR2,0x20000000 // SRAM, FPGA, PCI 0x20000000..0x2FFFFFFF
.long _FRV400_LBUS_AM2,0x0FFFFFFF
.long _FRV400_LBUS_CR2,0x00000000
 
.long _FRV400_LBUS_BR3,0x00000000 // SDRAM?
.long _FRV400_LBUS_AM3,0xFFFFFFFF
.long _FRV400_LBUS_CR3,0x00000F07
 
.long _FRV400_GPIO_SIR,0x000c954f // Routing for Rx0, Rx1, CTS
.long _FRV400_GPIO_SOR,0x00036ab0 // Routing for Tx0, Tx1, RTS, TOUT0, TOUT1
.long _FRV400_SDRAM_CTL,0x05022000 // SDRAM mode/control
.long _FRV400_SDRAM_AN0,0x00010101
.long _FRV400_SDRAM_ART,0x00000820
.long _FRV400_SDRAM_RCN,0x00000000
.long _FRV400_SDRAM_MS, 0x00020200
.long _FRV400_SDRAM_CFG,0x80000000
 
//? .long _FRV400_CLK_CTRL,0x00000001 // External clock divisor (/2)
//
// PCI controller/bridge
//
.long _FRV400_PCI_SLBUS_CONFIG, 0x000800E2 // This matches the docs
// .long _FRV400_PCI_SLBUS_CONFIG, 0x000000E0 // This matches the samples
.long _FRV400_PCI_ECS0_CONFIG, 0x00000000
.long _FRV400_PCI_ECS1_CONFIG, 0x000003C1
.long _FRV400_PCI_ECS2_CONFIG, 0x000001C1
.long _FRV400_PCI_ECS0_RANGE, 0x00000000
.long _FRV400_PCI_ECS0_ADDR, 0x00000000
.long _FRV400_PCI_ECS1_RANGE, 0x00007FFE
.long _FRV400_PCI_ECS1_ADDR, 0x08108000
.long _FRV400_PCI_ECS2_RANGE, 0x00007FFE
.long _FRV400_PCI_ECS2_ADDR, 0x08100000
.long _FRV400_PCI_PCIIO_RANGE, 0x0001FFFE
.long _FRV400_PCI_PCIIO_ADDR, 0x00120000
.long _FRV400_PCI_PCIMEM_RANGE, 0x0003FFFE
.long _FRV400_PCI_PCIMEM_ADDR, 0x00140000
.long _FRV400_PCI_PCIIO_PCI_ADDR, 0x24000001
.long _FRV400_PCI_PCIMEM_PCI_ADDR, 0x28000000
.long _FRV400_MB_PCI_ARBITER, 0x00000001
.long _FRV400_MB_PCI_ARBITER, 0x00000001
.long _FRV400_PCI_SLBUS_CONFIG, 0x800800E2
// .long _FRV400_PCI_SLBUS_CONFIG, 0x800000E0
.long 0
.long _FRV400_SDRAM_STS
10: movsg lr,gr4 // _platform_tab -> list of initializations
20: ldi @(gr4,0),gr5 // Register
ldi @(gr4,4),gr6 // Value
cmp gr5,gr0,icc0 // End of list?
beq icc0,0,30f
sti gr6,@(gr5,0)
addi gr4,2*4,gr4
bra 20b // Next item
30: ldi @(gr6,0),gr5 // gr6 == _FRV400_SDRAM_STS
cmp gr5,gr0,icc0
bne icc0,0,30b // Wait for SDRAM ready
 
//
// Note: it is unclear from the documentation if this works at all. There is no
// description of how these registers are searched and what would happen if they
// overlap. If it turns out that they are not allowed to overlap, then this setup
// will have to be restructured.
//
li 0x03F0003D,gr4 // Set 0x03FXXXXX supervisor only, no cache - PCI window (1MB)
movgs gr4,DAMPR0
li 0x000000C9,gr4 // Set 0x0XXXXXXX supervisor only, cache - SDRAM
movgs gr4,DAMPR1
li 0x200000BD,gr4 // Set 0x2XXXXXXX supervisor only, no cache - Motherboard resources
movgs gr4,DAMPR6
li 0x100000BD,gr4 // Set 0x1XXXXXXX supervisor only, no cache - PCI bridge
movgs gr4,DAMPR7
movsg hsr0,gr4
li (1<<25),gr5 // Enable data MMU
or gr4,gr5,gr4
movgs gr4,hsr0
 
.endm
#endif // _CYGONCE_PLATFORM_INC_H_
/frv400/v2_0/include/hal_diag.h
0,0 → 1,94
#ifndef CYGONCE_HAL_DIAG_H
#define CYGONCE_HAL_DIAG_H
 
/*=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors: nickg, gthomas
// Date: 1998-09-11
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_if.h>
 
/*---------------------------------------------------------------------------*/
 
#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
 
#include <cyg/hal/hal_if.h>
 
#define HAL_DIAG_INIT() hal_if_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
 
// Not the best place for this, but ...
extern void hal_delay_us(cyg_int32 usecs);
 
#define HAL_DELAY_US(n) hal_delay_us(n);
 
#else
 
/*---------------------------------------------------------------------------*/
/* functions implemented in hal_diag.c */
 
externC void hal_diag_init(void);
externC void hal_diag_write_char(char c);
externC void hal_diag_read_char(char *c);
 
#define HAL_DIAG_INIT() hal_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
 
#endif
 
/*---------------------------------------------------------------------------*/
/* end of hal_diag.h */
#endif /* CYGONCE_HAL_DIAG_H */
/frv400/v2_0/include/plf_io.h
0,0 → 1,126
#ifndef CYGONCE_PLF_IO_H
#define CYGONCE_PLF_IO_H
 
//=============================================================================
//
// plf_io.h
//
// Platform specific IO support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt, jskov
// Contributors: hmt, jskov, gthomas
// Date: 1999-08-09
// Purpose: Fujitsu FR-V400 PCI IO support macros
// Description:
// Usage: #include <cyg/hal/plf_io.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include CYGBLD_HAL_PLATFORM_H
#include CYGBLD_HAL_PLF_DEFS_H
 
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/plf_ints.h> // Interrupt vectors
 
// Restrict device [slot] space
#define CYG_PCI_MAX_BUS 1 // Only one BUS
#define CYG_PCI_MIN_DEV 16 // Slots start at 16
#define CYG_PCI_MAX_DEV 21 // ... and end at 20
 
//-----------------------------------------------------------------------------
// Resources
 
// Map PCI device resources starting from these addresses in PCI space.
#define HAL_PCI_ALLOC_BASE_MEMORY 0x28000000
#define HAL_PCI_ALLOC_BASE_IO 0x24000000
 
// This is where the PCI spaces are mapped in the CPU's address space.
#define HAL_PCI_PHYSICAL_MEMORY_BASE 0 // 0x28000000
#define HAL_PCI_PHYSICAL_IO_BASE 0 // 0x24000000
 
// These seem to be defined multiple ways?
#define CYGMEM_SECTION_pci_window 0x03F00000
#define CYGMEM_SECTION_pci_window_SIZE 0x00100000
#define CYGHWR_HAL_FRV_FRV400_PCI_MEM_MAP_BASE 0x03F00000
#define CYGHWR_HAL_FRV_FRV400_PCI_MEM_MAP_SIZE 0x00100000
 
// Initialize the PCI environment
externC void _frv400_pci_init(void);
#define HAL_PCI_INIT() \
_frv400_pci_init()
 
// Translate the PCI interrupt requested by the device (INTA#, INTB#,
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
externC void _frv400_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid);
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
_frv400_pci_translate_interrupt(__bus, __devfn, &__vec, &__valid)
 
// Read a value from the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
externC cyg_uint8 _frv400_pci_cfg_read_uint8(int bus, int dev, int offset);
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
__val = _frv400_pci_cfg_read_uint8(__bus, __devfn, __offset)
externC cyg_uint16 _frv400_pci_cfg_read_uint16(int bus, int dev, int offset);
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
__val = _frv400_pci_cfg_read_uint16(__bus, __devfn, __offset)
externC cyg_uint32 _frv400_pci_cfg_read_uint32(int bus, int dev, int offset);
#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
__val = _frv400_pci_cfg_read_uint32(__bus, __devfn, __offset)
 
// Write a value to the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
externC void _frv400_pci_cfg_write_uint8(int bus, int dev, int offset, cyg_uint8 val);
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
_frv400_pci_cfg_write_uint8(__bus, __devfn, __offset, __val)
 
externC void _frv400_pci_cfg_write_uint16(int bus, int dev, int offset, cyg_uint16 val);
#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
_frv400_pci_cfg_write_uint16(__bus, __devfn, __offset, __val)
 
externC void _frv400_pci_cfg_write_uint32(int bus, int dev, int offset, cyg_uint32 val);
#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
_frv400_pci_cfg_write_uint32(__bus, __devfn, __offset, __val)
 
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_PLF_IO_H
/frv400/v2_0/ChangeLog
0,0 → 1,156
2002-08-29 Mark Salter <msalter@redhat.com>
 
* include/plf_stub.h: Add HAL_STUB_HW_BREAKPOINT_LIST_SIZE and
HAL_STUB_HW_WATCHPOINT_LIST_SIZE.
 
2002-05-07 Gary Thomas <gthomas@redhat.com>
 
* cdl/hal_frv_frv400.cdl:
Make CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT more standard.
 
2001-12-10 Richard Sandiford <rsandifo@redhat.com>
 
* src/frv400_misc.c (hal_interrupt_mask): Disable LAN interrupts
in the FPGA's register.
(hal_interrupt_unmask): Re-enable them.
 
2001-12-10 Richard Sandiford <rsandifo@redhat.com>
 
* src/frv400_misc.c (hal_clock_reset): Shift high word of timer left.
(hal_clock_read): Likewise.
(hal_delay_us): Increase timeout. Correct off-by-one error when
time is a multiple of _MIN_DELAY us.
 
2001-12-10 Richard Sandiford <rsandifo@redhat.com>
 
* include/plf_stub.h (HAL_FRV_ENTER_DEBUG_MODE): Remove NOPs.
Mark LR as clobbered due to changes in vectors.S:_break.
(HAL_FRV_EXIT_DEBUG_MODE): Remove NOPs. Don't modify PSR or BPSR.
* src/frv400_misc.c (get_bpsr, set_bpsr): New.
(break_handler): Rework. Set up BPSR to reflect the current
privelege level and trap state before exiting from debug mode.
Re-enter debugging mode and restore the old BPSR before returning.
(cyg_hal_plf_hw_breakpoint): Remove unnecessary DDR diddling.
(cyg_hal_plf_hw_watchpoint): Likewise.
 
2001-11-28 Hugo Tyson <hmt@redhat.com>
 
* include/plf_stub.h (HAL_FRV_ENTER_DEBUG_MODE): New macro; simple
performs a "break" to enter debug mode (with cooperation from
RedBoot/stubs/traphandler).
(HAL_FRV_EXIT_DEBUG_MODE): New macro; jumps through hoops to
return to normal mode from debug mode. Can only be used from
debug mode, or the CPU halts. The hoops are on fire.
(HAL_STUB_HW_BREAKPOINT):
(HAL_STUB_HW_WATCHPOINT):
(HAL_STUB_IS_STOPPED_BY_HARDWARE): Defines APIs so that stubs can
set hardware debug support, and tell whether we stopped for a
hardware debug reason.
 
* src/frv400_misc.c (break_handler): Special handler for break
instruction and all debug traps, to enable below.
(cyg_hal_plf_hw_breakpoint):
(cyg_hal_plf_hw_watchpoint):
(cyg_hal_plf_is_stopped_by_hardware): New routines to manipulate
hardware debug resources.
 
* include/frv400.h (_BRR_SB): Some new symbols for debug regs.
 
2001-10-23 Gary Thomas <gthomas@redhat.com>
 
* src/frv400_misc.c: Try to avoid [re]init PCI bus.
 
* include/frv400.h: Moved common register layouts to 'arch'.
 
2001-10-20 Gary Thomas <gthomas@redhat.com>
 
* src/frv400_misc.c (hal_delay_us): Handle small delays properly.
 
2001-10-19 Julian Smart <julians@redhat.com>
 
* Added CYPKG_MEMALLOC to redboot_ROMRAM.ecm so the release script
knows about it.
 
2001-10-16 Gary Thomas <gthomas@redhat.com>
 
* src/frv400_misc.c (_frv400_pci_translate_interrupt):
Handle interrupts from PCI slots.
 
* include/plf_ints.h (HAL_PLATFORM_RESET): Remove unused variable.
 
2001-10-15 Gary Thomas <gthomas@redhat.com>
 
* include/platform.inc: Getting on-board SRAM to function. Of course,
the hardware doesn't match the documentation...
 
2001-10-12 Gary Thomas <gthomas@redhat.com>
 
* src/frv400_misc.c (hal_interrupt_acknowledge): Fix support for
onboard (LAN) interrupts.
 
* include/plf_ints.h: Define PCI based interrupts.
 
* src/frv400_misc.c (hal_hardware_init):
* include/frv400.h: Add support for onboard FPGA (local interrupts).
 
2001-10-11 Gary Thomas <gthomas@redhat.com>
 
* src/frv400_misc.c: Clean up PCI code.
 
* misc/redboot_ROMRAM.ecm: Add BSP syscalls.
2001-10-01 Gary Thomas <gthomas@redhat.com>
 
* cdl/hal_frv_frv400.cdl:
* include/pkgconf/mlt_frv_frv400_ram.ldi:
* include/pkgconf/mlt_frv_frv400_rom.ldi:
* include/pkgconf/mlt_frv_frv400_ram.h:
* include/pkgconf/mlt_frv_frv400_rom.h:
* include/pkgconf/mlt_frv_frv400_romram.ldi:
* include/pkgconf/mlt_frv_frv400_romram.h:
* include/plf_ints.h:
* include/platform.inc:
* include/hal_diag.h:
* include/plf_stub.h:
* include/plf_cache.h:
* include/frv400.h:
* include/plf_io.h:
* src/hal_diag.c:
* src/frv400_misc.c:
* misc/redboot_ROMRAM.ecm:
* misc/redboot_RAM.ecm: New port for FRV400.
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/frv400/v2_0/src/hal_diag.c
0,0 → 1,413
/*=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors:nickg, gthomas
// Date: 1998-03-02
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
#include <pkgconf/hal_frv_frv400.h> // board specific configury
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h> // basic machine info
#include <cyg/hal/hal_intr.h> // interrupt macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/drv_api.h>
#include <cyg/hal/hal_if.h> // interface API
#include <cyg/hal/hal_misc.h> // Helper functions
 
#include <cyg/hal/frv400.h> // Platform specific (registers, etc)
 
extern long _system_clock;
#define _ROUND(n) ((((n)*100)+50)/100)
#define _BRG(r) _ROUND(_system_clock/((r)*16))
 
/*---------------------------------------------------------------------------*/
/* From serial_16550.h */
// Define the serial registers.
#define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0
#define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0
#define CYG_DEV_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
#define CYG_DEV_IER 0x08 // interrupt enable register, read/write, dlab = 0
#define CYG_DEV_DLM 0x08 // divisor latch (MS), read/write, dlab = 1
#define CYG_DEV_IIR 0x10 // interrupt identification register, read, dlab = 0
#define CYG_DEV_FCR 0x10 // fifo control register, write, dlab = 0
#define CYG_DEV_LCR 0x18 // line control register, read/write
#define CYG_DEV_MCR 0x20 // modem control register, read/write
#define CYG_DEV_LSR 0x28 // line status register, read
#define CYG_DEV_MSR 0x30 // modem status register, read
 
#define CYG_DEV_CLK 0x90 // Prescaler clock control register - Fujitsu special
#define CYG_DEV_PSC 0x98 // Prescaler value
 
// Interrupt Enable Register
#define SIO_IER_RCV 0x01
#define SIO_IER_XMT 0x02
#define SIO_IER_LS 0x04
#define SIO_IER_MS 0x08
 
// The line status register bits.
#define SIO_LSR_DR 0x01 // data ready
#define SIO_LSR_OE 0x02 // overrun error
#define SIO_LSR_PE 0x04 // parity error
#define SIO_LSR_FE 0x08 // framing error
#define SIO_LSR_BI 0x10 // break interrupt
#define SIO_LSR_THRE 0x20 // transmitter holding register empty
#define SIO_LSR_TEMT 0x40 // transmitter register empty
#define SIO_LSR_ERR 0x80 // any error condition
 
// The modem status register bits.
#define SIO_MSR_DCTS 0x01 // delta clear to send
#define SIO_MSR_DDSR 0x02 // delta data set ready
#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
#define SIO_MSR_DDCD 0x08 // delta data carrier detect
#define SIO_MSR_CTS 0x10 // clear to send
#define SIO_MSR_DSR 0x20 // data set ready
#define SIO_MSR_RI 0x40 // ring indicator
#define SIO_MSR_DCD 0x80 // data carrier detect
 
// The line control register bits.
#define SIO_LCR_WLS0 0x01 // word length select bit 0
#define SIO_LCR_WLS1 0x02 // word length select bit 1
#define SIO_LCR_STB 0x04 // number of stop bits
#define SIO_LCR_PEN 0x08 // parity enable
#define SIO_LCR_EPS 0x10 // even parity select
#define SIO_LCR_SP 0x20 // stick parity
#define SIO_LCR_SB 0x40 // set break
#define SIO_LCR_DLAB 0x80 // divisor latch access bit
 
// Modem Control Register
#define SIO_MCR_DTR 0x01
#define SIO_MCR_RTS 0x02
#define SIO_MCR_INT 0x08 // Enable interrupts
 
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector;
} channel_data_t;
 
//-----------------------------------------------------------------------------
 
static void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = chan->base;
cyg_uint8 lcr;
int _brg = _BRG(CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD);
 
// 8-1-no parity.
HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
 
// Set the baud rate
HAL_READ_UINT8(base+CYG_DEV_LCR, lcr);
lcr |= SIO_LCR_DLAB;
HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
HAL_WRITE_UINT8(base+CYG_DEV_DLL, _brg & 0xFF);
HAL_WRITE_UINT8(base+CYG_DEV_DLM, _brg >> 8);
lcr &= ~SIO_LCR_DLAB;
HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
 
// Enable & clear FIFO
HAL_WRITE_UINT8(base+CYG_DEV_FCR, 0x07);
 
// Configure interrupt
HAL_INTERRUPT_CONFIGURE(chan->isr_vector, 1, 1); // Interrupt when IRQ is high
}
 
void
cyg_hal_plf_serial_putc(void *__ch_data, char c)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lsr;
CYGARC_HAL_SAVE_GP();
 
#ifdef CYGSEM_HAL_DIAG_USES_LEDS
*(cyg_uint32 *)_FRV400_MB_LEDS = ~(0xC000 | c);
#endif // CYGSEM_HAL_DIAG_USES_LEDS
do {
HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
} while ((lsr & SIO_LSR_THRE) == 0);
 
HAL_WRITE_UINT8(base+CYG_DEV_THR, c);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lsr;
 
HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
if ((lsr & SIO_LSR_DR) == 0)
return false;
 
HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
 
return true;
}
 
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
#ifdef CYGSEM_HAL_DIAG_USES_LEDS
*(cyg_uint32 *)_FRV400_MB_LEDS = ~(0x1000);
#endif // CYGSEM_HAL_DIAG_USES_LEDS
while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
#ifdef CYGSEM_HAL_DIAG_USES_LEDS
*(cyg_uint32 *)_FRV400_MB_LEDS = ~(0x3000 | ch);
#endif // CYGSEM_HAL_DIAG_USES_LEDS
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static channel_data_t pid_ser_channels[] = {
{ (cyg_uint8*)_FRV400_UART0, 1000, CYGNUM_HAL_INTERRUPT_SERIALA },
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
{ (cyg_uint8*)_FRV400_UART1, 1000, CYGNUM_HAL_INTERRUPT_SERIALB },
#endif
};
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
 
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
HAL_WRITE_UINT8(chan->base+CYG_DEV_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS);
 
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
 
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
 
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
char c;
cyg_uint8 lsr;
CYGARC_HAL_SAVE_GP();
 
*__ctrlc = 0;
HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr);
if ( (lsr & SIO_LSR_DR) != 0 ) {
 
HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
 
res = CYG_ISR_HANDLED;
}
 
cyg_drv_interrupt_acknowledge(chan->isr_vector);
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Special case - turn on clocks for UARTS
HAL_WRITE_UINT32(_FRV400_UART0+CYG_DEV_CLK, 0x80<<24);
 
// Disable interrupts.
HAL_INTERRUPT_MASK(pid_ser_channels[0].isr_vector);
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
HAL_INTERRUPT_MASK(pid_ser_channels[1].isr_vector);
#endif
 
// Init channels
cyg_hal_plf_serial_init_channel(&pid_ser_channels[0]);
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
cyg_hal_plf_serial_init_channel(&pid_ser_channels[1]);
#endif
 
// Setup procs in the vector table
 
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &pid_ser_channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &pid_ser_channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
#endif
 
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
cyg_hal_plf_serial_init();
}
 
/*---------------------------------------------------------------------------*/
/* End of hal_diag.c */
/frv400/v2_0/src/frv400_misc.c
0,0 → 1,1082
//==========================================================================
//
// frv400_misc.c
//
// HAL misc board support code for Fujitsu MB93091 ( FR-V 400)
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas
// Date: 2001-09-07
// Purpose: HAL board support
// Description: Implementations of HAL board interfaces
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/infra/diag.h> // diag_printf() and friends
 
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_arch.h> // Register state info
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h> // Interrupt names
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/frv400.h> // Hardware definitions
#include <cyg/hal/hal_if.h> // calling interface API
 
#include <pkgconf/io_pci.h>
#include <cyg/io/pci_hw.h>
#include <cyg/io/pci.h>
 
static cyg_uint32 _period;
 
void hal_clock_initialize(cyg_uint32 period)
{
_period = period;
// Set timer #1 to run in terminal count mode for period
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL1|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
HAL_WRITE_UINT8(_FRV400_TCSR1, period & 0xFF);
HAL_WRITE_UINT8(_FRV400_TCSR1, period >> 8);
// Configure interrupt
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_TIMER1, 1, 1); // Interrupt when TOUT1 is high
}
 
void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
cyg_int16 offset;
cyg_uint8 _val;
 
// Latch & read counter from timer #1
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_LATCH|_FRV400_TCTR_RLOHI|_FRV400_TCTR_SEL1);
HAL_READ_UINT8(_FRV400_TCSR1, _val);
offset = _val;
HAL_READ_UINT8(_FRV400_TCSR1, _val);
offset |= _val << 8; // This will be the number of clocks beyond 0
period += offset;
// Reinitialize with adjusted count
// Set timer #1 to run in terminal count mode for period
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL1|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
HAL_WRITE_UINT8(_FRV400_TCSR1, period & 0xFF);
HAL_WRITE_UINT8(_FRV400_TCSR1, period >> 8);
}
 
// Read the current value of the clock, returning the number of hardware "ticks"
// that have occurred (i.e. how far away the current value is from the start)
 
void hal_clock_read(cyg_uint32 *pvalue)
{
cyg_int16 offset;
cyg_uint8 _val;
 
// Latch & read counter from timer #1
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_LATCH|_FRV400_TCTR_RLOHI|_FRV400_TCTR_SEL1);
HAL_READ_UINT8(_FRV400_TCSR1, _val);
offset = _val;
HAL_READ_UINT8(_FRV400_TCSR1, _val);
offset |= _val << 8;
 
// 'offset' is the current timer value
*pvalue = _period - offset;
}
 
// Delay for some number of useconds.
// Assumptions:
// Use timer #2
// Min granularity is 10us
#define _MIN_DELAY 10
 
void hal_delay_us(int us)
{
cyg_uint8 stat;
int timeout;
 
while (us >= _MIN_DELAY) {
us -= _MIN_DELAY;
// Set timer #2 to run in terminal count mode for _MIN_DELAY us
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_SEL2|_FRV400_TCTR_RLOHI|_FRV400_TCTR_MODE0);
HAL_WRITE_UINT8(_FRV400_TCSR2, _MIN_DELAY & 0xFF);
HAL_WRITE_UINT8(_FRV400_TCSR2, _MIN_DELAY >> 8);
timeout = 100000;
// Wait for TOUT to indicate terminal count reached
do {
HAL_WRITE_UINT8(_FRV400_TCTR, _FRV400_TCTR_RB|_FRV400_TCTR_RB_NCOUNT|_FRV400_TCTR_RB_CTR2);
HAL_READ_UINT8(_FRV400_TCSR2, stat);
if (--timeout == 0) break;
} while ((stat & _FRV400_TCxSR_TOUT) == 0);
}
}
 
//
// Early stage hardware initialization
// Some initialization has already been done before we get here. For now
// just set up the interrupt environment.
 
long _system_clock; // Calculated clock frequency
 
void hal_hardware_init(void)
{
cyg_uint32 clk;
 
// Set up interrupt controller
HAL_WRITE_UINT16(_FRV400_IRC_MASK, 0xFFFE); // All masked
HAL_WRITE_UINT16(_FRV400_IRC_RC, 0xFFFE); // All cleared
HAL_WRITE_UINT16(_FRV400_IRC_IRL, 0x10); // Clear IRL (interrupt request latch)
 
// Onboard FPGA interrupts
HAL_WRITE_UINT16(_FRV400_FPGA_CONTROL, _FRV400_FPGA_CONTROL_IRQ); // Enable IRQ registers
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, // Set up for LAN, PCI INTx
0x7FFE &
~(_FRV400_FPGA_IRQ_LAN |
_FRV400_FPGA_IRQ_INTA |
_FRV400_FPGA_IRQ_INTB |
_FRV400_FPGA_IRQ_INTC |
_FRV400_FPGA_IRQ_INTD)
);
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_LEVELS, // Set up for LAN, PCI INTx
0x7FFE &
~(_FRV400_FPGA_IRQ_LAN |
_FRV400_FPGA_IRQ_INTA |
_FRV400_FPGA_IRQ_INTB |
_FRV400_FPGA_IRQ_INTC |
_FRV400_FPGA_IRQ_INTD)
);
HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 0); // Level, low
 
// Set up system clock
HAL_READ_UINT32(_FRV400_MB_CLKSW, clk);
_system_clock = (((clk&0xFF) * 125 * 2) / 240) * 1000000;
 
// Set scalers to achieve 1us resolution in timer
HAL_WRITE_UINT8(_FRV400_TPRV, _system_clock / (1000*1000));
HAL_WRITE_UINT8(_FRV400_TCKSL0, 0x80);
HAL_WRITE_UINT8(_FRV400_TCKSL1, 0x80);
HAL_WRITE_UINT8(_FRV400_TCKSL2, 0x80);
 
hal_if_init();
 
// Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
 
_frv400_pci_init();
}
 
//
// Interrupt control
//
 
void hal_interrupt_mask(int vector)
{
cyg_uint16 _mask;
 
switch (vector) {
case CYGNUM_HAL_INTERRUPT_LAN:
HAL_READ_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
_mask |= _FRV400_FPGA_IRQ_LAN;
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
break;
}
HAL_READ_UINT16(_FRV400_IRC_MASK, _mask);
_mask |= (1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
HAL_WRITE_UINT16(_FRV400_IRC_MASK, _mask);
}
 
void hal_interrupt_unmask(int vector)
{
cyg_uint16 _mask;
 
switch (vector) {
case CYGNUM_HAL_INTERRUPT_LAN:
HAL_READ_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
_mask &= ~_FRV400_FPGA_IRQ_LAN;
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_MASK, _mask);
break;
}
HAL_READ_UINT16(_FRV400_IRC_MASK, _mask);
_mask &= ~(1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
HAL_WRITE_UINT16(_FRV400_IRC_MASK, _mask);
}
 
void hal_interrupt_acknowledge(int vector)
{
cyg_uint16 _mask;
 
switch (vector) {
case CYGNUM_HAL_INTERRUPT_LAN:
HAL_WRITE_UINT16(_FRV400_FPGA_IRQ_REQUEST, // Clear LAN interrupt
0x7FFE & ~_FRV400_FPGA_IRQ_LAN);
break;
}
_mask = (1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
HAL_WRITE_UINT16(_FRV400_IRC_RC, _mask);
HAL_WRITE_UINT16(_FRV400_IRC_IRL, 0x10); // Clears IRL latch
}
 
//
// Configure an interrupt
// level - boolean (0=> edge, 1=>level)
// up - edge: (0=>falling edge, 1=>rising edge)
// level: (0=>low, 1=>high)
//
void hal_interrupt_configure(int vector, int level, int up)
{
cyg_uint16 _irr, _tmr, _trig;
 
if (level) {
if (up) {
_trig = 0; // level, high
} else {
_trig = 1; // level, low
}
} else {
if (up) {
_trig = 2; // edge, rising
} else {
_trig = 3; // edge, falling
}
}
switch (vector) {
case CYGNUM_HAL_INTERRUPT_TIMER0:
HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xFFFC) | (_trig<<0);
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_TIMER1:
HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xFFF3) | (_trig<<2);
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_TIMER2:
HAL_READ_UINT16(_FRV400_IRC_IRR5, _irr);
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
HAL_WRITE_UINT16(_FRV400_IRC_IRR5, _irr);
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xFFCF) | (_trig<<4);
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_DMA0:
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xFCFF) | (_trig<<8);
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_DMA1:
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xF3FF) | (_trig<<10);
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_DMA2:
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xCFFF) | (_trig<<12);
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_DMA3:
HAL_READ_UINT16(_FRV400_IRC_IRR4, _irr);
_irr = (_irr & 0x0FFF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<12);
HAL_WRITE_UINT16(_FRV400_IRC_IRR4, _irr);
HAL_READ_UINT16(_FRV400_IRC_ITM0, _tmr);
_tmr = (_tmr & 0x3FFF) | (_trig<<14);
HAL_WRITE_UINT16(_FRV400_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_UART0:
HAL_READ_UINT16(_FRV400_IRC_IRR6, _irr);
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
HAL_WRITE_UINT16(_FRV400_IRC_IRR6, _irr);
HAL_READ_UINT16(_FRV400_IRC_ITM1, _tmr);
_tmr = (_tmr & 0xFCFF) | (_trig<<8);
HAL_WRITE_UINT16(_FRV400_IRC_ITM1, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_UART1:
HAL_READ_UINT16(_FRV400_IRC_IRR6, _irr);
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
HAL_WRITE_UINT16(_FRV400_IRC_IRR6, _irr);
HAL_READ_UINT16(_FRV400_IRC_ITM1, _tmr);
_tmr = (_tmr & 0xF3FF) | (_trig<<10);
HAL_WRITE_UINT16(_FRV400_IRC_ITM1, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_EXT0:
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
_tmr = (_tmr & 0xFFFC) | (_trig<<0);
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_EXT1:
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
_tmr = (_tmr & 0xFFF3) | (_trig<<2);
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_EXT2:
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
_tmr = (_tmr & 0xFFCF) | (_trig<<4);
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_EXT3:
HAL_READ_UINT16(_FRV400_IRC_IRR3, _irr);
_irr = (_irr & 0x0FFF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<12);
HAL_WRITE_UINT16(_FRV400_IRC_IRR3, _irr);
HAL_READ_UINT16(_FRV400_IRC_TM1, _tmr);
_tmr = (_tmr & 0xFF3F) | (_trig<<6);
HAL_WRITE_UINT16(_FRV400_IRC_TM1, _tmr);
break;
default:
; // Nothing to do
};
}
 
void hal_interrupt_set_level(int vector, int level)
{
// UNIMPLEMENTED(__FUNCTION__);
}
 
// PCI support
 
externC void
_frv400_pci_init(void)
{
static int _init = 0;
cyg_uint8 next_bus;
cyg_uint32 cmd_state;
 
if (_init) return;
_init = 1;
 
// Enable controller - most of the basic configuration
// was set up at boot time in "platform.inc"
 
// Setup for bus mastering
HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND, cmd_state);
if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) {
HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
 
// Setup latency timer field
HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 32);
 
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
 
}
 
externC void
_frv400_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid)
{
cyg_uint8 req;
cyg_uint8 dev = CYG_PCI_DEV_GET_DEV(devfn);
 
if (dev == CYG_PCI_MIN_DEV) {
// On board LAN
*vec = CYGNUM_HAL_INTERRUPT_LAN;
*valid = true;
} else {
HAL_PCI_CFG_READ_UINT8(bus, devfn, CYG_PCI_CFG_INT_PIN, req);
if (0 != req) {
CYG_ADDRWORD __translation[4] = {
CYGNUM_HAL_INTERRUPT_PCIINTC, /* INTC# */
CYGNUM_HAL_INTERRUPT_PCIINTB, /* INTB# */
CYGNUM_HAL_INTERRUPT_PCIINTA, /* INTA# */
CYGNUM_HAL_INTERRUPT_PCIINTD}; /* INTD# */
/* The PCI lines from the different slots are wired like this */
/* on the PCI backplane: */
/* pin6A pin7B pin7A pin8B */
/* I/O Slot 1 INTA# INTB# INTC# INTD# */
/* I/O Slot 2 INTD# INTA# INTB# INTC# */
/* I/O Slot 3 INTC# INTD# INTA# INTB# */
/* */
/* (From PCI Development Backplane, 3.2.2 Interrupts) */
/* */
/* Devsel signals are wired to, resulting in device IDs: */
/* I/O Slot 1 AD30 / dev 19 [(8+1)&3 = 1] */
/* I/O Slot 2 AD29 / dev 18 [(7+1)&3 = 0] */
/* I/O Slot 3 AD28 / dev 17 [(6+1)&3 = 3] */
*vec = __translation[((req+dev)&3)];
*valid = true;
} else {
/* Device will not generate interrupt requests. */
*valid = false;
}
diag_printf("Int - dev: %d, req: %d, vector: %d\n", dev, req, *vec);
}
}
 
// PCI configuration space access
#define _EXT_ENABLE 0x80000000 // Could be 0x80000000
 
static __inline__ cyg_uint32
_cfg_addr(int bus, int devfn, int offset)
{
return _EXT_ENABLE | (bus << 22) | (devfn << 8) | (offset << 0);
}
 
externC cyg_uint8
_frv400_pci_cfg_read_uint8(int bus, int devfn, int offset)
{
cyg_uint32 cfg_addr, addr, status;
cyg_uint8 cfg_val = (cyg_uint8)0xFF;
 
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
// PCI bridge
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x03);
} else {
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x03);
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x03);
}
HAL_READ_UINT8(addr, cfg_val);
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
cfg_val = (cyg_uint8)0xFF;
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
}
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
return cfg_val;
}
 
externC cyg_uint16
_frv400_pci_cfg_read_uint16(int bus, int devfn, int offset)
{
cyg_uint32 cfg_addr, addr, status;
cyg_uint16 cfg_val = (cyg_uint16)0xFFFF;
 
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
// PCI bridge
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x02);
} else {
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
}
HAL_READ_UINT16(addr, cfg_val);
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
cfg_val = (cyg_uint16)0xFFFF;
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
}
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
return cfg_val;
}
 
externC cyg_uint32
_frv400_pci_cfg_read_uint32(int bus, int devfn, int offset)
{
cyg_uint32 cfg_addr, addr, status;
cyg_uint32 cfg_val = (cyg_uint32)0xFFFFFFFF;
 
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x) = ", __FUNCTION__, bus, devfn, offset);
#endif // CYGPKG_IO_PCI_DEBUG
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
// PCI bridge
addr = _FRV400_PCI_CONFIG + (offset << 1);
} else {
cfg_addr = _cfg_addr(bus, devfn, offset);
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
addr = _FRV400_PCI_CONFIG_DATA;
}
HAL_READ_UINT32(addr, cfg_val);
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
cfg_val = (cyg_uint32)0xFFFFFFFF;
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
}
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%x\n", cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
return cfg_val;
}
 
externC void
_frv400_pci_cfg_write_uint8(int bus, int devfn, int offset, cyg_uint8 cfg_val)
{
cyg_uint32 cfg_addr, addr, status;
 
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
// PCI bridge
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x03);
} else {
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x03);
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x03);
}
HAL_WRITE_UINT8(addr, cfg_val);
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
}
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
}
 
externC void
_frv400_pci_cfg_write_uint16(int bus, int devfn, int offset, cyg_uint16 cfg_val)
{
cyg_uint32 cfg_addr, addr, status;
 
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
// PCI bridge
addr = _FRV400_PCI_CONFIG + ((offset << 1) ^ 0x02);
} else {
cfg_addr = _cfg_addr(bus, devfn, offset ^ 0x02);
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
addr = _FRV400_PCI_CONFIG_DATA + ((offset & 0x03) ^ 0x02);
}
HAL_WRITE_UINT16(addr, cfg_val);
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
}
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
}
 
externC void
_frv400_pci_cfg_write_uint32(int bus, int devfn, int offset, cyg_uint32 cfg_val)
{
cyg_uint32 cfg_addr, addr, status;
 
#ifdef CYGPKG_IO_PCI_DEBUG
diag_printf("%s(bus=%x, devfn=%x, offset=%x, val=%x)\n", __FUNCTION__, bus, devfn, offset, cfg_val);
#endif // CYGPKG_IO_PCI_DEBUG
if ((bus == 0) && (CYG_PCI_DEV_GET_DEV(devfn) == 0)) {
// PCI bridge
addr = _FRV400_PCI_CONFIG + (offset << 1);
} else {
cfg_addr = _cfg_addr(bus, devfn, offset);
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, cfg_addr);
addr = _FRV400_PCI_CONFIG_DATA;
}
HAL_WRITE_UINT32(addr, cfg_val);
HAL_READ_UINT16(_FRV400_PCI_STAT_CMD, status);
if (status & _FRV400_PCI_STAT_ERROR_MASK) {
// Cycle failed - clean up and get out
HAL_WRITE_UINT16(_FRV400_PCI_STAT_CMD, status & _FRV400_PCI_STAT_ERROR_MASK);
}
HAL_WRITE_UINT32(_FRV400_PCI_CONFIG_ADDR, 0);
}
 
// ------------------------------------------------------------------------
//
// Hardware breakpoint/watchpoint support
// ======================================
//
// Now follows a load of extreme unpleasantness to deal with the totally
// broken debug model of this device.
//
// To modify the special hardware debug registers, it is necessary to put
// the CPU into "debug mode". This can only be done by executing a break
// instruction, or taking a special hardware break event as described by
// the special hardware debug registers.
//
// But once in debug mode, no break is taken, and break instructions are
// ignored, because we are in debug mode.
//
// So we must exit debug mode for normal running, which you can only do via
// a rett #1 instruction. Because rett is for returning from traps, it
// halts the CPU if you do it with traps enabled. So you have to mess
// about disabling traps before the rett. Also, because rett #1 is for
// returning from a *debug* trap, you can only issue it from debug mode -
// or it halts the CPU.
//
// To be able to set and unset hardware debug breakpoints and watchpoints,
// we must enter debug mode (via a "break" instruction). Fortunately, it
// is possible to return from a "break" remaining in debug mode, using a
// rett #0, so we can arrange that a break instruction just means "go to
// debug mode".
//
// So we can manipulate the special hardware debug registers by executing a
// "break", doing the work, then doing the magic sequence to rett #1.
// These are encapsulated in HAL_FRV_ENTER_DEBUG_MODE() and
// HAL_FRV_EXIT_DEBUG_MODE() from plf_stub.h
//
// So, we get into break_hander() for two reasons:
// 1) a break instruction. Detect this and do nothing; return skipping
// over the break instruction. CPU remains in debug mode.
// 2) a hardware debug trap. Continue just as for a normal exception;
// GDB and the stubs will handle it. But first, exit debug mode, or
// stuff happening in the stubs will go wrong.
//
// In order to be certain that we are in debug mode, for performing (2)
// safely, vectors.S installs a special debug trap handler on vector #255.
// That's the reason for break_handler() existing as a separate routine.
//
// Note that there is no need to define CYGSEM_HAL_FRV_HW_DEBUG for the
// FRV_FRV400 target; while we do use Hardware Debug, we don't use *that*
// sort of hardware debug, specifically we do not use hardware single-step,
// because it breaks as soon as we exit debug mode, ie. whilst we are still
// within the stub. So in fact defining CYGSEM_HAL_FRV_HW_DEBUG is bad; I
// guess it is mis-named.
//
 
// ------------------------------------------------------------------------
// First a load of ugly boilerplate for register access.
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/hal/hal_stub.h> // HAL_STUB_HW_STOP_NONE et al
#include <cyg/hal/frv_stub.h> // register names PC, PSR et al
#include <cyg/hal/plf_stub.h> // HAL_FRV_EXIT_DEBUG_MODE()
 
// First a load of glue
static inline unsigned get_bpsr(void) {
unsigned retval;
asm volatile ( "movsg bpsr,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_bpsr(unsigned val) {
asm volatile ( "movgs %0,bpsr\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_dcr(void) {
unsigned retval;
asm volatile ( "movsg dcr,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_dcr(unsigned val) {
asm volatile ( "movgs %0,dcr\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_brr(void) {
unsigned retval;
asm volatile ( "movsg brr,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_brr(unsigned val) {
asm volatile ( "movgs %0,brr\n" : /* no outputs */ : "r" (val) );}
 
// Four Instruction Break Address Registers
static inline unsigned get_ibar0(void) {
unsigned retval;
asm volatile ( "movsg ibar0,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_ibar0(unsigned val) {
asm volatile ( "movgs %0,ibar0\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_ibar1(void) {
unsigned retval;
asm volatile ( "movsg ibar1,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_ibar1(unsigned val){
asm volatile ( "movgs %0,ibar1\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_ibar2(void) {
unsigned retval;
asm volatile ( "movsg ibar2,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_ibar2(unsigned val) {
asm volatile ( "movgs %0,ibar2\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_ibar3(void) {
unsigned retval;
asm volatile ( "movsg ibar3,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_ibar3(unsigned val){
asm volatile ( "movgs %0,ibar3\n" : /* no outputs */ : "r" (val) );}
 
// Two Data Break Address Registers
static inline unsigned get_dbar0(void) {
unsigned retval;
asm volatile ( "movsg dbar0,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_dbar0(unsigned val){
asm volatile ( "movgs %0,dbar0\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_dbar1(void){
unsigned retval;
asm volatile ( "movsg dbar1,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_dbar1(unsigned val){
asm volatile ( "movgs %0,dbar1\n" : /* no outputs */ : "r" (val) );}
 
// Two times two Data Break Data Registers
static inline unsigned get_dbdr00(void){
unsigned retval;
asm volatile ( "movsg dbdr00,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_dbdr00(unsigned val){
asm volatile ( "movgs %0,dbdr00\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_dbdr01(void){
unsigned retval;
asm volatile ( "movsg dbdr01,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_dbdr01(unsigned val){
asm volatile ( "movgs %0,dbdr01\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_dbdr10(void){
unsigned retval;
asm volatile ( "movsg dbdr10,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_dbdr10(unsigned val){
asm volatile ( "movgs %0,dbdr10\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_dbdr11(void){
unsigned retval;
asm volatile ( "movsg dbdr11,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_dbdr11(unsigned val){
asm volatile ( "movgs %0,dbdr11\n" : /* no outputs */ : "r" (val) );}
 
// Two times two Data Break Mask Registers
static inline unsigned get_dbmr00(void){
unsigned retval;
asm volatile ( "movsg dbmr00,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_dbmr00(unsigned val){
asm volatile ( "movgs %0,dbmr00\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_dbmr01(void){
unsigned retval;
asm volatile ( "movsg dbmr01,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_dbmr01(unsigned val){
asm volatile ( "movgs %0,dbmr01\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_dbmr10(void){
unsigned retval;
asm volatile ( "movsg dbmr10,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_dbmr10(unsigned val){
asm volatile ( "movgs %0,dbmr10\n" : /* no outputs */ : "r" (val) );}
 
static inline unsigned get_dbmr11(void){
unsigned retval;
asm volatile ( "movsg dbmr11,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_dbmr11(unsigned val){
asm volatile ( "movgs %0,dbmr11\n" : /* no outputs */ : "r" (val) );}
 
// and here's the prototype. Which compiles, believe it or not.
static inline unsigned get_XXXX(void){
unsigned retval;
asm volatile ( "movsg XXXX,%0\n" : "=r" (retval) : /* no inputs */ );
return retval;}
static inline void set_XXXX(unsigned val){
asm volatile ( "movgs %0,XXXX\n" : /* no outputs */ : "r" (val) );}
 
// ------------------------------------------------------------------------
// This is called in the same manner as exception_handler() in hal_misc.c
// Comments compare and contrast what we do here.
 
static unsigned int saved_brr = 0;
 
void
break_handler(HAL_SavedRegisters *regs)
{
unsigned int i, old_bpsr;
 
// See if it an actual "break" instruction.
i = get_brr();
saved_brr |= i; // do not lose previous state
// Acknowledge the trap, clear the "factor" (== cause)
set_brr( 0 );
 
// Now leave debug mode so that it's safe to run the stub code.
 
// Unfortunately, leaving debug mode isn't a self-contained
// operation. The only means of doing it is with a "rett #1"
// instruction, which will also restore the previous values of
// the ET and S status flags. We can massage the BPSR
// register so that the flags keep their current values, but
// we need to save the old one first.
i = old_bpsr = get_bpsr ();
i |= _BPSR_BS; // Stay in supervisor mode
i &= ~_BPSR_BET; // Keep traps disabled
set_bpsr (i);
HAL_FRV_EXIT_DEBUG_MODE();
 
// Only perturb this variable if stopping, not
// just for a break instruction.
_hal_registers = regs;
 
// Continue with the standard mechanism:
__handle_exception();
 
// Go back into debug mode.
HAL_FRV_ENTER_DEBUG_MODE();
// Restore the original BPSR register.
set_bpsr (old_bpsr);
return;
}
 
// ------------------------------------------------------------------------
 
// Now the routines to manipulate said hardware break and watchpoints.
 
int cyg_hal_plf_hw_breakpoint(int setflag, void *vaddr, int len)
{
unsigned int addr = (unsigned)vaddr;
unsigned int dcr;
unsigned int retcode = 0;
 
HAL_FRV_ENTER_DEBUG_MODE();
dcr = get_dcr();
 
// GDB manual suggests that idempotency is required, so first remove
// any identical BP in residence. Implements remove arm anyway.
if ( 0 != (dcr & (_DCR_IBE0 | _DCR_IBCE0)) &&
get_ibar0() == addr )
dcr &=~(_DCR_IBE0 | _DCR_IBCE0);
else if ( 0 != (dcr & (_DCR_IBE1 | _DCR_IBCE1)) &&
get_ibar1() == addr )
dcr &=~(_DCR_IBE1 | _DCR_IBCE1);
else if ( 0 != (dcr & (_DCR_IBE2 | _DCR_IBCE2)) &&
get_ibar2() == addr )
dcr &=~(_DCR_IBE2 | _DCR_IBCE2);
else if ( 0 != (dcr & (_DCR_IBE3 | _DCR_IBCE3)) &&
get_ibar3() == addr )
dcr &=~(_DCR_IBE3 | _DCR_IBCE3);
else
retcode = -1;
if (setflag) {
retcode = 0; // it is OK really
if ( 0 == (dcr & (_DCR_IBE0 | _DCR_IBCE0)) ) {
set_ibar0(addr);
dcr |= _DCR_IBE0;
}
else if ( 0 == (dcr & (_DCR_IBE1 | _DCR_IBCE1)) ) {
set_ibar1(addr);
dcr |= _DCR_IBE1;
}
else if ( 0 == (dcr & (_DCR_IBE2 | _DCR_IBCE2)) ) {
set_ibar2(addr);
dcr |= _DCR_IBE2;
}
else if ( 0 == (dcr & (_DCR_IBE3 | _DCR_IBCE3)) ) {
set_ibar3(addr);
dcr |= _DCR_IBE3;
}
else
retcode = -1;
}
 
if ( 0 == retcode )
set_dcr(dcr);
HAL_FRV_EXIT_DEBUG_MODE();
return retcode;
}
 
int cyg_hal_plf_hw_watchpoint(int setflag, void *vaddr, int len, int type)
{
unsigned int addr = (unsigned)vaddr;
unsigned int mode;
unsigned int dcr;
unsigned int retcode = 0;
unsigned long long mask;
unsigned int mask0, mask1;
int i;
 
// Check the length fits within one block.
if ( ((~7) & (addr + len - 1)) != ((~7) & addr) )
return -1;
 
// Assuming big-endian like the platform seems to be...
 
// Get masks for the 8-byte span. 00 means enabled, ff means ignore a
// byte, which is why this looks funny at first glance.
mask = 0x00ffffffffffffffULL >> ((len - 1) << 3);
for (i = 0; i < (addr & 7); i++) {
mask >>= 8;
mask |= 0xff00000000000000ULL;
}
 
mask0 = mask >> 32;
mask1 = mask & 0xffffffffULL;
 
addr &=~7; // round to 8-byte block
 
HAL_FRV_ENTER_DEBUG_MODE();
dcr = get_dcr();
 
// GDB manual suggests that idempotency is required, so first remove
// any identical WP in residence. Implements remove arm anyway.
if ( 0 != (dcr & (7 * _DCR_DBASE0)) &&
get_dbar0() == addr &&
get_dbmr00() == mask0 && get_dbmr01() == mask1 )
dcr &=~(7 * _DCR_DBASE0);
else if ( 0 != (dcr & (7 * _DCR_DBASE1)) &&
get_dbar1() == addr&&
get_dbmr10() == mask0 && get_dbmr11() == mask1 )
dcr &=~(7 * _DCR_DBASE1);
else
retcode = -1;
 
if (setflag) {
retcode = 0; // it is OK really
if (type == 2) mode = 2; // break on write
else if (type == 3) mode = 4; // break on read
else if (type == 4) mode = 6; // break on any access
else {
mode = 0; // actually add no enable at all.
retcode = -1;
}
if ( 0 == (dcr & (7 * _DCR_DBASE0)) ) {
set_dbar0(addr);
// Data and Mask 0,1 to zero (mask no bits/bytes)
set_dbdr00(0); set_dbdr01(0); set_dbmr00(mask0); set_dbmr01(mask1);
mode *= _DCR_DBASE0;
dcr |= mode;
}
else if ( 0 == (dcr & (7 * _DCR_DBASE1)) ) {
set_dbar1(addr);
set_dbdr10(0); set_dbdr11(0); set_dbmr10(mask0); set_dbmr11(mask1);
mode *= _DCR_DBASE1;
dcr |= mode;
}
else
retcode = -1;
}
 
if ( 0 == retcode )
set_dcr(dcr);
HAL_FRV_EXIT_DEBUG_MODE();
return retcode;
}
 
// Return indication of whether or not we stopped because of a
// watchpoint or hardware breakpoint. If stopped by a watchpoint,
// also set '*data_addr_p' to the data address which triggered the
// watchpoint.
int cyg_hal_plf_is_stopped_by_hardware(void **data_addr_p)
{
unsigned int brr;
int retcode = HAL_STUB_HW_STOP_NONE;
unsigned long long mask;
 
// There was a debug event. Check the BRR for details
brr = saved_brr;
saved_brr = 0;
 
if ( brr & (_BRR_IB0 | _BRR_IB1 | _BRR_IB2 | _BRR_IB3) ) {
// then it was an instruction break
retcode = HAL_STUB_HW_STOP_BREAK;
}
else if ( brr & (_BRR_DB0 | _BRR_DB1) ) {
unsigned int addr, kind;
kind = get_dcr();
if ( brr & (_BRR_DB0) ) {
addr = get_dbar0();
kind &= 7 * _DCR_DBASE0;
kind /= _DCR_DBASE0;
mask = (((unsigned long long)get_dbmr00())<<32) | (unsigned long long)get_dbmr01();
} else {
addr = get_dbar1();
kind &= 7 * _DCR_DBASE1;
kind /= _DCR_DBASE1;
mask = (((unsigned long long)get_dbmr10())<<32) | (unsigned long long)get_dbmr11();
}
 
if ( data_addr_p ) {
// Scan for a zero byte in the mask - this gives the true address.
// 0123456789abcdef
while ( 0 != (0xff00000000000000LLU & mask) ) {
mask <<= 8;
addr++;
}
*data_addr_p = (void *)addr;
}
 
// Inverse of the mapping above in the "set" code.
if (kind == 2) retcode = HAL_STUB_HW_STOP_WATCH;
else if (kind == 6) retcode = HAL_STUB_HW_STOP_AWATCH;
else if (kind == 4) retcode = HAL_STUB_HW_STOP_RWATCH;
}
return retcode;
}
 
// ------------------------------------------------------------------------
 
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
/*------------------------------------------------------------------------*/
// EOF frv400_misc.c
/frv400/v2_0/misc/redboot_RAM.ecm
0,0 → 1,87
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware frv400 ;
template redboot ;
package -hardware CYGPKG_HAL_FRV v2_0 ;
package -hardware CYGPKG_HAL_FRV_FRV400 v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVS_ETH_FRV_FRV400 v2_0 ;
package -hardware CYGPKG_DEVS_ETH_NS_DP83902A v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_FRV_FRV400 v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 4096
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
user_value 0x00040000
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV160 {
inferred_value 1
};
 
 
/frv400/v2_0/misc/install_notes
0,0 → 1,162
3 October, 2001
 
Installing RedBoot on Fujitsu FRV400 system.
 
Orient the motherboard like this:
 
+-------------------------------------------------------------+
| |
| |========================| |==========================| |
| |========================| |==========================| |
| CPU board |
| +-+-+ |
| |o|o| |
| |o|o| |
| |o|o| |
| |o|o| +-+ |
| |o|o| |o| Special power |
| |o|o| |o| cable to CPU board |
| |o|o| |o| |
| |o|o| |o| |
| +-+-+ +-+ |
| |
| ATX |
|Power |
| +------------------------------+ |
| | | | |
| +------------------------------+ |
| PCI slot |
| |
| +------------------------------+ |
| | | | |
| +------------------------------+ |
| PCI slot |
| |
| +------------------------------+ |
| | | | |
| +------------------------------+ |
| PCI slot |
| |
| +--------+ +--------+ +--------+ |
| |xxoooooX| |oooooooo| |xxoxxxxx| R1 |
| +--------+ +--------+ +--------+ R |
| SW1 CLK1 CLK2 R SS==]
| R SS ]
| R SS ]
| R SS==]
| R |
| |
| |
| |
+-------------------------------------------------------------+
 
For the switches, x is down (on this diagram), o is up and X
will be both.
 
There is also a ribbon cable from the CPU board to the serial
connectors. Orient this cable so that the red stripe connects
to pin R1 and is at the bottom of the CPU board. Directions
are in the hardware installation guide, but this part wasn't
terribly clear to me.
 
1. Bring up the existing Fujitsu board monitor.
 
Attach a serial cable to the top serial port - 38400/8N1.
Make sure that SW1-1 (X above) is up.
Turn on power. You will also have to press the RED button.
 
2. Download RedBoot into the FLASH.
 
Using the attached programs (minicom has a terrible time
with ASCII downloads - use these instead), download the
frv.ROM image. Use these commands
*************************************************************
** VDK LOADER for FR400 (BOOT ROM:IC8) **
** **
** Version 1.02 **
** ALL RIGHTS RESERVED, COPYRIGHT(C) FUJITSU LIMITED 2000 **
*************************************************************
 
Would you like to check SDRAM and SRAM ? (Y/N) : n
 
>r 3f00000
Flash ROM : IC7. OK ? (Y/N) Y
Blank check
Blank error !! Erase ? (Y/N) Y
Erase..
Work memory clear
Hex Data Offset Address=0x03F00000
Recieve....
At this point, send the file frv.ROM using simple ASCII protocol.
Since minicom does this poorly, I use the attached 'dl_slow' script.
I set up minicom like this:
lqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqk
x Name Program Name U/D FullScr IO-Red. Multi x
x A zmodem /usr/bin/sz -vv -b Y U N Y Y x
x B ymodem /usr/bin/sb -vv Y U N Y Y x
x C xmodem /usr/bin/sx -vv -k Y U N Y N x
x D zmodem /usr/bin/rz -vv -b -E N D N Y Y x
x E ymodem /usr/bin/rb -vv N D N Y Y x
x F xmodem /usr/bin/rx -vv Y D N Y N x
x G kermit /usr/bin/kermit -i -l %l -s Y U Y N N x
x H kermit /usr/bin/kermit -i -l %l -r N D Y N N x
x I ascii /usr/bin/ascii-xfr -dsv Y U N Y N x
x J slow /home/gthomas/bin/dl_slow Y U N Y N x
x K - x
x L - x
x M Zmodem download string activates... D x
x N Use filename selection window...... No x
x O Prompt for download directory...... No x
x x
x Change which setting? (SPACE to delete) x
mqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqqj
 
You'll know if the file is being transferred correctly by the LEDs doing a
little address dance (i.e. they are showing the address being loaded).
 
When the download completes, you may need to hit 'enter' a couple of times.
Then you should see:
Write Start...
Write OK!
Verify Start...
Verify OK!
Complete !!
 
 
>
 
At this point, change SW1-1 to be down (x). Press reset (the bottom blue
button on the CPU). You should get:
 
+FLASH configuration checksum error or invalid key
RedBoot(tm) bootstrap and debug environment [ROMRAM]
Non-certified release, version UNKNOWN - built 13:39:14, Oct 2 2001
 
Platform: MB93091-CB10 evaluation board (Fujitsu FR400)
Copyright (C) 2000, 2001, Red Hat, Inc.
 
RAM: 0x00000000-0x04000000, 0x00007000-0x03fed000 available
FLASH: 0xff000000 - 0xff200000, 32 blocks of 0x00010000 bytes each.
RedBoot>
 
Be sure and run 'fis init'.
 
Notes:
 
* There are two FLASH devices on the motherboard. Using SW1-1, they swap
memory addresses. We use one (IC7) and the Fujitsu loader uses the other.
I see no reason (ATM) to replace the Fujitsu monitor other than to let
RedBoot be the primary. This way, reverting SW1-1, at least you can always
reprogram RedBoot.
 
CAUTION!! Do not change SW1-1 until after you've programmed RedBoot. If
you do it beforehand, you'll overwrite the Fujitsu monitor.
 
 
 
 
 
 
/frv400/v2_0/misc/redboot_ROMRAM.ecm
0,0 → 1,104
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware frv400 ;
template redboot ;
package -hardware CYGPKG_HAL_FRV v2_0 ;
package -hardware CYGPKG_HAL_FRV_FRV400 v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVS_ETH_FRV_FRV400 v2_0 ;
package -hardware CYGPKG_DEVS_ETH_NS_DP83902A v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_FRV_FRV400 v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
package CYGPKG_COMPRESS_ZLIB v2_0 ;
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 4096
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROMRAM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
user_value 0x00040000
};
 
cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS {
user_value 1
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV160 {
inferred_value 1
};
 
cdl_option CYGSEM_COMPRESS_ZLIB_NEEDS_MALLOC {
inferred_value 0
};
 
 
/arch/v2_0/cdl/hal_frv.cdl
0,0 → 1,157
# ====================================================================
#
# hal_frv.cdl
#
# FUJITSU architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): bartv
# Original data: gthomas
# Contributors:
# Date: 2001-09-07
#
#####DESCRIPTIONEND####
#
# ====================================================================
cdl_package CYGPKG_HAL_FRV {
display "FUJITSU architecture"
parent CYGPKG_HAL
hardware
include_dir cyg/hal
define_header hal_frv.h
description "
The FUJITSU architecture HAL package provides generic
support for this processor architecture. It is also
necessary to select a specific target platform HAL
package."
 
compile hal_misc.c context.S frv_stub.c hal_syscall.c
 
# special rule used to build any include files, etc, used by assembly code
make -priority 1 {
frv.inc : <PACKAGE>/src/hal_mk_defs.c
$(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,frv.tmp -o hal_mk_defs.tmp -S $<
fgrep .equ hal_mk_defs.tmp | sed s/#// | sed s/\\.equ/#define/ > $@
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 frv.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm frv.tmp hal_mk_defs.tmp
}
 
make {
<PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S
$(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 vectors.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm vectors.tmp
}
 
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/frv.ld
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm target.tmp
}
 
cdl_interface CYGINT_HAL_FRV_ARCH_FR400 {
display "The CPU architecture supports the FR400 architecture"
}
 
cdl_interface CYGINT_HAL_FRV_ARCH_FR500 {
display "The CPU architecture supports the FR500 architecture"
}
 
cdl_option CYGHWR_HAL_FRV_CPU_FAMILY {
display "FUJITSU CPU family"
flavor data
legal_values { (CYGINT_HAL_FRV_ARCH_FR400 != 0) ? "FR400" : ""
(CYGINT_HAL_FRV_ARCH_FR500 != 0) ? "FR500" : ""
"" }
default_value { (CYGINT_HAL_FRV_ARCH_FR400 != 0) ? "FR400" :
(CYGINT_HAL_FRV_ARCH_FR500 != 0) ? "FR500" :
"unknown" }
no_define
description "
It is possible to optimize code for different
FUJITSU CPU families. This option selects which CPU to
optimize for on boards that support multiple CPU types."
}
 
cdl_option CYGBLD_LINKER_SCRIPT {
display "Linker script"
flavor data
no_define
calculated { "src/frv.ld" }
}
 
cdl_interface CYGINT_HAL_FRV_MEM_REAL_REGION_TOP {
display "Implementations of hal_frv_mem_real_region_top()"
}
 
cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE {
display "Number of breakpoints supported by the HAL."
flavor data
default_value 32
active_if CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
description "
This option determines the number of breakpoints supported by the HAL."
}
 
cdl_option CYGSEM_HAL_FRV_USE_BREAK_INSTRUCTION {
display "Use 'break' for breakpoints."
flavor bool
default_value 1
active_if { CYGINT_HAL_FRV_ARCH_FR500 != 0 }
requires CYGNUM_HAL_BREAKPOINT_LIST_SIZE
description "
Select this option to use the 'break' instruction for breakpoints.
This option can only be used if the GDB stubs use local breakpoints."
}
 
cdl_option CYGSEM_HAL_FRV_HW_DEBUG {
display "Hardware debug features available"
flavor bool
default_value 1
active_if { CYGINT_HAL_FRV_ARCH_FR500 != 0 }
description "
Select this option to enable the use of a hardware debug unit."
}
}
/arch/v2_0/include/frv_stub.h
0,0 → 1,154
#ifndef CYGONCE_HAL_FRV_STUB_H
#define CYGONCE_HAL_FRV_STUB_H
//========================================================================
//
// frv_stub.h
//
// FUJITSU-specific definitions for generic stub
//
//========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Red Hat, gthomas
// Contributors: Red Hat, gthomas
// Date: 2001-09-14
// Purpose:
// Description: FUJITSU-specific definitions for generic stub
// Usage:
//
//####DESCRIPTIONEND####
//
//========================================================================
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define NUMREGS (147)
 
#define REGSIZE( _x_ ) (4)
 
#define NUMREGBYTES (NUMREGS*4)
 
#ifndef TARGET_REGISTER_T_DEFINED
#define TARGET_REGISTER_T_DEFINED
typedef cyg_uint32 target_register_t;
#endif
 
// This information needs to match what GDB wants
enum regnames {
R0, R1, R2, R3, R4, R5, R6, R7,
R8, R9, R10, R11, R12, R13, R14, R15,
R16, R17, R18, R19, R20, R21, R22, R23,
R24, R25, R26, R27, R28, R29, R30, R31,
R32, R33, R34, R35, R36, R37, R38, R39,
R40, R41, R42, R43, R44, R45, R46, R47,
R48, R49, R50, R51, R52, R53, R54, R55,
R56, R57, R58, R59, R60, R61, R62, R63,
FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
FP8, FP9, FP10, FP11, FP12, FP13, FP14, FP15,
FP16, FP17, FP18, FP19, FP20, FP21, FP22, FP23,
FP24, FP25, FP26, FP27, FP28, FP29, FP30, FP31,
FP32, FP33, FP34, FP35, FP36, FP37, FP38, FP39,
FP40, FP41, FP42, FP43, FP44, FP45, FP46, FP47,
FP48, FP49, FP50, FP51, FP52, FP53, FP54, FP55,
FP56, FP57, FP58, FP59, FP60, FP61, FP62, FP63,
PC, PSR, CCR, CCCR,
_X132, _X133, _X134, _X135, _X136, _X137, _X138,
_X139, _X140, _X141, _X142, _X143, _X144,
LR, LCR
};
#define SP R1
 
typedef enum regnames regnames_t;
 
/* Given a trap value TRAP, return the corresponding signal. */
extern int __computeSignal (unsigned int trap_number);
 
/* Return the SPARC trap number corresponding to the last-taken trap. */
extern int __get_trap_number (void);
 
/* Return the currently-saved value corresponding to register REG. */
extern target_register_t get_register (regnames_t reg);
 
/* Store VALUE in the register corresponding to WHICH. */
extern void put_register (regnames_t which, target_register_t value);
 
/* Set the currently-saved pc register value to PC. This also updates NPC
as needed. */
extern void set_pc (target_register_t pc);
 
/* Set things up so that the next user resume will execute one instruction.
This may be done by setting breakpoints or setting a single step flag
in the saved user registers, for example. */
void __single_step (void);
 
/* Clear the single-step state. */
void __clear_single_step (void);
 
/* If the breakpoint we hit is in the breakpoint() instruction, return a
non-zero value. */
extern int __is_breakpoint_function (void);
 
/* Skip the current instruction. */
extern void __skipinst (void);
 
extern void __install_breakpoints (void);
 
extern void __clear_breakpoints (void);
 
extern int __is_bsp_syscall(void);
 
//------------------------------------------------------------------------
// Special definition of CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION
 
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
// we can only do this at all if break support is enabled:
 
#define CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION( _old_ ) \
do { \
HAL_DISABLE_INTERRUPTS(_old_); \
cyg_hal_gdb_place_break((target_register_t)&&cyg_hal_gdb_break_place ); \
} while ( 0 )
 
#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
 
 
#ifdef __cplusplus
} /* extern "C" */
#endif
 
#endif // ifndef CYGONCE_HAL_FRV_STUB_H
/arch/v2_0/include/hal_io.h
0,0 → 1,184
#ifndef CYGONCE_HAL_IO_H
#define CYGONCE_HAL_IO_H
 
//=============================================================================
//
// hal_io.h
//
// HAL device IO register support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors: nickg, gthomas
// Date: 1998-09-11
// Purpose: Define IO register support
// Description: The macros defined here provide the HAL APIs for handling
// device IO control registers.
//
// Usage:
// #include <cyg/hal/hal_io.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/system.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/basetype.h>
 
//-----------------------------------------------------------------------------
// IO Register address.
// This type is for recording the address of an IO register.
 
typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
 
 
//-----------------------------------------------------------------------------
// BYTE Register access.
// Individual and vectorized access to 8 bit registers.
 
#define HAL_READ_UINT8( _register_, _value_ ) \
CYG_MACRO_START \
((_value_) = *((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)))); \
HAL_IO_BARRIER(); \
CYG_MACRO_END
 
#define HAL_WRITE_UINT8( _register_, _value_ ) \
CYG_MACRO_START \
(*((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_))) = (_value_)); \
HAL_IO_BARRIER(); \
CYG_MACRO_END
 
#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)); \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
(_buf_)[_i_] = _r_[_j_]; \
CYG_MACRO_END
 
#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)); \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
_r_[_j_] = (_buf_)[_i_]; \
CYG_MACRO_END
 
//-----------------------------------------------------------------------------
// 16 bit access.
// Individual and vectorized access to 16 bit registers.
#define HAL_READ_UINT16( _register_, _value_ ) \
CYG_MACRO_START \
((_value_) = *((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)))); \
HAL_IO_BARRIER(); \
CYG_MACRO_END
 
#define HAL_WRITE_UINT16( _register_, _value_ ) \
CYG_MACRO_START \
(*((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_))) = (_value_)); \
HAL_IO_BARRIER(); \
CYG_MACRO_END
 
#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)); \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
(_buf_)[_i_] = _r_[_j_]; \
CYG_MACRO_END
 
#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)); \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
_r_[_j_] = (_buf_)[_i_]; \
CYG_MACRO_END
 
//-----------------------------------------------------------------------------
// 32 bit access.
// Individual and vectorized access to 32 bit registers.
 
// Note: same macros for little- and big-endian systems.
#define HAL_READ_UINT32( _register_, _value_ ) \
CYG_MACRO_START \
((_value_) = *((volatile CYG_WORD32 *)(_register_))); \
HAL_IO_BARRIER(); \
CYG_MACRO_END
 
#define HAL_WRITE_UINT32( _register_, _value_ ) \
CYG_MACRO_START \
(*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \
HAL_IO_BARRIER(); \
CYG_MACRO_END
 
#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
(_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
CYG_MACRO_END
 
#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
CYG_MACRO_END
 
// Enforce a flow "barrier" to prevent optimizing compiler from reordering
// operations.
#define HAL_IO_BARRIER() \
__asm__ volatile("membar" : : );
 
 
//-----------------------------------------------------------------------------
// Include plf_io.h for platforms that define it.
#ifdef CYGBLD_HAL_PLATFORM_IO_H
#include CYGBLD_HAL_PLATFORM_IO_H
#endif
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_IO_H
// End of hal_io.h
/arch/v2_0/include/basetype.h
0,0 → 1,69
#ifndef CYGONCE_HAL_BASETYPE_H
#define CYGONCE_HAL_BASETYPE_H
 
//=============================================================================
//
// basetype.h
//
// Standard types for this architecture.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors: nickg, gthomas
// Date: 1998-09-11
// Purpose: Define architecture base types.
// Usage: Included by "cyg_type.h", do not use directly
 
//
//####DESCRIPTIONEND####
//
 
//-----------------------------------------------------------------------------
// Characterize the architecture
 
#define CYG_BYTEORDER CYG_MSBFIRST // Big endian
 
//-----------------------------------------------------------------------------
// ARM does not usually use labels with underscores.
 
#define CYG_LABEL_NAME(_name_) _name_
#define CYG_LABEL_DEFN(_name_) _name_
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_BASETYPE_H
// End of basetype.h
/arch/v2_0/include/hal_intr.h
0,0 → 1,365
#ifndef CYGONCE_HAL_INTR_H
#define CYGONCE_HAL_INTR_H
 
//==========================================================================
//
// hal_intr.h
//
// HAL Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors: nickg, gthomas,
// jlarmour
// Date: 1999-02-20
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock.
//
// Usage: #include <cyg/hal/hal_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
// This is to allow a variant to decide that there is no platform-specific
// interrupts file; and that in turn can be overridden by a platform that
// refines the variant's ideas.
#ifdef CYGBLD_HAL_PLF_INTS_H
# include CYGBLD_HAL_PLF_INTS_H // should include variant data as required
#else
# ifdef CYGBLD_HAL_VAR_INTS_H
# include CYGBLD_HAL_VAR_INTS_H
# else
# include <cyg/hal/plf_ints.h> // default less-complex platforms
# endif
#endif
 
// Spurious interrupt (no interrupt source could be found)
#define CYGNUM_HAL_INTERRUPT_NONE -1
 
//--------------------------------------------------------------------------
// FUJITSU exception vectors.
 
// The Fujitsu FR-V architecture supports up to 256 interrupt/exceptions.
// Each vectors to a specific VSR which is 16 bytes (4 instructions) long.
 
// These vectors correspond to VSRs. These values are the ones to use for
// HAL_VSR_GET/SET
 
#define CYGNUM_HAL_VECTOR_RESET 0x00
#define CYGNUM_HAL_VECTOR_INSTR_ACCESS_MMU_MISS 0x01
#define CYGNUM_HAL_VECTOR_INSTR_ACCESS_ERROR 0x02
#define CYGNUM_HAL_VECTOR_INSTR_ACCESS_EXCEPTION 0x03
#define CYGNUM_HAL_VECTOR_PRIVELEDGED_INSTRUCTION 0x06
#define CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION 0x07
#define CYGNUM_HAL_VECTOR_REGISTER_EXCEPTION 0x08
#define CYGNUM_HAL_VECTOR_FP_DISABLED 0x0A
#define CYGNUM_HAL_VECTOR_MP_DISABLED 0x0B
#define CYGNUM_HAL_VECTOR_FP_EXCEPTION 0x0D
#define CYGNUM_HAL_VECTOR_MP_EXCEPTION 0x0E
#define CYGNUM_HAL_VECTOR_MEMORY_ADDRESS_NOT_ALIGNED 0x10
#define CYGNUM_HAL_VECTOR_DATA_ACCESS_ERROR 0x11
#define CYGNUM_HAL_VECTOR_DATA_ACCESS_MMU_MISS 0x12
#define CYGNUM_HAL_VECTOR_DATA_ACCESS_EXCEPTION 0x13
#define CYGNUM_HAL_VECTOR_DATA_STORE_ERROR 0x14
#define CYGNUM_HAL_VECTOR_DIVISION_EXCEPTION 0x17
#define CYGNUM_HAL_VECTOR_COMMIT_EXCEPTION 0x19
#define CYGNUM_HAL_VECTOR_COMPOUND_EXCEPTION 0x20
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1 0x21
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_2 0x22
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_3 0x23
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_4 0x24
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_5 0x25
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_6 0x26
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_7 0x27
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_8 0x28
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_9 0x29
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_10 0x2A
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_11 0x2B
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_12 0x2C
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_13 0x2D
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_14 0x2E
#define CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15 0x2F
#define CYGNUM_HAL_VECTOR_SYSCALL 0x80 // tira gr0,#0
#define CYGNUM_HAL_VECTOR_BREAKPOINT_TRAP 0x81 // tira gr0,#1
#define CYGNUM_HAL_VECTOR_BREAKPOINT 0xFF // break
 
#define CYGNUM_HAL_VSR_MIN 0
#define CYGNUM_HAL_VSR_MAX 255
#define CYGNUM_HAL_VSR_COUNT 256
#define CYGNUM_HAL_ISR_COUNT 256 // 1-1 mapping
 
// Exception vectors. These are the values used when passed out to an
// external exception handler using cyg_hal_deliver_exception()
 
#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION
#define CYGNUM_HAL_EXCEPTION_INTERRUPT \
CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT
 
#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_INSTR_ACCESS_ERROR
#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DATA_ACCESS_ERROR
 
#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION
#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_DATA_ACCESS
#define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX - \
CYGNUM_HAL_EXCEPTION_MIN + 1)
 
#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1
#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15
 
//--------------------------------------------------------------------------
// Static data used by HAL
 
// ISR tables
externC CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
externC CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
externC CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
 
// VSR table
externC CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
 
// Platform setup memory size (0 if unknown by hardware)
externC CYG_ADDRWORD hal_dram_size;
// what, if anything, this means, is platform dependent:
externC CYG_ADDRWORD hal_dram_type;
 
#if CYGINT_HAL_FRV_MEM_REAL_REGION_TOP
 
externC cyg_uint8 *hal_frv_mem_real_region_top( cyg_uint8 *_regionend_ );
# define HAL_MEM_REAL_REGION_TOP( _regionend_ ) \
hal_frv_mem_real_region_top( _regionend_ )
#endif
 
//--------------------------------------------------------------------------
// Default ISR
// The #define is used to test whether this routine exists, and to allow
// code outside the HAL to call it.
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
 
#define HAL_DEFAULT_ISR hal_default_isr
 
//--------------------------------------------------------------------------
// Interrupt state storage
 
typedef cyg_uint32 CYG_INTERRUPT_STATE;
 
//--------------------------------------------------------------------------
// Interrupt control macros
 
externC cyg_uint32 hal_disable_interrupts(void);
externC void hal_enable_interrupts(void);
externC void hal_restore_interrupts(cyg_uint32);
externC cyg_uint32 hal_query_interrupts(void);
 
// On this processor, interrupts are controlled by level. Since eCos
// only has the notion of "off" and "on", this will be emulated by
// NONE-level and ALL-level.
#define HAL_DISABLE_INTERRUPTS(_old_) \
CYG_MACRO_START \
register cyg_uint32 reg; \
asm volatile ( \
"movsg psr,%0\n" \
"\tsetlos (0x0F<<3),gr5\n" \
"\tor %0,gr5,gr5\n" \
"\tmovgs gr5,psr\n" \
: "=r" (reg) \
: \
: "gr5" /* Clobber list */ \
); \
(_old_) = (reg); \
CYG_MACRO_END
 
#define HAL_ENABLE_INTERRUPTS() \
CYG_MACRO_START \
asm volatile ( \
"movsg psr,gr4\n" \
"\tsetlos (0x0F<<3),gr5\n" \
"\tnot gr5,gr5\n" \
"\tand gr4,gr5,gr5\n" \
"\tmovgs gr5,psr\n" \
: \
: \
: "gr4","gr5" /* Clobber list */ \
); \
CYG_MACRO_END
 
// This should work, but breaks compiler
#if 0
#define HAL_RESTORE_INTERRUPTS(_old_) \
CYG_MACRO_START \
asm volatile ( \
"movsg psr,gr4\n" \
"\tsetlos 1,gr5\n" \
"\tand %0,gr5,gr5\n" \
"\tor gr5,gr4,gr4\n" \
"\tmovgs gr4,psr\n" \
: \
: "g" (_old_) \
: "gr4","gr5" /* Clobber list */ \
); \
CYG_MACRO_END
#else
#define HAL_RESTORE_INTERRUPTS(_old_) \
hal_restore_interrupts(_old_)
#endif
 
#define HAL_QUERY_INTERRUPTS(_old_) \
_old_ = hal_query_interrupts()
 
//--------------------------------------------------------------------------
// Routine to execute DSRs using separate interrupt stack
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
externC void hal_interrupt_stack_call_pending_DSRs(void);
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
hal_interrupt_stack_call_pending_DSRs()
 
#if 0 // Interrupt stacks not implemented yet
// these are offered solely for stack usage testing
// if they are not defined, then there is no interrupt stack.
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
// use them to declare these extern however you want:
// extern char HAL_INTERRUPT_STACK_BASE[];
// extern char HAL_INTERRUPT_STACK_TOP[];
// is recommended
#endif // 0
#endif
 
//--------------------------------------------------------------------------
// Vector translation.
 
#ifndef HAL_TRANSLATE_VECTOR
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
(_index_) = (_vector_)
#endif
 
//--------------------------------------------------------------------------
// Interrupt and VSR attachment macros
 
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
CYG_MACRO_START \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
\
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
(_state_) = 0; \
else \
(_state_) = 1; \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
CYG_MACRO_START \
if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)hal_default_isr ) \
{ \
hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_; \
hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_; \
hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_; \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
CYG_MACRO_START \
if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ ) \
{ \
hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)hal_default_isr; \
hal_interrupt_data[_vector_] = 0; \
hal_interrupt_objects[_vector_] = 0; \
} \
CYG_MACRO_END
 
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
*(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
 
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
CYG_MACRO_START \
if( _poldvsr_ != NULL ) \
*(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
CYG_MACRO_END
 
//--------------------------------------------------------------------------
// Interrupt controller access
 
externC void hal_interrupt_mask(int);
externC void hal_interrupt_unmask(int);
externC void hal_interrupt_acknowledge(int);
externC void hal_interrupt_configure(int, int, int);
externC void hal_interrupt_set_level(int, int);
 
#define HAL_INTERRUPT_MASK( _vector_ ) \
hal_interrupt_mask( _vector_ )
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
hal_interrupt_unmask( _vector_ )
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
hal_interrupt_acknowledge( _vector_ )
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
hal_interrupt_configure( _vector_, _level_, _up_ )
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
hal_interrupt_set_level( _vector_, _level_ )
 
//--------------------------------------------------------------------------
// Clock control
 
externC void hal_clock_initialize(cyg_uint32);
externC void hal_clock_read(cyg_uint32 *);
externC void hal_clock_reset(cyg_uint32, cyg_uint32);
 
#define HAL_CLOCK_INITIALIZE( _period_ ) hal_clock_initialize( _period_ )
#define HAL_CLOCK_RESET( _vec_, _period_ ) hal_clock_reset( _vec_, _period_ )
#define HAL_CLOCK_READ( _pvalue_ ) hal_clock_read( _pvalue_ )
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
# ifndef HAL_CLOCK_LATENCY
# define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( (cyg_uint32 *)_pvalue_ )
# endif
#endif
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_INTR_H
// End of hal_intr.h
/arch/v2_0/include/hal_arch.h
0,0 → 1,347
#ifndef CYGONCE_HAL_ARCH_H
#define CYGONCE_HAL_ARCH_H
 
//==========================================================================
//
// hal_arch.h
//
// Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors: nickg, gthomas
// Date: 2001-09-07
// Purpose: Define architecture abstractions
// Usage: #include <cyg/hal/hal_arch.h>
 
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h> // To decide on stack usage
#include <cyg/infra/cyg_type.h>
 
#if CYGINT_HAL_FRV_ARCH_FR400 != 0
#define _NGPR 32
#define _NFPR 32
#endif
#if CYGINT_HAL_FRV_ARCH_FR500 != 0
#define _NGPR 64
#define _NFPR 64
#endif
 
#ifndef _NGPR
#error No architecture defined?
#endif
 
//--------------------------------------------------------------------------
// Common "special" register definitions
 
// Processor status register
#define _PSR_PIVL_SHIFT 3
#define _PSR_PIVL_MASK (0xF<<(_PSR_PIVL_SHIFT)) // Interrupt mask level
#define _PSR_S (1<<2) // Supervisor state
#define _PSR_PS (1<<1) // Previous supervisor state
#define _PSR_ET (1<<0) // Enable interrupts
 
#define _PSR_INITIAL (_PSR_S|_PSR_PS|_PSR_ET) // Supervisor mode, exceptions
 
// Hardware status register
#define _HSR0_ICE (1<<31) // Instruction cache enable
#define _HSR0_DCE (1<<30) // Data cache enable
#define _HSR0_IMMU (1<<26) // Instruction MMU enable
#define _HSR0_DMMU (1<<25) // Data MMU enable
 
// Debug Control Register
#define _DCR_EBE (1 << 30)
#define _DCR_SE (1 << 29)
#define _DCR_DRBE0 (1 << 19)
#define _DCR_DWBE0 (1 << 18)
#define _DCR_DDBE0 (1 << 17)
#define _DCR_DRBE1 (1 << 16)
#define _DCR_DWBE1 (1 << 15)
#define _DCR_DDBE1 (1 << 14)
#define _DCR_DRBE2 (1 << 13)
#define _DCR_DWBE2 (1 << 12)
#define _DCR_DDBE2 (1 << 11)
#define _DCR_DRBE3 (1 << 10)
#define _DCR_DWBE3 (1 << 9)
#define _DCR_DDBE3 (1 << 8)
#define _DCR_IBE0 (1 << 7)
#define _DCR_IBCE0 (1 << 6)
#define _DCR_IBE1 (1 << 5)
#define _DCR_IBCE1 (1 << 4)
#define _DCR_IBE2 (1 << 3)
#define _DCR_IBCE2 (1 << 2)
#define _DCR_IBE3 (1 << 1)
#define _DCR_IBCE3 (1 << 0)
 
// Initial contents for special registers
 
#define _CCR_INITIAL 0
#define _LCR_INITIAL 0
#define _CCCR_INITIAL 0
 
//--------------------------------------------------------------------------
//
// Saved thread state
//
typedef struct
{
cyg_uint32 gpr[_NGPR]; // Saved general purpose registers
cyg_uint32 pc; // Current [next] instruction location
cyg_uint32 psr; // Processor status register
cyg_uint32 lr; // Link register
cyg_uint32 ccr; // Condition codes
cyg_uint32 cccr;
cyg_uint32 lcr;
cyg_int32 vector; // Reason for last exception
} HAL_SavedRegisters;
 
//-------------------------------------------------------------------------
// Exception handling function.
// This function is defined by the kernel according to this prototype. It is
// invoked from the HAL to deal with any CPU exceptions that the HAL does
// not want to deal with itself. It usually invokes the kernel's exception
// delivery mechanism.
 
externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
 
//-------------------------------------------------------------------------
// Bit manipulation macros
 
externC int hal_lsbindex(int);
externC int hal_msbindex(int);
 
#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbindex(mask)
#define HAL_MSBIT_INDEX(index, mask) index = hal_msbindex(mask)
 
//-------------------------------------------------------------------------
// Context Initialization
// Initialize the context of a thread.
// Arguments:
// _sparg_ name of variable containing current sp, will be changed to new sp
// _thread_ thread object address, passed as argument to entry point
// _entry_ entry point address.
// _id_ bit pattern used in initializing registers, for debugging.
 
#define _HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
CYG_MACRO_START \
register CYG_WORD _sp_ = ((CYG_WORD)_sparg_) &~15; \
register HAL_SavedRegisters *_regs_; \
int _i_; \
_regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \
for( _i_ = 1; _i_ < _NGPR; _i_++) \
(_regs_)->gpr[_i_] = (_id_)|_i_; \
(_regs_)->gpr[8] = (CYG_WORD)(_thread_); /* R8 = arg1 = thread ptr */ \
(_regs_)->gpr[1] = (CYG_WORD)(_sp_); /* SP = top of stack */ \
(_regs_)->lr = (CYG_WORD)(_entry_); /* LR = entry point */ \
(_regs_)->pc = (CYG_WORD)(_entry_); /* PC = [initial] entry point */ \
(_regs_)->psr = _PSR_INITIAL; /* PSR = Interrupt enabled */ \
(_regs_)->ccr = _CCR_INITIAL; \
(_regs_)->lcr = _LCR_INITIAL; \
(_regs_)->ccr = _CCCR_INITIAL; \
_sparg_ = (CYG_ADDRESS)_regs_; \
CYG_MACRO_END
 
//--------------------------------------------------------------------------
// Context switch macros.
// The arguments are pointers to locations where the stack pointer
// of the current thread is to be stored, and from where the sp of the
// next thread is to be fetched.
 
externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
externC void hal_thread_load_context( CYG_ADDRESS to )
__attribute__ ((noreturn));
 
#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \
(CYG_ADDRESS)_fspptr_);
 
#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
 
//--------------------------------------------------------------------------
// Execution reorder barrier.
// When optimizing the compiler can reorder code. In multithreaded systems
// where the order of actions is vital, this can sometimes cause problems.
// This macro may be inserted into places where reordering should not happen.
 
#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
 
//--------------------------------------------------------------------------
// Breakpoint support
// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
// if executed.
// HAL_BREAKINST is the value of the breakpoint instruction and
// HAL_BREAKINST_SIZE is its size in bytes.
 
// The choices for breakpoints seem to be:
// break 0x801000C0
// tira gr0,#1 0xC0700001
#ifdef CYGSEM_HAL_FRV_USE_BREAK_INSTRUCTION
#define HAL_BREAKPOINT(_label_) \
asm volatile (" .globl " #_label_ "\n" \
#_label_":\tbreak\n" \
);
 
#define HAL_BREAKINST 0x801000C0
#else
#define HAL_BREAKPOINT(_label_) \
asm volatile (" .globl " #_label_ "\n" \
#_label_":\ttira\tgr0,#1\n" \
);
 
#define HAL_BREAKINST 0xC0700001
#endif
#define HAL_BREAKINST_SIZE 4
#define HAL_BREAKINST_TYPE cyg_uint32
 
//--------------------------------------------------------------------------
// Thread register state manipulation for GDB support.
 
// GDB expects the registers in this structure:
// gr0..gr31, gr32..gr63 - 4 bytes each
// fpr0..fpr31, fpr32..fpr63 - 4 bytes each
// pc, psr, ccr, cccr - 4 bytes each
// 14 <unused> - 4 bytes each
// lr, lcr - 4 bytes each
 
// Translate a stack pointer as saved by the thread context macros above into
// a pointer to a HAL_SavedRegisters structure.
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
(_regs_) = (HAL_SavedRegisters *)(_sp_)
 
// Copy a set of registers from a HAL_SavedRegisters structure into a
// GDB ordered array.
#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \
CYG_MACRO_START \
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ <= _NGPR; _i_++ ) \
_regval_[_i_] = (_regs_)->gpr[_i_]; \
_regval_[128] = (_regs_)->pc; \
_regval_[129] = (_regs_)->psr; \
_regval_[130] = (_regs_)->ccr; \
_regval_[135] = (_regs_)->vector; \
_regval_[145] = (_regs_)->lr; \
_regval_[146] = (_regs_)->lcr; \
CYG_MACRO_END
 
// Copy a GDB ordered array into a HAL_SavedRegisters structure.
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
CYG_MACRO_START \
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ <= _NGPR; _i_++ ) \
(_regs_)->gpr[_i_] = _regval_[_i_]; \
\
(_regs_)->pc = _regval_[128]; \
(_regs_)->psr = _regval_[129]; \
(_regs_)->ccr = _regval_[130]; \
(_regs_)->lr = _regval_[145]; \
(_regs_)->lcr = _regval_[146]; \
CYG_MACRO_END
 
//--------------------------------------------------------------------------
// HAL setjmp
 
#define CYGARC_JMP_BUF_SIZE 0x110
 
typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
 
externC int hal_setjmp(hal_jmp_buf env);
externC void hal_longjmp(hal_jmp_buf env, int val);
 
//--------------------------------------------------------------------------
// Idle thread code.
// This macro is called in the idle thread loop, and gives the HAL the
// chance to insert code. Typical idle thread behaviour might be to halt the
// processor.
 
externC void hal_idle_thread_action(cyg_uint32 loop_count);
 
#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
 
//---------------------------------------------------------------------------
 
// Minimal and sensible stack sizes: the intention is that applications
// will use these to provide a stack size in the first instance prior to
// proper analysis. Idle thread stack should be this big.
 
// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
 
// This is not a config option because it should not be adjusted except
// under "enough rope" sort of disclaimers.
 
// A minimal, optimized stack frame, rounded up - no autos
#define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 150)
 
// Stack needed for a context switch: this is implicit in the estimate for
// interrupts so not explicitly used below:
#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 150)
 
// Interrupt + call to ISR, interrupt_end() and the DSR
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
((4 * 150) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
 
// Space for the maximum number of nested interrupts, plus room to call functions
#define CYGNUM_HAL_MAX_INTERRUPT_NESTING 4
 
#define CYGNUM_HAL_STACK_SIZE_MINIMUM \
(CYGNUM_HAL_MAX_INTERRUPT_NESTING * CYGNUM_HAL_STACK_INTERRUPT_SIZE + \
2 * CYGNUM_HAL_STACK_FRAME_SIZE)
 
#define CYGNUM_HAL_STACK_SIZE_TYPICAL \
(CYGNUM_HAL_STACK_SIZE_MINIMUM + \
16 * CYGNUM_HAL_STACK_FRAME_SIZE)
 
 
//--------------------------------------------------------------------------
// Macros for switching context between two eCos instances (jump from
// code in ROM to code in RAM or vice versa).
#define CYGARC_HAL_SAVE_GP()
#define CYGARC_HAL_RESTORE_GP()
 
#endif // CYGONCE_HAL_ARCH_H
// End of hal_arch.h
/arch/v2_0/include/hal_cache.h
0,0 → 1,298
#ifndef CYGONCE_HAL_CACHE_H
#define CYGONCE_HAL_CACHE_H
 
//=============================================================================
//
// hal_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors:hmt
// Date: 2000-05-08
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/hal_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <cyg/infra/cyg_type.h>
#include CYGBLD_HAL_PLF_DEFS_H
#include <cyg/hal/plf_cache.h> // Platform (model) details
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache
 
// Enable the instruction cache
#define HAL_ICACHE_ENABLE() \
CYG_MACRO_START \
cyg_uint32 mask = _HSR0_ICE; \
asm volatile ( \
"movsg hsr0,gr4\n" \
"\tor gr4,%0,gr4\n" \
"\tmovgs gr4,hsr0\n" \
: \
: "r"(mask) \
: "gr4" /* Clobber list */ \
); \
CYG_MACRO_END
 
// Disable the instruction cache (and invalidate it, required semanitcs)
#define HAL_ICACHE_DISABLE() \
CYG_MACRO_START \
cyg_uint32 mask = ~_HSR0_ICE; \
asm volatile ( \
"movsg hsr0,gr4\n" \
"\tand gr4,%0,gr4\n" \
"\tmovgs gr4,hsr0\n" \
: \
: "r"(mask) \
: "gr4" /* Clobber list */ \
); \
CYG_MACRO_END
 
// Query the state of the instruction cache
#define HAL_ICACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
register cyg_uint32 reg; \
asm volatile ("movsg hsr0,%0" \
: "=r"(reg) \
: \
); \
(_state_) = (0 != (_HSR0_ICE & reg)); \
CYG_MACRO_END
 
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
asm volatile ("icei @(gr4,gr0),1" \
: \
: \
); \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
// (which includes flushing out pending writes)
#define HAL_ICACHE_SYNC() \
CYG_MACRO_START \
HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
CYG_MACRO_END
 
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)
 
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
//#define HAL_ICACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_ICACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Instruction cache line control
 
// Invalidate cache lines in the given range without writing to memory.
#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) \
CYG_MACRO_START \
cyg_uint32 _b = _base_; \
cyg_uint32 _s = _size_; \
while (_s > HAL_DCACHE_LINE_SIZE) { \
asm volatile ("ici @(%0,gr0)" \
: \
: "r"(_b) \
); \
_s -= HAL_DCACHE_LINE_SIZE; \
_b += HAL_DCACHE_LINE_SIZE; \
} \
CYG_MACRO_END
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
// Enable the data cache
#define HAL_DCACHE_ENABLE() \
CYG_MACRO_START \
cyg_uint32 mask = _HSR0_DCE; \
asm volatile ( \
"movsg hsr0,gr4\n" \
"\tor gr4,%0,gr4\n" \
"\tmovgs gr4,hsr0\n" \
: \
: "r"(mask) \
: "gr4" /* Clobber list */ \
); \
CYG_MACRO_END
 
// Disable the data cache (and invalidate it, required semanitcs)
#define HAL_DCACHE_DISABLE() \
CYG_MACRO_START \
cyg_uint32 mask = ~_HSR0_DCE; \
asm volatile ( \
"movsg hsr0,gr4\n" \
"\tand gr4,%0,gr4\n" \
"\tmovgs gr4,hsr0\n" \
: \
: "r"(mask) \
: "gr4" /* Clobber list */ \
); \
CYG_MACRO_END
 
// Query the state of the data cache
#define HAL_DCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
register cyg_uint32 reg; \
asm volatile ("movsg hsr0,%0" \
: "=r"(reg) \
: \
); \
(_state_) = (0 != (_HSR0_DCE & reg)); \
CYG_MACRO_END
 
// Flush (invalidate) the entire dcache
#define HAL_DCACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
asm volatile ("dcei @(gr4,gr0),1" \
: \
: \
); \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC() \
CYG_MACRO_START \
asm volatile ("dcef @(gr4,gr0),1" \
: \
: \
); \
CYG_MACRO_END
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
#define HAL_DCACHE_WRITETHRU_MODE 0
#define HAL_DCACHE_WRITEBACK_MODE 1
 
// Get the current writeback mode - or only writeback mode if fixed
#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
_mode_ = HAL_DCACHE_WRITETHRU_MODE; \
CYG_MACRO_END
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
//#define HAL_DCACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_DCACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
CYG_MACRO_START \
HAL_DCACHE_STORE( _base_ , _size_ ); \
HAL_DCACHE_INVALIDATE( _base_ , _size_ ); \
CYG_MACRO_END
 
// Invalidate cache lines in the given range without writing to memory.
#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
CYG_MACRO_START \
cyg_uint32 _b = _base_; \
cyg_uint32 _s = _size_; \
while (_s > HAL_DCACHE_LINE_SIZE) { \
asm volatile ("dci @(%0,gr0)" \
: \
: "r"(_b) \
); \
_s -= HAL_DCACHE_LINE_SIZE; \
_b += HAL_DCACHE_LINE_SIZE; \
} \
CYG_MACRO_END
// Write dirty cache lines to memory for the given address range.
#define HAL_DCACHE_STORE( _base_ , _size_ ) \
CYG_MACRO_START \
cyg_uint32 _b = _base_; \
cyg_uint32 _s = _size_; \
while (_s > HAL_DCACHE_LINE_SIZE) { \
asm volatile ("dcf @(%0,gr0)" \
: \
: "r"(_b) \
); \
_s -= HAL_DCACHE_LINE_SIZE; \
_b += HAL_DCACHE_LINE_SIZE; \
} \
CYG_MACRO_END
 
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
 
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h
/arch/v2_0/ChangeLog
0,0 → 1,130
2003-04-10 Nick Garnett <nickg@balti.calivar.com>
 
* src/frv.ld:
Added .eh_frame to data section. This is a stopgap fix to allow
C++ programs that define exceptions to link and run. It does not
allow them to actually throw exceptions, since that depends on
compiler changes that have not been made. Further, more
far-reaching, linker script changes will also be needs when that
happens.
Added libsupc++.a to GROUP() directive for GCC versions later than
3.0.
 
2003-01-31 Mark Salter <msalter@redhat.com>
 
* src/hal_syscall.c (hal_syscall_handler): Let generic syscall code
handle exit.
 
2002-04-15 Jonathan Larmour <jlarmour@redhat.com>
 
* src/hal_syscall.c (hal_syscall_handler): Add extra sig argument to
__do_syscall.
 
2001-12-10 Richard Sandiford <rsandifo@redhat.com>
 
* src/vectors.S (save_state): Remove unnecessary DDR diddling when
handling breaks. Use BPCSR rather than BPCSR-4 as the break address.
(restore_state): Take two new arguments: the register that the
PC should be loaded into, and the argument to the rett instruction.
(_break): If handling a break instruction, return to the following
instruction using a normal "ret". Ignore other kinds of break if
they were triggered when traps were disabled; assume that an
interrupt or exception handler has triggered a stack watchpoint
accidentally. Correct GP calculation. Return using "rett #1"
rather than "rett #0".
 
2001-11-28 Hugo Tyson <hmt@redhat.com>
 
* src/vectors.S (_vectors): if defined(CYGPKG_HAL_FRV_FRV400) &&
defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS), add macro break_VSR
to create a VSR entry which leaps to _break; rearrange the
initialization of the VSR table so that the counts are correct;
use break_VSR in slot 255; define _break which calls break_handler()
much akin to exception handler().
 
Note that there is no need to define CYGSEM_HAL_FRV_HW_DEBUG for
the FRV_FRV400 target; while we do use Hardware Debug, we don't
use *that* sort of hardware debug, specifically we do not use
hardware single-step, because it breaks as soon as we exit debug
mode, ie whilst we are still within the stub. But vectors.S does
the same tidy-up of machine state, conditioned on FVR400 instead.
 
2001-10-17 Gary Thomas <gthomas@redhat.com>
 
* src/frv_stub.c: Slight cleanup - only need |VLIW|+1 possible
breakpoint locations.
 
2001-10-16 Gary Thomas <gthomas@redhat.com>
 
* src/vectors.S (_exception_return): Remove *bad* workaround code
now that single step VLIW works properly.
 
* src/frv_stub.c (__clear_single_step):
(__single_step): Restructure to support VLIW sequences.
 
2001-10-15 Gary Thomas <gthomas@redhat.com>
 
* include/hal_arch.h: Remove [bogus] CYG_HAL_TABLE macros since
the common ones work fine on this architecture.
 
* src/vectors.S:
* src/frv_stub.c:
* cdl/hal_frv.cdl: Add CDL to describe various [hardware] debug
options.
 
2001-10-01 Gary Thomas <gthomas@redhat.com>
 
* src/vectors.S: [FRV400] can't return from exception to a packed
instruction - this yields illegal instruction.
2001-10-11 Gary Thomas <gthomas@redhat.com>
 
* cdl/hal_frv.cdl:
* include/basetype.h:
* include/hal_arch.h:
* include/hal_intr.h:
* include/frv_stub.h:
* include/hal_io.h:
* include/hal_cache.h:
* src/frv_stub.c:
* src/hal_mk_defs.c:
* src/frv.ld:
* src/hal_misc.c:
* src/vectors.S:
* src/context.S:
* src/hal_syscall.c: New port for FRV architecture.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/arch/v2_0/src/hal_syscall.c
0,0 → 1,107
//=============================================================================
//
// hal_syscall.c
//
//
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): msalter
// Contributors:msalter, gthomas
// Date: 2000-11-5
// Purpose:
// Description:
//
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_REDBOOT
#include <pkgconf/redboot.h>
#endif
 
#if defined(CYGSEM_REDBOOT_BSP_SYSCALLS)
 
#include <cyg/hal/hal_stub.h> // Our header
#include <cyg/hal/hal_arch.h> // HAL_BREAKINST
#include <cyg/hal/hal_cache.h> // HAL_xCACHE_x
#include <cyg/hal/hal_intr.h> // interrupt disable/restore
 
#include <cyg/hal/hal_if.h> // ROM calling interface
#include <cyg/hal/hal_misc.h> // Helper functions
 
extern int __do_syscall(int func, // syscall function number
long arg1, long arg2, // up to four args.
long arg3, long arg4,
int *retval, // syscall return value
int *sig); // signal to return (or 0)
 
#define SYS_exit 1
#define SYS_interrupt 1000
 
int
hal_syscall_handler(void)
{
int func, arg1, arg2, arg3, arg4;
int err, res, sig;
 
func = get_register(R7);
arg1 = get_register(R8);
arg2 = get_register(R9);
arg3 = get_register(R10);
arg4 = get_register(R11);
 
if (func == SYS_interrupt) {
// A console interrupt landed us here.
// Invoke the debug agent so as to cause a SIGINT.
return SIGINT;
}
 
if ((res = __do_syscall(func, arg1, arg2, arg3, arg4, &err, &sig)) != 0) {
// Skip over trap instruction
put_register(PC, get_register(PC)+4);
put_register(R8, err);
return sig;
}
 
return SIGTRAP;
}
#endif // CYGSEM_REDBOOT_BSP_SYSCALLS
/arch/v2_0/src/hal_misc.c
0,0 → 1,275
/*==========================================================================
//
// hal_misc.c
//
// HAL miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors: nickg, gthomas
// Date: 1999-02-20
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//=========================================================================*/
 
#include <pkgconf/hal.h>
#include <pkgconf/hal_frv.h>
#ifdef CYGPKG_KERNEL
#include <pkgconf/kernel.h>
#endif
#ifdef CYGPKG_CYGMON
#include <pkgconf/cygmon.h>
#endif
 
#include <cyg/infra/cyg_type.h>
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/infra/diag.h>
 
#include <cyg/hal/hal_arch.h> // HAL header
#include <cyg/hal/hal_intr.h> // HAL header
#include <cyg/hal/hal_cache.h> // HAL header
 
/*------------------------------------------------------------------------*/
/* First level C exception handler. */
 
externC void __handle_exception (void);
 
externC HAL_SavedRegisters *_hal_registers;
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
// Historical - this datum is defined by the GDB stubs if present
externC
#endif
void* volatile __mem_fault_handler;
 
#if 0
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
/* Force exception handling into the GDB stubs. This is done by taking over
the exception vectors while executing in the stubs. This allows for the
debugged program to handle exceptions itself, except while the GDB
processing is underway. The only vector that can't be handled this way
is the illegal instruction vector which is used for breakpoint/single-step
and must be maintained by the stubs at all times.
Note: the interrupt vectors are _not_ preempted as the stubs probably can't
handle them properly.
*/
 
#define ARM_VECTORS 8
extern unsigned long vectors[]; // exception vectors as defined by the stubs
 
#if !defined(CYGPKG_CYGMON)
static unsigned long *hardware_vectors = (unsigned long *)0x20;
static unsigned long hold_vectors[ARM_VECTORS];
static int exception_level;
 
static void
__take_over_debug_traps(void)
{
hold_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
hold_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
}
 
static void
__restore_debug_traps(void)
{
hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = hold_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = hold_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
}
#endif // !CYGPKG_CYGMON
#endif
 
#endif // if 0
 
void
exception_handler(HAL_SavedRegisters *regs)
{
// Special case handler for code which has chosen to take care
// of data exceptions (i.e. code which expects them to happen)
// This is common in discovery code, e.g. checking for a particular
// device which may generate an exception when probing if the
// device is not present
if (__mem_fault_handler &&
regs->vector == CYGNUM_HAL_EXCEPTION_DATA_ACCESS) {
regs->pc = (unsigned long)__mem_fault_handler;
return; // Caught an exception inside stubs
}
 
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) && !defined(CYGPKG_CYGMON)
//?? if (++exception_level == 1) __take_over_debug_traps();
 
_hal_registers = regs;
__handle_exception();
 
//?? if (--exception_level == 0) __restore_debug_traps();
 
#elif defined(CYGPKG_KERNEL_EXCEPTIONS)
 
// We should decode the vector and pass a more appropriate
// value as the second argument. For now we simply pass a
// pointer to the saved registers. We should also divert
// breakpoint and other debug vectors into the debug stubs.
 
cyg_hal_deliver_exception( regs->vector, (CYG_ADDRWORD)regs );
 
#else
 
CYG_FAIL("Exception!!!");
#endif
return;
}
 
void hal_spurious_IRQ(HAL_SavedRegisters *regs) CYGBLD_ATTRIB_WEAK;
void
hal_spurious_IRQ(HAL_SavedRegisters *regs)
{
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
exception_handler(regs);
#else
CYG_FAIL("Spurious interrupt!!");
#endif
}
 
/*------------------------------------------------------------------------*/
/* C++ support - run initial constructors */
 
#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
cyg_bool cyg_hal_stop_constructors;
#endif
 
typedef void (*pfunc) (void);
extern pfunc __CTOR_LIST__[];
extern pfunc __CTOR_END__[];
 
void
cyg_hal_invoke_constructors (void)
{
#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
static pfunc *p = &__CTOR_END__[-1];
cyg_hal_stop_constructors = 0;
for (; p >= __CTOR_LIST__; p--) {
(*p) ();
if (cyg_hal_stop_constructors) {
p--;
break;
}
}
#else
pfunc *p;
 
for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--) {
(*p) ();
}
#endif
}
 
/*------------------------------------------------------------------------*/
/* Architecture default ISR */
 
externC cyg_uint32
hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
CYG_TRACE1(true, "Interrupt: %d", vector);
 
CYG_FAIL("Spurious Interrupt!!!");
return 0;
}
 
/*------------------------------------------------------------------------*/
/* Idle thread action */
 
void
hal_idle_thread_action( cyg_uint32 count )
{
}
 
/*-------------------------------------------------------------------------*/
/* Misc functions */
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS__
/* This function will generate a breakpoint exception. It is used at the
beginning of a program to sync up with a debugger and can be used
otherwise as a quick means to stop program execution and "break" into
the debugger. */
 
void
breakpoint(void)
{
HAL_BREAKPOINT(_breakinst);
}
 
 
/* This function returns the opcode for a 'trap' instruction. */
 
unsigned long
__break_opcode (void)
{
return HAL_BREAKINST;
}
#endif
 
int
hal_lsbindex(int mask)
{
int i;
for (i = 0; i < 32; i++) {
if (mask & (1<<i)) return (i);
}
return (-1);
}
 
int
hal_msbindex(int mask)
{
int i;
for (i = 31; i >= 0; i--) {
if (mask & (1<<i)) return (i);
}
return (-1);
}
 
/*------------------------------------------------------------------------*/
// EOF hal_misc.c
/arch/v2_0/src/context.S
0,0 → 1,369
// #===========================================================================
// #
// # context.S
// #
// # FUJITSU context switch code
// #
// #===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
// #===========================================================================
// ######DESCRIPTIONBEGIN####
// #
// # Author(s): nickg, gthomas
// # Contributors: nickg, gthomas
// # Date: 1998-09-15
// # Purpose: FUJITSU context switch code
// # Description: This file contains implementations of the thread context
// # switch routines. It also contains the longjmp() and setjmp()
// # routines.
// #
// #####DESCRIPTIONEND####
// #
// #===========================================================================
 
#include <pkgconf/hal.h>
 
#include "frv.inc"
 
.text
// ----------------------------------------------------------------------------
// hal_thread_switch_context(new, old)
// Switch thread contexts
// new = address of context of next thread to execute
// old = address of context save location of current thread
// thread state is saved on the current stack
 
.globl hal_thread_switch_context
hal_thread_switch_context:
subi sp,_TS_size,sp // Space for saved frame
sti gr2,@(sp,_TS_GPR2) // Save registers
sti gr3,@(sp,_TS_GPR3)
sti gr4,@(sp,_TS_GPR4)
sti gr5,@(sp,_TS_GPR5)
sti gr6,@(sp,_TS_GPR6)
sti gr7,@(sp,_TS_GPR7)
sti gr8,@(sp,_TS_GPR8)
sti gr9,@(sp,_TS_GPR9)
sti gr10,@(sp,_TS_GPR10)
sti gr11,@(sp,_TS_GPR11)
sti gr12,@(sp,_TS_GPR12)
sti gr13,@(sp,_TS_GPR13)
sti gr14,@(sp,_TS_GPR14)
sti gr15,@(sp,_TS_GPR15)
sti gr16,@(sp,_TS_GPR16)
sti gr17,@(sp,_TS_GPR17)
sti gr18,@(sp,_TS_GPR18)
sti gr19,@(sp,_TS_GPR19)
sti gr20,@(sp,_TS_GPR20)
sti gr21,@(sp,_TS_GPR21)
sti gr22,@(sp,_TS_GPR22)
sti gr23,@(sp,_TS_GPR23)
sti gr24,@(sp,_TS_GPR24)
sti gr25,@(sp,_TS_GPR25)
sti gr26,@(sp,_TS_GPR26)
sti gr27,@(sp,_TS_GPR27)
sti gr28,@(sp,_TS_GPR28)
sti gr29,@(sp,_TS_GPR29)
sti gr30,@(sp,_TS_GPR30)
sti gr31,@(sp,_TS_GPR31)
#if _NGPR != 32
sti gr32,@(sp,_TS_GPR32)
sti gr33,@(sp,_TS_GPR33)
sti gr34,@(sp,_TS_GPR34)
sti gr35,@(sp,_TS_GPR35)
sti gr36,@(sp,_TS_GPR36)
sti gr37,@(sp,_TS_GPR37)
sti gr38,@(sp,_TS_GPR38)
sti gr39,@(sp,_TS_GPR39)
sti gr40,@(sp,_TS_GPR40)
sti gr41,@(sp,_TS_GPR41)
sti gr42,@(sp,_TS_GPR42)
sti gr43,@(sp,_TS_GPR43)
sti gr44,@(sp,_TS_GPR44)
sti gr45,@(sp,_TS_GPR45)
sti gr46,@(sp,_TS_GPR46)
sti gr47,@(sp,_TS_GPR47)
sti gr48,@(sp,_TS_GPR48)
sti gr49,@(sp,_TS_GPR49)
sti gr50,@(sp,_TS_GPR50)
sti gr51,@(sp,_TS_GPR51)
sti gr52,@(sp,_TS_GPR52)
sti gr53,@(sp,_TS_GPR53)
sti gr54,@(sp,_TS_GPR54)
sti gr55,@(sp,_TS_GPR55)
sti gr56,@(sp,_TS_GPR56)
sti gr57,@(sp,_TS_GPR57)
sti gr58,@(sp,_TS_GPR58)
sti gr59,@(sp,_TS_GPR59)
sti gr60,@(sp,_TS_GPR60)
sti gr61,@(sp,_TS_GPR61)
sti gr62,@(sp,_TS_GPR62)
sti gr63,@(sp,_TS_GPR63)
#endif
movsg psr,gr4
sti gr4,@(sp,_TS_PSR)
movsg lr,gr4
sti gr4,@(sp,_TS_PC)
movsg ccr,gr4
sti gr4,@(sp,_TS_CCR)
movsg lcr,gr4
sti gr4,@(sp,_TS_LCR)
movsg cccr,gr4
sti gr4,@(sp,_TS_CCCR)
addi sp,_TS_size,gr4
sti gr4,@(sp,_TS_SP)
sti sp,@(gr9,0) // Pointer to saved context
 
# Now load the destination thread by dropping through
# to hal_thread_load_context
// ----------------------------------------------------------------------------
// hal_thread_load_context(new)
// Load thread context
// new = address of context of next thread to execute
// Note that this function is also the second half of
// hal_thread_switch_context and is simply dropped into from it.
 
.globl hal_thread_load_context
hal_thread_load_context:
ldi @(gr8,0),sp // Saved context
ldi @(sp,_TS_PSR),gr8
setlos #~_PSR_ET,gr9 // Turn off exceptions
and gr8,gr9,gr8
setlos #_PSR_PS|_PSR_S,gr9 // Stay in supervisor mode
or gr8,gr9,gr8
movgs gr8,psr
ldi @(sp,_TS_PC),gr8
movgs gr8,pcsr
ldi @(sp,_TS_CCR),gr8
movgs gr8,ccr
ldi @(sp,_TS_LCR),gr8
movgs gr8,lcr
ldi @(sp,_TS_CCCR),gr8
movgs gr8,cccr
ldi @(sp,_TS_GPR2),gr2 // Restore registers
ldi @(sp,_TS_GPR3),gr3
ldi @(sp,_TS_GPR4),gr4
ldi @(sp,_TS_GPR5),gr5
ldi @(sp,_TS_GPR6),gr6
ldi @(sp,_TS_GPR7),gr7
ldi @(sp,_TS_GPR8),gr8
ldi @(sp,_TS_GPR9),gr9
ldi @(sp,_TS_GPR10),gr10
ldi @(sp,_TS_GPR11),gr11
ldi @(sp,_TS_GPR12),gr12
ldi @(sp,_TS_GPR13),gr13
ldi @(sp,_TS_GPR14),gr14
ldi @(sp,_TS_GPR15),gr15
ldi @(sp,_TS_GPR16),gr16
ldi @(sp,_TS_GPR17),gr17
ldi @(sp,_TS_GPR18),gr18
ldi @(sp,_TS_GPR19),gr19
ldi @(sp,_TS_GPR20),gr20
ldi @(sp,_TS_GPR21),gr21
ldi @(sp,_TS_GPR22),gr22
ldi @(sp,_TS_GPR23),gr23
ldi @(sp,_TS_GPR24),gr24
ldi @(sp,_TS_GPR25),gr25
ldi @(sp,_TS_GPR26),gr26
ldi @(sp,_TS_GPR27),gr27
ldi @(sp,_TS_GPR28),gr28
ldi @(sp,_TS_GPR29),gr29
ldi @(sp,_TS_GPR30),gr30
ldi @(sp,_TS_GPR31),gr31
#if _NGPR != 32
ldi @(sp,_TS_GPR32),gr32
ldi @(sp,_TS_GPR33),gr33
ldi @(sp,_TS_GPR34),gr34
ldi @(sp,_TS_GPR35),gr35
ldi @(sp,_TS_GPR36),gr36
ldi @(sp,_TS_GPR37),gr37
ldi @(sp,_TS_GPR38),gr38
ldi @(sp,_TS_GPR39),gr39
ldi @(sp,_TS_GPR40),gr40
ldi @(sp,_TS_GPR41),gr41
ldi @(sp,_TS_GPR42),gr42
ldi @(sp,_TS_GPR43),gr43
ldi @(sp,_TS_GPR44),gr44
ldi @(sp,_TS_GPR45),gr45
ldi @(sp,_TS_GPR46),gr46
ldi @(sp,_TS_GPR47),gr47
ldi @(sp,_TS_GPR48),gr48
ldi @(sp,_TS_GPR49),gr49
ldi @(sp,_TS_GPR50),gr50
ldi @(sp,_TS_GPR51),gr51
ldi @(sp,_TS_GPR52),gr52
ldi @(sp,_TS_GPR53),gr53
ldi @(sp,_TS_GPR54),gr54
ldi @(sp,_TS_GPR55),gr55
ldi @(sp,_TS_GPR56),gr56
ldi @(sp,_TS_GPR57),gr57
ldi @(sp,_TS_GPR58),gr58
ldi @(sp,_TS_GPR59),gr59
ldi @(sp,_TS_GPR60),gr60
ldi @(sp,_TS_GPR61),gr61
ldi @(sp,_TS_GPR62),gr62
ldi @(sp,_TS_GPR63),gr63
#endif
ldi @(sp,_TS_SP),sp
rett #0
 
// ----------------------------------------------------------------------------
// HAL longjmp, setjmp implementations - based on newlib
// Register jmpbuf offset
// R16-R31 0x0-0x03c
// R48-R63 0x40-0x7c
// FR16-FR31 0x80-0xbc
// FR48-FR63 0xc0-0xfc
// LR 0x100
// SP 0x104
// FP 0x108
//
// R8 contains the pointer to jmpbuf
 
.text
.global hal_setjmp
.type hal_setjmp,@function
hal_setjmp:
stdi gr16, @(gr8,0)
stdi gr18, @(gr8,8)
stdi gr20, @(gr8,16)
stdi gr22, @(gr8,24)
stdi gr24, @(gr8,32)
stdi gr26, @(gr8,40)
stdi gr28, @(gr8,48)
stdi gr30, @(gr8,56)
#if _NGPR != 32
stdi gr48, @(gr8,64)
stdi gr50, @(gr8,72)
stdi gr52, @(gr8,80)
stdi gr54, @(gr8,88)
stdi gr56, @(gr8,96)
stdi gr58, @(gr8,104)
stdi gr60, @(gr8,112)
stdi gr62, @(gr8,120)
#endif
 
#if _NFPR != 0
stdfi fr16, @(gr8,128)
stdfi fr18, @(gr8,136)
stdfi fr20, @(gr8,144)
stdfi fr22, @(gr8,152)
stdfi fr24, @(gr8,160)
stdfi fr26, @(gr8,168)
stdfi fr28, @(gr8,176)
stdfi fr30, @(gr8,184)
#if _NFPR != 32
stdfi fr48, @(gr8,192)
stdfi fr50, @(gr8,200)
stdfi fr52, @(gr8,208)
stdfi fr54, @(gr8,216)
stdfi fr56, @(gr8,224)
stdfi fr58, @(gr8,232)
stdfi fr60, @(gr8,240)
stdfi fr62, @(gr8,248)
#endif
#endif
 
movsg lr, gr4
sti gr4, @(gr8,256)
sti sp, @(gr8,260)
sti fp, @(gr8,264)
mov gr0,gr8
ret
.Lend1:
.size hal_setjmp,.Lend1-hal_setjmp
 
.global hal_longjmp
.type hal_longjmp,@function
hallongjmp:
lddi @(gr8,0), gr16
lddi @(gr8,8), gr18
lddi @(gr8,16), gr20
lddi @(gr8,24), gr22
lddi @(gr8,32), gr24
lddi @(gr8,40), gr26
lddi @(gr8,48), gr28
lddi @(gr8,56), gr30
#if _NGPR != 32
lddi @(gr8,64), gr48
lddi @(gr8,72), gr50
lddi @(gr8,80), gr52
lddi @(gr8,88), gr54
lddi @(gr8,96), gr56
lddi @(gr8,104), gr58
lddi @(gr8,112), gr60
lddi @(gr8,120), gr62
#endif
 
#if _NFPR != 0
lddfi @(gr8,128), fr16
lddfi @(gr8,136), fr18
lddfi @(gr8,144), fr20
lddfi @(gr8,152), fr22
lddfi @(gr8,160), fr24
lddfi @(gr8,168), fr26
lddfi @(gr8,176), fr28
lddfi @(gr8,184), fr30
#if _NFPR != 32
lddfi @(gr8,192), fr48
lddfi @(gr8,200), fr50
lddfi @(gr8,208), fr52
lddfi @(gr8,216), fr54
lddfi @(gr8,224), fr56
lddfi @(gr8,232), fr58
lddfi @(gr8,240), fr60
lddfi @(gr8,248), fr62
#endif
#endif
 
ldi @(gr8,256), gr4
movgs gr4,lr
 
ldi @(gr8,260), sp
ldi @(gr8,264), fp
# Value to return is in r9. If zero, return 1
cmp gr9, gr0, icc0
setlos #1, gr8
ckne icc0, cc4
cmov gr9, gr8, cc4, 1
ret
.Lend2:
.size hal_longjmp,.Lend2-hal_longjmp2
// ----------------------------------------------------------------------------
// end of context.S
/arch/v2_0/src/vectors.S
0,0 → 1,853
// #========================================================================
// #
// # vectors.S
// #
// # Fujitsu exception vectors
// #
// #========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
// #========================================================================
// ######DESCRIPTIONBEGIN####
// #
// # Author(s): gthomas
// # Contributors: gthomas
// # Date: 2001-09-16
// # Purpose: Fujitsu exception vectors
// # Description: This file defines the code placed into the exception
// # vectors. It also contains the first level default VSRs
// # that save and restore state for both exceptions and
// # interrupts.
// #
// #####DESCRIPTIONEND####
// #
// #========================================================================
 
#include <pkgconf/hal.h>
#include CYGBLD_HAL_PLF_DEFS_H
#include "frv.inc"
#include <cyg/hal/platform.inc>
 
.macro lda a r
sethi #gprelhi(\a),\r
setlo #gprello(\a),\r
add \r,gr16,\r
.endm
 
.macro li v r
sethi #((\v)>>16),\r
setlo #((\v)&0xFFFF),\r
.endm
.macro save_GDB_exception_regs base,orig
// 'orig' points to an area where some registers were already saved
// orig+0: GPR4
// orig+4: GPR5
// orig+8: GPR6
// orig+12: GPR16
// orig+16: LR
// orig+20: CCR
sti gr4,@(\base,_TS_VECTOR)
addi \orig,24,gr5
sti gr5,@(\base,_TS_SP)
ldi @(\orig,0),gr5
sti gr5,@(\base,_TS_GPR4)
ldi @(\orig,4),gr5
sti gr5,@(\base,_TS_GPR5)
ldi @(\orig,8),gr5
sti gr5,@(\base,_TS_GPR6)
ldi @(\orig,12),gr5
sti gr5,@(\base,_TS_GPR16)
ldi @(\orig,16),gr5
sti gr5,@(\base,_TS_LR)
ldi @(\orig,20),gr5
sti gr5,@(\base,_TS_CCR)
.endm
.macro save_exception_regs base
sti gr4,@(\base,_TS_VECTOR)
sti gr5,@(\base,_TS_GPR5)
addi sp,_TS_size,gr5
sti gr5,@(\base,_TS_SP)
sti gr6,@(\base,_TS_GPR6)
sti gr16,@(\base,_TS_GPR16)
movsg lr,gr5
sti gr5,@(\base,_TS_LR)
movsg ccr,gr5
sti gr5,@(\base,_TS_CCR)
.endm
 
// Save the machine state after an interrupt/exception
// Note: it might be possible to use stdi/lddi instructions here,
// but it would require that the stack pointer always be 64 bit
// (doubleword) aligned.
.macro save_state base
sti gr0,@(\base,_TS_GPR0)
sti gr2,@(\base,_TS_GPR2)
sti gr3,@(\base,_TS_GPR3)
sti gr7,@(\base,_TS_GPR7)
sti gr8,@(\base,_TS_GPR8)
sti gr9,@(\base,_TS_GPR9)
sti gr10,@(\base,_TS_GPR10)
sti gr11,@(\base,_TS_GPR11)
sti gr12,@(\base,_TS_GPR12)
sti gr13,@(\base,_TS_GPR13)
sti gr14,@(\base,_TS_GPR14)
sti gr15,@(\base,_TS_GPR15)
sti gr17,@(\base,_TS_GPR17)
sti gr18,@(\base,_TS_GPR18)
sti gr19,@(\base,_TS_GPR19)
sti gr20,@(\base,_TS_GPR20)
sti gr21,@(\base,_TS_GPR21)
sti gr22,@(\base,_TS_GPR22)
sti gr23,@(\base,_TS_GPR23)
sti gr24,@(\base,_TS_GPR24)
sti gr25,@(\base,_TS_GPR25)
sti gr26,@(\base,_TS_GPR26)
sti gr27,@(\base,_TS_GPR27)
sti gr28,@(\base,_TS_GPR28)
sti gr29,@(\base,_TS_GPR29)
sti gr30,@(\base,_TS_GPR30)
sti gr31,@(\base,_TS_GPR31)
#if _NGPR != 32
sti gr32,@(\base,_TS_GPR32)
sti gr33,@(\base,_TS_GPR33)
sti gr34,@(\base,_TS_GPR34)
sti gr35,@(\base,_TS_GPR35)
sti gr36,@(\base,_TS_GPR36)
sti gr37,@(\base,_TS_GPR37)
sti gr38,@(\base,_TS_GPR38)
sti gr39,@(\base,_TS_GPR39)
sti gr40,@(\base,_TS_GPR40)
sti gr41,@(\base,_TS_GPR41)
sti gr42,@(\base,_TS_GPR42)
sti gr43,@(\base,_TS_GPR43)
sti gr44,@(\base,_TS_GPR44)
sti gr45,@(\base,_TS_GPR45)
sti gr46,@(\base,_TS_GPR46)
sti gr47,@(\base,_TS_GPR47)
sti gr48,@(\base,_TS_GPR48)
sti gr49,@(\base,_TS_GPR49)
sti gr50,@(\base,_TS_GPR50)
sti gr51,@(\base,_TS_GPR51)
sti gr52,@(\base,_TS_GPR52)
sti gr53,@(\base,_TS_GPR53)
sti gr54,@(\base,_TS_GPR54)
sti gr55,@(\base,_TS_GPR55)
sti gr56,@(\base,_TS_GPR56)
sti gr57,@(\base,_TS_GPR57)
sti gr58,@(\base,_TS_GPR58)
sti gr59,@(\base,_TS_GPR59)
sti gr60,@(\base,_TS_GPR60)
sti gr61,@(\base,_TS_GPR61)
sti gr62,@(\base,_TS_GPR62)
sti gr63,@(\base,_TS_GPR63)
#endif
movsg psr,gr5
sti gr5,@(\base,_TS_PSR)
movsg lcr,gr5
sti gr5,@(\base,_TS_LCR)
movsg cccr,gr5
sti gr5,@(\base,_TS_CCCR)
movsg bpcsr,gr5
#if defined( CYGSEM_HAL_FRV_HW_DEBUG ) || defined(CYGPKG_HAL_FRV_FRV400)
cmpi gr4,#CYGNUM_HAL_VECTOR_BREAKPOINT,icc0
beq icc0,0,10f
#endif
5: movsg pcsr,gr5
cmpi gr4,#CYGNUM_HAL_VECTOR_SYSCALL,icc0
blt icc0,0,10f
6: subi gr5,#4,gr5 // traps show PC+4
10: sti gr5,@(\base,_TS_PC)
.endm
 
// Restore the machine state after an interrupt/exception
.macro restore_state base,pcreg,retv
ldi @(\base,_TS_PC),gr5
movgs gr5,\pcreg
ldi @(\base,_TS_CCR),gr5
movgs gr5,ccr
ldi @(\base,_TS_LR),gr5
movgs gr5,lr
ldi @(\base,_TS_PSR),gr5
movgs gr5,psr
ldi @(\base,_TS_LCR),gr5
movgs gr5,lcr
ldi @(\base,_TS_CCCR),gr5
movgs gr5,cccr
ldi @(\base,_TS_GPR2),gr2
ldi @(\base,_TS_GPR3),gr3
ldi @(\base,_TS_GPR4),gr4
ldi @(\base,_TS_GPR5),gr5
ldi @(\base,_TS_GPR6),gr6
ldi @(\base,_TS_GPR7),gr7
ldi @(\base,_TS_GPR8),gr8
ldi @(\base,_TS_GPR9),gr9
ldi @(\base,_TS_GPR10),gr10
ldi @(\base,_TS_GPR11),gr11
ldi @(\base,_TS_GPR12),gr12
ldi @(\base,_TS_GPR13),gr13
ldi @(\base,_TS_GPR14),gr14
ldi @(\base,_TS_GPR15),gr15
ldi @(\base,_TS_GPR16),gr16
ldi @(\base,_TS_GPR17),gr17
ldi @(\base,_TS_GPR18),gr18
ldi @(\base,_TS_GPR19),gr19
ldi @(\base,_TS_GPR20),gr20
ldi @(\base,_TS_GPR21),gr21
ldi @(\base,_TS_GPR22),gr22
ldi @(\base,_TS_GPR23),gr23
ldi @(\base,_TS_GPR24),gr24
ldi @(\base,_TS_GPR25),gr25
ldi @(\base,_TS_GPR26),gr26
ldi @(\base,_TS_GPR27),gr27
ldi @(\base,_TS_GPR28),gr28
ldi @(\base,_TS_GPR29),gr29
ldi @(\base,_TS_GPR30),gr30
ldi @(\base,_TS_GPR31),gr31
#if _NGPR != 32
ldi @(\base,_TS_GPR32),gr32
ldi @(\base,_TS_GPR33),gr33
ldi @(\base,_TS_GPR34),gr34
ldi @(\base,_TS_GPR35),gr35
ldi @(\base,_TS_GPR36),gr36
ldi @(\base,_TS_GPR37),gr37
ldi @(\base,_TS_GPR38),gr38
ldi @(\base,_TS_GPR39),gr39
ldi @(\base,_TS_GPR40),gr40
ldi @(\base,_TS_GPR41),gr41
ldi @(\base,_TS_GPR42),gr42
ldi @(\base,_TS_GPR43),gr43
ldi @(\base,_TS_GPR44),gr44
ldi @(\base,_TS_GPR45),gr45
ldi @(\base,_TS_GPR46),gr46
ldi @(\base,_TS_GPR47),gr47
ldi @(\base,_TS_GPR48),gr48
ldi @(\base,_TS_GPR49),gr49
ldi @(\base,_TS_GPR50),gr50
ldi @(\base,_TS_GPR51),gr51
ldi @(\base,_TS_GPR52),gr52
ldi @(\base,_TS_GPR53),gr53
ldi @(\base,_TS_GPR54),gr54
ldi @(\base,_TS_GPR55),gr55
ldi @(\base,_TS_GPR56),gr56
ldi @(\base,_TS_GPR57),gr57
ldi @(\base,_TS_GPR58),gr58
ldi @(\base,_TS_GPR59),gr59
ldi @(\base,_TS_GPR60),gr60
ldi @(\base,_TS_GPR61),gr61
ldi @(\base,_TS_GPR62),gr62
ldi @(\base,_TS_GPR63),gr63
#endif
ldi @(\base,_TS_SP),gr1 // This has to be last - Stack pointer
rett #\retv
.endm
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
 
.macro exception_VSR
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
subi sp,24,sp
sti gr4,@(sp,0)
#else
subi sp,_TS_size,sp
sti gr4,@(sp,_TS_GPR4)
#endif
addi gr0,#((.-8)-_vectors)/16,gr4
bra _exception
.endm
 
#if defined(CYGPKG_HAL_FRV_FRV400) && defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
.macro break_VSR
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
subi sp,24,sp
sti gr4,@(sp,0)
#else
subi sp,_TS_size,sp
sti gr4,@(sp,_TS_GPR4)
#endif
addi gr0,#((.-8)-_vectors)/16,gr4
bra _break
.endm
#endif // CYGPKG_HAL_FRV_FRV400 && STUBS
 
.macro interrupt_VSR
subi sp,_TS_size,sp
sti gr4,@(sp,_TS_GPR4)
addi gr0,#((.-8)-_vectors)/16,gr4
bra _interrupt
.endm
.section ".rom_vectors","ax"
_vectors:
call reset_vector
nop // I hate fencepost stuff like this....
nop // (NEXT_INDEX_AFTER_THIS - 1) - (PREVIOUS_INDEX_FILLED)
nop // (LAST_INDEX_TO_FILL) - (PREVIOUS_INDEX_FILLED)
.rept (CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1-1)-0
exception_VSR
.endr
.rept (CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15) - (CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1-1)
interrupt_VSR
.endr
.rept (254) - CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15
exception_VSR
.endr
#if defined(CYGPKG_HAL_FRV_FRV400) && defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
break_VSR // in index 255
#else
exception_VSR // another one
#endif // CYGPKG_HAL_FRV_FRV400 && STUBS
//
// Handle a break
//
// just like _exception, but it calls break_handler instead.
//
#if defined(CYGPKG_HAL_FRV_FRV400) && defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
_break:
// Save current register state
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
sti gr5,@(sp,4)
 
// First, check BRR to see whether we're processing a break
// instruction. The stub uses this instruction to enter debug mode.
movsg brr,gr5
andicc gr5,#2,gr0,icc0
beq icc0,#0,1f
 
// It is a break instruction. Clear BRR to acknowledge it.
movgs gr0,brr
 
// Set LR to the address of the instruction after the break.
// Since software breaks are post-execution ones, BPCSR already
// contains the right address.
movsg bpcsr,gr5
movgs gr5,lr
 
// Restore the other registers and return as if the break were a
// call. Don't worry, the user of the break instruction knows
// that LR will be clobbered!
ldi @(sp,0),gr4
ldi @(sp,4),gr5
addi sp,#24,sp
ret
 
1:
// We didn't come here from a break instruction so assume a
// breakpoint or watchpoint has been triggered. Since the
// interrupt and exception handlers save their registers on the
// application stack, there's a chance that these handlers could
// trigger watchpoints accidentally. We should just ignore
// the watchpoint when that happens.
 
// Use the previous value of SPR:ET to decide whether the break
// was triggered by stub or user code. The stub runs with traps
// disabled, while any user code that disables traps will not be
// debuggable.
movsg bpsr,gr5
andicc gr5,#1,gr0,icc0
bne icc0,#2,1f
 
// Hmm, it looks like the GDB stub has triggered an old watchpoint.
// Acknowledge it by clearing brr and return as if nothing had
// happened.
movgs gr0,brr
ldi @(sp,0),gr4
ldi @(sp,4),gr5
addi sp,#24,sp
rett #1
1:
sti gr6,@(sp,8)
sti gr16,@(sp,12)
movsg lr,gr5
sti gr5,@(sp,16)
movsg ccr,gr5
sti gr5,@(sp,20)
// Set the global offset register (gr16)
call .Lbrk
.Lbrk: movsg lr,gr16
sethi #gprelhi(.Lbrk),gr5
setlo #gprello(.Lbrk),gr5
sub gr16,gr5,gr16
mov sp,gr6 // Original stack pointer
lda __GDB_stack,gr5 // already on GDB stack?
cmp sp,gr5,icc0
bhi icc0,0,10f // no - need to switch
lda __GDB_stack_base,gr5
cmp sp,gr5,icc0
bhi icc0,0,11f
10: lda __GDB_stack,sp // already on GDB stack?
11:
subi sp,_TS_size,sp // Space for scratch saves
save_GDB_exception_regs sp,gr6
save_state sp
#else
save_exception_regs sp
save_state sp
#endif
LED 0x0FFF
add sp,gr0,gr8
call break_handler
restore_state sp,bpcsr,1
#endif // CYGPKG_HAL_FRV_FRV400 && STUBS
 
//
// Handle an exception
//
_exception:
// Save current register state
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
sti gr5,@(sp,4)
sti gr6,@(sp,8)
sti gr16,@(sp,12)
movsg lr,gr5
sti gr5,@(sp,16)
movsg ccr,gr5
sti gr5,@(sp,20)
// Set the global offset register (gr16)
call .Lexp
.Lexp: movsg lr,gr16
sethi #gprelhi(.Lexp),gr5
setlo #gprello(.Lexp),gr5
sub gr16,gr5,gr16
mov sp,gr6 // Original stack pointer
lda __GDB_stack,gr5 // already on GDB stack?
cmp sp,gr5,icc0
bhi icc0,0,10f // no - need to switch
lda __GDB_stack_base,gr5
cmp sp,gr5,icc0
bhi icc0,0,11f
10: lda __GDB_stack,sp // already on GDB stack?
11:
subi sp,_TS_size,sp // Space for scratch saves
save_GDB_exception_regs sp,gr6
save_state sp
#else
save_exception_regs sp
save_state sp
#endif
LED 0x0FFF
add sp,gr0,gr8
call exception_handler
bra _exception_return
 
//
// Handle an interrupt
// Separated from exception handling to support eCos multi-level
// (ISR/DSR) interrupt structure.
//
_interrupt:
save_exception_regs sp
save_state sp
 
mov gr4,gr30 // save vector #
// Set the global offset register (gr16)
call .Lexp1
.Lexp1: movsg lr,gr16
sethi #gprelhi(.Lexp1),gr5
setlo #gprello(.Lexp1),gr5
sub gr16,gr5,gr16
LED 0x0700
 
lda hal_vsr_table,gr8
slli gr30,#2,gr4 // Vector in GR30
ld @(gr8,gr4),gr8 // Handler (VSR) defined?
cmpi gr8,0,icc0
beq icc0,0,10f // No - use default
LED 0x0702
callil @(gr8,0) // Yes - call it
bra _exception_return
 
//
// Default interrupt processing
//
10:
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
// If we are supporting Ctrl-C interrupts from GDB, we must squirrel
// away a pointer to the save interrupt state here so that we can
// plant a breakpoint at some later time.
 
.extern hal_saved_interrupt_state
lda hal_saved_interrupt_state,gr5
sti sp,@(gr5,0)
#endif
lda hal_interrupt_data,gr5
lda hal_interrupt_handlers,gr6
mov gr30,gr8 // Interrupt vector #
slli gr30,#2,gr4
ld @(gr5,gr4),gr9 // data pointer
ld @(gr6,gr4),gr6 // function
callil @(gr6,0)
LED 0x0701
// FIXME - no DSR processing
 
//
// Return from an exception/interrupt
//
_exception_return:
LED 0x0000
restore_state sp,pcsr,0
 
.global reset_vector
reset_vector:
 
// Make sure the CPU is in the proper mode (system), interrupts disabled
movsg psr,gr4
li ~(_PSR_ET|_PSR_PS|_PSR_PIVL_MASK),gr5
and gr4,gr5,gr4
li (_PSR_S|_PSR_ET|(0x0F<<_PSR_PIVL_SHIFT)),gr5
or gr4,gr5,gr4
movgs gr4,psr
// Make sure caches, MMUs are disabled
movsg hsr0,gr4
li ~(_HSR0_ICE|_HSR0_DCE|_HSR0_IMMU|_HSR0_DMMU),gr5
and gr4,gr5,gr4
movgs gr4,hsr0
// Initialize hardware platform - this macro only contains
// code which must be run before any "normal" accesses are
// allowed, such as enabling DRAM controllers, etc.
platform_init
#if defined(CYG_HAL_STARTUP_ROMRAM)
// Relocate code from ROM to static RAM
call 10f // Actual address loaded at
5: .long _vectors
.long 20f
.long 5b-_vectors
.long __rom_data_end
10: movsg lr,gr4
ldi @(gr4,0),gr6
ldi @(gr4,4),gr10
ldi @(gr4,8),gr7
ldi @(gr4,12),gr8
sub gr4,gr7,gr4 // GR4 - absolute base address
subi gr4,#4,gr4
subi gr6,#4,gr6
setlos #4,gr7
15: ldu @(gr4,gr7),gr5
stu gr5,@(gr6,gr7)
cmp gr6,gr8,icc0
bne icc0,0,15b
jmpl @(gr10,gr0)
20: nop
#endif
 
// Fall through to normal program startup
#endif // CYG_HAL_STARTUP_ROM
 
.text
.global _start
_start:
// Set the global offset register (gr16)
call .Lcall
.Lcall:
movsg lr,gr4
sethi #gprelhi(.Lcall),gr5
setlo #gprello(.Lcall),gr5
sub gr4,gr5,gr16
 
LED 0x0000
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
// Set up trap base register
lda _vectors,gr4
movgs gr4,tbr
 
LED 0x0001
// Relocate [copy] data from ROM to RAM
lda __rom_data_start,gr4
lda __ram_data_start,gr5
lda __ram_data_end,gr6
cmp gr5,gr6,icc0
beq icc0,0,2f
setlos #4,gr7
sub gr4,gr7,gr4
sub gr5,gr7,gr5
1: ldu @(gr4,gr7),gr8
stu gr8,@(gr5,gr7)
cmp gr5,gr6,icc0
bne icc0,0,1b
2:
#endif
// Set up stack, initial environment
lda __startup_stack,gr4
mov gr4,sp
 
// Enable caches early, based on configuration
#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
icei @(gr4,gr0),1 // purges current contents
movsg hsr0,gr4
li _HSR0_ICE,gr5 // enable instruction cache
or gr4,gr5,gr4
movgs gr4,hsr0
#endif
#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
dcef @(gr4,gr0),1 // flush contents to memory
dcei @(gr4,gr0),1 // purges current contents
movsg hsr0,gr4
li _HSR0_DCE,gr5 // enable data cache
or gr4,gr5,gr4
movgs gr4,hsr0
#endif
LED 0x0002
// Clear BSS space
lda __bss_start,gr4
lda __bss_end,gr5
1: sti gr0,@(gr4,0)
addi gr4,#4,gr4
cmp gr4,gr5,icc0
bne icc0,0,1b
 
// Initialize interrupt handlers, etc
li CYGNUM_HAL_ISR_COUNT,gr4
lda hal_interrupt_handlers,gr5
subi gr5,4,gr5
lda hal_default_isr,gr6
lda hal_vsr_table,gr8
subi gr8,4,gr8
// Note: this should be controlled by a CDL option
lda _handle_interrupt,gr9
setlos #4,gr7
10: stu gr6,@(gr5,gr7)
stu gr9,@(gr8,gr7)
subi gr4,1,gr4
cmp gr4,gr0,icc0
bne icc0,0,10b
 
LED 0x0003
// Initialize hardware
call hal_hardware_init
 
LED 0x0004
// Run any C++ initializations
call cyg_hal_invoke_constructors
 
LED 0x0005
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
call initialize_stub
#endif
 
LED 0x0006
 
// Start eCos application
call cyg_start
 
0: LED 0x0999 // Should never get here
bra 0b
 
//
// Interrupt processing
//
_handle_interrupt:
mov sp,gr31 // Save pointer to state frame
movsg lr,gr29
 
// Set the global offset register (gr16)
call 10f
10: movsg lr,gr4
sethi #gprelhi(10b),gr5
setlo #gprello(10b),gr5
sub gr4,gr5,gr16
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
// Switch to interrupt stack
#endif
// The entire CPU state is now stashed on the stack,
// increment the scheduler lock and handle the interrupt
 
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
.extern cyg_scheduler_sched_lock
lda cyg_scheduler_sched_lock,gr8
ldi @(gr8,0),gr9
addi gr9,1,gr9
sti gr9,@(gr8,0)
#endif
 
#if defined(CYGPKG_KERNEL_INSTRUMENT) && \
defined(CYGDBG_KERNEL_INSTRUMENT_INTR)
setlos #RAISE_INTR,gr8 // arg0 = type = INTR,RAISE
ldi @(gr31,_TS_VECTOR),gr9 // arg1 = vector
mov gr0,gr10 // arg2 = 0
call cyg_instrument // call instrument function
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)
// If we are supporting Ctrl-C interrupts from GDB, we must squirrel
// away a pointer to the save interrupt state here so that we can
// plant a breakpoint at some later time.
 
.extern hal_saved_interrupt_state
lda hal_saved_interrupt_state,gr5
sti sp,@(gr5,0)
#endif
lda hal_interrupt_data,gr5
lda hal_interrupt_handlers,gr7
mov gr30,gr8 // Interrupt vector #
slli gr30,#2,gr4
ld @(gr5,gr4),gr9 // data pointer
ld @(gr7,gr4),gr6 // function
callil @(gr6,0)
LED 0x0701
 
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
// The return value from the handler (in gr8) will indicate whether a
// DSR is to be posted. Pass this together with a pointer to the
// interrupt object we have just used to the interrupt tidy up routine.
 
lda hal_interrupt_objects,gr5
slli gr30,#2,gr4
ld @(gr5,gr4),gr9
mov gr31,gr10 // register frame
 
call interrupt_end // post any bottom layer handler
// threads and call scheduler
#endif
movgs gr29,lr
ret
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
// Execute pending DSRs the interrupt stack
// Note: this can only be called from code running on a thread stack
.globl hal_interrupt_stack_call_pending_DSRs
hal_interrupt_stack_call_pending_DSRs:
subi sp,32,sp // Save important registers
movsg lr,gr8
sti gr8,@(sp,0)
// Turn on interrupts, switch to interrupt stack
call cyg_interrupt_call_pending_DSRs
// Turn off interrupts, switch back to thread stack
ldi @(sp,0),gr8
movgs gr8,lr
addi sp,32,sp
ret
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
 
//
// Restore interrupt state
// GR8 has state
//
.global hal_restore_interrupts
hal_restore_interrupts:
movsg psr,gr4
setlos _PSR_PIVL_MASK,gr5
and gr8,gr5,gr8 // Save level being restored
not gr5,gr5
and gr4,gr5,gr4 // Clear out current level
or gr8,gr4,gr4 // Insert new level
movgs gr4,psr
ret
.global hal_query_interrupts
hal_query_interrupts:
movsg psr,gr8
setlos _PSR_PIVL_MASK,gr5
and gr8,gr5,gr8
ret
//
// "Vectors" - fixed location data items
// This section contains any data which might be shared between
// an eCos application and any other environment, e.g. the debug
// ROM.
//
.section ".fixed_vectors"
 
// Space for the virtual vectors
.balign 16
// Vectors used to communicate between eCos and ROM environments
.globl hal_virtual_vector_table
hal_virtual_vector_table:
.rept CYGNUM_CALL_IF_TABLE_SIZE
.long 0
.endr
 
.globl hal_vsr_table
hal_vsr_table:
.rept CYGNUM_HAL_ISR_COUNT // exceptions & interrupts
.long 0
.endr
 
.section ".data"
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
.balign 16
__GDB_stack_base:
.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE // rather than 1k
.byte 0
.endr
__GDB_stack:
#endif
.balign 16
__startup_stack_base:
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
.rept 512
#else
.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
#endif
.byte 0
.endr
.balign 16
.global __startup_stack
__startup_stack:
 
.globl hal_interrupt_handlers
hal_interrupt_handlers:
.rept CYGNUM_HAL_ISR_COUNT
.long 0
.endr
 
.globl hal_interrupt_data
hal_interrupt_data:
.rept CYGNUM_HAL_ISR_COUNT
.long 0
.endr
 
.globl hal_interrupt_objects
hal_interrupt_objects:
.rept CYGNUM_HAL_ISR_COUNT
.long 0
.endr
/arch/v2_0/src/frv.ld
0,0 → 1,158
//=============================================================================
//
// MLT linker script for Fujitsu (FR-V)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
#include <pkgconf/system.h>
 
STARTUP(vectors.o)
ENTRY(_start)
#ifdef EXTRAS
INPUT(extras.o)
#endif
#if (__GNUC__ >= 3)
GROUP(libtarget.a libgcc.a libsupc++.a)
#else
GROUP(libtarget.a libgcc.a)
#endif
 
#define ALIGN_LMA 8
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
#define LMA_EQ_VMA
#define FORCE_OUTPUT . = .
 
#define SECTIONS_BEGIN \
/* Debug information */ \
.debug_aranges 0 : { *(.debug_aranges) } \
.debug_pubnames 0 : { *(.debug_pubnames) } \
.debug_info 0 : { *(.debug_info) } \
.debug_abbrev 0 : { *(.debug_abbrev) } \
.debug_line 0 : { *(.debug_line) } \
.debug_frame 0 : { *(.debug_frame) } \
.debug_str 0 : { *(.debug_str) } \
.debug_loc 0 : { *(.debug_loc) } \
.debug_macinfo 0 : { *(.debug_macinfo) }
 
#define SECTION_fixed_vectors(_region_, _vma_, _lma_) \
.fixed_vectors _vma_ : _lma_ \
{ FORCE_OUTPUT; KEEP (*(.fixed_vectors)) } \
> _region_
 
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ FORCE_OUTPUT; KEEP (*(.rom_vectors)) } \
> _region_
 
#define SECTION_text(_region_, _vma_, _lma_) \
.text _vma_ : _lma_ \
{ _stext = ABSOLUTE(.); \
PROVIDE (__stext = ABSOLUTE(.)); \
*(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) \
*(.glue_7) *(.glue_7t) \
} > _region_ \
_etext = .; PROVIDE (__etext = .);
 
#define SECTION_fini(_region_, _vma_, _lma_) \
.fini _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.fini) } \
> _region_
 
#define SECTION_rodata(_region_, _vma_, _lma_) \
.rodata _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata*) } \
> _region_
 
#define SECTION_rodata1(_region_, _vma_, _lma_) \
.rodata1 _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata1) } \
> _region_
 
#define SECTION_fixup(_region_, _vma_, _lma_) \
.fixup _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.fixup) } \
> _region_
 
#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
.gcc_except_table _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.gcc_except_table) } \
> _region_
 
#define SECTION_mmu_tables(_region_, _vma_, _lma_) \
.mmu_tables _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.mmu_tables) } \
> _region_
 
#define SECTION_sram(_region_, _vma_, _lma_) \
.sram _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.sram*) } \
> _region_
 
#define SECTION_data(_region_, _vma_, _lma_) \
.data _vma_ : _lma_ \
{ __ram_data_start = ABSOLUTE (.); *(.data*) *(.data1) \
. = ALIGN (8); \
KEEP(*( SORT (.ecos.table.*))) ; \
. = ALIGN (8); \
__CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.ctors*))) __CTOR_END__ = ABSOLUTE (.); \
__DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.dtors*))) __DTOR_END__ = ABSOLUTE (.); \
*(.sdata*) \
*(.eh_frame) \
. = ALIGN (8); *(.2ram.*) \
/* Global pointer stuff */ \
. = ALIGN(8); _gp = . + 2048; __global = _gp; \
_GOT_START_ = ABSOLUTE (.); *(.got) _GOT_END_ = ABSOLUTE (.); \
_GOT_PLT_START_ = ABSOLUTE (.); *(.got_plt) _GOT_PLT_END_ = ABSOLUTE (.); \
_GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \
_GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \
_DYNAMIC_ = ABSOLUTE (.); *(.dynamic) _DYNAMIC_ = ABSOLUTE (.); \
} \
> _region_ \
__rom_data_start = LOADADDR (.data); \
__ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); \
__rom_data_end = LOADADDR (.data) + SIZEOF(.data);
 
#define SECTION_bss(_region_, _vma_, _lma_) \
.bss _vma_ : _lma_ \
{ __bss_start = ABSOLUTE (.); \
*(.scommon) *(.dynbss) *(.sbss) *(.sbss.*) *(.bss*) *(.bss.*) *(COMMON) \
__bss_end = ABSOLUTE (.); } \
> _region_
 
#define SECTIONS_END . = ALIGN(8); _end = .; PROVIDE (end = .);
 
#include <pkgconf/hal_frv.h>
#include CYGHWR_MEMORY_LAYOUT_LDI
/arch/v2_0/src/frv_stub.c
0,0 → 1,382
//========================================================================
//
// frv_stub.c
//
// Helper functions for stub, generic to all FUJITSU processors
//
//========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Red Hat, gthomas
// Contributors: Red Hat, gthomas, jskov, msalter
// Date: 2001-09-16
// Purpose:
// Description: Helper functions for stub, generic to all FUJITSU processors
// Usage:
//
//####DESCRIPTIONEND####
//
//========================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_REDBOOT
#include <pkgconf/redboot.h>
#endif
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/hal/hal_stub.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_cache.h>
 
#ifndef FALSE
#define FALSE 0
#define TRUE 1
#endif
 
#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
#include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id
#endif
 
#if defined(CYGNUM_HAL_BREAKPOINT_LIST_SIZE) && (CYGNUM_HAL_BREAKPOINT_LIST_SIZE > 0)
cyg_uint32 __frv_breakinst = HAL_BREAKINST;
#endif
 
// Sadly, this doesn't seem to work on the FRV400 either
//#define USE_HW_STEP
 
#ifdef CYGSEM_HAL_FRV_HW_DEBUG
static inline unsigned __get_dcr(void)
{
unsigned retval;
 
asm volatile (
"movsg dcr,%0\n"
: "=r" (retval)
: /* no inputs */ );
 
return retval;
}
 
static inline void __set_dcr(unsigned val)
{
asm volatile (
"movgs %0,dcr\n"
: /* no outputs */
: "r" (val) );
}
 
#endif
 
/* Given a trap value TRAP, return the corresponding signal. */
 
int __computeSignal (unsigned int trap_number)
{
// should also catch CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION here but we
// can't tell the different between a real one and a breakpoint :-(
switch (trap_number) {
// Interrupts
case CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1 ... CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15:
return SIGINT;
case CYGNUM_HAL_VECTOR_INSTR_ACCESS_MMU_MISS:
case CYGNUM_HAL_VECTOR_INSTR_ACCESS_ERROR:
case CYGNUM_HAL_VECTOR_INSTR_ACCESS_EXCEPTION:
case CYGNUM_HAL_VECTOR_MEMORY_ADDRESS_NOT_ALIGNED:
case CYGNUM_HAL_VECTOR_DATA_ACCESS_ERROR:
case CYGNUM_HAL_VECTOR_DATA_ACCESS_MMU_MISS:
case CYGNUM_HAL_VECTOR_DATA_ACCESS_EXCEPTION:
case CYGNUM_HAL_VECTOR_DATA_STORE_ERROR:
return SIGBUS;
case CYGNUM_HAL_VECTOR_PRIVELEDGED_INSTRUCTION:
case CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION:
case CYGNUM_HAL_VECTOR_REGISTER_EXCEPTION:
case CYGNUM_HAL_VECTOR_FP_DISABLED:
case CYGNUM_HAL_VECTOR_MP_DISABLED:
case CYGNUM_HAL_VECTOR_FP_EXCEPTION:
case CYGNUM_HAL_VECTOR_MP_EXCEPTION:
case CYGNUM_HAL_VECTOR_DIVISION_EXCEPTION:
case CYGNUM_HAL_VECTOR_COMMIT_EXCEPTION:
case CYGNUM_HAL_VECTOR_COMPOUND_EXCEPTION:
return SIGILL;
default:
return SIGTRAP;
}
}
 
 
/* Return the trap number corresponding to the last-taken trap. */
int __get_trap_number (void)
{
// The vector is not not part of the GDB register set so get it
// directly from the save context.
return _hal_registers->vector;
}
 
 
#if defined(CYGSEM_REDBOOT_BSP_SYSCALLS)
int __is_bsp_syscall(void)
{
// Might want to be more specific here
return (_hal_registers->vector == CYGNUM_HAL_VECTOR_SYSCALL);
}
#endif // defined(CYGSEM_REDBOOT_BSP_SYSCALLS)
 
/* Set the currently-saved pc register value to PC. */
 
void set_pc (target_register_t pc)
{
put_register (PC, pc);
}
 
 
/*----------------------------------------------------------------------
* Single-step support
*/
 
/* Set things up so that the next user resume will execute one instruction.
This may be done by setting breakpoints or setting a single step flag
in the saved user registers, for example. */
 
#ifndef CYGSEM_HAL_FRV_HW_DEBUG
#if CYGINT_HAL_FRV_ARCH_FR400 == 1
#define VLIW_DEPTH 2
#endif
#if CYGINT_HAL_FRV_ARCH_FR500 == 1
#define VLIW_DEPTH 4
#endif
/*
* Structure to hold opcodes hoisted when breakpoints are
* set for single-stepping or async interruption.
*/
struct _bp_save {
unsigned long *addr;
unsigned long opcode;
};
 
/*
* We single-step by setting breakpoints.
*
* This is where we save the original instructions.
*/
static struct _bp_save step_bp[VLIW_DEPTH+1];
 
//**************************************************************
//************ CAUTION!! ***************************************
//**************************************************************
//
// Attempt to analyze the current instruction. This code is not
// perfect in the case of VLIW sequences, although it's close.
// Consider these sequences:
//
// ldi.p @(gr5,0),gr4
// jmpl @(gr4,gr0)
// and
//
// ldi.p @(gr5,0),gr4
// add.p gr6,gr7,gr8
// jmpl @(gr4,gr0)
//
// In these cases, the only way to effectively calculate the
// target address (of the jump) would be to simulate the actions
// of the pipelined instructions which come beforehand.
//
// Of course, this only affects single stepping through a VLIW
// sequence which contains such pipelined effects and a branch.
// Hopefully this is rare.
//
// Note: testing of the above sequence on the FR400 yielded an
// illegal instruction (invalid VLIW sequence), so this may not
// turn out to be a problem in practice, just theory.
//
//**************************************************************
//**************************************************************
 
static int
_analyze_instr(unsigned long pc, unsigned long *targ,
unsigned long *next, int *is_vliw)
{
unsigned long opcode;
int n, is_branch = 0;
 
opcode = *(unsigned long *)pc;
switch ((opcode >> 18) & 0x7f) {
case 6:
case 7:
/* bcc, fbcc */
is_branch = 1;
n = (int)(opcode << 16);
n >>= 16;
*targ = pc + n*4;
pc += 4;
break;
case 12:
/* jmpl */
n = (int)(get_register((opcode>>12)&63));
n += (int)(get_register(opcode&63));
pc = n;
break;
case 13:
/* jmpil */
n = (int)(get_register((opcode>>12)&63));
n += (((int)(opcode << 20)) >> 20);
pc = n;
break;
case 15:
/* call */
n = (opcode >> 25) << 18;
n |= (opcode & 0x3ffff);
n <<= 8;
n >>= 8;
pc += n*4;
break;
case 14:
/* ret */
is_branch = 1;
*targ = get_register(LR);
pc += 4;
break;
default:
pc += 4;
break;
}
*next = pc;
*is_vliw = (opcode & 0x80000000) == 0;
return is_branch;
}
#endif
 
void __single_step (void)
{
#ifdef CYGSEM_HAL_FRV_HW_DEBUG
__set_dcr(__get_dcr() | _DCR_SE);
diag_printf("Setting single step - DCR: %x\n", __get_dcr());
#else
unsigned long pc, targ, next_pc;
int i, is_branch = 0;
int is_vliw;
 
for (i = 0; i < VLIW_DEPTH+1; i++) {
step_bp[i].addr = NULL;
}
 
pc = get_register(PC);
i = 1;
while (i < (VLIW_DEPTH+1)) {
is_branch = _analyze_instr(pc, &targ, &next_pc, &is_vliw);
if (is_branch && next_pc != targ) {
step_bp[i].addr = (unsigned long *)targ;
step_bp[i].opcode = *(unsigned long *)targ;
*(unsigned long *)targ = HAL_BREAKINST;
HAL_DCACHE_STORE(targ, 4);
HAL_ICACHE_INVALIDATE(targ, 4);
}
if (is_vliw) {
pc += 4;
i++;
} else {
break;
}
}
step_bp[0].addr = (unsigned long *)next_pc;
step_bp[0].opcode = *(unsigned long *)next_pc;
*(unsigned long *)next_pc = HAL_BREAKINST;
HAL_DCACHE_STORE(next_pc, 4);
HAL_ICACHE_INVALIDATE(next_pc, 4);
#endif
}
 
/* Clear the single-step state. */
 
void __clear_single_step (void)
{
#ifdef CYGSEM_HAL_FRV_HW_DEBUG
__set_dcr(__get_dcr() & ~_DCR_SE);
#else
struct _bp_save *p;
int i;
 
for (i = 0; i < VLIW_DEPTH+1; i++) {
p = &step_bp[i];
if (p->addr) {
*(p->addr) = p->opcode;
HAL_DCACHE_STORE((cyg_uint32)p->addr, 4);
HAL_ICACHE_INVALIDATE((cyg_uint32)p->addr, 4);
p->addr = NULL;
}
}
#endif
}
 
void __install_breakpoints (void)
{
#if defined(CYGNUM_HAL_BREAKPOINT_LIST_SIZE) && (CYGNUM_HAL_BREAKPOINT_LIST_SIZE > 0)
/* Install the breakpoints in the breakpoint list */
__install_breakpoint_list();
#endif
}
 
void __clear_breakpoints (void)
{
#if defined(CYGNUM_HAL_BREAKPOINT_LIST_SIZE) && (CYGNUM_HAL_BREAKPOINT_LIST_SIZE > 0)
__clear_breakpoint_list();
#endif
}
 
/* If the breakpoint we hit is in the breakpoint() instruction, return a
non-zero value. */
 
int
__is_breakpoint_function ()
{
return get_register (PC) == (target_register_t)&_breakinst;
}
 
 
/* Skip the current instruction. Since this is only called by the
stub when the PC points to a breakpoint or trap instruction,
we can safely just skip 4. */
 
void __skipinst (void)
{
unsigned long pc = get_register(PC);
 
pc += 4;
put_register(PC, pc);
}
 
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
/arch/v2_0/src/hal_mk_defs.c
0,0 → 1,193
/*==========================================================================
//
// hal_mk_defs.c
//
// HAL (architecture) "make defs" program
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas
// Date: 2001-09-07
// Purpose: FUJISTU architecture dependent definition generator
// Description: This file contains code that can be compiled by the target
// compiler and used to generate machine specific definitions
// suitable for use in assembly code.
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // HAL header
#include <cyg/hal/hal_intr.h> // HAL header
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
# include <cyg/kernel/instrmnt.h>
#endif
#include <cyg/hal/hal_if.h>
 
/*
* This program is used to generate definitions needed by
* assembly language modules.
*
* This technique was first used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*/
 
#define DEFINE(sym, val) \
asm volatile("\n.equ\t" #sym " %0" : : "i" (val))
 
int
main(void)
{
#ifdef CYGPKG_KERNEL
DEFINE(RAISE_INTR, CYG_INSTRUMENT_CLASS_INTR|CYG_INSTRUMENT_EVENT_INTR_RAISE);
#endif
#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT)
DEFINE(CYGNUM_CALL_IF_TABLE_SIZE, CYGNUM_CALL_IF_TABLE_SIZE);
#endif
DEFINE(CYGNUM_HAL_INTERRUPT_NONE, CYGNUM_HAL_INTERRUPT_NONE);
DEFINE(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE, CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE);
DEFINE(CYGNUM_HAL_ISR_COUNT, CYGNUM_HAL_ISR_COUNT);
DEFINE(CYGNUM_HAL_VECTOR_SYSCALL, CYGNUM_HAL_VECTOR_SYSCALL);
DEFINE(CYGNUM_HAL_VECTOR_BREAKPOINT, CYGNUM_HAL_VECTOR_BREAKPOINT);
DEFINE(CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1, CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1);
DEFINE(CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15, CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_15);
 
// Register state
DEFINE(_TS_GPR0, offsetof(HAL_SavedRegisters, gpr[0]));
DEFINE(_TS_GPR1, offsetof(HAL_SavedRegisters, gpr[1]));
DEFINE(_TS_SP, offsetof(HAL_SavedRegisters, gpr[1]));
DEFINE(_TS_GPR2, offsetof(HAL_SavedRegisters, gpr[2]));
DEFINE(_TS_GPR3, offsetof(HAL_SavedRegisters, gpr[3]));
DEFINE(_TS_GPR4, offsetof(HAL_SavedRegisters, gpr[4]));
DEFINE(_TS_GPR5, offsetof(HAL_SavedRegisters, gpr[5]));
DEFINE(_TS_GPR6, offsetof(HAL_SavedRegisters, gpr[6]));
DEFINE(_TS_GPR7, offsetof(HAL_SavedRegisters, gpr[7]));
DEFINE(_TS_GPR8, offsetof(HAL_SavedRegisters, gpr[8]));
DEFINE(_TS_GPR9, offsetof(HAL_SavedRegisters, gpr[9]));
DEFINE(_TS_GPR10, offsetof(HAL_SavedRegisters, gpr[10]));
DEFINE(_TS_GPR11, offsetof(HAL_SavedRegisters, gpr[11]));
DEFINE(_TS_GPR12, offsetof(HAL_SavedRegisters, gpr[12]));
DEFINE(_TS_GPR13, offsetof(HAL_SavedRegisters, gpr[13]));
DEFINE(_TS_GPR14, offsetof(HAL_SavedRegisters, gpr[14]));
DEFINE(_TS_GPR15, offsetof(HAL_SavedRegisters, gpr[15]));
DEFINE(_TS_GPR16, offsetof(HAL_SavedRegisters, gpr[16]));
DEFINE(_TS_GPR17, offsetof(HAL_SavedRegisters, gpr[17]));
DEFINE(_TS_GPR18, offsetof(HAL_SavedRegisters, gpr[18]));
DEFINE(_TS_GPR19, offsetof(HAL_SavedRegisters, gpr[19]));
DEFINE(_TS_GPR20, offsetof(HAL_SavedRegisters, gpr[20]));
DEFINE(_TS_GPR21, offsetof(HAL_SavedRegisters, gpr[21]));
DEFINE(_TS_GPR22, offsetof(HAL_SavedRegisters, gpr[22]));
DEFINE(_TS_GPR23, offsetof(HAL_SavedRegisters, gpr[23]));
DEFINE(_TS_GPR24, offsetof(HAL_SavedRegisters, gpr[24]));
DEFINE(_TS_GPR25, offsetof(HAL_SavedRegisters, gpr[25]));
DEFINE(_TS_GPR26, offsetof(HAL_SavedRegisters, gpr[26]));
DEFINE(_TS_GPR27, offsetof(HAL_SavedRegisters, gpr[27]));
DEFINE(_TS_GPR28, offsetof(HAL_SavedRegisters, gpr[28]));
DEFINE(_TS_GPR29, offsetof(HAL_SavedRegisters, gpr[29]));
DEFINE(_TS_GPR30, offsetof(HAL_SavedRegisters, gpr[30]));
DEFINE(_TS_GPR31, offsetof(HAL_SavedRegisters, gpr[31]));
#if _NGPR != 32
DEFINE(_TS_GPR32, offsetof(HAL_SavedRegisters, gpr[32]));
DEFINE(_TS_GPR33, offsetof(HAL_SavedRegisters, gpr[33]));
DEFINE(_TS_GPR34, offsetof(HAL_SavedRegisters, gpr[34]));
DEFINE(_TS_GPR35, offsetof(HAL_SavedRegisters, gpr[35]));
DEFINE(_TS_GPR36, offsetof(HAL_SavedRegisters, gpr[36]));
DEFINE(_TS_GPR37, offsetof(HAL_SavedRegisters, gpr[37]));
DEFINE(_TS_GPR38, offsetof(HAL_SavedRegisters, gpr[38]));
DEFINE(_TS_GPR39, offsetof(HAL_SavedRegisters, gpr[39]));
DEFINE(_TS_GPR40, offsetof(HAL_SavedRegisters, gpr[40]));
DEFINE(_TS_GPR41, offsetof(HAL_SavedRegisters, gpr[41]));
DEFINE(_TS_GPR42, offsetof(HAL_SavedRegisters, gpr[42]));
DEFINE(_TS_GPR43, offsetof(HAL_SavedRegisters, gpr[43]));
DEFINE(_TS_GPR44, offsetof(HAL_SavedRegisters, gpr[44]));
DEFINE(_TS_GPR45, offsetof(HAL_SavedRegisters, gpr[45]));
DEFINE(_TS_GPR46, offsetof(HAL_SavedRegisters, gpr[46]));
DEFINE(_TS_GPR47, offsetof(HAL_SavedRegisters, gpr[47]));
DEFINE(_TS_GPR48, offsetof(HAL_SavedRegisters, gpr[48]));
DEFINE(_TS_GPR49, offsetof(HAL_SavedRegisters, gpr[49]));
DEFINE(_TS_GPR50, offsetof(HAL_SavedRegisters, gpr[50]));
DEFINE(_TS_GPR51, offsetof(HAL_SavedRegisters, gpr[51]));
DEFINE(_TS_GPR52, offsetof(HAL_SavedRegisters, gpr[52]));
DEFINE(_TS_GPR53, offsetof(HAL_SavedRegisters, gpr[53]));
DEFINE(_TS_GPR54, offsetof(HAL_SavedRegisters, gpr[54]));
DEFINE(_TS_GPR55, offsetof(HAL_SavedRegisters, gpr[55]));
DEFINE(_TS_GPR56, offsetof(HAL_SavedRegisters, gpr[56]));
DEFINE(_TS_GPR57, offsetof(HAL_SavedRegisters, gpr[57]));
DEFINE(_TS_GPR58, offsetof(HAL_SavedRegisters, gpr[58]));
DEFINE(_TS_GPR59, offsetof(HAL_SavedRegisters, gpr[59]));
DEFINE(_TS_GPR60, offsetof(HAL_SavedRegisters, gpr[60]));
DEFINE(_TS_GPR61, offsetof(HAL_SavedRegisters, gpr[61]));
DEFINE(_TS_GPR62, offsetof(HAL_SavedRegisters, gpr[62]));
DEFINE(_TS_GPR63, offsetof(HAL_SavedRegisters, gpr[63]));
#endif
DEFINE(_TS_PC, offsetof(HAL_SavedRegisters, pc));
DEFINE(_TS_PSR, offsetof(HAL_SavedRegisters, psr));
DEFINE(_TS_LR, offsetof(HAL_SavedRegisters, lr));
DEFINE(_TS_CCR, offsetof(HAL_SavedRegisters, ccr));
DEFINE(_TS_LCR, offsetof(HAL_SavedRegisters, lcr));
DEFINE(_TS_CCCR, offsetof(HAL_SavedRegisters, cccr));
DEFINE(_TS_LR, offsetof(HAL_SavedRegisters, lr));
DEFINE(_TS_VECTOR, offsetof(HAL_SavedRegisters, vector));
#define _roundup(n,s) ((((n)+(s-1))/s)*s)
DEFINE(_TS_size, _roundup(sizeof(HAL_SavedRegisters),8));
 
DEFINE(_NGPR, _NGPR);
DEFINE(_NFPR, _NFPR);
 
DEFINE(_PSR_ET, _PSR_ET);
DEFINE(_PSR_S, _PSR_S);
DEFINE(_PSR_PS, _PSR_PS);
DEFINE(_PSR_PIVL_MASK, _PSR_PIVL_MASK);
DEFINE(_PSR_PIVL_SHIFT, _PSR_PIVL_SHIFT);
 
DEFINE(_HSR0_ICE, _HSR0_ICE);
DEFINE(_HSR0_DCE, _HSR0_DCE);
DEFINE(_HSR0_IMMU, _HSR0_IMMU);
DEFINE(_HSR0_DMMU, _HSR0_DMMU);
 
return 0;
}
 
 
/*------------------------------------------------------------------------*/
// EOF hal_mk_defs.c

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