URL
https://opencores.org/ocsvn/pci32tlite_oc/pci32tlite_oc/trunk
Subversion Repositories pci32tlite_oc
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- This comparison shows the changes necessary to convert path
/pci32tlite_oc
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/doc/pci32tLite_oc_um_dm.odt
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Index: trunk/doc/pci32tLite_oc_um_dm.pdf
===================================================================
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Index: trunk/doc/pci32tLite_oc_um_dm.pdf
===================================================================
--- trunk/doc/pci32tLite_oc_um_dm.pdf (nonexistent)
+++ trunk/doc/pci32tLite_oc_um_dm.pdf (revision 10)
trunk/doc/pci32tLite_oc_um_dm.pdf
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Index: trunk/history.txt
===================================================================
--- trunk/history.txt (nonexistent)
+++ trunk/history.txt (revision 10)
@@ -0,0 +1,10 @@
+pci32tlite_oc IP core revision history.
+
+Project: pci32tlite_oc
+Description: IP PCI Target 32 Bits (WB compatible)
+
+v3.1 2022-01-19 Peio Azkarate
+ - Remove previous versions history.
+ - Remove maxii_uart project (released as a separate project).
+ - Add pci32tlite_oc.ipfpga file.
+ - Add pci32tLite_oc_oc_um_dm.odt and update pci32tLite_oc_oc_um_dm.pdf.
Index: trunk/lgpl-3.0.txt
===================================================================
--- trunk/lgpl-3.0.txt (nonexistent)
+++ trunk/lgpl-3.0.txt (revision 10)
@@ -0,0 +1,165 @@
+ GNU LESSER GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+
+ This version of the GNU Lesser General Public License incorporates
+the terms and conditions of version 3 of the GNU General Public
+License, supplemented by the additional permissions listed below.
+
+ 0. Additional Definitions.
+
+ As used herein, "this License" refers to version 3 of the GNU Lesser
+General Public License, and the "GNU GPL" refers to version 3 of the GNU
+General Public License.
+
+ "The Library" refers to a covered work governed by this License,
+other than an Application or a Combined Work as defined below.
+
+ An "Application" is any work that makes use of an interface provided
+by the Library, but which is not otherwise based on the Library.
+Defining a subclass of a class defined by the Library is deemed a mode
+of using an interface provided by the Library.
+
+ A "Combined Work" is a work produced by combining or linking an
+Application with the Library. The particular version of the Library
+with which the Combined Work was made is also called the "Linked
+Version".
+
+ The "Minimal Corresponding Source" for a Combined Work means the
+Corresponding Source for the Combined Work, excluding any source code
+for portions of the Combined Work that, considered in isolation, are
+based on the Application, and not on the Linked Version.
+
+ The "Corresponding Application Code" for a Combined Work means the
+object code and/or source code for the Application, including any data
+and utility programs needed for reproducing the Combined Work from the
+Application, but excluding the System Libraries of the Combined Work.
+
+ 1. Exception to Section 3 of the GNU GPL.
+
+ You may convey a covered work under sections 3 and 4 of this License
+without being bound by section 3 of the GNU GPL.
+
+ 2. Conveying Modified Versions.
+
+ If you modify a copy of the Library, and, in your modifications, a
+facility refers to a function or data to be supplied by an Application
+that uses the facility (other than as an argument passed when the
+facility is invoked), then you may convey a copy of the modified
+version:
+
+ a) under this License, provided that you make a good faith effort to
+ ensure that, in the event an Application does not supply the
+ function or data, the facility still operates, and performs
+ whatever part of its purpose remains meaningful, or
+
+ b) under the GNU GPL, with none of the additional permissions of
+ this License applicable to that copy.
+
+ 3. Object Code Incorporating Material from Library Header Files.
+
+ The object code form of an Application may incorporate material from
+a header file that is part of the Library. You may convey such object
+code under terms of your choice, provided that, if the incorporated
+material is not limited to numerical parameters, data structure
+layouts and accessors, or small macros, inline functions and templates
+(ten or fewer lines in length), you do both of the following:
+
+ a) Give prominent notice with each copy of the object code that the
+ Library is used in it and that the Library and its use are
+ covered by this License.
+
+ b) Accompany the object code with a copy of the GNU GPL and this license
+ document.
+
+ 4. Combined Works.
+
+ You may convey a Combined Work under terms of your choice that,
+taken together, effectively do not restrict modification of the
+portions of the Library contained in the Combined Work and reverse
+engineering for debugging such modifications, if you also do each of
+the following:
+
+ a) Give prominent notice with each copy of the Combined Work that
+ the Library is used in it and that the Library and its use are
+ covered by this License.
+
+ b) Accompany the Combined Work with a copy of the GNU GPL and this license
+ document.
+
+ c) For a Combined Work that displays copyright notices during
+ execution, include the copyright notice for the Library among
+ these notices, as well as a reference directing the user to the
+ copies of the GNU GPL and this license document.
+
+ d) Do one of the following:
+
+ 0) Convey the Minimal Corresponding Source under the terms of this
+ License, and the Corresponding Application Code in a form
+ suitable for, and under terms that permit, the user to
+ recombine or relink the Application with a modified version of
+ the Linked Version to produce a modified Combined Work, in the
+ manner specified by section 6 of the GNU GPL for conveying
+ Corresponding Source.
+
+ 1) Use a suitable shared library mechanism for linking with the
+ Library. A suitable mechanism is one that (a) uses at run time
+ a copy of the Library already present on the user's computer
+ system, and (b) will operate properly with a modified version
+ of the Library that is interface-compatible with the Linked
+ Version.
+
+ e) Provide Installation Information, but only if you would otherwise
+ be required to provide such information under section 6 of the
+ GNU GPL, and only to the extent that such information is
+ necessary to install and execute a modified version of the
+ Combined Work produced by recombining or relinking the
+ Application with a modified version of the Linked Version. (If
+ you use option 4d0, the Installation Information must accompany
+ the Minimal Corresponding Source and Corresponding Application
+ Code. If you use option 4d1, you must provide the Installation
+ Information in the manner specified by section 6 of the GNU GPL
+ for conveying Corresponding Source.)
+
+ 5. Combined Libraries.
+
+ You may place library facilities that are a work based on the
+Library side by side in a single library together with other library
+facilities that are not Applications and are not covered by this
+License, and convey such a combined library under terms of your
+choice, if you do both of the following:
+
+ a) Accompany the combined library with a copy of the same work based
+ on the Library, uncombined with any other library facilities,
+ conveyed under the terms of this License.
+
+ b) Give prominent notice with the combined library that part of it
+ is a work based on the Library, and explaining where to find the
+ accompanying uncombined form of the same work.
+
+ 6. Revised Versions of the GNU Lesser General Public License.
+
+ The Free Software Foundation may publish revised and/or new versions
+of the GNU Lesser General Public License from time to time. Such new
+versions will be similar in spirit to the present version, but may
+differ in detail to address new problems or concerns.
+
+ Each version is given a distinguishing version number. If the
+Library as you received it specifies that a certain numbered version
+of the GNU Lesser General Public License "or any later version"
+applies to it, you have the option of following the terms and
+conditions either of that published version or of any later version
+published by the Free Software Foundation. If the Library as you
+received it does not specify a version number of the GNU Lesser
+General Public License, you may choose any version of the GNU Lesser
+General Public License ever published by the Free Software Foundation.
+
+ If the Library as you received it specifies that a proxy can decide
+whether future versions of the GNU Lesser General Public License shall
+apply, that proxy's public statement of acceptance of any version is
+permanent authorization for you to choose that version for the
+Library.
Index: trunk/pci32tlite_oc.ipfpga
===================================================================
--- trunk/pci32tlite_oc.ipfpga (nonexistent)
+++ trunk/pci32tlite_oc.ipfpga (revision 10)
@@ -0,0 +1,47 @@
+# Project: pci32tlite_oc
+# Description: Compilation resource file.
+
+[PROJECT]
+pci32tlite_oc
+[END]
+
+[IP_LIST]
+[END]
+
+[IP_SIM_LIST]
+[END]
+
+[PROJECT_LIBRARY]
+onalib
+[END]
+
+[PROJECT_SOURCES]
+rtl/onalib.vhd onalib
+rtl/pcidec.vhd
+rtl/pciwbsequ.vhd
+rtl/pciregs.vhd
+rtl/pcidmux.vhd
+rtl/pcipargen.vhd
+rtl/pci32tlite.vhd
+[END]
+
+[TB_SOURCES]
+[END]
+
+[MODELSIM]
+vhdl_options -2008 -explicit
+[END]
+
+[MSIM]
+[END]
+
+[GHDL]
+# --std=08 --std=93c
+ghdl_options --ieee=standard --std=08 --warn-no-attribute --warn-no-shared --warn-no-hide -fexplicit -fsynopsys \
+-frelaxed -frelaxed-rules --no-vital-checks --warn-binding --mb-comments --warn-no-pure
+[END]
+
+[DIR_STRUCT]
+# Set directories relative to project directory
+sim_dir sim/
+[END]
Index: trunk/rtl/onalib.vhd
===================================================================
--- trunk/rtl/onalib.vhd (nonexistent)
+++ trunk/rtl/onalib.vhd (revision 10)
@@ -0,0 +1,599 @@
+--+-------------------------------------------------------------------------------------------------+
+--| |
+--| Fileo: onalib.vhd |
+--| |
+--| Project: onalib |
+--| |
+--| Description: Libreria de componentes en VHDL. |
+--| |
+--+-------------------------------------------------------------------------------------------------+
+--| Component | Descripcion |
+--+-------------------------------------------------------------------------------------------------+
+--| sync(clk, d, q) | Sincronizacion de una señal a traves de un FF. |
+--| | Sin reset. |
+--+-------------------------------------------------------------------------------------------------+
+--| sync2(clk, d, q) | Doble Sincronizacion de una señal a traves de dos |
+--| | FF. Sin reset. |
+--+-------------------------------------------------------------------------------------------------+
+--| sync2h(clk, rst, d, q) | Doble Sincronizacion de una señal a traves de dos |
+--| | FF. Con reset e inicializacion a '1'. |
+--+-------------------------------------------------------------------------------------------------+
+--| sync2l(clk, rst, d, q) | Doble Sincronizacion de una señal a traves de dos |
+--| | FF. Con reset e inicializacion a '0'. |
+--+-------------------------------------------------------------------------------------------------+
+--| syncrsld(clk, rst, ld, d, q) | Sincronizacion de una señal a traves de un FF |
+--| | con reset y load. |
+--+-------------------------------------------------------------------------------------------------+
+--| syncv(size)(clock, d, q) | Sincronizacion de un vector (generic) |
+--| | con reset y load. |
+--+-------------------------------------------------------------------------------------------------+
+--| decoder3to8(i, o) | Decoder 3 to 8 |
+--+-------------------------------------------------------------------------------------------------+
+--| pfs(clk, a, y) | Pulso a '1' en Flanco de Subida |
+--+-------------------------------------------------------------------------------------------------+
+--| pfb(clk, a, y) | Pulso a '1' en Flanco de bajada |
+--+-------------------------------------------------------------------------------------------------+
+--+-----------------------------------------------------------------+
+--| |
+--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
+--| |
+--| This source file may be used and distributed without |
+--| restriction provided that this copyright statement is not |
+--| removed from the file and that any derivative work contains |
+--| the original copyright notice and the associated disclaimer. |
+--| |
+--| This source file is free software; you can redistribute it |
+--| and/or modify it under the terms of the GNU Lesser General |
+--| Public License as published by the Free Software Foundation; |
+--| either version 2.1 of the License, or (at your option) any |
+--| later version. |
+--| |
+--| This source is distributed in the hope that it will be |
+--| useful, but WITHOUT ANY WARRANTY; without even the implied |
+--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
+--| PURPOSE. See the GNU Lesser General Public License for more |
+--| details. |
+--| |
+--| You should have received a copy of the GNU Lesser General |
+--| Public License along with this source; if not, download it |
+--| from http://www.opencores.org/lgpl.shtml |
+--| |
+--+-----------------------------------------------------------------+
+
+--+-----------------------------------------------------------------------------+
+--| PACKAGE COMPONENTS DECLARATION |
+--+-----------------------------------------------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package onapackage is
+
+ component sync
+ port (
+
+ clk : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+ );
+ end component;
+
+ component synch
+ port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+ );
+ end component;
+
+ component syncl
+ port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+ );
+ end component;
+
+ component sync2
+ port (
+
+ clk : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+ );
+ end component;
+
+ component sync2h
+ port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+ );
+ end component;
+
+ component sync2l
+ port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+ );
+ end component;
+
+ component syncv
+ generic ( size: integer := 8 );
+ port (
+
+ clk : in std_logic;
+ d : in std_logic_vector(size-1 downto 0);
+ q : out std_logic_vector(size-1 downto 0)
+
+ );
+ end component;
+
+ component syncv2h
+ generic ( size: integer := 8 );
+ port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ d : in std_logic_vector(size-1 downto 0);
+ q : out std_logic_vector(size-1 downto 0)
+
+ );
+ end component;
+
+ component decoder3to8
+ port (
+
+ i : in std_logic_vector(2 downto 0);
+ o : out std_logic_vector(7 downto 0)
+
+ );
+ end component;
+
+ component pfs
+ port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ a : in std_logic;
+ y : out std_logic
+
+ );
+ end component;
+
+ component pfb
+ port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ a : in std_logic;
+ y : out std_logic
+
+ );
+ end component;
+
+end onapackage;
+
+
+
+--+-----------------------------------------------------------------------------+
+--| ENTITY & ARCHITECTURE |
+--+-----------------------------------------------------------------------------+
+
+
+--+-----------------------------------------+
+--| sync |
+--+-----------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sync is
+port (
+
+ clk : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+);
+end sync;
+
+architecture rtl of sync is
+begin
+
+ SYNCP: process( clk, d )
+ begin
+
+ if ( rising_edge(clk) ) then
+ q <= d;
+ end if;
+
+ end process SYNCP;
+
+end rtl;
+
+--+-----------------------------------------+
+--| synch |
+--+-----------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity synch is
+port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+);
+end synch;
+
+architecture rtl of synch is
+begin
+
+ SYNCHP: process( clk, rst, d )
+ begin
+ if (rst = '1') then
+ q <= '1';
+ elsif ( rising_edge(clk) ) then
+ q <= d;
+ end if;
+
+ end process SYNCHP;
+
+end rtl;
+
+--+-----------------------------------------+
+--| syncl |
+--+-----------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity syncl is
+port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+);
+end syncl;
+
+architecture rtl of syncl is
+begin
+
+ SYNCLP: process( clk, rst, d )
+ begin
+ if (rst = '1') then
+ q <= '0';
+ elsif ( rising_edge(clk) ) then
+ q <= d;
+ end if;
+
+ end process SYNCLP;
+
+end rtl;
+
+
+--+-----------------------------------------+
+--| sync2 |
+--+-----------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sync2 is
+ port (
+
+ clk : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+ );
+end sync2;
+
+architecture rtl of sync2 is
+ signal tmp: std_logic;
+begin
+
+ SYNC2P: process ( clk, d, tmp)
+ begin
+
+ if ( rising_edge(clk) ) then
+ tmp <= d;
+ q <= tmp;
+ end if;
+
+ end process SYNC2P;
+
+end rtl;
+
+--+-----------------------------------------+
+--| sync2h |
+--+-----------------------------------------+
+-- sync2 con inicializacion a '1' con el reset
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sync2h is
+ port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+ );
+end sync2h;
+
+architecture rtl of sync2h is
+ signal tmp: std_logic;
+begin
+
+ SYNC2HP: process ( clk, rst, d, tmp)
+ begin
+
+ if (rst = '1') then
+ tmp <= '1';
+ q <= '1';
+ elsif ( rising_edge(clk) ) then
+ tmp <= d;
+ q <= tmp;
+ end if;
+
+ end process SYNC2HP;
+
+end rtl;
+
+--+-----------------------------------------+
+--| sync2l |
+--+-----------------------------------------+
+-- sync2 con inicializacion a '0' con el reset
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity sync2l is
+ port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+
+ );
+end sync2l;
+
+architecture rtl of sync2l is
+ signal tmp: std_logic;
+begin
+
+ SYNC2LP: process ( clk, rst, d, tmp)
+ begin
+
+ if (rst = '1') then
+ tmp <= '0';
+ q <= '0';
+ elsif ( rising_edge(clk) ) then
+ tmp <= d;
+ q <= tmp;
+ end if;
+
+ end process SYNC2LP;
+
+end rtl;
+
+
+
+--+-----------------------------------------+
+--| syncv |
+--+-----------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity syncv is
+generic ( size: integer := 8 );
+port (
+
+ clk : in std_logic;
+ d : in std_logic_vector(size-1 downto 0);
+ q : out std_logic_vector(size-1 downto 0)
+
+);
+end syncv;
+
+architecture rtl of syncv is
+begin
+
+ SYNCVP: process( clk, d )
+ begin
+
+ if ( rising_edge(clk) ) then
+ q <= d;
+ end if;
+
+ end process SYNCVP;
+
+end rtl;
+
+--+-----------------------------------------+
+--| syncv2h |
+--+-----------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity syncv2h is
+generic ( size: integer := 8 );
+port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ d : in std_logic_vector(size-1 downto 0);
+ q : out std_logic_vector(size-1 downto 0)
+
+);
+end syncv2h;
+
+architecture rtl of syncv2h is
+ signal tmp: std_logic_vector(size-1 downto 0);
+begin
+
+ SYNCV2HP: process( clk, d, rst )
+ begin
+
+ if (rst = '1') then
+ tmp <= (others => '1');
+ q <= (others => '1');
+ elsif ( rising_edge(clk) ) then
+ tmp <= d;
+ q <= tmp;
+ end if;
+
+ end process SYNCV2HP;
+
+end rtl;
+
+
+--+-----------------------------------------+
+--| decoder3to8 |
+--+-----------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity decoder3to8 is
+port (
+
+ i : in std_logic_vector(2 downto 0);
+ o : out std_logic_vector(7 downto 0)
+
+);
+end decoder3to8;
+
+architecture rtl of decoder3to8 is
+begin
+
+ DECOD3TO8P: process( i )
+ begin
+
+ if ( i = "111" ) then o <= "01111111";
+ elsif ( i = "110" ) then o <= "10111111";
+ elsif ( i = "101" ) then o <= "11011111";
+ elsif ( i = "100" ) then o <= "11101111";
+ elsif ( i = "011" ) then o <= "11110111";
+ elsif ( i = "010" ) then o <= "11111011";
+ elsif ( i = "001" ) then o <= "11111101";
+ elsif ( i = "000" ) then o <= "11111110";
+ else
+ o <= "11111111";
+ end if;
+
+ end process DECOD3TO8P;
+
+end rtl;
+
+
+--+-----------------------------------------+
+--| pfs |
+--+-----------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pfs is
+port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ a : in std_logic;
+ y : out std_logic
+
+);
+end pfs;
+
+architecture rtl of pfs is
+
+ signal a_s : std_logic;
+ signal a_s2 : std_logic;
+
+begin
+
+ PFSP: process( clk, rst, a )
+ begin
+
+ if ( rst = '1' ) then
+ a_s <= '0';
+ a_s2 <= '1';
+ elsif ( rising_edge(clk) ) then
+ a_s <= a;
+ a_s2 <= a_s;
+ end if;
+
+ end process PFSP;
+
+ y <= a_s and (not a_s2);
+
+end rtl;
+
+--+-----------------------------------------+
+--| pfb |
+--+-----------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pfb is
+port (
+
+ clk : in std_logic;
+ rst : in std_logic;
+ a : in std_logic;
+ y : out std_logic
+
+);
+end pfb;
+
+architecture rtl of pfb is
+
+ signal a_s : std_logic;
+ signal a_s2 : std_logic;
+
+begin
+
+ PFBP: process( clk, rst, a )
+ begin
+
+ if ( rst = '1' ) then
+ a_s <= '1';
+ a_s2 <= '0';
+ elsif ( rising_edge(clk) ) then
+ a_s <= a;
+ a_s2 <= a_s;
+ end if;
+
+ end process PFBP;
+
+ y <= (not a_s) and a_s2;
+
+end rtl;
+
Index: trunk/rtl/pci32tlite.vhd
===================================================================
--- trunk/rtl/pci32tlite.vhd (nonexistent)
+++ trunk/rtl/pci32tlite.vhd (revision 10)
@@ -0,0 +1,481 @@
+--+-------------------------------------------------------------------------------------------------+
+--| |
+--| File: pci32tLite.vhd |
+--| |
+--| Components: pcidec.vhd |
+--| pciwbsequ.vhd |
+--| pcidmux.vhd |
+--| pciregs.vhd |
+--| pcipargen.vhd |
+--| ona.vhd |
+--| |
+--+-------------------------------------------------------------------------------------------------+
+--| |
+--| Revision history : |
+--| Date Version Author Description |
+--| 2005-05-13 R00A00 PAU First alfa revision |
+--| |
+--| 2006-11-27 R01 PAU * BUG fast back-to-back transactions |
+--| * TIMEOUT: Target termination with RETRY |
+--| 2007-09-19 R02 PAU * "intb" and "serr" signals not defined as TRI. They have to be |
+--| defined Opendrain in the FPGA (externally to the IP Core). |
+--| * Small changes due to onalib.vhd improvement. |
+--| * Removed TIMEOUT. Added wb_rty_i for Target termination with |
+--| RETRY. |
+--| * Support Burst Cicles. |
+--| * Add Whisbone data bus configuration generics: WBSIZE and |
+--| WBENDIAN. |
+--| * Add wb_adr_o(1..0) signals. |
+--| * wb_dat_i,wb_dat_o,wb_sel_o size depends on WBSIZE. |
+--| * Advice: Change WB <-> PCI databus routing for "BIG"/16 WB |
+--| configuration and DWORD PCI transactions (DWORD is not |
+--| recomended when WB 16 configuration). |
+--| 2008-06-16 R03 PAU * Add "1BARIO" configuration option for BARS generic. |
+--| * fix bug with WBENDIAN generic in pciwbsequ. |
+--| * Change PCI Burts to WB traslation behavior. |
+--| * Add "classcode" generic. |
+--| * Change BAR0 reset state to "0". |
+--| * Fix pcidmux bug for LITTLE/8 configuration. |
+--| 2022-01-10 v3.1 Peio Azkarate |
+--| * Project changes, Not rtl changes. |
+--+-------------------------------------------------------------------------------------------------+
+--+-----------------------------------------------------------------+
+--| |
+--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
+--| |
+--| This source file may be used and distributed without |
+--| restriction provided that this copyright statement is not |
+--| removed from the file and that any derivative work contains |
+--| the original copyright notice and the associated disclaimer. |
+--| |
+--| This source file is free software; you can redistribute it |
+--| and/or modify it under the terms of the GNU Lesser General |
+--| Public License as published by the Free Software Foundation; |
+--| either version 2.1 of the License, or (at your option) any |
+--| later version. |
+--| |
+--| This source is distributed in the hope that it will be |
+--| useful, but WITHOUT ANY WARRANTY; without even the implied |
+--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
+--| PURPOSE. See the GNU Lesser General Public License for more |
+--| details. |
+--| |
+--| You should have received a copy of the GNU Lesser General |
+--| Public License along with this source; if not, download it |
+--| from http://www.opencores.org/lgpl.shtml |
+--| |
+--+-----------------------------------------------------------------+
+
+--+-----------------------------------------------------------------------------+
+--| LIBRARIES |
+--+-----------------------------------------------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+--+-----------------------------------------------------------------------------+
+--| ENTITY |
+--+-----------------------------------------------------------------------------+
+entity pci32tLite is
+generic (
+ vendorID : std_logic_vector(15 downto 0) := x"4150";
+ deviceID : std_logic_vector(15 downto 0) := x"0001";
+ revisionID : std_logic_vector(7 downto 0) := x"90";
+ subsystemID : std_logic_vector(15 downto 0) := x"0000";
+ subsystemvID : std_logic_vector(15 downto 0) := x"1172";
+ classcodeID : std_logic_vector(23 downto 0) := x"068000";
+ -- BAR&WB_CFG (dont delete)
+ BARS : string := "1BARMEM";
+ WBSIZE : integer := 16;
+ WBENDIAN : string := "BIG"
+);
+port (
+ -- General
+ clk33 : in std_logic;
+ rst : in std_logic;
+
+ -- PCI target 32bits
+ ad : inout std_logic_vector(31 downto 0);
+ cbe : in std_logic_vector(3 downto 0);
+ par : out std_logic;
+ frame : in std_logic;
+ irdy : in std_logic;
+ trdy : out std_logic;
+ devsel : out std_logic;
+ stop : out std_logic;
+ idsel : in std_logic;
+ perr : out std_logic;
+ serr : out std_logic;
+ intb : out std_logic;
+
+ -- Master whisbone
+ wb_adr_o : out std_logic_vector(24 downto 0);
+ wb_dat_i : in std_logic_vector(WBSIZE-1 downto 0);
+ wb_dat_o : out std_logic_vector(WBSIZE-1 downto 0);
+ wb_sel_o : out std_logic_vector(((WBSIZE/8)-1) downto 0);
+ wb_we_o : out std_logic;
+ wb_stb_o : out std_logic;
+ wb_cyc_o : out std_logic;
+ wb_ack_i : in std_logic;
+ wb_rty_i : in std_logic;
+ wb_err_i : in std_logic;
+ wb_int_i : in std_logic
+
+);
+end pci32tLite;
+
+
+--+-----------------------------------------------------------------------------+
+--| ARCHITECTURE |
+--+-----------------------------------------------------------------------------+
+
+architecture rtl of pci32tLite is
+
+--+-----------------------------------------------------------------------------+
+--| COMPONENTS |
+--+-----------------------------------------------------------------------------+
+
+ component pcidec
+ generic (
+ BARS : string := "1BARMEM"
+ );
+ port (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ --
+ ad_i : in std_logic_vector(31 downto 0);
+ cbe_i : in std_logic_vector(3 downto 0);
+ idsel_i : in std_logic;
+ bar0_i : in std_logic_vector(31 downto 9);
+ memEN_i : in std_logic;
+ ioEN_i : in std_logic;
+ pciadrLD_i : in std_logic;
+ adrcfg_o : out std_logic;
+ adrmem_o : out std_logic;
+ adr_o : out std_logic_vector(24 downto 0);
+ cmd_o : out std_logic_vector(3 downto 0)
+ );
+ end component;
+
+
+ component pciwbsequ
+ generic (
+ BARS : string := "1BARMEM";
+ WBSIZE : integer := 16;
+ WBENDIAN : string := "BIG"
+ );
+ port (
+ -- General
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ -- pci
+ cmd_i : in std_logic_vector(3 downto 0);
+ cbe_i : in std_logic_vector(3 downto 0);
+ frame_i : in std_logic;
+ irdy_i : in std_logic;
+ devsel_o : out std_logic;
+ trdy_o : out std_logic;
+ stop_o : out std_logic;
+ -- control
+ adrcfg_i : in std_logic;
+ adrmem_i : in std_logic;
+ pciadrLD_o : out std_logic;
+ pcidOE_o : out std_logic;
+ parOE_o : out std_logic;
+ wbdatLD_o : out std_logic;
+ wrcfg_o : out std_logic;
+ rdcfg_o : out std_logic;
+ -- whisbone
+ wb_sel_o : out std_logic_vector(((WBSIZE/8)-1) downto 0);
+ wb_we_o : out std_logic;
+ wb_stb_o : out std_logic;
+ wb_cyc_o : out std_logic;
+ wb_ack_i : in std_logic;
+ wb_rty_i : in std_logic;
+ wb_err_i : in std_logic
+ );
+ end component;
+
+
+ component pcidmux
+ generic (
+ BARS : string := "1BARMEM";
+ WBSIZE : integer := 16;
+ WBENDIAN : string := "BIG"
+ );
+ port (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ --
+ d_io : inout std_logic_vector(31 downto 0);
+ pcidatout_o : out std_logic_vector(31 downto 0);
+ pcidOE_i : in std_logic;
+ wbdatLD_i : in std_logic;
+ rdcfg_i : in std_logic;
+ cbe_i : in std_logic_vector(3 downto 0);
+ wb_dat_i : in std_logic_vector((WBSIZE-1) downto 0);
+ wb_dat_o : out std_logic_vector((WBSIZE-1) downto 0);
+ rg_dat_i : in std_logic_vector(31 downto 0);
+ rg_dat_o : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+
+ component pciregs
+ generic (
+ vendorID : std_logic_vector(15 downto 0);
+ deviceID : std_logic_vector(15 downto 0);
+ revisionID : std_logic_vector(7 downto 0);
+ subsystemID : std_logic_vector(15 downto 0);
+ subsystemvID : std_logic_vector(15 downto 0);
+ classcodeID : std_logic_vector(23 downto 0);
+ BARS : string := "1BARMEM"
+ );
+ port (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ --
+ adr_i : in std_logic_vector(7 downto 2);
+ cbe_i : in std_logic_vector(3 downto 0);
+ dat_i : in std_logic_vector(31 downto 0);
+ dat_o : out std_logic_vector(31 downto 0);
+ wrcfg_i : in std_logic;
+ rdcfg_i : in std_logic;
+ perr_i : in std_logic;
+ serr_i : in std_logic;
+ tabort_i : in std_logic;
+ bar0_o : out std_logic_vector(31 downto 9);
+ perrEN_o : out std_logic;
+ serrEN_o : out std_logic;
+ memEN_o : out std_logic;
+ ioEN_o : out std_logic
+ );
+ end component;
+
+
+ component pcipargen
+ port (
+
+ clk_i : in std_logic;
+ pcidatout_i : in std_logic_vector(31 downto 0);
+ cbe_i : in std_logic_vector(3 downto 0);
+ parOE_i : in std_logic;
+ par_o : out std_logic
+
+ );
+ end component;
+
+
+--+-----------------------------------------------------------------------------+
+--| CONSTANTS |
+--+-----------------------------------------------------------------------------+
+--+-----------------------------------------------------------------------------+
+--| SIGNALS |
+--+-----------------------------------------------------------------------------+
+
+ signal bar0 : std_logic_vector(31 downto 9);
+ signal memEN : std_logic;
+ signal ioEN : std_logic;
+ signal pciadrLD : std_logic;
+ signal adrcfg : std_logic;
+ signal adrmem : std_logic;
+ signal adr : std_logic_vector(24 downto 0);
+ signal cmd : std_logic_vector(3 downto 0);
+ signal pcidOE : std_logic;
+ signal parOE : std_logic;
+ signal wbdatLD : std_logic;
+ signal wrcfg : std_logic;
+ signal rdcfg : std_logic;
+ signal pcidatread : std_logic_vector(31 downto 0);
+ signal pcidatwrite : std_logic_vector(31 downto 0);
+ signal pcidatout : std_logic_vector(31 downto 0);
+ signal parerr : std_logic;
+ signal syserr : std_logic;
+ signal tabort : std_logic;
+ signal perrEN : std_logic;
+ signal serrEN : std_logic;
+
+begin
+ -- ASSERT
+ assert (BARS = "1BARMEM" or BARS = "1BARIO")
+ report "ERROR : Bad BAR configuration"
+ severity Failure;
+ assert ((WBSIZE = 32 and WBENDIAN = "LITTLE") or (WBSIZE = 16) or (WBSIZE = 8 and WBENDIAN = "LITTLE"))
+ report "ERROR : Bad WBSIZE/WBENDIAN configuration"
+ severity Failure;
+
+ --+-------------------------------------------------------------------------+
+ --| Component instances |
+ --+-------------------------------------------------------------------------+
+
+ --+-----------------------------------------+
+ --| PCI decoder |
+ --+-----------------------------------------+
+ u1: component pcidec
+ generic map (
+ BARS => BARS
+ )
+ port map (
+
+ clk_i => clk33,
+ rst_i => rst,
+ --
+ ad_i => ad,
+ cbe_i => cbe,
+ idsel_i => idsel,
+ bar0_i => bar0,
+ memEN_i => memEN,
+ ioEN_i => ioEN,
+ pciadrLD_i => pciadrLD,
+ adrcfg_o => adrcfg,
+ adrmem_o => adrmem,
+ adr_o => adr,
+ cmd_o => cmd
+ );
+
+
+ --+-----------------------------------------+
+ --| PCI-WB Sequencer |
+ --+-----------------------------------------+
+ u2: component pciwbsequ
+ generic map (
+ BARS => BARS,
+ WBSIZE => WBSIZE,
+ WBENDIAN => WBENDIAN
+ )
+ port map (
+ -- General
+ clk_i => clk33,
+ rst_i => rst,
+ -- pci
+ cmd_i => cmd,
+ cbe_i => cbe,
+ frame_i => frame,
+ irdy_i => irdy,
+ devsel_o => devsel,
+ trdy_o => trdy,
+ stop_o => stop,
+ -- control
+ adrcfg_i => adrcfg,
+ adrmem_i => adrmem,
+ pciadrLD_o => pciadrLD,
+ pcidOE_o => pcidOE,
+ parOE_o => parOE,
+ wbdatLD_o => wbdatLD,
+ wrcfg_o => wrcfg,
+ rdcfg_o => rdcfg,
+ -- whisbone
+ wb_sel_o => wb_sel_o(((WBSIZE/8)-1) downto 0),
+ wb_we_o => wb_we_o,
+ wb_stb_o => wb_stb_o,
+ wb_cyc_o => wb_cyc_o,
+ wb_ack_i => wb_ack_i,
+ wb_rty_i => wb_rty_i,
+ wb_err_i => wb_err_i
+ );
+
+
+ --+-----------------------------------------+
+ --| PCI-wb datamultiplexer |
+ --+-----------------------------------------+
+ u3: component pcidmux
+ generic map (
+ BARS => BARS,
+ WBSIZE => WBSIZE,
+ WBENDIAN => WBENDIAN
+ )
+ port map (
+ clk_i => clk33,
+ rst_i => rst,
+ --
+ d_io => ad,
+ pcidatout_o => pcidatout,
+ pcidOE_i => pcidOE,
+ wbdatLD_i => wbdatLD,
+ rdcfg_i => rdcfg,
+ cbe_i => cbe,
+ wb_dat_i => wb_dat_i((WBSIZE-1) downto 0),
+ wb_dat_o => wb_dat_o((WBSIZE-1) downto 0),
+ rg_dat_i => pcidatread,
+ rg_dat_o => pcidatwrite
+ );
+
+
+ --+-----------------------------------------+
+ --| PCI registers |
+ --+-----------------------------------------+
+ u4: component pciregs
+ generic map (
+ vendorID => vendorID,
+ deviceID => deviceID,
+ revisionID => revisionID,
+ subsystemID => subsystemID,
+ subsystemvID => subsystemvID,
+ classcodeID => classcodeID,
+ BARS => BARS
+ )
+ port map (
+ clk_i => clk33,
+ rst_i => rst,
+ --
+ adr_i => adr(7 downto 2),
+ cbe_i => cbe,
+ dat_i => pcidatwrite,
+ dat_o => pcidatread,
+ wrcfg_i => wrcfg,
+ rdcfg_i => rdcfg,
+ perr_i => parerr,
+ serr_i => syserr,
+ tabort_i => tabort,
+ bar0_o => bar0,
+ perrEN_o => perrEN,
+ serrEN_o => serrEN,
+ memEN_o => memEN,
+ ioEN_o => ioEN
+
+ );
+
+ --+-----------------------------------------+
+ --| PCI Parity Gnerator |
+ --+-----------------------------------------+
+ u5: component pcipargen
+ port map (
+ clk_i => clk33,
+ pcidatout_i => pcidatout,
+ cbe_i => cbe,
+ parOE_i => parOE,
+ par_o => par
+ );
+
+ --+-----------------------------------------+
+ --| Whisbone Address bus |
+ --+-----------------------------------------+
+ wb_adr_o <= adr;
+
+ --+-----------------------------------------+
+ --| unimplemented |
+ --+-----------------------------------------+
+ parerr <= '0';
+ syserr <= '0';
+ tabort <= '0';
+
+ --+-----------------------------------------+
+ --| unused outputs |
+ --+-----------------------------------------+
+ -- El pin de interrupcion "serr" debe ser OPENDRAIN.
+ -- Definirlo as� en la FPGA.
+ -- #perr:
+ -- #serr:
+ perr <= 'Z';
+ --serr <= 'Z';
+ serr <= '1';
+
+ --+-----------------------------------------+
+ --| Interrupt |
+ --+-----------------------------------------+
+ -- El pin de interrupcion "intb" debe ser OPENDRAIN.
+ -- Definirlo as� en la FPGA.
+ --intb <= '0' when ( wb_int_i = '1' ) else 'Z';
+ intb <= not wb_int_i;
+
+end rtl;
Index: trunk/rtl/pcidec.vhd
===================================================================
--- trunk/rtl/pcidec.vhd (nonexistent)
+++ trunk/rtl/pcidec.vhd (revision 10)
@@ -0,0 +1,175 @@
+--+-------------------------------------------------------------------------------------------------+
+--| |
+--| File: pcidec.vhd |
+--| |
+--| Project: pci32tLite |
+--| |
+--| Description: PCI decoder and PCI signals loader. |
+--| * LoaD signals: "ad" -> adr, cbe -> cmd. |
+--| * Decode memory and configuration space. |
+--| |
+--+-------------------------------------------------------------------------------------------------+
+
+--+-----------------------------------------------------------------+
+--| |
+--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
+--| |
+--| This source file may be used and distributed without |
+--| restriction provided that this copyright statement is not |
+--| removed from the file and that any derivative work contains |
+--| the original copyright notice and the associated disclaimer. |
+--| |
+--| This source file is free software; you can redistribute it |
+--| and/or modify it under the terms of the GNU Lesser General |
+--| Public License as published by the Free Software Foundation; |
+--| either version 2.1 of the License, or (at your option) any |
+--| later version. |
+--| |
+--| This source is distributed in the hope that it will be |
+--| useful, but WITHOUT ANY WARRANTY; without even the implied |
+--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
+--| PURPOSE. See the GNU Lesser General Public License for more |
+--| details. |
+--| |
+--| You should have received a copy of the GNU Lesser General |
+--| Public License along with this source; if not, download it |
+--| from http://www.opencores.org/lgpl.shtml |
+--| |
+--+-----------------------------------------------------------------+
+
+--+-----------------------------------------------------------------------------+
+--| LIBRARIES |
+--+-----------------------------------------------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+--+-----------------------------------------------------------------------------+
+--| ENTITY |
+--+-----------------------------------------------------------------------------+
+
+entity pcidec is
+generic (
+ BARS : string := "1BARMEM"
+);
+port (
+
+ -- General
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ -- pci
+ ad_i : in std_logic_vector(31 downto 0);
+ cbe_i : in std_logic_vector(3 downto 0);
+ idsel_i : in std_logic;
+ -- control
+ bar0_i : in std_logic_vector(31 downto 9);
+ memEN_i : in std_logic;
+ ioEN_i : in std_logic;
+ pciadrLD_i : in std_logic;
+ adrcfg_o : out std_logic;
+ adrmem_o : out std_logic;
+ adr_o : out std_logic_vector(24 downto 0);
+ cmd_o : out std_logic_vector(3 downto 0)
+
+);
+end pcidec;
+
+
+architecture rtl of pcidec is
+
+
+--+-----------------------------------------------------------------------------+
+--| COMPONENTS |
+--+-----------------------------------------------------------------------------+
+--+-----------------------------------------------------------------------------+
+--| CONSTANTS |
+--+-----------------------------------------------------------------------------+
+--+-----------------------------------------------------------------------------+
+--| SIGNALS |
+--+-----------------------------------------------------------------------------+
+
+ signal adr : std_logic_vector(31 downto 0);
+ signal cmd : std_logic_vector(3 downto 0);
+ signal idsel_s : std_logic;
+ signal a1 : std_logic;
+ signal a0 : std_logic;
+
+begin
+
+ --+-------------------------------------------------------------------------+
+ --| Load PCI Signals |
+ --+-------------------------------------------------------------------------+
+
+ PCILD: process( rst_i, clk_i, ad_i, cbe_i, idsel_i )
+ begin
+
+ if( rst_i = '1' ) then
+ adr <= ( others => '1' );
+ cmd <= ( others => '1' );
+ idsel_s <= '0';
+ elsif( rising_edge(clk_i) ) then
+
+ if ( pciadrLD_i = '1' ) then
+
+ adr <= ad_i;
+ cmd <= cbe_i;
+ idsel_s <= idsel_i;
+
+ end if;
+ end if;
+
+ end process PCILD;
+
+
+
+
+ --+-------------------------------------------------------------------------+
+ --| Decoder |
+ --+-------------------------------------------------------------------------+
+
+ barmem_g: if (BARS="1BARMEM") generate
+ adrmem_o <= '1' when ( ( memEN_i = '1' )
+ and ( adr(31 downto 25) = bar0_i(31 downto 25) )
+ and ( adr(1 downto 0) = "00" )
+ and ( cmd(3 downto 1) = "011" ) )
+ else '0';
+ end generate;
+
+ bario_g: if (BARS="1BARIO") generate
+ adrmem_o <= '1' when ( ( ioEN_i = '1' )
+ and ( adr(31 downto 16) = "0000000000000000")
+ and ( adr(15 downto 9) = bar0_i(15 downto 9) )
+ and ( cmd(3 downto 1) = "001" ) )
+ else '0';
+ end generate;
+
+ adrcfg_o <= '1' when ( ( idsel_s = '1' )
+ and ( adr(1 downto 0) = "00" )
+ and ( cmd(3 downto 1) = "101" ) )
+ else '0';
+
+
+ --+-------------------------------------------------------------------------+
+ --| Adresses WB A(1)/A(0) |
+ --+-------------------------------------------------------------------------+
+ barmema1a0_g: if (BARS="1BARMEM") generate
+ a1 <= cbe_i(1) and cbe_i(0);
+ a0 <= cbe_i(2) and cbe_i(0);
+ end generate;
+
+ barioa1a0_g: if (BARS="1BARIO") generate
+ a1 <= adr(1);
+ a0 <= adr(0);
+ end generate;
+
+
+ --+-------------------------------------------------------------------------+
+ --| Other outs |
+ --+-------------------------------------------------------------------------+
+
+ adr_o <= adr(24 downto 2) & a1 & a0;
+ cmd_o <= cmd;
+
+
+end rtl;
Index: trunk/rtl/pcidmux.vhd
===================================================================
--- trunk/rtl/pcidmux.vhd (nonexistent)
+++ trunk/rtl/pcidmux.vhd (revision 10)
@@ -0,0 +1,256 @@
+--+-------------------------------------------------------------------------------------------------+
+--| |
+--| File: pcidmux.vhd |
+--| |
+--| Project: pci32tLite |
+--| |
+--| Description: Data Multiplex wb <-> regs <-> pci |
+--| Data Multiplex D16 whisbone <-> D32 PCI. |
+--| |
+--+-------------------------------------------------------------------------------------------------+
+--+-----------------------------------------------------------------+
+--| |
+--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
+--| |
+--| This source file may be used and distributed without |
+--| restriction provided that this copyright statement is not |
+--| removed from the file and that any derivative work contains |
+--| the original copyright notice and the associated disclaimer. |
+--| |
+--| This source file is free software; you can redistribute it |
+--| and/or modify it under the terms of the GNU Lesser General |
+--| Public License as published by the Free Software Foundation; |
+--| either version 2.1 of the License, or (at your option) any |
+--| later version. |
+--| |
+--| This source is distributed in the hope that it will be |
+--| useful, but WITHOUT ANY WARRANTY; without even the implied |
+--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
+--| PURPOSE. See the GNU Lesser General Public License for more |
+--| details. |
+--| |
+--| You should have received a copy of the GNU Lesser General |
+--| Public License along with this source; if not, download it |
+--| from http://www.opencores.org/lgpl.shtml |
+--| |
+--+-----------------------------------------------------------------+
+
+
+--+-----------------------------------------------------------------------------+
+--| LIBRARIES |
+--+-----------------------------------------------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+--+-----------------------------------------------------------------------------+
+--| ENTITY |
+--+-----------------------------------------------------------------------------+
+
+entity pcidmux is
+generic (
+ BARS : string := "1BARMEM";
+ WBSIZE : integer := 16;
+ WBENDIAN : string := "BIG"
+);
+port (
+
+ -- General
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ --
+ d_io : inout std_logic_vector(31 downto 0);
+ pcidatout_o : out std_logic_vector(31 downto 0);
+ --
+ pcidOE_i : in std_logic;
+ wbdatLD_i : in std_logic;
+ rdcfg_i : in std_logic;
+ cbe_i : in std_logic_vector(3 downto 0);
+ --
+ wb_dat_i : in std_logic_vector((WBSIZE-1) downto 0);
+ wb_dat_o : out std_logic_vector((WBSIZE-1) downto 0);
+ rg_dat_i : in std_logic_vector(31 downto 0);
+ rg_dat_o : out std_logic_vector(31 downto 0)
+
+);
+end pcidmux;
+
+
+architecture rtl of pcidmux is
+
+
+--+-----------------------------------------------------------------------------+
+--| COMPONENTS |
+--+-----------------------------------------------------------------------------+
+--+-----------------------------------------------------------------------------+
+--| CONSTANTS |
+--+-----------------------------------------------------------------------------+
+--+-----------------------------------------------------------------------------+
+--| SIGNALS |
+--+-----------------------------------------------------------------------------+
+
+ signal pcidatin : std_logic_vector(31 downto 0);
+ signal pcidatout : std_logic_vector(31 downto 0);
+ signal wb_dat_is : std_logic_vector((WBSIZE-1) downto 0);
+ signal wbrgdMX : std_logic;
+ signal wbdMX : std_logic_vector(1 downto 0);
+
+begin
+
+ -- Mux control signals
+ wbrgdMX <= not rdcfg_i;
+ wbdMX(0) <= '0' when ( cbe_i(0) = '0' or cbe_i(2) = '0' ) else '1';
+ wbdMX(1) <= '0' when ( cbe_i(0) = '0' or cbe_i(1) = '0' ) else '1';
+
+ --+-------------------------------------------------------------------------+
+ --| Load Whisbone Datain |
+ --+-------------------------------------------------------------------------+
+
+ WBDATLD: process( rst_i, clk_i, wbdatLD_i, wb_dat_i )
+ begin
+
+ if( rst_i = '1' ) then
+ wb_dat_is <= ( others => '1' );
+ elsif( rising_edge(clk_i) ) then
+
+ if ( wbdatLD_i = '1' ) then
+ wb_dat_is <= wb_dat_i;
+ end if;
+
+ end if;
+
+ end process WBDATLD;
+
+
+ --+-------------------------------------------------------------------------+
+ --| Route PCI data in toward Registers and Whisbone |
+ --+-------------------------------------------------------------------------+
+ rg_dat_o <= pcidatin;
+
+
+ --+-------------------------------------------------------------------------+
+ --| PCI <-> WB Data route and swap |
+ --+-------------------------------------------------------------------------+
+ --+-----------------------------------------+
+ --| PCI(Little endian) <-> WB(Little endian)|
+ --| WB bus 32Bits |
+ --+-----------------------------------------+
+ dat32: if (WBSIZE = 32 and WBENDIAN = "LITTLE") generate
+ pcidatout(31 downto 0) <= wb_dat_is(31 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(31 downto 0);
+ wb_dat_o(31 downto 0) <= pcidatin(31 downto 0);
+ end generate;
+
+ --+-----------------------------------------+
+ --| PCI(Little endian) <-> WB(Big endian) |
+ --| WB bus 16Bits |
+ --+-----------------------------------------+
+ dat16b: if (WBSIZE = 16 and WBENDIAN = "BIG") generate
+ --pcidatout(31 downto 24) <= wb_dat_is(7 downto 0) when ( wbrgdMX_i = '1' ) else rg_dat_i(31 downto 24);
+ --pcidatout(23 downto 16) <= wb_dat_is(15 downto 8) when ( wbrgdMX_i = '1' ) else rg_dat_i(23 downto 16);
+ --pcidatout(15 downto 8) <= wb_dat_is(7 downto 0) when ( wbrgdMX_i = '1' ) else rg_dat_i(15 downto 8);
+ --pcidatout(7 downto 0) <= wb_dat_is(15 downto 8) when ( wbrgdMX_i = '1' ) else rg_dat_i(7 downto 0);
+ --wb_dat_o(15 downto 8) <= pcidatin(23 downto 16) when ( wbdMX_i(1) = '1' ) else pcidatin(7 downto 0);
+ --wb_dat_o(7 downto 0) <= pcidatin(31 downto 24) when ( wbdMX_i(1) = '1' ) else pcidatin(15 downto 8);
+ PCIWBMUX: process(cbe_i, pcidatin, wbrgdMX, wb_dat_is, rg_dat_i)
+ begin
+ case cbe_i is
+ when b"1100" =>
+ wb_dat_o(7 downto 0) <= pcidatin(7 downto 0);
+ wb_dat_o(15 downto 8) <= pcidatin(15 downto 8);
+ when b"0011" =>
+ wb_dat_o(7 downto 0) <= pcidatin(23 downto 16);
+ wb_dat_o(15 downto 8) <= pcidatin(31 downto 24);
+ when b"1110" =>
+ wb_dat_o(7 downto 0) <= (others => '1');
+ wb_dat_o(15 downto 8) <= pcidatin(7 downto 0);
+ when b"1101" =>
+ wb_dat_o(7 downto 0) <= pcidatin(15 downto 8);
+ wb_dat_o(15 downto 8) <= (others => '1');
+ when b"1011" =>
+ wb_dat_o(7 downto 0) <= (others => '1');
+ wb_dat_o(15 downto 8) <= pcidatin(23 downto 16);
+ when b"0111" =>
+ wb_dat_o(7 downto 0) <= pcidatin(31 downto 24);
+ wb_dat_o(15 downto 8) <= (others => '1');
+ when others =>
+ wb_dat_o(15 downto 0) <= pcidatin(15 downto 0);
+ end case;
+
+ if (wbrgdMX = '1') then
+ case cbe_i is
+ when b"1100" =>
+ pcidatout(31 downto 16) <= (others => '1');
+ pcidatout(15 downto 0) <= wb_dat_is(15 downto 0);
+ when b"0011" =>
+ pcidatout(31 downto 16) <= wb_dat_is(15 downto 0);
+ pcidatout(15 downto 0) <= (others => '1');
+ when b"1110" =>
+ pcidatout(31 downto 8) <= (others => '1');
+ pcidatout(7 downto 0) <= wb_dat_is(15 downto 8);
+ when b"1101" =>
+ pcidatout(31 downto 16) <= (others => '1');
+ pcidatout(15 downto 8) <= wb_dat_is(7 downto 0);
+ pcidatout(7 downto 0) <= (others => '1');
+ when b"1011" =>
+ pcidatout(31 downto 24) <= (others => '1');
+ pcidatout(23 downto 16) <= wb_dat_is(15 downto 8);
+ pcidatout(15 downto 0) <= (others => '1');
+ when b"0111" =>
+ pcidatout(31 downto 24) <= wb_dat_is(7 downto 0);
+ pcidatout(23 downto 0) <= (others => '1');
+ when others =>
+ pcidatout(15 downto 0) <= wb_dat_is(15 downto 0);
+ pcidatout(31 downto 16) <= (others => '1');
+ end case;
+ else
+ pcidatout(31 downto 0) <= rg_dat_i(31 downto 0);
+ end if;
+
+ end process PCIWBMUX;
+
+ end generate;
+
+ --+-----------------------------------------+
+ --| PCI(Little endian) <-> WB(Little endian)|
+ --| WB bus 16Bits |
+ --+-----------------------------------------+
+ dat16l: if (WBSIZE = 16 and WBENDIAN = "LITTLE") generate
+ pcidatout(31 downto 16) <= wb_dat_is when ( wbrgdMX = '1' ) else rg_dat_i(31 downto 16);
+ pcidatout(15 downto 0) <= wb_dat_is when ( wbrgdMX = '1' ) else rg_dat_i(15 downto 0);
+ wb_dat_o(15 downto 0) <= pcidatin(31 downto 16) when ( wbdMX(1) = '1' ) else pcidatin(15 downto 0);
+ end generate;
+
+ --+-----------------------------------------+
+ --| PCI(Little endian) <-> WB(Little endian)|
+ --| WB bus 8Bits |
+ --+-----------------------------------------+
+ dat8l: if (WBSIZE = 8 and WBENDIAN = "LITTLE") generate
+ --pcidatout(31 downto 24) <= wb_dat_is(7 downto 0);
+ --pcidatout(23 downto 16) <= wb_dat_is(7 downto 0);
+ --pcidatout(15 downto 8) <= wb_dat_is(7 downto 0);
+ --pcidatout(7 downto 0) <= wb_dat_is(7 downto 0);
+ pcidatout(31 downto 24) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(31 downto 24);
+ pcidatout(23 downto 16) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(23 downto 16);
+ pcidatout(15 downto 8) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(15 downto 8);
+ pcidatout(7 downto 0) <= wb_dat_is(7 downto 0) when ( wbrgdMX = '1' ) else rg_dat_i(7 downto 0);
+ with wbdMX select
+ wb_dat_o(7 downto 0) <= pcidatin(7 downto 0) when "00",
+ pcidatin(15 downto 8) when "01",
+ pcidatin(23 downto 16) when "10",
+ pcidatin(31 downto 24) when "11",
+ (others => '0') when others;
+ end generate;
+
+
+ --+-----------------------------------------+
+ --| Data out for parity generation |
+ --+-----------------------------------------+
+ pcidatout_o <= pcidatout;
+
+ --+-------------------------------------------------------------------------+
+ --| PCI data in/out with Triestate |
+ --+-------------------------------------------------------------------------+
+ pcidatin <= d_io;
+ d_io <= pcidatout when ( pcidOE_i = '1' ) else ( others => 'Z' );
+
+end rtl;
Index: trunk/rtl/pcipargen.vhd
===================================================================
--- trunk/rtl/pcipargen.vhd (nonexistent)
+++ trunk/rtl/pcipargen.vhd (revision 10)
@@ -0,0 +1,114 @@
+--+-------------------------------------------------------------------------------------------------+
+--| |
+--| File: pcipargen.vhd |
+--| |
+--| Project: pci32tLite |
+--| |
+--| Description: PCI Parity Generator. |
+--| |
+--+-------------------------------------------------------------------------------------------------+
+--+-----------------------------------------------------------------+
+--| |
+--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
+--| |
+--| This source file may be used and distributed without |
+--| restriction provided that this copyright statement is not |
+--| removed from the file and that any derivative work contains |
+--| the original copyright notice and the associated disclaimer. |
+--| |
+--| This source file is free software; you can redistribute it |
+--| and/or modify it under the terms of the GNU Lesser General |
+--| Public License as published by the Free Software Foundation; |
+--| either version 2.1 of the License, or (at your option) any |
+--| later version. |
+--| |
+--| This source is distributed in the hope that it will be |
+--| useful, but WITHOUT ANY WARRANTY; without even the implied |
+--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
+--| PURPOSE. See the GNU Lesser General Public License for more |
+--| details. |
+--| |
+--| You should have received a copy of the GNU Lesser General |
+--| Public License along with this source; if not, download it |
+--| from http://www.opencores.org/lgpl.shtml |
+--| |
+--+-----------------------------------------------------------------+
+
+
+--+-----------------------------------------------------------------------------+
+--| LIBRARIES |
+--+-----------------------------------------------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library onalib;
+use onalib.onapackage.all;
+
+
+--+-----------------------------------------------------------------------------+
+--| ENTITY |
+--+-----------------------------------------------------------------------------+
+
+entity pcipargen is
+port (
+
+ clk_i : in std_logic;
+ pcidatout_i : in std_logic_vector(31 downto 0);
+ cbe_i : in std_logic_vector(3 downto 0);
+ parOE_i : in std_logic;
+ par_o : out std_logic
+
+);
+end pcipargen;
+
+
+architecture rtl of pcipargen is
+
+
+--+-----------------------------------------------------------------------------+
+--| COMPONENTS |
+--+-----------------------------------------------------------------------------+
+--+-----------------------------------------------------------------------------+
+--| CONSTANTS |
+--+-----------------------------------------------------------------------------+
+--+-----------------------------------------------------------------------------+
+--| SIGNALS |
+--+-----------------------------------------------------------------------------+
+
+ signal d : std_logic_vector(31 downto 0);
+ signal pardat : std_logic;
+ signal parcbe : std_logic;
+ signal par : std_logic;
+ signal par_s : std_logic;
+
+begin
+
+
+ d <= pcidatout_i;
+
+
+ --+-------------------------------------------------------------------------+
+ --| building parity |
+ --+-------------------------------------------------------------------------+
+
+ pardat <= d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor
+ d(8) xor d(9) xor d(10) xor d(11) xor d(12) xor d(13) xor d(14) xor d(15) xor
+ d(16) xor d(17) xor d(18) xor d(19) xor d(20) xor d(21) xor d(22) xor d(23) xor
+ d(24) xor d(25) xor d(26) xor d(27) xor d(28) xor d(29) xor d(30) xor d(31);
+
+ parcbe <= cbe_i(0) xor cbe_i(1) xor cbe_i(2) xor cbe_i(3);
+
+ par <= pardat xor parcbe;
+
+ u1: sync port map ( clk => clk_i, d => par, q => par_s );
+
+
+ --+-------------------------------------------------------------------------+
+ --| PAR |
+ --+-------------------------------------------------------------------------+
+
+ par_o <= par_s when ( parOE_i = '1' ) else 'Z';
+
+
+end rtl;
Index: trunk/rtl/pciregs.vhd
===================================================================
--- trunk/rtl/pciregs.vhd (nonexistent)
+++ trunk/rtl/pciregs.vhd (revision 10)
@@ -0,0 +1,525 @@
+--+-------------------------------------------------------------------------------------------------+
+--| |
+--| File: pciregs.vhd |
+--| |
+--| Project: pci32tLite |
+--| |
+--| Description: PCI Registers |
+--| |
+--| +-----------------------------------------------------------------------+ |
+--| | PCI CONFIGURATION SPACE REGISTERS | |
+--| +-----------------------------------------------------------------------+ |
+--| |
+--| +-------------------------------------------------------------------+ |
+--| | REGISTER | adr(7..2) | offset | Byte Enable | Size | |
+--| +-------------------------------------------------------------------+ |
+--| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | |
+--| +-------------------------------------------------------------------+ |
+--| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | |
+--| +-------------------------------------------------------------------+ |
+--| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | |
+--| +-------------------------------------------------------------------+ |
+--| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | |
+--| +-------------------------------------------------------------------+ |
+--| | REVISIONID | 000010 (r) | 08 | 0 | 1 | |
+--| +-------------------------------------------------------------------+ |
+--| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | |
+--| +-------------------------------------------------------------------+ |
+--| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | |
+--| +-------------------------------------------------------------------+ |
+--| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | |
+--| +-------------------------------------------------------------------+ |
+--| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | |
+--| +-------------------------------------------------------------------+ |
+--| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | |
+--| +-------------------------------------------------------------------+ |
+--| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | |
+--| +-------------------------------------------------------------------+ |
+--| | INTPIN | 001111 (r) | 3D | 1 | 1 | |
+--| +-------------------------------------------------------------------+ |
+--| (w*) Reseteable |
+--| |
+--| +-----------------------------------------------+ |
+--| | VENDORID (r) Vendor ID register | |
+--| +-----------------------------------------------+-----------------------+ |
+--| | Identifies manufacturer of device. | |
+--| | VENDORIDr : vendorID (generic) | |
+--| +-----------------------------------------------------------------------+ |
+--| |
+--| +-----------------------------------------------+ |
+--| | DEVICEID (r) Device ID register | |
+--| +-----------------------------------------------+-----------------------+ |
+--| | Identifies the device. | |
+--| | DEVICEIDr : deviceID (generic) | |
+--| +-----------------------------------------------------------------------+ |
+--| |
+--| +-----------------------------------------------+ |
+--| | CMD (r/w) CoMmanD register | |
+--| +-----------------------------------------------+------------------------------+ |
+--| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb | (15-8) |
+--| +------------------------------------------------------------------------------+ |
+--| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb|IOSPACEENb| (7-0) |
+--| +------------------------------------------------------------------------------+ |
+--| | SERRENb : System ERRor ENable (1 = Enabled) | |
+--| | PERRENb : Parity ERRor ENable (1 = Enabled) | |
+--| | MEMSPACEENb : MEMory SPACE ENable (1 = Enabled) | |
+--| | IOSPACEENb : IO SPACE ENable (1 = Enabled) | |
+--| +-----------------------------------------------------------------------+ |
+--| |
+--| +-----------------------------------------------+ |
+--| | ST (r/w*) STatus register | |
+--| +-----------------------------------------------+-------------------------+ |
+--| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) |
+--| +-------------------------------------------------------------------------+ |
+--| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) |
+--| +-------------------------------------------------------------------------+ |
+--| | PERRDTb : Parity ERRor DeTected | |
+--| | SERRSIb : System ERRor SIgnaled | |
+--| | TABORTSIb : Target ABORT SIgnaled | |
+--| +-----------------------------------------------------------------------+ |
+--| |
+--| +-----------------------------------------------+ |
+--| | REVISIONID (r) Revision ID register | |
+--| +-----------------------------------------------+-----------------------+ |
+--| | Identifies a device revision. | |
+--| +-----------------------------------------------------------------------+ |
+--| +-----------------------------------------------+ |
+--| | CLASSCODE (r) CLASS CODE register | |
+--| +-----------------------------------------------+-----------------------+ |
+--| | Identifies the generic funtion of the device. | |
+--| +-----------------------------------------------------------------------+ |
+--| +-----------------------------------------------+ |
+--| | HEADERTYPE (r) Header Type register | |
+--| +-----------------------------------------------+-----------------------+ |
+--| | Identifies the layout of the second part of the predefined header. | |
+--| +-----------------------------------------------------------------------+ |
+--| |
+--| +-----------------------------------------------+ |
+--| | BAR0 (r/w) Base AddRess 0 register | |
+--| +-----------------------------------------------+-----------------------+ |
+--| | BAR032MBb(6..0) | -- | (31-24) |
+--| +-----------------------------------------------------------------------+ |
+--| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | |
+--| +-----------------------------------------------------------------------+ |
+--| |
+--| +-----------------------------------------------+ |
+--| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | |
+--| +-----------------------------------------------+-----------------------+ |
+--| | Identifies vendor of add-in board or subsystem. | |
+--| | SUBSYSTEMVIDr : subsystemvID (generic) | |
+--| +-----------------------------------------------------------------------+ |
+--| |
+--| +-----------------------------------------------+ |
+--| | SUBSYSTEMID (r) SUBSYSTEM ID register | |
+--| +-----------------------------------------------+-----------------------+ |
+--| | Vendor specific. | |
+--| | SUBSYTEMIDr : subsytemID (generic) | |
+--| +-----------------------------------------------------------------------+ |
+--| |
+--| +-----------------------------------------------+ |
+--| | INTLINE (r/w) INTerrupt LINE register | |
+--| +-----------------------------------------------+-----------------------+ |
+--| | INTLINEr(7..0) | (7..0) |
+--| +-----------------------------------------------------------------------+ |
+--| | Interrupt Line routing information | |
+--| +-----------------------------------------------------------------------+ |
+--| |
+--| +-----------------------------------------------+ |
+--| | INTPIN (r) INTerrupt PIN register | |
+--| +-----------------------------------------------+-----------------------+ |
+--| | Tells which interrupt pin the device uses: 01=INTA | |
+--| +-----------------------------------------------------------------------+ |
+--| |
+--+-------------------------------------------------------------------------------------------------+
+--+-----------------------------------------------------------------+
+--| |
+--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
+--| |
+--| This source file may be used and distributed without |
+--| restriction provided that this copyright statement is not |
+--| removed from the file and that any derivative work contains |
+--| the original copyright notice and the associated disclaimer. |
+--| |
+--| This source file is free software; you can redistribute it |
+--| and/or modify it under the terms of the GNU Lesser General |
+--| Public License as published by the Free Software Foundation; |
+--| either version 2.1 of the License, or (at your option) any |
+--| later version. |
+--| |
+--| This source is distributed in the hope that it will be |
+--| useful, but WITHOUT ANY WARRANTY; without even the implied |
+--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
+--| PURPOSE. See the GNU Lesser General Public License for more |
+--| details. |
+--| |
+--| You should have received a copy of the GNU Lesser General |
+--| Public License along with this source; if not, download it |
+--| from http://www.opencores.org/lgpl.shtml |
+--| |
+--+-----------------------------------------------------------------+
+
+
+--+-----------------------------------------------------------------------------+
+--| LIBRARIES |
+--+-----------------------------------------------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library onalib;
+use onalib.onapackage.all;
+
+
+--+-----------------------------------------------------------------------------+
+--| ENTITY |
+--+-----------------------------------------------------------------------------+
+
+entity pciregs is
+generic (
+
+ vendorID : std_logic_vector(15 downto 0);
+ deviceID : std_logic_vector(15 downto 0);
+ revisionID : std_logic_vector(7 downto 0);
+ subsystemID : std_logic_vector(15 downto 0);
+ subsystemvID : std_logic_vector(15 downto 0);
+ classcodeID : std_logic_vector(23 downto 0);
+ BARS : string := "1BARMEM"
+
+);
+port (
+
+ -- General
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ --
+ adr_i : in std_logic_vector(5 downto 0);
+ cbe_i : in std_logic_vector(3 downto 0);
+ dat_i : in std_logic_vector(31 downto 0);
+ dat_o : out std_logic_vector(31 downto 0);
+ --
+ wrcfg_i : in std_logic;
+ rdcfg_i : in std_logic;
+ perr_i : in std_logic;
+ serr_i : in std_logic;
+ tabort_i : in std_logic;
+ --
+ bar0_o : out std_logic_vector(31 downto 9);
+ perrEN_o : out std_logic;
+ serrEN_o : out std_logic;
+ memEN_o : out std_logic;
+ ioEN_o : out std_logic
+
+);
+end pciregs;
+
+
+architecture rtl of pciregs is
+
+
+--+-----------------------------------------------------------------------------+
+--| COMPONENTS |
+--+-----------------------------------------------------------------------------+
+--+-----------------------------------------------------------------------------+
+--| CONSTANTS |
+--+-----------------------------------------------------------------------------+
+
+ --constant CLASSCODEr : std_logic_vector(23 downto 0) := X"068000"; -- Bridge-OtherBridgeDevice
+ constant CLASSCODEr : std_logic_vector(23 downto 0) := classcodeID;
+ constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81...
+ constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00";
+ constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed
+ constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID;
+ constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID;
+ constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID;
+ constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID;
+ constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA#
+
+
+--+-----------------------------------------------------------------------------+
+--| SIGNALS |
+--+-----------------------------------------------------------------------------+
+
+ signal dataout : std_logic_vector(31 downto 0);
+ signal tabortPFS : std_logic;
+ signal serrPFS : std_logic;
+ signal perrPFS : std_logic;
+ signal adrSTCMD : std_logic;
+ signal adrBAR0 : std_logic;
+ signal adrINT : std_logic;
+ signal we0CMD : std_logic;
+ signal we1CMD : std_logic;
+ signal we3ST : std_logic;
+ signal we3BAR0 : std_logic;
+ signal we0INT : std_logic;
+ signal we1INT : std_logic;
+ signal st11SEN : std_logic;
+ signal st11REN : std_logic;
+ signal st14SEN : std_logic;
+ signal st14REN : std_logic;
+ signal st15SEN : std_logic;
+ signal st15REN : std_logic;
+
+
+ --+---------------------------------------------------------+
+ --| CONFIGURATION SPACE REGISTERS |
+ --+---------------------------------------------------------+
+
+ -- INTERRUPT LINE register
+ signal INTLINEr : std_logic_vector(7 downto 0);
+ -- COMMAND register bits
+ signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit)
+ signal IOSPACEENb : std_logic; -- IO SPACE ENable (bit)
+ signal PERRENb : std_logic; -- Parity ERRor ENable (bit)
+ signal SERRENb : std_logic; -- SERR ENable (bit)
+ -- STATUS register bits
+ --signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits)
+ signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit)
+ signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit)
+ signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit)
+ -- BAR0 register bits
+ signal BAR0b : std_logic_vector(31 downto 0);
+
+
+begin
+
+ --+-----------------------------------------+
+ --| BAR0 32MBytes Memory Space |
+ --+-----------------------------------------+
+ barmem_g: if (BARS="1BARMEM") generate
+ BAR0b(24 downto 0) <= (others => '0');
+ end generate;
+
+ --+-----------------------------------------+
+ --| BAR0 512Bytes Io Space |
+ --+-----------------------------------------+
+ bario_g: if (BARS="1BARIO") generate
+ BAR0b(31 downto 16) <= (others => '0');
+ BAR0b(8 downto 1) <= (others => '0');
+ BAR0b(0) <= '1';
+ end generate;
+
+ --+-------------------------------------------------------------------------+
+ --| Component instances |
+ --+-------------------------------------------------------------------------+
+
+ u1: pfs port map ( clk => clk_i, rst => rst_i, a => tabort_i, y => tabortPFS );
+ u2: pfs port map ( clk => clk_i, rst => rst_i, a => serr_i, y => serrPFS );
+ u3: pfs port map ( clk => clk_i, rst => rst_i, a => perr_i, y => perrPFS );
+
+
+ --+-------------------------------------------------------------------------+
+ --| Registers Address Decoder |
+ --+-------------------------------------------------------------------------+
+
+ adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0';
+ adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0';
+ adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0';
+
+
+ --+-------------------------------------------------------------------------+
+ --| WRITE ENABLE REGISTERS |
+ --+-------------------------------------------------------------------------+
+
+ --+-----------------------------------------+
+ --| Write Enable Registers |
+ --+-----------------------------------------+
+
+ we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0));
+ we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1));
+ --we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2));
+ we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3));
+ --we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2));
+ we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3));
+ we0INT <= adrINT and wrcfg_i and (not cbe_i(0));
+ --we1INT <= adrINT and wrcfg_i and (not cbe_i(1));
+
+ --+-----------------------------------------+
+ --| Set Enable & Reset Enable bits |
+ --+-----------------------------------------+
+ st11SEN <= tabortPFS;
+ st11REN <= we3ST and dat_i(27);
+ st14SEN <= serrPFS;
+ st14REN <= we3ST and dat_i(30);
+ st15SEN <= perrPFS;
+ st15REN <= we3ST and dat_i(31);
+
+
+ --+-------------------------------------------------------------------------+
+ --| WRITE REGISTERS |
+ --+-------------------------------------------------------------------------+
+
+ --+---------------------------------------------------------+
+ --| COMMAND REGISTER Write |
+ --+---------------------------------------------------------+
+
+ REGCMDWR: process( clk_i, rst_i, we0CMD, we1CMD, dat_i )
+ begin
+ if( rst_i = '1' ) then
+ IOSPACEENb <= '0';
+ MEMSPACEENb <= '0';
+ PERRENb <= '0';
+ SERRENb <= '0';
+ elsif( rising_edge( clk_i ) ) then
+
+ -- Byte 0
+ if( we0CMD = '1' ) then
+ IOSPACEENb <= dat_i(0);
+ MEMSPACEENb <= dat_i(1);
+ PERRENb <= dat_i(6);
+ end if;
+
+ -- Byte 1
+ if( we1CMD = '1' ) then
+ SERRENb <= dat_i(8);
+ end if;
+
+ end if;
+
+ end process REGCMDWR;
+
+
+ --+---------------------------------------------------------+
+ --| STATUS REGISTER WRITE (Reset only) |
+ --+---------------------------------------------------------+
+
+ REGSTWR: process( clk_i, rst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN )
+ begin
+
+ if( rst_i = '1' ) then
+ TABORTSIb <= '0';
+ SERRSIb <= '0';
+ PERRDTb <= '0';
+ elsif( rising_edge( clk_i ) ) then
+
+ -- TarGet ABORT SIgnaling bit
+ if( st11SEN = '1' ) then
+ TABORTSIb <= '1';
+ elsif ( st11REN = '1' ) then
+ TABORTSIb <= '0';
+ end if;
+
+ -- System ERRor SIgnaling bit
+ if( st14SEN = '1' ) then
+ SERRSIb <= '1';
+ elsif ( st14REN = '1' ) then
+ SERRSIb <= '0';
+ end if;
+
+ -- Parity ERRor DEtected bit
+ if( st15SEN = '1' ) then
+ PERRDTb <= '1';
+ elsif ( st15REN = '1' ) then
+ PERRDTb <= '0';
+ end if;
+
+ end if;
+
+ end process REGSTWR;
+
+
+ --+---------------------------------------------------------+
+ --| INTERRUPT REGISTER Write |
+ --+---------------------------------------------------------+
+
+ REGINTWR: process( clk_i, rst_i, we0INT, dat_i )
+ begin
+
+ if( rst_i = '1' ) then
+ INTLINEr <= ( others => '0' );
+ elsif( rising_edge( clk_i ) ) then
+ -- Byte 0
+ if( we0INT = '1' ) then
+ INTLINEr <= dat_i(7 downto 0);
+ end if;
+ end if;
+ end process REGINTWR;
+
+
+ --+---------------------------------------------------------+
+ --| BAR0 32MBytes MEM address space (bits 31-25) |
+ --+---------------------------------------------------------+
+ rbarmem_g: if (BARS="1BARMEM") generate
+ RBAR0MEMWR: process( clk_i, rst_i, we3BAR0, dat_i )
+ begin
+ if( rst_i = '1' ) then
+ BAR0b(31 downto 25) <= ( others => '0' );
+ elsif( rising_edge( clk_i ) ) then
+ -- Byte 3
+ if( we3BAR0 = '1' ) then
+ BAR0b(31 downto 25) <= dat_i(31 downto 25);
+ end if;
+ end if;
+ end process RBAR0MEMWR;
+ end generate;
+
+ --+---------------------------------------------------------+
+ --| BAR0 512Bytes IO address space (bits 15-9) |
+ --+---------------------------------------------------------+
+ rbario_g: if (BARS="1BARIO") generate
+ RBAR0IOWR: process( clk_i, rst_i, we3BAR0, dat_i )
+ begin
+ if( rst_i = '1' ) then
+ BAR0b(15 downto 9) <= ( others => '0' );
+ elsif( rising_edge( clk_i ) ) then
+ -- Byte 3
+ if( we3BAR0 = '1' ) then
+ BAR0b(15 downto 9) <= dat_i(15 downto 9);
+ end if;
+ end if;
+ end process RBAR0IOWR;
+ end generate;
+
+
+
+ --+-------------------------------------------------------------------------+
+ --| Registers MUX (READ) |
+ --+-------------------------------------------------------------------------+
+ RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, IOSPACEENb, BAR0b,
+ INTLINEr, rdcfg_i )
+ begin
+
+ if ( rdcfg_i = '1' ) then
+
+ case adr_i is
+
+ when b"000000" =>
+ dataout <= DEVICEIDr & VENDORIDr;
+ when b"000001" =>
+ dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" &
+ b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & IOSPACEENb;
+ when b"000010" =>
+ dataout <= CLASSCODEr & REVISIONIDr;
+ when b"000100" =>
+ dataout <= BAR0b;
+ when b"001011" =>
+ dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr;
+ when b"001111" =>
+ dataout <= b"0000000000000000" & INTPINr & INTLINEr;
+ when others =>
+ dataout <= ( others => '0' );
+
+ end case;
+
+ else
+
+ dataout <= ( others => '0' );
+
+ end if;
+
+ end process RRMUX;
+
+ dat_o <= dataout;
+
+
+ --+-------------------------------------------------------------------------+
+ --| BAR0 & COMMAND REGS bits outputs |
+ --+-------------------------------------------------------------------------+
+
+ bar0_o <= BAR0b(31 downto 9);
+ perrEN_o <= PERRENb;
+ serrEN_o <= SERRENb;
+ memEN_o <= MEMSPACEENb;
+ ioEN_o <= IOSPACEENb;
+
+
+end rtl;
Index: trunk/rtl/pciwbsequ.vhd
===================================================================
--- trunk/rtl/pciwbsequ.vhd (nonexistent)
+++ trunk/rtl/pciwbsequ.vhd (revision 10)
@@ -0,0 +1,386 @@
+--+-------------------------------------------------------------------------------------------------+
+--| |
+--| Fileo: pciwbsequ.vhd |
+--| |
+--| Project: pci32tLite |
+--| |
+--| Description: FSM controling pci to whisbone transactions. |
+--| |
+--+-------------------------------------------------------------------------------------------------+
+--+-----------------------------------------------------------------+
+--| |
+--| Copyright (C) 2005-2008 Peio Azkarate, peio.azkarate@gmail.com |
+--| |
+--| This source file may be used and distributed without |
+--| restriction provided that this copyright statement is not |
+--| removed from the file and that any derivative work contains |
+--| the original copyright notice and the associated disclaimer. |
+--| |
+--| This source file is free software; you can redistribute it |
+--| and/or modify it under the terms of the GNU Lesser General |
+--| Public License as published by the Free Software Foundation; |
+--| either version 2.1 of the License, or (at your option) any |
+--| later version. |
+--| |
+--| This source is distributed in the hope that it will be |
+--| useful, but WITHOUT ANY WARRANTY; without even the implied |
+--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
+--| PURPOSE. See the GNU Lesser General Public License for more |
+--| details. |
+--| |
+--| You should have received a copy of the GNU Lesser General |
+--| Public License along with this source; if not, download it |
+--| from http://www.opencores.org/lgpl.shtml |
+--| |
+--+-----------------------------------------------------------------+
+
+
+--+-----------------------------------------------------------------------------+
+--| LIBRARIES |
+--+-----------------------------------------------------------------------------+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library onalib;
+use onalib.onapackage.all;
+
+--+-----------------------------------------------------------------------------+
+--| ENTITY |
+--+-----------------------------------------------------------------------------+
+
+entity pciwbsequ is
+generic (
+ BARS : string := "1BARMEM";
+ WBSIZE : integer := 16;
+ WBENDIAN : string := "BIG"
+);
+port (
+ -- General
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ -- pci
+ cmd_i : in std_logic_vector(3 downto 0);
+ cbe_i : in std_logic_vector(3 downto 0);
+ frame_i : in std_logic;
+ irdy_i : in std_logic;
+ devsel_o : out std_logic;
+ trdy_o : out std_logic;
+ stop_o : out std_logic;
+ -- control
+ adrcfg_i : in std_logic;
+ adrmem_i : in std_logic;
+ pciadrLD_o : out std_logic;
+ pcidOE_o : out std_logic;
+ parOE_o : out std_logic;
+ wbdatLD_o : out std_logic;
+ wrcfg_o : out std_logic;
+ rdcfg_o : out std_logic;
+ -- whisbone
+ wb_sel_o : out std_logic_vector(((WBSIZE/8)-1) downto 0);
+ wb_we_o : out std_logic;
+ wb_stb_o : out std_logic;
+ wb_cyc_o : out std_logic;
+ wb_ack_i : in std_logic;
+ wb_rty_i : in std_logic;
+ wb_err_i : in std_logic
+
+);
+end pciwbsequ;
+
+
+architecture rtl of pciwbsequ is
+
+
+--+-----------------------------------------------------------------------------+
+--| COMPONENTS |
+--+-----------------------------------------------------------------------------+
+--+-----------------------------------------------------------------------------+
+--| CONSTANTS |
+--+-----------------------------------------------------------------------------+
+--+-----------------------------------------------------------------------------+
+--| SIGNALS |
+--+-----------------------------------------------------------------------------+
+
+ type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, BACKOFF, TURN_ARL, TURN_ARE );
+ signal pst_pci : PciFSM;
+ signal nxt_pci : PciFSM;
+
+ signal bbusy : std_logic;
+ signal idle : std_logic;
+ signal sdata1 : std_logic;
+ signal sdata2 : std_logic;
+ signal sdata1NX : std_logic;
+ signal sdata2NX : std_logic;
+ signal turnarlNX : std_logic;
+ signal turnarl : std_logic;
+ signal devselNX_n : std_logic;
+ signal trdyNX_n : std_logic;
+ signal stopNx_n : std_logic;
+ signal devsel : std_logic;
+ signal trdy : std_logic;
+ signal stop : std_logic;
+ signal adrpci : std_logic;
+ signal acking : std_logic;
+ signal retrying : std_logic;
+ signal rdcfg : std_logic;
+ signal targOE : std_logic;
+ signal pcidOE : std_logic;
+ signal pcidOE_s : std_logic;
+
+begin
+
+
+ --+-------------------------------------------------------------------------+
+ --| PCI-Whisbone Sequencer |
+ --+-------------------------------------------------------------------------+
+
+ --+-------------------------------------------------------------+
+ --| FSM PCI-Whisbone |
+ --+-------------------------------------------------------------+
+ PCIFSM_CLOCKED: process( rst_i, clk_i, nxt_pci )
+ begin
+ if( rst_i = '1' ) then
+ pst_pci <= PCIIDLE;
+ elsif( rising_edge(clk_i) ) then
+ pst_pci <= nxt_pci;
+ end if;
+ end process PCIFSM_CLOCKED;
+
+
+ PCIFSM_COMB: process( pst_pci, frame_i, irdy_i, adrcfg_i, adrpci, acking, retrying )
+ begin
+
+ devselNX_n <= '1';
+ trdyNX_n <= '1';
+ stopNX_n <= '1';
+
+ case pst_pci is
+
+ when PCIIDLE =>
+ if ( frame_i = '0' ) then
+ nxt_pci <= B_BUSY;
+ else
+ nxt_pci <= PCIIDLE;
+ end if;
+
+ when B_BUSY =>
+ if ( adrpci = '0' ) then
+ nxt_pci <= TURN_ARE;
+ else
+ nxt_pci <= S_DATA1;
+ devselNX_n <= '0';
+ end if;
+
+ when S_DATA1 =>
+ if (acking = '1') then
+ if (frame_i = '0') then
+ stopNX_n <= '0';
+ end if;
+ nxt_pci <= S_DATA2;
+ devselNX_n <= '0';
+ trdyNX_n <= '0';
+ elsif (retrying = '1') then
+ nxt_pci <= BACKOFF;
+ devselNX_n <= '0';
+ stopNX_n <= '0';
+ else
+ nxt_pci <= S_DATA1;
+ devselNX_n <= '0';
+ end if;
+
+ when S_DATA2 =>
+ nxt_pci <= TURN_ARL;
+
+ when BACKOFF =>
+ if ( frame_i = '1' and irdy_i = '0' ) then
+ nxt_pci <= TURN_ARL;
+ else
+ nxt_pci <= BACKOFF;
+ devselNX_n <= '0';
+ stopNX_n <= '0';
+ end if;
+
+ when TURN_ARL =>
+ if (frame_i = '0') then
+ nxt_pci <= B_BUSY;
+ else
+ nxt_pci <= PCIIDLE;
+ end if;
+
+ when TURN_ARE =>
+ if (frame_i = '0') then
+ nxt_pci <= TURN_ARE;
+ else
+ nxt_pci <= PCIIDLE;
+ end if;
+
+ end case;
+
+ end process PCIFSM_COMB;
+
+
+ --+-------------------------------------------------------------+
+ --| FSM control signals |
+ --+-------------------------------------------------------------+
+
+ adrpci <= adrmem_i or adrcfg_i;
+ acking <= '1' when ( wb_ack_i = '1' or wb_err_i = '1' ) or ( adrcfg_i = '1' and irdy_i = '0')
+ else '0';
+ retrying <= '1' when ( wb_rty_i = '1' ) else '0';
+
+
+ --+-------------------------------------------------------------+
+ --| FSM derived Control signals |
+ --+-------------------------------------------------------------+
+ idle <= '1' when ( pst_pci = PCIIDLE ) else '0';
+ bbusy <= '1' when ( pst_pci = B_BUSY ) else '0';
+ sdata1 <= '1' when ( pst_pci = S_DATA1 ) else '0';
+ sdata2 <= '1' when ( pst_pci = S_DATA2 ) else '0';
+ --turnar <= '1' when ( pst_pci = TURN_AR ) else '0';
+ turnarl <= '1' when ( pst_pci = TURN_ARL ) else '0';
+ sdata1NX <= '1' when ( nxt_pci = S_DATA1 ) else '0';
+ sdata2NX <= '1' when ( nxt_pci = S_DATA2 ) else '0';
+ --turnarNX <= '1' when ( nxt_pci = TURN_AR ) else '0';
+ turnarlNX <= '1' when ( nxt_pci = TURN_ARL ) else '0';
+
+
+ --+-------------------------------------------------------------+
+ --| PCI Data Output Enable |
+ --+-------------------------------------------------------------+
+
+ PCIDOE_P: process( rst_i, clk_i, cmd_i(0), sdata1NX, turnarlNX )
+ begin
+
+ if ( rst_i = '1' ) then
+ pcidOE <= '0';
+ elsif ( rising_edge(clk_i) ) then
+
+ if ( sdata1NX = '1' and cmd_i(0) = '0' ) then
+ pcidOE <= '1';
+ elsif ( turnarlNX = '1' ) then
+ pcidOE <= '0';
+ end if;
+
+ end if;
+
+ end process PCIDOE_P;
+
+ pcidOE_o <= pcidOE;
+
+
+ --+-------------------------------------------------------------+
+ --| PAR Output Enable |
+ --| PCI Read data phase |
+ --| PAR is valid 1 cicle after data is valid |
+ --+-------------------------------------------------------------+
+ uu1: syncl port map ( clk => clk_i, rst => rst_i, d => pcidOE, q => pcidOE_s );
+ parOE_o <= pcidOE_s;
+
+
+ --+-------------------------------------------------------------+
+ --| Target s/t/s signals OE control |
+ --+-------------------------------------------------------------+
+
+ TARGOE_P: process( rst_i, clk_i, sdata1NX, turnarl )
+ begin
+
+ if ( rst_i = '1' ) then
+ targOE <= '0';
+ elsif ( rising_edge(clk_i) ) then
+
+ if ( sdata1NX = '1' ) then
+ targOE <= '1';
+ elsif ( turnarl = '1' ) then
+ targOE <= '0';
+ end if;
+
+ end if;
+
+ end process TARGOE_P;
+
+
+ --+-------------------------------------------------------------------------+
+ --| WHISBONE outs |
+ --+-------------------------------------------------------------------------+
+
+ cyc_p: process(rst_i, clk_i, adrmem_i, bbusy, acking, retrying, frame_i)
+ begin
+ if ( rst_i = '1' ) then
+ wb_cyc_o <= '0';
+ elsif ( rising_edge(clk_i) ) then
+ if (adrmem_i = '1' and bbusy = '1' ) then
+ wb_cyc_o <= '1';
+ elsif ((acking = '1' or retrying = '1') and frame_i = '1') then
+ wb_cyc_o <= '0';
+ end if;
+ end if;
+ end process cyc_p;
+
+ wb_stb_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' and irdy_i = '0' ) else '0';
+ wb_we_o <= cmd_i(0);
+
+ --+-----------------------------------------+
+ --| wb_sel_o generation depending on WBSIZE |
+ --| and WBENDIAN "generics" configuration |
+ --+-----------------------------------------+
+ sel32: if (WBSIZE = 32) generate
+ wb_sel_o(3) <= not cbe_i(3);
+ wb_sel_o(2) <= not cbe_i(2);
+ wb_sel_o(1) <= not cbe_i(1);
+ wb_sel_o(0) <= not cbe_i(0);
+ end generate;
+
+ sel16b: if (WBSIZE = 16 and WBENDIAN = "BIG") generate
+ wb_sel_o(1) <= (not cbe_i(0)) or (not cbe_i(2));
+ wb_sel_o(0) <= (not cbe_i(1)) or (not cbe_i(3));
+ end generate;
+
+ sel16l: if (WBSIZE = 16 and WBENDIAN = "LITTLE") generate
+ wb_sel_o(1) <= (not cbe_i(1)) or (not cbe_i(3));
+ wb_sel_o(0) <= (not cbe_i(0)) or (not cbe_i(2));
+ end generate;
+
+ sel8: if (WBSIZE = 8) generate
+ wb_sel_o(0) <= not (cbe_i(0) and cbe_i(1) and cbe_i(2) and cbe_i(3));
+ end generate;
+
+
+ --+-------------------------------------------------------------------------+
+ --| Syncronized PCI outs |
+ --+-------------------------------------------------------------------------+
+
+ PCISIG: process( rst_i, clk_i, devselNX_n, trdyNX_n, stopNX_n)
+ begin
+ if( rst_i = '1' ) then
+ devsel <= '1';
+ trdy <= '1';
+ stop <= '1';
+ elsif( rising_edge(clk_i) ) then
+ devsel <= devselNX_n;
+ trdy <= trdyNX_n;
+ stop <= stopNX_n;
+ end if;
+ end process PCISIG;
+
+ devsel_o <= devsel when ( targOE = '1' ) else 'Z';
+ trdy_o <= trdy when ( targOE = '1' ) else 'Z';
+ stop_o <= stop when ( targOE = '1' ) else 'Z';
+
+
+ --+-------------------------------------------------------------------------+
+ --| Other outs |
+ --+-------------------------------------------------------------------------+
+
+ -- rd/wr Configuration Space Registers
+ wrcfg_o <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '1' and sdata2 = '1' ) else '0';
+ rdcfg <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '0' and ( sdata1 = '1' or sdata2 = '1' ) ) else '0';
+ rdcfg_o <= rdcfg;
+
+ -- LoaD enable signals
+ --pciadrLD_o <= '1' when(frame_i = '0' and idle = '1') else '0';
+ -- added turnarl to support Fast Back to Back
+ pciadrLD_o <= '1' when(frame_i = '0' and (idle = '1' or turnarl = '1')) else '0';
+ wbdatLD_o <= wb_ack_i;
+
+end rtl;